1 #include <linux/export.h> 2 #include <linux/bitops.h> 3 #include <linux/elf.h> 4 #include <linux/mm.h> 5 6 #include <linux/io.h> 7 #include <linux/sched.h> 8 #include <linux/sched/clock.h> 9 #include <linux/random.h> 10 #include <asm/processor.h> 11 #include <asm/apic.h> 12 #include <asm/cpu.h> 13 #include <asm/spec-ctrl.h> 14 #include <asm/smp.h> 15 #include <asm/pci-direct.h> 16 #include <asm/delay.h> 17 18 #ifdef CONFIG_X86_64 19 # include <asm/mmconfig.h> 20 # include <asm/set_memory.h> 21 #endif 22 23 #include "cpu.h" 24 25 static const int amd_erratum_383[]; 26 static const int amd_erratum_400[]; 27 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum); 28 29 /* 30 * nodes_per_socket: Stores the number of nodes per socket. 31 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX 32 * Node Identifiers[10:8] 33 */ 34 static u32 nodes_per_socket = 1; 35 36 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) 37 { 38 u32 gprs[8] = { 0 }; 39 int err; 40 41 WARN_ONCE((boot_cpu_data.x86 != 0xf), 42 "%s should only be used on K8!\n", __func__); 43 44 gprs[1] = msr; 45 gprs[7] = 0x9c5a203a; 46 47 err = rdmsr_safe_regs(gprs); 48 49 *p = gprs[0] | ((u64)gprs[2] << 32); 50 51 return err; 52 } 53 54 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val) 55 { 56 u32 gprs[8] = { 0 }; 57 58 WARN_ONCE((boot_cpu_data.x86 != 0xf), 59 "%s should only be used on K8!\n", __func__); 60 61 gprs[0] = (u32)val; 62 gprs[1] = msr; 63 gprs[2] = val >> 32; 64 gprs[7] = 0x9c5a203a; 65 66 return wrmsr_safe_regs(gprs); 67 } 68 69 /* 70 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause 71 * misexecution of code under Linux. Owners of such processors should 72 * contact AMD for precise details and a CPU swap. 73 * 74 * See http://www.multimania.com/poulot/k6bug.html 75 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6" 76 * (Publication # 21266 Issue Date: August 1998) 77 * 78 * The following test is erm.. interesting. AMD neglected to up 79 * the chip setting when fixing the bug but they also tweaked some 80 * performance at the same time.. 81 */ 82 83 extern __visible void vide(void); 84 __asm__(".globl vide\n" 85 ".type vide, @function\n" 86 ".align 4\n" 87 "vide: ret\n"); 88 89 static void init_amd_k5(struct cpuinfo_x86 *c) 90 { 91 #ifdef CONFIG_X86_32 92 /* 93 * General Systems BIOSen alias the cpu frequency registers 94 * of the Elan at 0x000df000. Unfortunately, one of the Linux 95 * drivers subsequently pokes it, and changes the CPU speed. 96 * Workaround : Remove the unneeded alias. 97 */ 98 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ 99 #define CBAR_ENB (0x80000000) 100 #define CBAR_KEY (0X000000CB) 101 if (c->x86_model == 9 || c->x86_model == 10) { 102 if (inl(CBAR) & CBAR_ENB) 103 outl(0 | CBAR_KEY, CBAR); 104 } 105 #endif 106 } 107 108 static void init_amd_k6(struct cpuinfo_x86 *c) 109 { 110 #ifdef CONFIG_X86_32 111 u32 l, h; 112 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT); 113 114 if (c->x86_model < 6) { 115 /* Based on AMD doc 20734R - June 2000 */ 116 if (c->x86_model == 0) { 117 clear_cpu_cap(c, X86_FEATURE_APIC); 118 set_cpu_cap(c, X86_FEATURE_PGE); 119 } 120 return; 121 } 122 123 if (c->x86_model == 6 && c->x86_stepping == 1) { 124 const int K6_BUG_LOOP = 1000000; 125 int n; 126 void (*f_vide)(void); 127 u64 d, d2; 128 129 pr_info("AMD K6 stepping B detected - "); 130 131 /* 132 * It looks like AMD fixed the 2.6.2 bug and improved indirect 133 * calls at the same time. 134 */ 135 136 n = K6_BUG_LOOP; 137 f_vide = vide; 138 OPTIMIZER_HIDE_VAR(f_vide); 139 d = rdtsc(); 140 while (n--) 141 f_vide(); 142 d2 = rdtsc(); 143 d = d2-d; 144 145 if (d > 20*K6_BUG_LOOP) 146 pr_cont("system stability may be impaired when more than 32 MB are used.\n"); 147 else 148 pr_cont("probably OK (after B9730xxxx).\n"); 149 } 150 151 /* K6 with old style WHCR */ 152 if (c->x86_model < 8 || 153 (c->x86_model == 8 && c->x86_stepping < 8)) { 154 /* We can only write allocate on the low 508Mb */ 155 if (mbytes > 508) 156 mbytes = 508; 157 158 rdmsr(MSR_K6_WHCR, l, h); 159 if ((l&0x0000FFFF) == 0) { 160 unsigned long flags; 161 l = (1<<0)|((mbytes/4)<<1); 162 local_irq_save(flags); 163 wbinvd(); 164 wrmsr(MSR_K6_WHCR, l, h); 165 local_irq_restore(flags); 166 pr_info("Enabling old style K6 write allocation for %d Mb\n", 167 mbytes); 168 } 169 return; 170 } 171 172 if ((c->x86_model == 8 && c->x86_stepping > 7) || 173 c->x86_model == 9 || c->x86_model == 13) { 174 /* The more serious chips .. */ 175 176 if (mbytes > 4092) 177 mbytes = 4092; 178 179 rdmsr(MSR_K6_WHCR, l, h); 180 if ((l&0xFFFF0000) == 0) { 181 unsigned long flags; 182 l = ((mbytes>>2)<<22)|(1<<16); 183 local_irq_save(flags); 184 wbinvd(); 185 wrmsr(MSR_K6_WHCR, l, h); 186 local_irq_restore(flags); 187 pr_info("Enabling new style K6 write allocation for %d Mb\n", 188 mbytes); 189 } 190 191 return; 192 } 193 194 if (c->x86_model == 10) { 195 /* AMD Geode LX is model 10 */ 196 /* placeholder for any needed mods */ 197 return; 198 } 199 #endif 200 } 201 202 static void init_amd_k7(struct cpuinfo_x86 *c) 203 { 204 #ifdef CONFIG_X86_32 205 u32 l, h; 206 207 /* 208 * Bit 15 of Athlon specific MSR 15, needs to be 0 209 * to enable SSE on Palomino/Morgan/Barton CPU's. 210 * If the BIOS didn't enable it already, enable it here. 211 */ 212 if (c->x86_model >= 6 && c->x86_model <= 10) { 213 if (!cpu_has(c, X86_FEATURE_XMM)) { 214 pr_info("Enabling disabled K7/SSE Support.\n"); 215 msr_clear_bit(MSR_K7_HWCR, 15); 216 set_cpu_cap(c, X86_FEATURE_XMM); 217 } 218 } 219 220 /* 221 * It's been determined by AMD that Athlons since model 8 stepping 1 222 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx 223 * As per AMD technical note 27212 0.2 224 */ 225 if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) { 226 rdmsr(MSR_K7_CLK_CTL, l, h); 227 if ((l & 0xfff00000) != 0x20000000) { 228 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", 229 l, ((l & 0x000fffff)|0x20000000)); 230 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); 231 } 232 } 233 234 set_cpu_cap(c, X86_FEATURE_K7); 235 236 /* calling is from identify_secondary_cpu() ? */ 237 if (!c->cpu_index) 238 return; 239 240 /* 241 * Certain Athlons might work (for various values of 'work') in SMP 242 * but they are not certified as MP capable. 243 */ 244 /* Athlon 660/661 is valid. */ 245 if ((c->x86_model == 6) && ((c->x86_stepping == 0) || 246 (c->x86_stepping == 1))) 247 return; 248 249 /* Duron 670 is valid */ 250 if ((c->x86_model == 7) && (c->x86_stepping == 0)) 251 return; 252 253 /* 254 * Athlon 662, Duron 671, and Athlon >model 7 have capability 255 * bit. It's worth noting that the A5 stepping (662) of some 256 * Athlon XP's have the MP bit set. 257 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for 258 * more. 259 */ 260 if (((c->x86_model == 6) && (c->x86_stepping >= 2)) || 261 ((c->x86_model == 7) && (c->x86_stepping >= 1)) || 262 (c->x86_model > 7)) 263 if (cpu_has(c, X86_FEATURE_MP)) 264 return; 265 266 /* If we get here, not a certified SMP capable AMD system. */ 267 268 /* 269 * Don't taint if we are running SMP kernel on a single non-MP 270 * approved Athlon 271 */ 272 WARN_ONCE(1, "WARNING: This combination of AMD" 273 " processors is not suitable for SMP.\n"); 274 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); 275 #endif 276 } 277 278 #ifdef CONFIG_NUMA 279 /* 280 * To workaround broken NUMA config. Read the comment in 281 * srat_detect_node(). 282 */ 283 static int nearby_node(int apicid) 284 { 285 int i, node; 286 287 for (i = apicid - 1; i >= 0; i--) { 288 node = __apicid_to_node[i]; 289 if (node != NUMA_NO_NODE && node_online(node)) 290 return node; 291 } 292 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { 293 node = __apicid_to_node[i]; 294 if (node != NUMA_NO_NODE && node_online(node)) 295 return node; 296 } 297 return first_node(node_online_map); /* Shouldn't happen */ 298 } 299 #endif 300 301 #ifdef CONFIG_SMP 302 /* 303 * Fix up cpu_core_id for pre-F17h systems to be in the 304 * [0 .. cores_per_node - 1] range. Not really needed but 305 * kept so as not to break existing setups. 306 */ 307 static void legacy_fixup_core_id(struct cpuinfo_x86 *c) 308 { 309 u32 cus_per_node; 310 311 if (c->x86 >= 0x17) 312 return; 313 314 cus_per_node = c->x86_max_cores / nodes_per_socket; 315 c->cpu_core_id %= cus_per_node; 316 } 317 318 /* 319 * Fixup core topology information for 320 * (1) AMD multi-node processors 321 * Assumption: Number of cores in each internal node is the same. 322 * (2) AMD processors supporting compute units 323 */ 324 static void amd_get_topology(struct cpuinfo_x86 *c) 325 { 326 u8 node_id; 327 int cpu = smp_processor_id(); 328 329 /* get information required for multi-node processors */ 330 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 331 u32 eax, ebx, ecx, edx; 332 333 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); 334 335 node_id = ecx & 0xff; 336 smp_num_siblings = ((ebx >> 8) & 0xff) + 1; 337 338 if (c->x86 == 0x15) 339 c->cu_id = ebx & 0xff; 340 341 if (c->x86 >= 0x17) { 342 c->cpu_core_id = ebx & 0xff; 343 344 if (smp_num_siblings > 1) 345 c->x86_max_cores /= smp_num_siblings; 346 } 347 348 /* 349 * We may have multiple LLCs if L3 caches exist, so check if we 350 * have an L3 cache by looking at the L3 cache CPUID leaf. 351 */ 352 if (cpuid_edx(0x80000006)) { 353 if (c->x86 == 0x17) { 354 /* 355 * LLC is at the core complex level. 356 * Core complex id is ApicId[3]. 357 */ 358 per_cpu(cpu_llc_id, cpu) = c->apicid >> 3; 359 } else { 360 /* LLC is at the node level. */ 361 per_cpu(cpu_llc_id, cpu) = node_id; 362 } 363 } 364 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { 365 u64 value; 366 367 rdmsrl(MSR_FAM10H_NODE_ID, value); 368 node_id = value & 7; 369 370 per_cpu(cpu_llc_id, cpu) = node_id; 371 } else 372 return; 373 374 if (nodes_per_socket > 1) { 375 set_cpu_cap(c, X86_FEATURE_AMD_DCM); 376 legacy_fixup_core_id(c); 377 } 378 } 379 #endif 380 381 /* 382 * On a AMD dual core setup the lower bits of the APIC id distinguish the cores. 383 * Assumes number of cores is a power of two. 384 */ 385 static void amd_detect_cmp(struct cpuinfo_x86 *c) 386 { 387 #ifdef CONFIG_SMP 388 unsigned bits; 389 int cpu = smp_processor_id(); 390 391 bits = c->x86_coreid_bits; 392 /* Low order bits define the core id (index of core in socket) */ 393 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1); 394 /* Convert the initial APIC ID into the socket ID */ 395 c->phys_proc_id = c->initial_apicid >> bits; 396 /* use socket ID also for last level cache */ 397 per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; 398 amd_get_topology(c); 399 #endif 400 } 401 402 u16 amd_get_nb_id(int cpu) 403 { 404 u16 id = 0; 405 #ifdef CONFIG_SMP 406 id = per_cpu(cpu_llc_id, cpu); 407 #endif 408 return id; 409 } 410 EXPORT_SYMBOL_GPL(amd_get_nb_id); 411 412 u32 amd_get_nodes_per_socket(void) 413 { 414 return nodes_per_socket; 415 } 416 EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket); 417 418 static void srat_detect_node(struct cpuinfo_x86 *c) 419 { 420 #ifdef CONFIG_NUMA 421 int cpu = smp_processor_id(); 422 int node; 423 unsigned apicid = c->apicid; 424 425 node = numa_cpu_node(cpu); 426 if (node == NUMA_NO_NODE) 427 node = per_cpu(cpu_llc_id, cpu); 428 429 /* 430 * On multi-fabric platform (e.g. Numascale NumaChip) a 431 * platform-specific handler needs to be called to fixup some 432 * IDs of the CPU. 433 */ 434 if (x86_cpuinit.fixup_cpu_id) 435 x86_cpuinit.fixup_cpu_id(c, node); 436 437 if (!node_online(node)) { 438 /* 439 * Two possibilities here: 440 * 441 * - The CPU is missing memory and no node was created. In 442 * that case try picking one from a nearby CPU. 443 * 444 * - The APIC IDs differ from the HyperTransport node IDs 445 * which the K8 northbridge parsing fills in. Assume 446 * they are all increased by a constant offset, but in 447 * the same order as the HT nodeids. If that doesn't 448 * result in a usable node fall back to the path for the 449 * previous case. 450 * 451 * This workaround operates directly on the mapping between 452 * APIC ID and NUMA node, assuming certain relationship 453 * between APIC ID, HT node ID and NUMA topology. As going 454 * through CPU mapping may alter the outcome, directly 455 * access __apicid_to_node[]. 456 */ 457 int ht_nodeid = c->initial_apicid; 458 459 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE) 460 node = __apicid_to_node[ht_nodeid]; 461 /* Pick a nearby node */ 462 if (!node_online(node)) 463 node = nearby_node(apicid); 464 } 465 numa_set_node(cpu, node); 466 #endif 467 } 468 469 static void early_init_amd_mc(struct cpuinfo_x86 *c) 470 { 471 #ifdef CONFIG_SMP 472 unsigned bits, ecx; 473 474 /* Multi core CPU? */ 475 if (c->extended_cpuid_level < 0x80000008) 476 return; 477 478 ecx = cpuid_ecx(0x80000008); 479 480 c->x86_max_cores = (ecx & 0xff) + 1; 481 482 /* CPU telling us the core id bits shift? */ 483 bits = (ecx >> 12) & 0xF; 484 485 /* Otherwise recompute */ 486 if (bits == 0) { 487 while ((1 << bits) < c->x86_max_cores) 488 bits++; 489 } 490 491 c->x86_coreid_bits = bits; 492 #endif 493 } 494 495 static void bsp_init_amd(struct cpuinfo_x86 *c) 496 { 497 498 #ifdef CONFIG_X86_64 499 if (c->x86 >= 0xf) { 500 unsigned long long tseg; 501 502 /* 503 * Split up direct mapping around the TSEG SMM area. 504 * Don't do it for gbpages because there seems very little 505 * benefit in doing so. 506 */ 507 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) { 508 unsigned long pfn = tseg >> PAGE_SHIFT; 509 510 pr_debug("tseg: %010llx\n", tseg); 511 if (pfn_range_is_mapped(pfn, pfn + 1)) 512 set_memory_4k((unsigned long)__va(tseg), 1); 513 } 514 } 515 #endif 516 517 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { 518 519 if (c->x86 > 0x10 || 520 (c->x86 == 0x10 && c->x86_model >= 0x2)) { 521 u64 val; 522 523 rdmsrl(MSR_K7_HWCR, val); 524 if (!(val & BIT(24))) 525 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n"); 526 } 527 } 528 529 if (c->x86 == 0x15) { 530 unsigned long upperbit; 531 u32 cpuid, assoc; 532 533 cpuid = cpuid_edx(0x80000005); 534 assoc = cpuid >> 16 & 0xff; 535 upperbit = ((cpuid >> 24) << 10) / assoc; 536 537 va_align.mask = (upperbit - 1) & PAGE_MASK; 538 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64; 539 540 /* A random value per boot for bit slice [12:upper_bit) */ 541 va_align.bits = get_random_int() & va_align.mask; 542 } 543 544 if (cpu_has(c, X86_FEATURE_MWAITX)) 545 use_mwaitx_delay(); 546 547 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 548 u32 ecx; 549 550 ecx = cpuid_ecx(0x8000001e); 551 nodes_per_socket = ((ecx >> 8) & 7) + 1; 552 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) { 553 u64 value; 554 555 rdmsrl(MSR_FAM10H_NODE_ID, value); 556 nodes_per_socket = ((value >> 3) & 7) + 1; 557 } 558 559 if (c->x86 >= 0x15 && c->x86 <= 0x17) { 560 unsigned int bit; 561 562 switch (c->x86) { 563 case 0x15: bit = 54; break; 564 case 0x16: bit = 33; break; 565 case 0x17: bit = 10; break; 566 default: return; 567 } 568 /* 569 * Try to cache the base value so further operations can 570 * avoid RMW. If that faults, do not enable SSBD. 571 */ 572 if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) { 573 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD); 574 setup_force_cpu_cap(X86_FEATURE_SSBD); 575 x86_amd_ls_cfg_ssbd_mask = 1ULL << bit; 576 } 577 } 578 } 579 580 static void early_detect_mem_encrypt(struct cpuinfo_x86 *c) 581 { 582 u64 msr; 583 584 /* 585 * BIOS support is required for SME and SEV. 586 * For SME: If BIOS has enabled SME then adjust x86_phys_bits by 587 * the SME physical address space reduction value. 588 * If BIOS has not enabled SME then don't advertise the 589 * SME feature (set in scattered.c). 590 * For SEV: If BIOS has not enabled SEV then don't advertise the 591 * SEV feature (set in scattered.c). 592 * 593 * In all cases, since support for SME and SEV requires long mode, 594 * don't advertise the feature under CONFIG_X86_32. 595 */ 596 if (cpu_has(c, X86_FEATURE_SME) || cpu_has(c, X86_FEATURE_SEV)) { 597 /* Check if memory encryption is enabled */ 598 rdmsrl(MSR_K8_SYSCFG, msr); 599 if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT)) 600 goto clear_all; 601 602 /* 603 * Always adjust physical address bits. Even though this 604 * will be a value above 32-bits this is still done for 605 * CONFIG_X86_32 so that accurate values are reported. 606 */ 607 c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f; 608 609 if (IS_ENABLED(CONFIG_X86_32)) 610 goto clear_all; 611 612 rdmsrl(MSR_K7_HWCR, msr); 613 if (!(msr & MSR_K7_HWCR_SMMLOCK)) 614 goto clear_sev; 615 616 return; 617 618 clear_all: 619 clear_cpu_cap(c, X86_FEATURE_SME); 620 clear_sev: 621 clear_cpu_cap(c, X86_FEATURE_SEV); 622 } 623 } 624 625 static void early_init_amd(struct cpuinfo_x86 *c) 626 { 627 u32 dummy; 628 629 early_init_amd_mc(c); 630 631 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); 632 633 /* 634 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 635 * with P/T states and does not stop in deep C-states 636 */ 637 if (c->x86_power & (1 << 8)) { 638 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 639 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 640 } 641 642 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */ 643 if (c->x86_power & BIT(12)) 644 set_cpu_cap(c, X86_FEATURE_ACC_POWER); 645 646 #ifdef CONFIG_X86_64 647 set_cpu_cap(c, X86_FEATURE_SYSCALL32); 648 #else 649 /* Set MTRR capability flag if appropriate */ 650 if (c->x86 == 5) 651 if (c->x86_model == 13 || c->x86_model == 9 || 652 (c->x86_model == 8 && c->x86_stepping >= 8)) 653 set_cpu_cap(c, X86_FEATURE_K6_MTRR); 654 #endif 655 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) 656 /* 657 * ApicID can always be treated as an 8-bit value for AMD APIC versions 658 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we 659 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families 660 * after 16h. 661 */ 662 if (boot_cpu_has(X86_FEATURE_APIC)) { 663 if (c->x86 > 0x16) 664 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 665 else if (c->x86 >= 0xf) { 666 /* check CPU config space for extended APIC ID */ 667 unsigned int val; 668 669 val = read_pci_config(0, 24, 0, 0x68); 670 if ((val >> 17 & 0x3) == 0x3) 671 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 672 } 673 } 674 #endif 675 676 /* 677 * This is only needed to tell the kernel whether to use VMCALL 678 * and VMMCALL. VMMCALL is never executed except under virt, so 679 * we can set it unconditionally. 680 */ 681 set_cpu_cap(c, X86_FEATURE_VMMCALL); 682 683 /* F16h erratum 793, CVE-2013-6885 */ 684 if (c->x86 == 0x16 && c->x86_model <= 0xf) 685 msr_set_bit(MSR_AMD64_LS_CFG, 15); 686 687 /* 688 * Check whether the machine is affected by erratum 400. This is 689 * used to select the proper idle routine and to enable the check 690 * whether the machine is affected in arch_post_acpi_init(), which 691 * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check. 692 */ 693 if (cpu_has_amd_erratum(c, amd_erratum_400)) 694 set_cpu_bug(c, X86_BUG_AMD_E400); 695 696 early_detect_mem_encrypt(c); 697 } 698 699 static void init_amd_k8(struct cpuinfo_x86 *c) 700 { 701 u32 level; 702 u64 value; 703 704 /* On C+ stepping K8 rep microcode works well for copy/memset */ 705 level = cpuid_eax(1); 706 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) 707 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 708 709 /* 710 * Some BIOSes incorrectly force this feature, but only K8 revision D 711 * (model = 0x14) and later actually support it. 712 * (AMD Erratum #110, docId: 25759). 713 */ 714 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) { 715 clear_cpu_cap(c, X86_FEATURE_LAHF_LM); 716 if (!rdmsrl_amd_safe(0xc001100d, &value)) { 717 value &= ~BIT_64(32); 718 wrmsrl_amd_safe(0xc001100d, value); 719 } 720 } 721 722 if (!c->x86_model_id[0]) 723 strcpy(c->x86_model_id, "Hammer"); 724 725 #ifdef CONFIG_SMP 726 /* 727 * Disable TLB flush filter by setting HWCR.FFDIS on K8 728 * bit 6 of msr C001_0015 729 * 730 * Errata 63 for SH-B3 steppings 731 * Errata 122 for all steppings (F+ have it disabled by default) 732 */ 733 msr_set_bit(MSR_K7_HWCR, 6); 734 #endif 735 set_cpu_bug(c, X86_BUG_SWAPGS_FENCE); 736 } 737 738 static void init_amd_gh(struct cpuinfo_x86 *c) 739 { 740 #ifdef CONFIG_MMCONF_FAM10H 741 /* do this for boot cpu */ 742 if (c == &boot_cpu_data) 743 check_enable_amd_mmconf_dmi(); 744 745 fam10h_check_enable_mmcfg(); 746 #endif 747 748 /* 749 * Disable GART TLB Walk Errors on Fam10h. We do this here because this 750 * is always needed when GART is enabled, even in a kernel which has no 751 * MCE support built in. BIOS should disable GartTlbWlk Errors already. 752 * If it doesn't, we do it here as suggested by the BKDG. 753 * 754 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012 755 */ 756 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10); 757 758 /* 759 * On family 10h BIOS may not have properly enabled WC+ support, causing 760 * it to be converted to CD memtype. This may result in performance 761 * degradation for certain nested-paging guests. Prevent this conversion 762 * by clearing bit 24 in MSR_AMD64_BU_CFG2. 763 * 764 * NOTE: we want to use the _safe accessors so as not to #GP kvm 765 * guests on older kvm hosts. 766 */ 767 msr_clear_bit(MSR_AMD64_BU_CFG2, 24); 768 769 if (cpu_has_amd_erratum(c, amd_erratum_383)) 770 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH); 771 } 772 773 #define MSR_AMD64_DE_CFG 0xC0011029 774 775 static void init_amd_ln(struct cpuinfo_x86 *c) 776 { 777 /* 778 * Apply erratum 665 fix unconditionally so machines without a BIOS 779 * fix work. 780 */ 781 msr_set_bit(MSR_AMD64_DE_CFG, 31); 782 } 783 784 static void init_amd_bd(struct cpuinfo_x86 *c) 785 { 786 u64 value; 787 788 /* re-enable TopologyExtensions if switched off by BIOS */ 789 if ((c->x86_model >= 0x10) && (c->x86_model <= 0x6f) && 790 !cpu_has(c, X86_FEATURE_TOPOEXT)) { 791 792 if (msr_set_bit(0xc0011005, 54) > 0) { 793 rdmsrl(0xc0011005, value); 794 if (value & BIT_64(54)) { 795 set_cpu_cap(c, X86_FEATURE_TOPOEXT); 796 pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n"); 797 } 798 } 799 } 800 801 /* 802 * The way access filter has a performance penalty on some workloads. 803 * Disable it on the affected CPUs. 804 */ 805 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) { 806 if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) { 807 value |= 0x1E; 808 wrmsrl_safe(MSR_F15H_IC_CFG, value); 809 } 810 } 811 } 812 813 static void init_amd_zn(struct cpuinfo_x86 *c) 814 { 815 set_cpu_cap(c, X86_FEATURE_ZEN); 816 /* 817 * Fix erratum 1076: CPB feature bit not being set in CPUID. It affects 818 * all up to and including B1. 819 */ 820 if (c->x86_model <= 1 && c->x86_stepping <= 1) 821 set_cpu_cap(c, X86_FEATURE_CPB); 822 } 823 824 static void init_amd(struct cpuinfo_x86 *c) 825 { 826 early_init_amd(c); 827 828 /* 829 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 830 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 831 */ 832 clear_cpu_cap(c, 0*32+31); 833 834 if (c->x86 >= 0x10) 835 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 836 837 /* get apicid instead of initial apic id from cpuid */ 838 c->apicid = hard_smp_processor_id(); 839 840 /* K6s reports MCEs but don't actually have all the MSRs */ 841 if (c->x86 < 6) 842 clear_cpu_cap(c, X86_FEATURE_MCE); 843 844 switch (c->x86) { 845 case 4: init_amd_k5(c); break; 846 case 5: init_amd_k6(c); break; 847 case 6: init_amd_k7(c); break; 848 case 0xf: init_amd_k8(c); break; 849 case 0x10: init_amd_gh(c); break; 850 case 0x12: init_amd_ln(c); break; 851 case 0x15: init_amd_bd(c); break; 852 case 0x17: init_amd_zn(c); break; 853 } 854 855 /* 856 * Enable workaround for FXSAVE leak on CPUs 857 * without a XSaveErPtr feature 858 */ 859 if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR))) 860 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK); 861 862 cpu_detect_cache_sizes(c); 863 864 /* Multi core CPU? */ 865 if (c->extended_cpuid_level >= 0x80000008) { 866 amd_detect_cmp(c); 867 srat_detect_node(c); 868 } 869 870 #ifdef CONFIG_X86_32 871 detect_ht(c); 872 #endif 873 874 init_amd_cacheinfo(c); 875 876 if (c->x86 >= 0xf) 877 set_cpu_cap(c, X86_FEATURE_K8); 878 879 if (cpu_has(c, X86_FEATURE_XMM2)) { 880 unsigned long long val; 881 int ret; 882 883 /* 884 * A serializing LFENCE has less overhead than MFENCE, so 885 * use it for execution serialization. On families which 886 * don't have that MSR, LFENCE is already serializing. 887 * msr_set_bit() uses the safe accessors, too, even if the MSR 888 * is not present. 889 */ 890 msr_set_bit(MSR_F10H_DECFG, 891 MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT); 892 893 /* 894 * Verify that the MSR write was successful (could be running 895 * under a hypervisor) and only then assume that LFENCE is 896 * serializing. 897 */ 898 ret = rdmsrl_safe(MSR_F10H_DECFG, &val); 899 if (!ret && (val & MSR_F10H_DECFG_LFENCE_SERIALIZE)) { 900 /* A serializing LFENCE stops RDTSC speculation */ 901 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 902 } else { 903 /* MFENCE stops RDTSC speculation */ 904 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); 905 } 906 } 907 908 /* 909 * Family 0x12 and above processors have APIC timer 910 * running in deep C states. 911 */ 912 if (c->x86 > 0x11) 913 set_cpu_cap(c, X86_FEATURE_ARAT); 914 915 /* 3DNow or LM implies PREFETCHW */ 916 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH)) 917 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM)) 918 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH); 919 920 /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */ 921 if (!cpu_has(c, X86_FEATURE_XENPV)) 922 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); 923 } 924 925 #ifdef CONFIG_X86_32 926 static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size) 927 { 928 /* AMD errata T13 (order #21922) */ 929 if ((c->x86 == 6)) { 930 /* Duron Rev A0 */ 931 if (c->x86_model == 3 && c->x86_stepping == 0) 932 size = 64; 933 /* Tbird rev A1/A2 */ 934 if (c->x86_model == 4 && 935 (c->x86_stepping == 0 || c->x86_stepping == 1)) 936 size = 256; 937 } 938 return size; 939 } 940 #endif 941 942 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) 943 { 944 u32 ebx, eax, ecx, edx; 945 u16 mask = 0xfff; 946 947 if (c->x86 < 0xf) 948 return; 949 950 if (c->extended_cpuid_level < 0x80000006) 951 return; 952 953 cpuid(0x80000006, &eax, &ebx, &ecx, &edx); 954 955 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask; 956 tlb_lli_4k[ENTRIES] = ebx & mask; 957 958 /* 959 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB 960 * characteristics from the CPUID function 0x80000005 instead. 961 */ 962 if (c->x86 == 0xf) { 963 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 964 mask = 0xff; 965 } 966 967 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 968 if (!((eax >> 16) & mask)) 969 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff; 970 else 971 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask; 972 973 /* a 4M entry uses two 2M entries */ 974 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1; 975 976 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 977 if (!(eax & mask)) { 978 /* Erratum 658 */ 979 if (c->x86 == 0x15 && c->x86_model <= 0x1f) { 980 tlb_lli_2m[ENTRIES] = 1024; 981 } else { 982 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 983 tlb_lli_2m[ENTRIES] = eax & 0xff; 984 } 985 } else 986 tlb_lli_2m[ENTRIES] = eax & mask; 987 988 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1; 989 } 990 991 static const struct cpu_dev amd_cpu_dev = { 992 .c_vendor = "AMD", 993 .c_ident = { "AuthenticAMD" }, 994 #ifdef CONFIG_X86_32 995 .legacy_models = { 996 { .family = 4, .model_names = 997 { 998 [3] = "486 DX/2", 999 [7] = "486 DX/2-WB", 1000 [8] = "486 DX/4", 1001 [9] = "486 DX/4-WB", 1002 [14] = "Am5x86-WT", 1003 [15] = "Am5x86-WB" 1004 } 1005 }, 1006 }, 1007 .legacy_cache_size = amd_size_cache, 1008 #endif 1009 .c_early_init = early_init_amd, 1010 .c_detect_tlb = cpu_detect_tlb_amd, 1011 .c_bsp_init = bsp_init_amd, 1012 .c_init = init_amd, 1013 .c_x86_vendor = X86_VENDOR_AMD, 1014 }; 1015 1016 cpu_dev_register(amd_cpu_dev); 1017 1018 /* 1019 * AMD errata checking 1020 * 1021 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or 1022 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that 1023 * have an OSVW id assigned, which it takes as first argument. Both take a 1024 * variable number of family-specific model-stepping ranges created by 1025 * AMD_MODEL_RANGE(). 1026 * 1027 * Example: 1028 * 1029 * const int amd_erratum_319[] = 1030 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), 1031 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), 1032 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); 1033 */ 1034 1035 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 } 1036 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 } 1037 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \ 1038 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end)) 1039 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff) 1040 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff) 1041 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff) 1042 1043 static const int amd_erratum_400[] = 1044 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), 1045 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); 1046 1047 static const int amd_erratum_383[] = 1048 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); 1049 1050 1051 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum) 1052 { 1053 int osvw_id = *erratum++; 1054 u32 range; 1055 u32 ms; 1056 1057 if (osvw_id >= 0 && osvw_id < 65536 && 1058 cpu_has(cpu, X86_FEATURE_OSVW)) { 1059 u64 osvw_len; 1060 1061 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); 1062 if (osvw_id < osvw_len) { 1063 u64 osvw_bits; 1064 1065 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), 1066 osvw_bits); 1067 return osvw_bits & (1ULL << (osvw_id & 0x3f)); 1068 } 1069 } 1070 1071 /* OSVW unavailable or ID unknown, match family-model-stepping range */ 1072 ms = (cpu->x86_model << 4) | cpu->x86_stepping; 1073 while ((range = *erratum++)) 1074 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) && 1075 (ms >= AMD_MODEL_RANGE_START(range)) && 1076 (ms <= AMD_MODEL_RANGE_END(range))) 1077 return true; 1078 1079 return false; 1080 } 1081 1082 void set_dr_addr_mask(unsigned long mask, int dr) 1083 { 1084 if (!boot_cpu_has(X86_FEATURE_BPEXT)) 1085 return; 1086 1087 switch (dr) { 1088 case 0: 1089 wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0); 1090 break; 1091 case 1: 1092 case 2: 1093 case 3: 1094 wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0); 1095 break; 1096 default: 1097 break; 1098 } 1099 } 1100