1 // SPDX-License-Identifier: GPL-2.0-only 2 #include <linux/export.h> 3 #include <linux/bitops.h> 4 #include <linux/elf.h> 5 #include <linux/mm.h> 6 7 #include <linux/io.h> 8 #include <linux/sched.h> 9 #include <linux/sched/clock.h> 10 #include <linux/random.h> 11 #include <linux/topology.h> 12 #include <asm/processor.h> 13 #include <asm/apic.h> 14 #include <asm/cacheinfo.h> 15 #include <asm/cpu.h> 16 #include <asm/spec-ctrl.h> 17 #include <asm/smp.h> 18 #include <asm/pci-direct.h> 19 #include <asm/delay.h> 20 #include <asm/debugreg.h> 21 22 #ifdef CONFIG_X86_64 23 # include <asm/mmconfig.h> 24 # include <asm/set_memory.h> 25 #endif 26 27 #include "cpu.h" 28 29 static const int amd_erratum_383[]; 30 static const int amd_erratum_400[]; 31 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum); 32 33 /* 34 * nodes_per_socket: Stores the number of nodes per socket. 35 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX 36 * Node Identifiers[10:8] 37 */ 38 static u32 nodes_per_socket = 1; 39 40 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) 41 { 42 u32 gprs[8] = { 0 }; 43 int err; 44 45 WARN_ONCE((boot_cpu_data.x86 != 0xf), 46 "%s should only be used on K8!\n", __func__); 47 48 gprs[1] = msr; 49 gprs[7] = 0x9c5a203a; 50 51 err = rdmsr_safe_regs(gprs); 52 53 *p = gprs[0] | ((u64)gprs[2] << 32); 54 55 return err; 56 } 57 58 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val) 59 { 60 u32 gprs[8] = { 0 }; 61 62 WARN_ONCE((boot_cpu_data.x86 != 0xf), 63 "%s should only be used on K8!\n", __func__); 64 65 gprs[0] = (u32)val; 66 gprs[1] = msr; 67 gprs[2] = val >> 32; 68 gprs[7] = 0x9c5a203a; 69 70 return wrmsr_safe_regs(gprs); 71 } 72 73 /* 74 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause 75 * misexecution of code under Linux. Owners of such processors should 76 * contact AMD for precise details and a CPU swap. 77 * 78 * See http://www.multimania.com/poulot/k6bug.html 79 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6" 80 * (Publication # 21266 Issue Date: August 1998) 81 * 82 * The following test is erm.. interesting. AMD neglected to up 83 * the chip setting when fixing the bug but they also tweaked some 84 * performance at the same time.. 85 */ 86 87 #ifdef CONFIG_X86_32 88 extern __visible void vide(void); 89 __asm__(".text\n" 90 ".globl vide\n" 91 ".type vide, @function\n" 92 ".align 4\n" 93 "vide: ret\n"); 94 #endif 95 96 static void init_amd_k5(struct cpuinfo_x86 *c) 97 { 98 #ifdef CONFIG_X86_32 99 /* 100 * General Systems BIOSen alias the cpu frequency registers 101 * of the Elan at 0x000df000. Unfortunately, one of the Linux 102 * drivers subsequently pokes it, and changes the CPU speed. 103 * Workaround : Remove the unneeded alias. 104 */ 105 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ 106 #define CBAR_ENB (0x80000000) 107 #define CBAR_KEY (0X000000CB) 108 if (c->x86_model == 9 || c->x86_model == 10) { 109 if (inl(CBAR) & CBAR_ENB) 110 outl(0 | CBAR_KEY, CBAR); 111 } 112 #endif 113 } 114 115 static void init_amd_k6(struct cpuinfo_x86 *c) 116 { 117 #ifdef CONFIG_X86_32 118 u32 l, h; 119 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT); 120 121 if (c->x86_model < 6) { 122 /* Based on AMD doc 20734R - June 2000 */ 123 if (c->x86_model == 0) { 124 clear_cpu_cap(c, X86_FEATURE_APIC); 125 set_cpu_cap(c, X86_FEATURE_PGE); 126 } 127 return; 128 } 129 130 if (c->x86_model == 6 && c->x86_stepping == 1) { 131 const int K6_BUG_LOOP = 1000000; 132 int n; 133 void (*f_vide)(void); 134 u64 d, d2; 135 136 pr_info("AMD K6 stepping B detected - "); 137 138 /* 139 * It looks like AMD fixed the 2.6.2 bug and improved indirect 140 * calls at the same time. 141 */ 142 143 n = K6_BUG_LOOP; 144 f_vide = vide; 145 OPTIMIZER_HIDE_VAR(f_vide); 146 d = rdtsc(); 147 while (n--) 148 f_vide(); 149 d2 = rdtsc(); 150 d = d2-d; 151 152 if (d > 20*K6_BUG_LOOP) 153 pr_cont("system stability may be impaired when more than 32 MB are used.\n"); 154 else 155 pr_cont("probably OK (after B9730xxxx).\n"); 156 } 157 158 /* K6 with old style WHCR */ 159 if (c->x86_model < 8 || 160 (c->x86_model == 8 && c->x86_stepping < 8)) { 161 /* We can only write allocate on the low 508Mb */ 162 if (mbytes > 508) 163 mbytes = 508; 164 165 rdmsr(MSR_K6_WHCR, l, h); 166 if ((l&0x0000FFFF) == 0) { 167 unsigned long flags; 168 l = (1<<0)|((mbytes/4)<<1); 169 local_irq_save(flags); 170 wbinvd(); 171 wrmsr(MSR_K6_WHCR, l, h); 172 local_irq_restore(flags); 173 pr_info("Enabling old style K6 write allocation for %d Mb\n", 174 mbytes); 175 } 176 return; 177 } 178 179 if ((c->x86_model == 8 && c->x86_stepping > 7) || 180 c->x86_model == 9 || c->x86_model == 13) { 181 /* The more serious chips .. */ 182 183 if (mbytes > 4092) 184 mbytes = 4092; 185 186 rdmsr(MSR_K6_WHCR, l, h); 187 if ((l&0xFFFF0000) == 0) { 188 unsigned long flags; 189 l = ((mbytes>>2)<<22)|(1<<16); 190 local_irq_save(flags); 191 wbinvd(); 192 wrmsr(MSR_K6_WHCR, l, h); 193 local_irq_restore(flags); 194 pr_info("Enabling new style K6 write allocation for %d Mb\n", 195 mbytes); 196 } 197 198 return; 199 } 200 201 if (c->x86_model == 10) { 202 /* AMD Geode LX is model 10 */ 203 /* placeholder for any needed mods */ 204 return; 205 } 206 #endif 207 } 208 209 static void init_amd_k7(struct cpuinfo_x86 *c) 210 { 211 #ifdef CONFIG_X86_32 212 u32 l, h; 213 214 /* 215 * Bit 15 of Athlon specific MSR 15, needs to be 0 216 * to enable SSE on Palomino/Morgan/Barton CPU's. 217 * If the BIOS didn't enable it already, enable it here. 218 */ 219 if (c->x86_model >= 6 && c->x86_model <= 10) { 220 if (!cpu_has(c, X86_FEATURE_XMM)) { 221 pr_info("Enabling disabled K7/SSE Support.\n"); 222 msr_clear_bit(MSR_K7_HWCR, 15); 223 set_cpu_cap(c, X86_FEATURE_XMM); 224 } 225 } 226 227 /* 228 * It's been determined by AMD that Athlons since model 8 stepping 1 229 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx 230 * As per AMD technical note 27212 0.2 231 */ 232 if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) { 233 rdmsr(MSR_K7_CLK_CTL, l, h); 234 if ((l & 0xfff00000) != 0x20000000) { 235 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", 236 l, ((l & 0x000fffff)|0x20000000)); 237 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); 238 } 239 } 240 241 /* calling is from identify_secondary_cpu() ? */ 242 if (!c->cpu_index) 243 return; 244 245 /* 246 * Certain Athlons might work (for various values of 'work') in SMP 247 * but they are not certified as MP capable. 248 */ 249 /* Athlon 660/661 is valid. */ 250 if ((c->x86_model == 6) && ((c->x86_stepping == 0) || 251 (c->x86_stepping == 1))) 252 return; 253 254 /* Duron 670 is valid */ 255 if ((c->x86_model == 7) && (c->x86_stepping == 0)) 256 return; 257 258 /* 259 * Athlon 662, Duron 671, and Athlon >model 7 have capability 260 * bit. It's worth noting that the A5 stepping (662) of some 261 * Athlon XP's have the MP bit set. 262 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for 263 * more. 264 */ 265 if (((c->x86_model == 6) && (c->x86_stepping >= 2)) || 266 ((c->x86_model == 7) && (c->x86_stepping >= 1)) || 267 (c->x86_model > 7)) 268 if (cpu_has(c, X86_FEATURE_MP)) 269 return; 270 271 /* If we get here, not a certified SMP capable AMD system. */ 272 273 /* 274 * Don't taint if we are running SMP kernel on a single non-MP 275 * approved Athlon 276 */ 277 WARN_ONCE(1, "WARNING: This combination of AMD" 278 " processors is not suitable for SMP.\n"); 279 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); 280 #endif 281 } 282 283 #ifdef CONFIG_NUMA 284 /* 285 * To workaround broken NUMA config. Read the comment in 286 * srat_detect_node(). 287 */ 288 static int nearby_node(int apicid) 289 { 290 int i, node; 291 292 for (i = apicid - 1; i >= 0; i--) { 293 node = __apicid_to_node[i]; 294 if (node != NUMA_NO_NODE && node_online(node)) 295 return node; 296 } 297 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { 298 node = __apicid_to_node[i]; 299 if (node != NUMA_NO_NODE && node_online(node)) 300 return node; 301 } 302 return first_node(node_online_map); /* Shouldn't happen */ 303 } 304 #endif 305 306 /* 307 * Fix up cpu_core_id for pre-F17h systems to be in the 308 * [0 .. cores_per_node - 1] range. Not really needed but 309 * kept so as not to break existing setups. 310 */ 311 static void legacy_fixup_core_id(struct cpuinfo_x86 *c) 312 { 313 u32 cus_per_node; 314 315 if (c->x86 >= 0x17) 316 return; 317 318 cus_per_node = c->x86_max_cores / nodes_per_socket; 319 c->cpu_core_id %= cus_per_node; 320 } 321 322 /* 323 * Fixup core topology information for 324 * (1) AMD multi-node processors 325 * Assumption: Number of cores in each internal node is the same. 326 * (2) AMD processors supporting compute units 327 */ 328 static void amd_get_topology(struct cpuinfo_x86 *c) 329 { 330 u8 node_id; 331 int cpu = smp_processor_id(); 332 333 /* get information required for multi-node processors */ 334 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 335 int err; 336 u32 eax, ebx, ecx, edx; 337 338 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); 339 340 node_id = ecx & 0xff; 341 342 if (c->x86 == 0x15) 343 c->cu_id = ebx & 0xff; 344 345 if (c->x86 >= 0x17) { 346 c->cpu_core_id = ebx & 0xff; 347 348 if (smp_num_siblings > 1) 349 c->x86_max_cores /= smp_num_siblings; 350 } 351 352 /* 353 * In case leaf B is available, use it to derive 354 * topology information. 355 */ 356 err = detect_extended_topology(c); 357 if (!err) 358 c->x86_coreid_bits = get_count_order(c->x86_max_cores); 359 360 cacheinfo_amd_init_llc_id(c, cpu, node_id); 361 362 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { 363 u64 value; 364 365 rdmsrl(MSR_FAM10H_NODE_ID, value); 366 node_id = value & 7; 367 368 per_cpu(cpu_llc_id, cpu) = node_id; 369 } else 370 return; 371 372 if (nodes_per_socket > 1) { 373 set_cpu_cap(c, X86_FEATURE_AMD_DCM); 374 legacy_fixup_core_id(c); 375 } 376 } 377 378 /* 379 * On a AMD dual core setup the lower bits of the APIC id distinguish the cores. 380 * Assumes number of cores is a power of two. 381 */ 382 static void amd_detect_cmp(struct cpuinfo_x86 *c) 383 { 384 unsigned bits; 385 int cpu = smp_processor_id(); 386 387 bits = c->x86_coreid_bits; 388 /* Low order bits define the core id (index of core in socket) */ 389 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1); 390 /* Convert the initial APIC ID into the socket ID */ 391 c->phys_proc_id = c->initial_apicid >> bits; 392 /* use socket ID also for last level cache */ 393 per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; 394 } 395 396 u16 amd_get_nb_id(int cpu) 397 { 398 return per_cpu(cpu_llc_id, cpu); 399 } 400 EXPORT_SYMBOL_GPL(amd_get_nb_id); 401 402 u32 amd_get_nodes_per_socket(void) 403 { 404 return nodes_per_socket; 405 } 406 EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket); 407 408 static void srat_detect_node(struct cpuinfo_x86 *c) 409 { 410 #ifdef CONFIG_NUMA 411 int cpu = smp_processor_id(); 412 int node; 413 unsigned apicid = c->apicid; 414 415 node = numa_cpu_node(cpu); 416 if (node == NUMA_NO_NODE) 417 node = per_cpu(cpu_llc_id, cpu); 418 419 /* 420 * On multi-fabric platform (e.g. Numascale NumaChip) a 421 * platform-specific handler needs to be called to fixup some 422 * IDs of the CPU. 423 */ 424 if (x86_cpuinit.fixup_cpu_id) 425 x86_cpuinit.fixup_cpu_id(c, node); 426 427 if (!node_online(node)) { 428 /* 429 * Two possibilities here: 430 * 431 * - The CPU is missing memory and no node was created. In 432 * that case try picking one from a nearby CPU. 433 * 434 * - The APIC IDs differ from the HyperTransport node IDs 435 * which the K8 northbridge parsing fills in. Assume 436 * they are all increased by a constant offset, but in 437 * the same order as the HT nodeids. If that doesn't 438 * result in a usable node fall back to the path for the 439 * previous case. 440 * 441 * This workaround operates directly on the mapping between 442 * APIC ID and NUMA node, assuming certain relationship 443 * between APIC ID, HT node ID and NUMA topology. As going 444 * through CPU mapping may alter the outcome, directly 445 * access __apicid_to_node[]. 446 */ 447 int ht_nodeid = c->initial_apicid; 448 449 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE) 450 node = __apicid_to_node[ht_nodeid]; 451 /* Pick a nearby node */ 452 if (!node_online(node)) 453 node = nearby_node(apicid); 454 } 455 numa_set_node(cpu, node); 456 #endif 457 } 458 459 static void early_init_amd_mc(struct cpuinfo_x86 *c) 460 { 461 #ifdef CONFIG_SMP 462 unsigned bits, ecx; 463 464 /* Multi core CPU? */ 465 if (c->extended_cpuid_level < 0x80000008) 466 return; 467 468 ecx = cpuid_ecx(0x80000008); 469 470 c->x86_max_cores = (ecx & 0xff) + 1; 471 472 /* CPU telling us the core id bits shift? */ 473 bits = (ecx >> 12) & 0xF; 474 475 /* Otherwise recompute */ 476 if (bits == 0) { 477 while ((1 << bits) < c->x86_max_cores) 478 bits++; 479 } 480 481 c->x86_coreid_bits = bits; 482 #endif 483 } 484 485 static void bsp_init_amd(struct cpuinfo_x86 *c) 486 { 487 488 #ifdef CONFIG_X86_64 489 if (c->x86 >= 0xf) { 490 unsigned long long tseg; 491 492 /* 493 * Split up direct mapping around the TSEG SMM area. 494 * Don't do it for gbpages because there seems very little 495 * benefit in doing so. 496 */ 497 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) { 498 unsigned long pfn = tseg >> PAGE_SHIFT; 499 500 pr_debug("tseg: %010llx\n", tseg); 501 if (pfn_range_is_mapped(pfn, pfn + 1)) 502 set_memory_4k((unsigned long)__va(tseg), 1); 503 } 504 } 505 #endif 506 507 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { 508 509 if (c->x86 > 0x10 || 510 (c->x86 == 0x10 && c->x86_model >= 0x2)) { 511 u64 val; 512 513 rdmsrl(MSR_K7_HWCR, val); 514 if (!(val & BIT(24))) 515 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n"); 516 } 517 } 518 519 if (c->x86 == 0x15) { 520 unsigned long upperbit; 521 u32 cpuid, assoc; 522 523 cpuid = cpuid_edx(0x80000005); 524 assoc = cpuid >> 16 & 0xff; 525 upperbit = ((cpuid >> 24) << 10) / assoc; 526 527 va_align.mask = (upperbit - 1) & PAGE_MASK; 528 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64; 529 530 /* A random value per boot for bit slice [12:upper_bit) */ 531 va_align.bits = get_random_int() & va_align.mask; 532 } 533 534 if (cpu_has(c, X86_FEATURE_MWAITX)) 535 use_mwaitx_delay(); 536 537 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 538 u32 ecx; 539 540 ecx = cpuid_ecx(0x8000001e); 541 nodes_per_socket = ((ecx >> 8) & 7) + 1; 542 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) { 543 u64 value; 544 545 rdmsrl(MSR_FAM10H_NODE_ID, value); 546 nodes_per_socket = ((value >> 3) & 7) + 1; 547 } 548 549 if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) && 550 !boot_cpu_has(X86_FEATURE_VIRT_SSBD) && 551 c->x86 >= 0x15 && c->x86 <= 0x17) { 552 unsigned int bit; 553 554 switch (c->x86) { 555 case 0x15: bit = 54; break; 556 case 0x16: bit = 33; break; 557 case 0x17: bit = 10; break; 558 default: return; 559 } 560 /* 561 * Try to cache the base value so further operations can 562 * avoid RMW. If that faults, do not enable SSBD. 563 */ 564 if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) { 565 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD); 566 setup_force_cpu_cap(X86_FEATURE_SSBD); 567 x86_amd_ls_cfg_ssbd_mask = 1ULL << bit; 568 } 569 } 570 } 571 572 static void early_detect_mem_encrypt(struct cpuinfo_x86 *c) 573 { 574 u64 msr; 575 576 /* 577 * BIOS support is required for SME and SEV. 578 * For SME: If BIOS has enabled SME then adjust x86_phys_bits by 579 * the SME physical address space reduction value. 580 * If BIOS has not enabled SME then don't advertise the 581 * SME feature (set in scattered.c). 582 * For SEV: If BIOS has not enabled SEV then don't advertise the 583 * SEV feature (set in scattered.c). 584 * 585 * In all cases, since support for SME and SEV requires long mode, 586 * don't advertise the feature under CONFIG_X86_32. 587 */ 588 if (cpu_has(c, X86_FEATURE_SME) || cpu_has(c, X86_FEATURE_SEV)) { 589 /* Check if memory encryption is enabled */ 590 rdmsrl(MSR_K8_SYSCFG, msr); 591 if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT)) 592 goto clear_all; 593 594 /* 595 * Always adjust physical address bits. Even though this 596 * will be a value above 32-bits this is still done for 597 * CONFIG_X86_32 so that accurate values are reported. 598 */ 599 c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f; 600 601 if (IS_ENABLED(CONFIG_X86_32)) 602 goto clear_all; 603 604 rdmsrl(MSR_K7_HWCR, msr); 605 if (!(msr & MSR_K7_HWCR_SMMLOCK)) 606 goto clear_sev; 607 608 return; 609 610 clear_all: 611 setup_clear_cpu_cap(X86_FEATURE_SME); 612 clear_sev: 613 setup_clear_cpu_cap(X86_FEATURE_SEV); 614 } 615 } 616 617 static void early_init_amd(struct cpuinfo_x86 *c) 618 { 619 u64 value; 620 u32 dummy; 621 622 early_init_amd_mc(c); 623 624 #ifdef CONFIG_X86_32 625 if (c->x86 == 6) 626 set_cpu_cap(c, X86_FEATURE_K7); 627 #endif 628 629 if (c->x86 >= 0xf) 630 set_cpu_cap(c, X86_FEATURE_K8); 631 632 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); 633 634 /* 635 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 636 * with P/T states and does not stop in deep C-states 637 */ 638 if (c->x86_power & (1 << 8)) { 639 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 640 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 641 } 642 643 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */ 644 if (c->x86_power & BIT(12)) 645 set_cpu_cap(c, X86_FEATURE_ACC_POWER); 646 647 #ifdef CONFIG_X86_64 648 set_cpu_cap(c, X86_FEATURE_SYSCALL32); 649 #else 650 /* Set MTRR capability flag if appropriate */ 651 if (c->x86 == 5) 652 if (c->x86_model == 13 || c->x86_model == 9 || 653 (c->x86_model == 8 && c->x86_stepping >= 8)) 654 set_cpu_cap(c, X86_FEATURE_K6_MTRR); 655 #endif 656 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) 657 /* 658 * ApicID can always be treated as an 8-bit value for AMD APIC versions 659 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we 660 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families 661 * after 16h. 662 */ 663 if (boot_cpu_has(X86_FEATURE_APIC)) { 664 if (c->x86 > 0x16) 665 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 666 else if (c->x86 >= 0xf) { 667 /* check CPU config space for extended APIC ID */ 668 unsigned int val; 669 670 val = read_pci_config(0, 24, 0, 0x68); 671 if ((val >> 17 & 0x3) == 0x3) 672 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 673 } 674 } 675 #endif 676 677 /* 678 * This is only needed to tell the kernel whether to use VMCALL 679 * and VMMCALL. VMMCALL is never executed except under virt, so 680 * we can set it unconditionally. 681 */ 682 set_cpu_cap(c, X86_FEATURE_VMMCALL); 683 684 /* F16h erratum 793, CVE-2013-6885 */ 685 if (c->x86 == 0x16 && c->x86_model <= 0xf) 686 msr_set_bit(MSR_AMD64_LS_CFG, 15); 687 688 /* 689 * Check whether the machine is affected by erratum 400. This is 690 * used to select the proper idle routine and to enable the check 691 * whether the machine is affected in arch_post_acpi_init(), which 692 * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check. 693 */ 694 if (cpu_has_amd_erratum(c, amd_erratum_400)) 695 set_cpu_bug(c, X86_BUG_AMD_E400); 696 697 early_detect_mem_encrypt(c); 698 699 /* Re-enable TopologyExtensions if switched off by BIOS */ 700 if (c->x86 == 0x15 && 701 (c->x86_model >= 0x10 && c->x86_model <= 0x6f) && 702 !cpu_has(c, X86_FEATURE_TOPOEXT)) { 703 704 if (msr_set_bit(0xc0011005, 54) > 0) { 705 rdmsrl(0xc0011005, value); 706 if (value & BIT_64(54)) { 707 set_cpu_cap(c, X86_FEATURE_TOPOEXT); 708 pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n"); 709 } 710 } 711 } 712 713 if (cpu_has(c, X86_FEATURE_TOPOEXT)) 714 smp_num_siblings = ((cpuid_ebx(0x8000001e) >> 8) & 0xff) + 1; 715 } 716 717 static void init_amd_k8(struct cpuinfo_x86 *c) 718 { 719 u32 level; 720 u64 value; 721 722 /* On C+ stepping K8 rep microcode works well for copy/memset */ 723 level = cpuid_eax(1); 724 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) 725 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 726 727 /* 728 * Some BIOSes incorrectly force this feature, but only K8 revision D 729 * (model = 0x14) and later actually support it. 730 * (AMD Erratum #110, docId: 25759). 731 */ 732 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) { 733 clear_cpu_cap(c, X86_FEATURE_LAHF_LM); 734 if (!rdmsrl_amd_safe(0xc001100d, &value)) { 735 value &= ~BIT_64(32); 736 wrmsrl_amd_safe(0xc001100d, value); 737 } 738 } 739 740 if (!c->x86_model_id[0]) 741 strcpy(c->x86_model_id, "Hammer"); 742 743 #ifdef CONFIG_SMP 744 /* 745 * Disable TLB flush filter by setting HWCR.FFDIS on K8 746 * bit 6 of msr C001_0015 747 * 748 * Errata 63 for SH-B3 steppings 749 * Errata 122 for all steppings (F+ have it disabled by default) 750 */ 751 msr_set_bit(MSR_K7_HWCR, 6); 752 #endif 753 set_cpu_bug(c, X86_BUG_SWAPGS_FENCE); 754 } 755 756 static void init_amd_gh(struct cpuinfo_x86 *c) 757 { 758 #ifdef CONFIG_MMCONF_FAM10H 759 /* do this for boot cpu */ 760 if (c == &boot_cpu_data) 761 check_enable_amd_mmconf_dmi(); 762 763 fam10h_check_enable_mmcfg(); 764 #endif 765 766 /* 767 * Disable GART TLB Walk Errors on Fam10h. We do this here because this 768 * is always needed when GART is enabled, even in a kernel which has no 769 * MCE support built in. BIOS should disable GartTlbWlk Errors already. 770 * If it doesn't, we do it here as suggested by the BKDG. 771 * 772 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012 773 */ 774 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10); 775 776 /* 777 * On family 10h BIOS may not have properly enabled WC+ support, causing 778 * it to be converted to CD memtype. This may result in performance 779 * degradation for certain nested-paging guests. Prevent this conversion 780 * by clearing bit 24 in MSR_AMD64_BU_CFG2. 781 * 782 * NOTE: we want to use the _safe accessors so as not to #GP kvm 783 * guests on older kvm hosts. 784 */ 785 msr_clear_bit(MSR_AMD64_BU_CFG2, 24); 786 787 if (cpu_has_amd_erratum(c, amd_erratum_383)) 788 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH); 789 } 790 791 #define MSR_AMD64_DE_CFG 0xC0011029 792 793 static void init_amd_ln(struct cpuinfo_x86 *c) 794 { 795 /* 796 * Apply erratum 665 fix unconditionally so machines without a BIOS 797 * fix work. 798 */ 799 msr_set_bit(MSR_AMD64_DE_CFG, 31); 800 } 801 802 static bool rdrand_force; 803 804 static int __init rdrand_cmdline(char *str) 805 { 806 if (!str) 807 return -EINVAL; 808 809 if (!strcmp(str, "force")) 810 rdrand_force = true; 811 else 812 return -EINVAL; 813 814 return 0; 815 } 816 early_param("rdrand", rdrand_cmdline); 817 818 static void clear_rdrand_cpuid_bit(struct cpuinfo_x86 *c) 819 { 820 /* 821 * Saving of the MSR used to hide the RDRAND support during 822 * suspend/resume is done by arch/x86/power/cpu.c, which is 823 * dependent on CONFIG_PM_SLEEP. 824 */ 825 if (!IS_ENABLED(CONFIG_PM_SLEEP)) 826 return; 827 828 /* 829 * The nordrand option can clear X86_FEATURE_RDRAND, so check for 830 * RDRAND support using the CPUID function directly. 831 */ 832 if (!(cpuid_ecx(1) & BIT(30)) || rdrand_force) 833 return; 834 835 msr_clear_bit(MSR_AMD64_CPUID_FN_1, 62); 836 837 /* 838 * Verify that the CPUID change has occurred in case the kernel is 839 * running virtualized and the hypervisor doesn't support the MSR. 840 */ 841 if (cpuid_ecx(1) & BIT(30)) { 842 pr_info_once("BIOS may not properly restore RDRAND after suspend, but hypervisor does not support hiding RDRAND via CPUID.\n"); 843 return; 844 } 845 846 clear_cpu_cap(c, X86_FEATURE_RDRAND); 847 pr_info_once("BIOS may not properly restore RDRAND after suspend, hiding RDRAND via CPUID. Use rdrand=force to reenable.\n"); 848 } 849 850 static void init_amd_jg(struct cpuinfo_x86 *c) 851 { 852 /* 853 * Some BIOS implementations do not restore proper RDRAND support 854 * across suspend and resume. Check on whether to hide the RDRAND 855 * instruction support via CPUID. 856 */ 857 clear_rdrand_cpuid_bit(c); 858 } 859 860 static void init_amd_bd(struct cpuinfo_x86 *c) 861 { 862 u64 value; 863 864 /* 865 * The way access filter has a performance penalty on some workloads. 866 * Disable it on the affected CPUs. 867 */ 868 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) { 869 if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) { 870 value |= 0x1E; 871 wrmsrl_safe(MSR_F15H_IC_CFG, value); 872 } 873 } 874 875 /* 876 * Some BIOS implementations do not restore proper RDRAND support 877 * across suspend and resume. Check on whether to hide the RDRAND 878 * instruction support via CPUID. 879 */ 880 clear_rdrand_cpuid_bit(c); 881 } 882 883 static void init_amd_zn(struct cpuinfo_x86 *c) 884 { 885 set_cpu_cap(c, X86_FEATURE_ZEN); 886 887 #ifdef CONFIG_NUMA 888 node_reclaim_distance = 32; 889 #endif 890 891 /* 892 * Fix erratum 1076: CPB feature bit not being set in CPUID. 893 * Always set it, except when running under a hypervisor. 894 */ 895 if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && !cpu_has(c, X86_FEATURE_CPB)) 896 set_cpu_cap(c, X86_FEATURE_CPB); 897 } 898 899 static void init_amd(struct cpuinfo_x86 *c) 900 { 901 early_init_amd(c); 902 903 /* 904 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 905 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 906 */ 907 clear_cpu_cap(c, 0*32+31); 908 909 if (c->x86 >= 0x10) 910 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 911 912 /* get apicid instead of initial apic id from cpuid */ 913 c->apicid = hard_smp_processor_id(); 914 915 /* K6s reports MCEs but don't actually have all the MSRs */ 916 if (c->x86 < 6) 917 clear_cpu_cap(c, X86_FEATURE_MCE); 918 919 switch (c->x86) { 920 case 4: init_amd_k5(c); break; 921 case 5: init_amd_k6(c); break; 922 case 6: init_amd_k7(c); break; 923 case 0xf: init_amd_k8(c); break; 924 case 0x10: init_amd_gh(c); break; 925 case 0x12: init_amd_ln(c); break; 926 case 0x15: init_amd_bd(c); break; 927 case 0x16: init_amd_jg(c); break; 928 case 0x17: init_amd_zn(c); break; 929 } 930 931 /* 932 * Enable workaround for FXSAVE leak on CPUs 933 * without a XSaveErPtr feature 934 */ 935 if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR))) 936 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK); 937 938 cpu_detect_cache_sizes(c); 939 940 amd_detect_cmp(c); 941 amd_get_topology(c); 942 srat_detect_node(c); 943 944 init_amd_cacheinfo(c); 945 946 if (cpu_has(c, X86_FEATURE_XMM2)) { 947 /* 948 * Use LFENCE for execution serialization. On families which 949 * don't have that MSR, LFENCE is already serializing. 950 * msr_set_bit() uses the safe accessors, too, even if the MSR 951 * is not present. 952 */ 953 msr_set_bit(MSR_F10H_DECFG, 954 MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT); 955 956 /* A serializing LFENCE stops RDTSC speculation */ 957 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 958 } 959 960 /* 961 * Family 0x12 and above processors have APIC timer 962 * running in deep C states. 963 */ 964 if (c->x86 > 0x11) 965 set_cpu_cap(c, X86_FEATURE_ARAT); 966 967 /* 3DNow or LM implies PREFETCHW */ 968 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH)) 969 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM)) 970 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH); 971 972 /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */ 973 if (!cpu_has(c, X86_FEATURE_XENPV)) 974 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); 975 } 976 977 #ifdef CONFIG_X86_32 978 static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size) 979 { 980 /* AMD errata T13 (order #21922) */ 981 if (c->x86 == 6) { 982 /* Duron Rev A0 */ 983 if (c->x86_model == 3 && c->x86_stepping == 0) 984 size = 64; 985 /* Tbird rev A1/A2 */ 986 if (c->x86_model == 4 && 987 (c->x86_stepping == 0 || c->x86_stepping == 1)) 988 size = 256; 989 } 990 return size; 991 } 992 #endif 993 994 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) 995 { 996 u32 ebx, eax, ecx, edx; 997 u16 mask = 0xfff; 998 999 if (c->x86 < 0xf) 1000 return; 1001 1002 if (c->extended_cpuid_level < 0x80000006) 1003 return; 1004 1005 cpuid(0x80000006, &eax, &ebx, &ecx, &edx); 1006 1007 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask; 1008 tlb_lli_4k[ENTRIES] = ebx & mask; 1009 1010 /* 1011 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB 1012 * characteristics from the CPUID function 0x80000005 instead. 1013 */ 1014 if (c->x86 == 0xf) { 1015 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 1016 mask = 0xff; 1017 } 1018 1019 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 1020 if (!((eax >> 16) & mask)) 1021 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff; 1022 else 1023 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask; 1024 1025 /* a 4M entry uses two 2M entries */ 1026 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1; 1027 1028 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 1029 if (!(eax & mask)) { 1030 /* Erratum 658 */ 1031 if (c->x86 == 0x15 && c->x86_model <= 0x1f) { 1032 tlb_lli_2m[ENTRIES] = 1024; 1033 } else { 1034 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 1035 tlb_lli_2m[ENTRIES] = eax & 0xff; 1036 } 1037 } else 1038 tlb_lli_2m[ENTRIES] = eax & mask; 1039 1040 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1; 1041 } 1042 1043 static const struct cpu_dev amd_cpu_dev = { 1044 .c_vendor = "AMD", 1045 .c_ident = { "AuthenticAMD" }, 1046 #ifdef CONFIG_X86_32 1047 .legacy_models = { 1048 { .family = 4, .model_names = 1049 { 1050 [3] = "486 DX/2", 1051 [7] = "486 DX/2-WB", 1052 [8] = "486 DX/4", 1053 [9] = "486 DX/4-WB", 1054 [14] = "Am5x86-WT", 1055 [15] = "Am5x86-WB" 1056 } 1057 }, 1058 }, 1059 .legacy_cache_size = amd_size_cache, 1060 #endif 1061 .c_early_init = early_init_amd, 1062 .c_detect_tlb = cpu_detect_tlb_amd, 1063 .c_bsp_init = bsp_init_amd, 1064 .c_init = init_amd, 1065 .c_x86_vendor = X86_VENDOR_AMD, 1066 }; 1067 1068 cpu_dev_register(amd_cpu_dev); 1069 1070 /* 1071 * AMD errata checking 1072 * 1073 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or 1074 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that 1075 * have an OSVW id assigned, which it takes as first argument. Both take a 1076 * variable number of family-specific model-stepping ranges created by 1077 * AMD_MODEL_RANGE(). 1078 * 1079 * Example: 1080 * 1081 * const int amd_erratum_319[] = 1082 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), 1083 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), 1084 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); 1085 */ 1086 1087 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 } 1088 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 } 1089 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \ 1090 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end)) 1091 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff) 1092 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff) 1093 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff) 1094 1095 static const int amd_erratum_400[] = 1096 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), 1097 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); 1098 1099 static const int amd_erratum_383[] = 1100 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); 1101 1102 1103 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum) 1104 { 1105 int osvw_id = *erratum++; 1106 u32 range; 1107 u32 ms; 1108 1109 if (osvw_id >= 0 && osvw_id < 65536 && 1110 cpu_has(cpu, X86_FEATURE_OSVW)) { 1111 u64 osvw_len; 1112 1113 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); 1114 if (osvw_id < osvw_len) { 1115 u64 osvw_bits; 1116 1117 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), 1118 osvw_bits); 1119 return osvw_bits & (1ULL << (osvw_id & 0x3f)); 1120 } 1121 } 1122 1123 /* OSVW unavailable or ID unknown, match family-model-stepping range */ 1124 ms = (cpu->x86_model << 4) | cpu->x86_stepping; 1125 while ((range = *erratum++)) 1126 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) && 1127 (ms >= AMD_MODEL_RANGE_START(range)) && 1128 (ms <= AMD_MODEL_RANGE_END(range))) 1129 return true; 1130 1131 return false; 1132 } 1133 1134 void set_dr_addr_mask(unsigned long mask, int dr) 1135 { 1136 if (!boot_cpu_has(X86_FEATURE_BPEXT)) 1137 return; 1138 1139 switch (dr) { 1140 case 0: 1141 wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0); 1142 break; 1143 case 1: 1144 case 2: 1145 case 3: 1146 wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0); 1147 break; 1148 default: 1149 break; 1150 } 1151 } 1152