1 // SPDX-License-Identifier: GPL-2.0-only 2 #include <linux/export.h> 3 #include <linux/bitops.h> 4 #include <linux/elf.h> 5 #include <linux/mm.h> 6 7 #include <linux/io.h> 8 #include <linux/sched.h> 9 #include <linux/sched/clock.h> 10 #include <linux/random.h> 11 #include <linux/topology.h> 12 #include <asm/processor.h> 13 #include <asm/apic.h> 14 #include <asm/cacheinfo.h> 15 #include <asm/cpu.h> 16 #include <asm/spec-ctrl.h> 17 #include <asm/smp.h> 18 #include <asm/pci-direct.h> 19 #include <asm/delay.h> 20 #include <asm/debugreg.h> 21 22 #ifdef CONFIG_X86_64 23 # include <asm/mmconfig.h> 24 # include <asm/set_memory.h> 25 #endif 26 27 #include "cpu.h" 28 29 static const int amd_erratum_383[]; 30 static const int amd_erratum_400[]; 31 static const int amd_erratum_1054[]; 32 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum); 33 34 /* 35 * nodes_per_socket: Stores the number of nodes per socket. 36 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX 37 * Node Identifiers[10:8] 38 */ 39 static u32 nodes_per_socket = 1; 40 41 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) 42 { 43 u32 gprs[8] = { 0 }; 44 int err; 45 46 WARN_ONCE((boot_cpu_data.x86 != 0xf), 47 "%s should only be used on K8!\n", __func__); 48 49 gprs[1] = msr; 50 gprs[7] = 0x9c5a203a; 51 52 err = rdmsr_safe_regs(gprs); 53 54 *p = gprs[0] | ((u64)gprs[2] << 32); 55 56 return err; 57 } 58 59 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val) 60 { 61 u32 gprs[8] = { 0 }; 62 63 WARN_ONCE((boot_cpu_data.x86 != 0xf), 64 "%s should only be used on K8!\n", __func__); 65 66 gprs[0] = (u32)val; 67 gprs[1] = msr; 68 gprs[2] = val >> 32; 69 gprs[7] = 0x9c5a203a; 70 71 return wrmsr_safe_regs(gprs); 72 } 73 74 /* 75 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause 76 * misexecution of code under Linux. Owners of such processors should 77 * contact AMD for precise details and a CPU swap. 78 * 79 * See http://www.multimania.com/poulot/k6bug.html 80 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6" 81 * (Publication # 21266 Issue Date: August 1998) 82 * 83 * The following test is erm.. interesting. AMD neglected to up 84 * the chip setting when fixing the bug but they also tweaked some 85 * performance at the same time.. 86 */ 87 88 #ifdef CONFIG_X86_32 89 extern __visible void vide(void); 90 __asm__(".text\n" 91 ".globl vide\n" 92 ".type vide, @function\n" 93 ".align 4\n" 94 "vide: ret\n"); 95 #endif 96 97 static void init_amd_k5(struct cpuinfo_x86 *c) 98 { 99 #ifdef CONFIG_X86_32 100 /* 101 * General Systems BIOSen alias the cpu frequency registers 102 * of the Elan at 0x000df000. Unfortunately, one of the Linux 103 * drivers subsequently pokes it, and changes the CPU speed. 104 * Workaround : Remove the unneeded alias. 105 */ 106 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ 107 #define CBAR_ENB (0x80000000) 108 #define CBAR_KEY (0X000000CB) 109 if (c->x86_model == 9 || c->x86_model == 10) { 110 if (inl(CBAR) & CBAR_ENB) 111 outl(0 | CBAR_KEY, CBAR); 112 } 113 #endif 114 } 115 116 static void init_amd_k6(struct cpuinfo_x86 *c) 117 { 118 #ifdef CONFIG_X86_32 119 u32 l, h; 120 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT); 121 122 if (c->x86_model < 6) { 123 /* Based on AMD doc 20734R - June 2000 */ 124 if (c->x86_model == 0) { 125 clear_cpu_cap(c, X86_FEATURE_APIC); 126 set_cpu_cap(c, X86_FEATURE_PGE); 127 } 128 return; 129 } 130 131 if (c->x86_model == 6 && c->x86_stepping == 1) { 132 const int K6_BUG_LOOP = 1000000; 133 int n; 134 void (*f_vide)(void); 135 u64 d, d2; 136 137 pr_info("AMD K6 stepping B detected - "); 138 139 /* 140 * It looks like AMD fixed the 2.6.2 bug and improved indirect 141 * calls at the same time. 142 */ 143 144 n = K6_BUG_LOOP; 145 f_vide = vide; 146 OPTIMIZER_HIDE_VAR(f_vide); 147 d = rdtsc(); 148 while (n--) 149 f_vide(); 150 d2 = rdtsc(); 151 d = d2-d; 152 153 if (d > 20*K6_BUG_LOOP) 154 pr_cont("system stability may be impaired when more than 32 MB are used.\n"); 155 else 156 pr_cont("probably OK (after B9730xxxx).\n"); 157 } 158 159 /* K6 with old style WHCR */ 160 if (c->x86_model < 8 || 161 (c->x86_model == 8 && c->x86_stepping < 8)) { 162 /* We can only write allocate on the low 508Mb */ 163 if (mbytes > 508) 164 mbytes = 508; 165 166 rdmsr(MSR_K6_WHCR, l, h); 167 if ((l&0x0000FFFF) == 0) { 168 unsigned long flags; 169 l = (1<<0)|((mbytes/4)<<1); 170 local_irq_save(flags); 171 wbinvd(); 172 wrmsr(MSR_K6_WHCR, l, h); 173 local_irq_restore(flags); 174 pr_info("Enabling old style K6 write allocation for %d Mb\n", 175 mbytes); 176 } 177 return; 178 } 179 180 if ((c->x86_model == 8 && c->x86_stepping > 7) || 181 c->x86_model == 9 || c->x86_model == 13) { 182 /* The more serious chips .. */ 183 184 if (mbytes > 4092) 185 mbytes = 4092; 186 187 rdmsr(MSR_K6_WHCR, l, h); 188 if ((l&0xFFFF0000) == 0) { 189 unsigned long flags; 190 l = ((mbytes>>2)<<22)|(1<<16); 191 local_irq_save(flags); 192 wbinvd(); 193 wrmsr(MSR_K6_WHCR, l, h); 194 local_irq_restore(flags); 195 pr_info("Enabling new style K6 write allocation for %d Mb\n", 196 mbytes); 197 } 198 199 return; 200 } 201 202 if (c->x86_model == 10) { 203 /* AMD Geode LX is model 10 */ 204 /* placeholder for any needed mods */ 205 return; 206 } 207 #endif 208 } 209 210 static void init_amd_k7(struct cpuinfo_x86 *c) 211 { 212 #ifdef CONFIG_X86_32 213 u32 l, h; 214 215 /* 216 * Bit 15 of Athlon specific MSR 15, needs to be 0 217 * to enable SSE on Palomino/Morgan/Barton CPU's. 218 * If the BIOS didn't enable it already, enable it here. 219 */ 220 if (c->x86_model >= 6 && c->x86_model <= 10) { 221 if (!cpu_has(c, X86_FEATURE_XMM)) { 222 pr_info("Enabling disabled K7/SSE Support.\n"); 223 msr_clear_bit(MSR_K7_HWCR, 15); 224 set_cpu_cap(c, X86_FEATURE_XMM); 225 } 226 } 227 228 /* 229 * It's been determined by AMD that Athlons since model 8 stepping 1 230 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx 231 * As per AMD technical note 27212 0.2 232 */ 233 if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) { 234 rdmsr(MSR_K7_CLK_CTL, l, h); 235 if ((l & 0xfff00000) != 0x20000000) { 236 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", 237 l, ((l & 0x000fffff)|0x20000000)); 238 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); 239 } 240 } 241 242 /* calling is from identify_secondary_cpu() ? */ 243 if (!c->cpu_index) 244 return; 245 246 /* 247 * Certain Athlons might work (for various values of 'work') in SMP 248 * but they are not certified as MP capable. 249 */ 250 /* Athlon 660/661 is valid. */ 251 if ((c->x86_model == 6) && ((c->x86_stepping == 0) || 252 (c->x86_stepping == 1))) 253 return; 254 255 /* Duron 670 is valid */ 256 if ((c->x86_model == 7) && (c->x86_stepping == 0)) 257 return; 258 259 /* 260 * Athlon 662, Duron 671, and Athlon >model 7 have capability 261 * bit. It's worth noting that the A5 stepping (662) of some 262 * Athlon XP's have the MP bit set. 263 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for 264 * more. 265 */ 266 if (((c->x86_model == 6) && (c->x86_stepping >= 2)) || 267 ((c->x86_model == 7) && (c->x86_stepping >= 1)) || 268 (c->x86_model > 7)) 269 if (cpu_has(c, X86_FEATURE_MP)) 270 return; 271 272 /* If we get here, not a certified SMP capable AMD system. */ 273 274 /* 275 * Don't taint if we are running SMP kernel on a single non-MP 276 * approved Athlon 277 */ 278 WARN_ONCE(1, "WARNING: This combination of AMD" 279 " processors is not suitable for SMP.\n"); 280 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); 281 #endif 282 } 283 284 #ifdef CONFIG_NUMA 285 /* 286 * To workaround broken NUMA config. Read the comment in 287 * srat_detect_node(). 288 */ 289 static int nearby_node(int apicid) 290 { 291 int i, node; 292 293 for (i = apicid - 1; i >= 0; i--) { 294 node = __apicid_to_node[i]; 295 if (node != NUMA_NO_NODE && node_online(node)) 296 return node; 297 } 298 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { 299 node = __apicid_to_node[i]; 300 if (node != NUMA_NO_NODE && node_online(node)) 301 return node; 302 } 303 return first_node(node_online_map); /* Shouldn't happen */ 304 } 305 #endif 306 307 /* 308 * Fix up cpu_core_id for pre-F17h systems to be in the 309 * [0 .. cores_per_node - 1] range. Not really needed but 310 * kept so as not to break existing setups. 311 */ 312 static void legacy_fixup_core_id(struct cpuinfo_x86 *c) 313 { 314 u32 cus_per_node; 315 316 if (c->x86 >= 0x17) 317 return; 318 319 cus_per_node = c->x86_max_cores / nodes_per_socket; 320 c->cpu_core_id %= cus_per_node; 321 } 322 323 /* 324 * Fixup core topology information for 325 * (1) AMD multi-node processors 326 * Assumption: Number of cores in each internal node is the same. 327 * (2) AMD processors supporting compute units 328 */ 329 static void amd_get_topology(struct cpuinfo_x86 *c) 330 { 331 u8 node_id; 332 int cpu = smp_processor_id(); 333 334 /* get information required for multi-node processors */ 335 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 336 int err; 337 u32 eax, ebx, ecx, edx; 338 339 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); 340 341 node_id = ecx & 0xff; 342 343 if (c->x86 == 0x15) 344 c->cu_id = ebx & 0xff; 345 346 if (c->x86 >= 0x17) { 347 c->cpu_core_id = ebx & 0xff; 348 349 if (smp_num_siblings > 1) 350 c->x86_max_cores /= smp_num_siblings; 351 } 352 353 /* 354 * In case leaf B is available, use it to derive 355 * topology information. 356 */ 357 err = detect_extended_topology(c); 358 if (!err) 359 c->x86_coreid_bits = get_count_order(c->x86_max_cores); 360 361 cacheinfo_amd_init_llc_id(c, cpu, node_id); 362 363 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { 364 u64 value; 365 366 rdmsrl(MSR_FAM10H_NODE_ID, value); 367 node_id = value & 7; 368 369 per_cpu(cpu_llc_id, cpu) = node_id; 370 } else 371 return; 372 373 if (nodes_per_socket > 1) { 374 set_cpu_cap(c, X86_FEATURE_AMD_DCM); 375 legacy_fixup_core_id(c); 376 } 377 } 378 379 /* 380 * On a AMD dual core setup the lower bits of the APIC id distinguish the cores. 381 * Assumes number of cores is a power of two. 382 */ 383 static void amd_detect_cmp(struct cpuinfo_x86 *c) 384 { 385 unsigned bits; 386 int cpu = smp_processor_id(); 387 388 bits = c->x86_coreid_bits; 389 /* Low order bits define the core id (index of core in socket) */ 390 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1); 391 /* Convert the initial APIC ID into the socket ID */ 392 c->phys_proc_id = c->initial_apicid >> bits; 393 /* use socket ID also for last level cache */ 394 per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; 395 } 396 397 u16 amd_get_nb_id(int cpu) 398 { 399 return per_cpu(cpu_llc_id, cpu); 400 } 401 EXPORT_SYMBOL_GPL(amd_get_nb_id); 402 403 u32 amd_get_nodes_per_socket(void) 404 { 405 return nodes_per_socket; 406 } 407 EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket); 408 409 static void srat_detect_node(struct cpuinfo_x86 *c) 410 { 411 #ifdef CONFIG_NUMA 412 int cpu = smp_processor_id(); 413 int node; 414 unsigned apicid = c->apicid; 415 416 node = numa_cpu_node(cpu); 417 if (node == NUMA_NO_NODE) 418 node = per_cpu(cpu_llc_id, cpu); 419 420 /* 421 * On multi-fabric platform (e.g. Numascale NumaChip) a 422 * platform-specific handler needs to be called to fixup some 423 * IDs of the CPU. 424 */ 425 if (x86_cpuinit.fixup_cpu_id) 426 x86_cpuinit.fixup_cpu_id(c, node); 427 428 if (!node_online(node)) { 429 /* 430 * Two possibilities here: 431 * 432 * - The CPU is missing memory and no node was created. In 433 * that case try picking one from a nearby CPU. 434 * 435 * - The APIC IDs differ from the HyperTransport node IDs 436 * which the K8 northbridge parsing fills in. Assume 437 * they are all increased by a constant offset, but in 438 * the same order as the HT nodeids. If that doesn't 439 * result in a usable node fall back to the path for the 440 * previous case. 441 * 442 * This workaround operates directly on the mapping between 443 * APIC ID and NUMA node, assuming certain relationship 444 * between APIC ID, HT node ID and NUMA topology. As going 445 * through CPU mapping may alter the outcome, directly 446 * access __apicid_to_node[]. 447 */ 448 int ht_nodeid = c->initial_apicid; 449 450 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE) 451 node = __apicid_to_node[ht_nodeid]; 452 /* Pick a nearby node */ 453 if (!node_online(node)) 454 node = nearby_node(apicid); 455 } 456 numa_set_node(cpu, node); 457 #endif 458 } 459 460 static void early_init_amd_mc(struct cpuinfo_x86 *c) 461 { 462 #ifdef CONFIG_SMP 463 unsigned bits, ecx; 464 465 /* Multi core CPU? */ 466 if (c->extended_cpuid_level < 0x80000008) 467 return; 468 469 ecx = cpuid_ecx(0x80000008); 470 471 c->x86_max_cores = (ecx & 0xff) + 1; 472 473 /* CPU telling us the core id bits shift? */ 474 bits = (ecx >> 12) & 0xF; 475 476 /* Otherwise recompute */ 477 if (bits == 0) { 478 while ((1 << bits) < c->x86_max_cores) 479 bits++; 480 } 481 482 c->x86_coreid_bits = bits; 483 #endif 484 } 485 486 static void bsp_init_amd(struct cpuinfo_x86 *c) 487 { 488 489 #ifdef CONFIG_X86_64 490 if (c->x86 >= 0xf) { 491 unsigned long long tseg; 492 493 /* 494 * Split up direct mapping around the TSEG SMM area. 495 * Don't do it for gbpages because there seems very little 496 * benefit in doing so. 497 */ 498 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) { 499 unsigned long pfn = tseg >> PAGE_SHIFT; 500 501 pr_debug("tseg: %010llx\n", tseg); 502 if (pfn_range_is_mapped(pfn, pfn + 1)) 503 set_memory_4k((unsigned long)__va(tseg), 1); 504 } 505 } 506 #endif 507 508 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { 509 510 if (c->x86 > 0x10 || 511 (c->x86 == 0x10 && c->x86_model >= 0x2)) { 512 u64 val; 513 514 rdmsrl(MSR_K7_HWCR, val); 515 if (!(val & BIT(24))) 516 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n"); 517 } 518 } 519 520 if (c->x86 == 0x15) { 521 unsigned long upperbit; 522 u32 cpuid, assoc; 523 524 cpuid = cpuid_edx(0x80000005); 525 assoc = cpuid >> 16 & 0xff; 526 upperbit = ((cpuid >> 24) << 10) / assoc; 527 528 va_align.mask = (upperbit - 1) & PAGE_MASK; 529 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64; 530 531 /* A random value per boot for bit slice [12:upper_bit) */ 532 va_align.bits = get_random_int() & va_align.mask; 533 } 534 535 if (cpu_has(c, X86_FEATURE_MWAITX)) 536 use_mwaitx_delay(); 537 538 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 539 u32 ecx; 540 541 ecx = cpuid_ecx(0x8000001e); 542 nodes_per_socket = ((ecx >> 8) & 7) + 1; 543 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) { 544 u64 value; 545 546 rdmsrl(MSR_FAM10H_NODE_ID, value); 547 nodes_per_socket = ((value >> 3) & 7) + 1; 548 } 549 550 if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) && 551 !boot_cpu_has(X86_FEATURE_VIRT_SSBD) && 552 c->x86 >= 0x15 && c->x86 <= 0x17) { 553 unsigned int bit; 554 555 switch (c->x86) { 556 case 0x15: bit = 54; break; 557 case 0x16: bit = 33; break; 558 case 0x17: bit = 10; break; 559 default: return; 560 } 561 /* 562 * Try to cache the base value so further operations can 563 * avoid RMW. If that faults, do not enable SSBD. 564 */ 565 if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) { 566 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD); 567 setup_force_cpu_cap(X86_FEATURE_SSBD); 568 x86_amd_ls_cfg_ssbd_mask = 1ULL << bit; 569 } 570 } 571 } 572 573 static void early_detect_mem_encrypt(struct cpuinfo_x86 *c) 574 { 575 u64 msr; 576 577 /* 578 * BIOS support is required for SME and SEV. 579 * For SME: If BIOS has enabled SME then adjust x86_phys_bits by 580 * the SME physical address space reduction value. 581 * If BIOS has not enabled SME then don't advertise the 582 * SME feature (set in scattered.c). 583 * For SEV: If BIOS has not enabled SEV then don't advertise the 584 * SEV feature (set in scattered.c). 585 * 586 * In all cases, since support for SME and SEV requires long mode, 587 * don't advertise the feature under CONFIG_X86_32. 588 */ 589 if (cpu_has(c, X86_FEATURE_SME) || cpu_has(c, X86_FEATURE_SEV)) { 590 /* Check if memory encryption is enabled */ 591 rdmsrl(MSR_K8_SYSCFG, msr); 592 if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT)) 593 goto clear_all; 594 595 /* 596 * Always adjust physical address bits. Even though this 597 * will be a value above 32-bits this is still done for 598 * CONFIG_X86_32 so that accurate values are reported. 599 */ 600 c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f; 601 602 if (IS_ENABLED(CONFIG_X86_32)) 603 goto clear_all; 604 605 rdmsrl(MSR_K7_HWCR, msr); 606 if (!(msr & MSR_K7_HWCR_SMMLOCK)) 607 goto clear_sev; 608 609 return; 610 611 clear_all: 612 setup_clear_cpu_cap(X86_FEATURE_SME); 613 clear_sev: 614 setup_clear_cpu_cap(X86_FEATURE_SEV); 615 } 616 } 617 618 static void early_init_amd(struct cpuinfo_x86 *c) 619 { 620 u64 value; 621 u32 dummy; 622 623 early_init_amd_mc(c); 624 625 #ifdef CONFIG_X86_32 626 if (c->x86 == 6) 627 set_cpu_cap(c, X86_FEATURE_K7); 628 #endif 629 630 if (c->x86 >= 0xf) 631 set_cpu_cap(c, X86_FEATURE_K8); 632 633 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); 634 635 /* 636 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 637 * with P/T states and does not stop in deep C-states 638 */ 639 if (c->x86_power & (1 << 8)) { 640 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 641 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 642 } 643 644 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */ 645 if (c->x86_power & BIT(12)) 646 set_cpu_cap(c, X86_FEATURE_ACC_POWER); 647 648 #ifdef CONFIG_X86_64 649 set_cpu_cap(c, X86_FEATURE_SYSCALL32); 650 #else 651 /* Set MTRR capability flag if appropriate */ 652 if (c->x86 == 5) 653 if (c->x86_model == 13 || c->x86_model == 9 || 654 (c->x86_model == 8 && c->x86_stepping >= 8)) 655 set_cpu_cap(c, X86_FEATURE_K6_MTRR); 656 #endif 657 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) 658 /* 659 * ApicID can always be treated as an 8-bit value for AMD APIC versions 660 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we 661 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families 662 * after 16h. 663 */ 664 if (boot_cpu_has(X86_FEATURE_APIC)) { 665 if (c->x86 > 0x16) 666 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 667 else if (c->x86 >= 0xf) { 668 /* check CPU config space for extended APIC ID */ 669 unsigned int val; 670 671 val = read_pci_config(0, 24, 0, 0x68); 672 if ((val >> 17 & 0x3) == 0x3) 673 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 674 } 675 } 676 #endif 677 678 /* 679 * This is only needed to tell the kernel whether to use VMCALL 680 * and VMMCALL. VMMCALL is never executed except under virt, so 681 * we can set it unconditionally. 682 */ 683 set_cpu_cap(c, X86_FEATURE_VMMCALL); 684 685 /* F16h erratum 793, CVE-2013-6885 */ 686 if (c->x86 == 0x16 && c->x86_model <= 0xf) 687 msr_set_bit(MSR_AMD64_LS_CFG, 15); 688 689 /* 690 * Check whether the machine is affected by erratum 400. This is 691 * used to select the proper idle routine and to enable the check 692 * whether the machine is affected in arch_post_acpi_init(), which 693 * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check. 694 */ 695 if (cpu_has_amd_erratum(c, amd_erratum_400)) 696 set_cpu_bug(c, X86_BUG_AMD_E400); 697 698 early_detect_mem_encrypt(c); 699 700 /* Re-enable TopologyExtensions if switched off by BIOS */ 701 if (c->x86 == 0x15 && 702 (c->x86_model >= 0x10 && c->x86_model <= 0x6f) && 703 !cpu_has(c, X86_FEATURE_TOPOEXT)) { 704 705 if (msr_set_bit(0xc0011005, 54) > 0) { 706 rdmsrl(0xc0011005, value); 707 if (value & BIT_64(54)) { 708 set_cpu_cap(c, X86_FEATURE_TOPOEXT); 709 pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n"); 710 } 711 } 712 } 713 714 if (cpu_has(c, X86_FEATURE_TOPOEXT)) 715 smp_num_siblings = ((cpuid_ebx(0x8000001e) >> 8) & 0xff) + 1; 716 } 717 718 static void init_amd_k8(struct cpuinfo_x86 *c) 719 { 720 u32 level; 721 u64 value; 722 723 /* On C+ stepping K8 rep microcode works well for copy/memset */ 724 level = cpuid_eax(1); 725 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) 726 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 727 728 /* 729 * Some BIOSes incorrectly force this feature, but only K8 revision D 730 * (model = 0x14) and later actually support it. 731 * (AMD Erratum #110, docId: 25759). 732 */ 733 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) { 734 clear_cpu_cap(c, X86_FEATURE_LAHF_LM); 735 if (!rdmsrl_amd_safe(0xc001100d, &value)) { 736 value &= ~BIT_64(32); 737 wrmsrl_amd_safe(0xc001100d, value); 738 } 739 } 740 741 if (!c->x86_model_id[0]) 742 strcpy(c->x86_model_id, "Hammer"); 743 744 #ifdef CONFIG_SMP 745 /* 746 * Disable TLB flush filter by setting HWCR.FFDIS on K8 747 * bit 6 of msr C001_0015 748 * 749 * Errata 63 for SH-B3 steppings 750 * Errata 122 for all steppings (F+ have it disabled by default) 751 */ 752 msr_set_bit(MSR_K7_HWCR, 6); 753 #endif 754 set_cpu_bug(c, X86_BUG_SWAPGS_FENCE); 755 } 756 757 static void init_amd_gh(struct cpuinfo_x86 *c) 758 { 759 #ifdef CONFIG_MMCONF_FAM10H 760 /* do this for boot cpu */ 761 if (c == &boot_cpu_data) 762 check_enable_amd_mmconf_dmi(); 763 764 fam10h_check_enable_mmcfg(); 765 #endif 766 767 /* 768 * Disable GART TLB Walk Errors on Fam10h. We do this here because this 769 * is always needed when GART is enabled, even in a kernel which has no 770 * MCE support built in. BIOS should disable GartTlbWlk Errors already. 771 * If it doesn't, we do it here as suggested by the BKDG. 772 * 773 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012 774 */ 775 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10); 776 777 /* 778 * On family 10h BIOS may not have properly enabled WC+ support, causing 779 * it to be converted to CD memtype. This may result in performance 780 * degradation for certain nested-paging guests. Prevent this conversion 781 * by clearing bit 24 in MSR_AMD64_BU_CFG2. 782 * 783 * NOTE: we want to use the _safe accessors so as not to #GP kvm 784 * guests on older kvm hosts. 785 */ 786 msr_clear_bit(MSR_AMD64_BU_CFG2, 24); 787 788 if (cpu_has_amd_erratum(c, amd_erratum_383)) 789 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH); 790 } 791 792 #define MSR_AMD64_DE_CFG 0xC0011029 793 794 static void init_amd_ln(struct cpuinfo_x86 *c) 795 { 796 /* 797 * Apply erratum 665 fix unconditionally so machines without a BIOS 798 * fix work. 799 */ 800 msr_set_bit(MSR_AMD64_DE_CFG, 31); 801 } 802 803 static bool rdrand_force; 804 805 static int __init rdrand_cmdline(char *str) 806 { 807 if (!str) 808 return -EINVAL; 809 810 if (!strcmp(str, "force")) 811 rdrand_force = true; 812 else 813 return -EINVAL; 814 815 return 0; 816 } 817 early_param("rdrand", rdrand_cmdline); 818 819 static void clear_rdrand_cpuid_bit(struct cpuinfo_x86 *c) 820 { 821 /* 822 * Saving of the MSR used to hide the RDRAND support during 823 * suspend/resume is done by arch/x86/power/cpu.c, which is 824 * dependent on CONFIG_PM_SLEEP. 825 */ 826 if (!IS_ENABLED(CONFIG_PM_SLEEP)) 827 return; 828 829 /* 830 * The nordrand option can clear X86_FEATURE_RDRAND, so check for 831 * RDRAND support using the CPUID function directly. 832 */ 833 if (!(cpuid_ecx(1) & BIT(30)) || rdrand_force) 834 return; 835 836 msr_clear_bit(MSR_AMD64_CPUID_FN_1, 62); 837 838 /* 839 * Verify that the CPUID change has occurred in case the kernel is 840 * running virtualized and the hypervisor doesn't support the MSR. 841 */ 842 if (cpuid_ecx(1) & BIT(30)) { 843 pr_info_once("BIOS may not properly restore RDRAND after suspend, but hypervisor does not support hiding RDRAND via CPUID.\n"); 844 return; 845 } 846 847 clear_cpu_cap(c, X86_FEATURE_RDRAND); 848 pr_info_once("BIOS may not properly restore RDRAND after suspend, hiding RDRAND via CPUID. Use rdrand=force to reenable.\n"); 849 } 850 851 static void init_amd_jg(struct cpuinfo_x86 *c) 852 { 853 /* 854 * Some BIOS implementations do not restore proper RDRAND support 855 * across suspend and resume. Check on whether to hide the RDRAND 856 * instruction support via CPUID. 857 */ 858 clear_rdrand_cpuid_bit(c); 859 } 860 861 static void init_amd_bd(struct cpuinfo_x86 *c) 862 { 863 u64 value; 864 865 /* 866 * The way access filter has a performance penalty on some workloads. 867 * Disable it on the affected CPUs. 868 */ 869 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) { 870 if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) { 871 value |= 0x1E; 872 wrmsrl_safe(MSR_F15H_IC_CFG, value); 873 } 874 } 875 876 /* 877 * Some BIOS implementations do not restore proper RDRAND support 878 * across suspend and resume. Check on whether to hide the RDRAND 879 * instruction support via CPUID. 880 */ 881 clear_rdrand_cpuid_bit(c); 882 } 883 884 static void init_amd_zn(struct cpuinfo_x86 *c) 885 { 886 set_cpu_cap(c, X86_FEATURE_ZEN); 887 888 #ifdef CONFIG_NUMA 889 node_reclaim_distance = 32; 890 #endif 891 892 /* 893 * Fix erratum 1076: CPB feature bit not being set in CPUID. 894 * Always set it, except when running under a hypervisor. 895 */ 896 if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && !cpu_has(c, X86_FEATURE_CPB)) 897 set_cpu_cap(c, X86_FEATURE_CPB); 898 } 899 900 static void init_amd(struct cpuinfo_x86 *c) 901 { 902 early_init_amd(c); 903 904 /* 905 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 906 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 907 */ 908 clear_cpu_cap(c, 0*32+31); 909 910 if (c->x86 >= 0x10) 911 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 912 913 /* get apicid instead of initial apic id from cpuid */ 914 c->apicid = hard_smp_processor_id(); 915 916 /* K6s reports MCEs but don't actually have all the MSRs */ 917 if (c->x86 < 6) 918 clear_cpu_cap(c, X86_FEATURE_MCE); 919 920 switch (c->x86) { 921 case 4: init_amd_k5(c); break; 922 case 5: init_amd_k6(c); break; 923 case 6: init_amd_k7(c); break; 924 case 0xf: init_amd_k8(c); break; 925 case 0x10: init_amd_gh(c); break; 926 case 0x12: init_amd_ln(c); break; 927 case 0x15: init_amd_bd(c); break; 928 case 0x16: init_amd_jg(c); break; 929 case 0x17: init_amd_zn(c); break; 930 } 931 932 /* 933 * Enable workaround for FXSAVE leak on CPUs 934 * without a XSaveErPtr feature 935 */ 936 if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR))) 937 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK); 938 939 cpu_detect_cache_sizes(c); 940 941 amd_detect_cmp(c); 942 amd_get_topology(c); 943 srat_detect_node(c); 944 945 init_amd_cacheinfo(c); 946 947 if (cpu_has(c, X86_FEATURE_XMM2)) { 948 /* 949 * Use LFENCE for execution serialization. On families which 950 * don't have that MSR, LFENCE is already serializing. 951 * msr_set_bit() uses the safe accessors, too, even if the MSR 952 * is not present. 953 */ 954 msr_set_bit(MSR_F10H_DECFG, 955 MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT); 956 957 /* A serializing LFENCE stops RDTSC speculation */ 958 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 959 } 960 961 /* 962 * Family 0x12 and above processors have APIC timer 963 * running in deep C states. 964 */ 965 if (c->x86 > 0x11) 966 set_cpu_cap(c, X86_FEATURE_ARAT); 967 968 /* 3DNow or LM implies PREFETCHW */ 969 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH)) 970 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM)) 971 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH); 972 973 /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */ 974 if (!cpu_has(c, X86_FEATURE_XENPV)) 975 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); 976 977 /* 978 * Turn on the Instructions Retired free counter on machines not 979 * susceptible to erratum #1054 "Instructions Retired Performance 980 * Counter May Be Inaccurate". 981 */ 982 if (cpu_has(c, X86_FEATURE_IRPERF) && 983 !cpu_has_amd_erratum(c, amd_erratum_1054)) 984 msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT); 985 } 986 987 #ifdef CONFIG_X86_32 988 static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size) 989 { 990 /* AMD errata T13 (order #21922) */ 991 if (c->x86 == 6) { 992 /* Duron Rev A0 */ 993 if (c->x86_model == 3 && c->x86_stepping == 0) 994 size = 64; 995 /* Tbird rev A1/A2 */ 996 if (c->x86_model == 4 && 997 (c->x86_stepping == 0 || c->x86_stepping == 1)) 998 size = 256; 999 } 1000 return size; 1001 } 1002 #endif 1003 1004 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) 1005 { 1006 u32 ebx, eax, ecx, edx; 1007 u16 mask = 0xfff; 1008 1009 if (c->x86 < 0xf) 1010 return; 1011 1012 if (c->extended_cpuid_level < 0x80000006) 1013 return; 1014 1015 cpuid(0x80000006, &eax, &ebx, &ecx, &edx); 1016 1017 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask; 1018 tlb_lli_4k[ENTRIES] = ebx & mask; 1019 1020 /* 1021 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB 1022 * characteristics from the CPUID function 0x80000005 instead. 1023 */ 1024 if (c->x86 == 0xf) { 1025 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 1026 mask = 0xff; 1027 } 1028 1029 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 1030 if (!((eax >> 16) & mask)) 1031 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff; 1032 else 1033 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask; 1034 1035 /* a 4M entry uses two 2M entries */ 1036 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1; 1037 1038 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 1039 if (!(eax & mask)) { 1040 /* Erratum 658 */ 1041 if (c->x86 == 0x15 && c->x86_model <= 0x1f) { 1042 tlb_lli_2m[ENTRIES] = 1024; 1043 } else { 1044 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 1045 tlb_lli_2m[ENTRIES] = eax & 0xff; 1046 } 1047 } else 1048 tlb_lli_2m[ENTRIES] = eax & mask; 1049 1050 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1; 1051 } 1052 1053 static const struct cpu_dev amd_cpu_dev = { 1054 .c_vendor = "AMD", 1055 .c_ident = { "AuthenticAMD" }, 1056 #ifdef CONFIG_X86_32 1057 .legacy_models = { 1058 { .family = 4, .model_names = 1059 { 1060 [3] = "486 DX/2", 1061 [7] = "486 DX/2-WB", 1062 [8] = "486 DX/4", 1063 [9] = "486 DX/4-WB", 1064 [14] = "Am5x86-WT", 1065 [15] = "Am5x86-WB" 1066 } 1067 }, 1068 }, 1069 .legacy_cache_size = amd_size_cache, 1070 #endif 1071 .c_early_init = early_init_amd, 1072 .c_detect_tlb = cpu_detect_tlb_amd, 1073 .c_bsp_init = bsp_init_amd, 1074 .c_init = init_amd, 1075 .c_x86_vendor = X86_VENDOR_AMD, 1076 }; 1077 1078 cpu_dev_register(amd_cpu_dev); 1079 1080 /* 1081 * AMD errata checking 1082 * 1083 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or 1084 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that 1085 * have an OSVW id assigned, which it takes as first argument. Both take a 1086 * variable number of family-specific model-stepping ranges created by 1087 * AMD_MODEL_RANGE(). 1088 * 1089 * Example: 1090 * 1091 * const int amd_erratum_319[] = 1092 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), 1093 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), 1094 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); 1095 */ 1096 1097 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 } 1098 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 } 1099 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \ 1100 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end)) 1101 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff) 1102 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff) 1103 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff) 1104 1105 static const int amd_erratum_400[] = 1106 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), 1107 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); 1108 1109 static const int amd_erratum_383[] = 1110 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); 1111 1112 /* #1054: Instructions Retired Performance Counter May Be Inaccurate */ 1113 static const int amd_erratum_1054[] = 1114 AMD_OSVW_ERRATUM(0, AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf)); 1115 1116 1117 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum) 1118 { 1119 int osvw_id = *erratum++; 1120 u32 range; 1121 u32 ms; 1122 1123 if (osvw_id >= 0 && osvw_id < 65536 && 1124 cpu_has(cpu, X86_FEATURE_OSVW)) { 1125 u64 osvw_len; 1126 1127 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); 1128 if (osvw_id < osvw_len) { 1129 u64 osvw_bits; 1130 1131 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), 1132 osvw_bits); 1133 return osvw_bits & (1ULL << (osvw_id & 0x3f)); 1134 } 1135 } 1136 1137 /* OSVW unavailable or ID unknown, match family-model-stepping range */ 1138 ms = (cpu->x86_model << 4) | cpu->x86_stepping; 1139 while ((range = *erratum++)) 1140 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) && 1141 (ms >= AMD_MODEL_RANGE_START(range)) && 1142 (ms <= AMD_MODEL_RANGE_END(range))) 1143 return true; 1144 1145 return false; 1146 } 1147 1148 void set_dr_addr_mask(unsigned long mask, int dr) 1149 { 1150 if (!boot_cpu_has(X86_FEATURE_BPEXT)) 1151 return; 1152 1153 switch (dr) { 1154 case 0: 1155 wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0); 1156 break; 1157 case 1: 1158 case 2: 1159 case 3: 1160 wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0); 1161 break; 1162 default: 1163 break; 1164 } 1165 } 1166