1 #include <linux/init.h> 2 #include <linux/bitops.h> 3 #include <linux/mm.h> 4 #include <asm/io.h> 5 #include <asm/processor.h> 6 #include <asm/apic.h> 7 8 #include <mach_apic.h> 9 #include "cpu.h" 10 11 /* 12 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause 13 * misexecution of code under Linux. Owners of such processors should 14 * contact AMD for precise details and a CPU swap. 15 * 16 * See http://www.multimania.com/poulot/k6bug.html 17 * http://www.amd.com/K6/k6docs/revgd.html 18 * 19 * The following test is erm.. interesting. AMD neglected to up 20 * the chip setting when fixing the bug but they also tweaked some 21 * performance at the same time.. 22 */ 23 24 extern void vide(void); 25 __asm__(".align 4\nvide: ret"); 26 27 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c) 28 { 29 if (cpuid_eax(0x80000000) >= 0x80000007) { 30 c->x86_power = cpuid_edx(0x80000007); 31 if (c->x86_power & (1<<8)) 32 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 33 } 34 } 35 36 static void __cpuinit init_amd(struct cpuinfo_x86 *c) 37 { 38 u32 l, h; 39 int mbytes = num_physpages >> (20-PAGE_SHIFT); 40 int r; 41 42 #ifdef CONFIG_SMP 43 unsigned long long value; 44 45 /* 46 * Disable TLB flush filter by setting HWCR.FFDIS on K8 47 * bit 6 of msr C001_0015 48 * 49 * Errata 63 for SH-B3 steppings 50 * Errata 122 for all steppings (F+ have it disabled by default) 51 */ 52 if (c->x86 == 15) { 53 rdmsrl(MSR_K7_HWCR, value); 54 value |= 1 << 6; 55 wrmsrl(MSR_K7_HWCR, value); 56 } 57 #endif 58 59 early_init_amd(c); 60 61 /* 62 * FIXME: We should handle the K5 here. Set up the write 63 * range and also turn on MSR 83 bits 4 and 31 (write alloc, 64 * no bus pipeline) 65 */ 66 67 /* 68 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 69 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 70 */ 71 clear_cpu_cap(c, 0*32+31); 72 73 r = get_model_name(c); 74 75 switch (c->x86) { 76 case 4: 77 /* 78 * General Systems BIOSen alias the cpu frequency registers 79 * of the Elan at 0x000df000. Unfortuantly, one of the Linux 80 * drivers subsequently pokes it, and changes the CPU speed. 81 * Workaround : Remove the unneeded alias. 82 */ 83 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ 84 #define CBAR_ENB (0x80000000) 85 #define CBAR_KEY (0X000000CB) 86 if (c->x86_model == 9 || c->x86_model == 10) { 87 if (inl (CBAR) & CBAR_ENB) 88 outl (0 | CBAR_KEY, CBAR); 89 } 90 break; 91 case 5: 92 if (c->x86_model < 6) { 93 /* Based on AMD doc 20734R - June 2000 */ 94 if (c->x86_model == 0) { 95 clear_cpu_cap(c, X86_FEATURE_APIC); 96 set_cpu_cap(c, X86_FEATURE_PGE); 97 } 98 break; 99 } 100 101 if (c->x86_model == 6 && c->x86_mask == 1) { 102 const int K6_BUG_LOOP = 1000000; 103 int n; 104 void (*f_vide)(void); 105 unsigned long d, d2; 106 107 printk(KERN_INFO "AMD K6 stepping B detected - "); 108 109 /* 110 * It looks like AMD fixed the 2.6.2 bug and improved indirect 111 * calls at the same time. 112 */ 113 114 n = K6_BUG_LOOP; 115 f_vide = vide; 116 rdtscl(d); 117 while (n--) 118 f_vide(); 119 rdtscl(d2); 120 d = d2-d; 121 122 if (d > 20*K6_BUG_LOOP) 123 printk("system stability may be impaired when more than 32 MB are used.\n"); 124 else 125 printk("probably OK (after B9730xxxx).\n"); 126 printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n"); 127 } 128 129 /* K6 with old style WHCR */ 130 if (c->x86_model < 8 || 131 (c->x86_model == 8 && c->x86_mask < 8)) { 132 /* We can only write allocate on the low 508Mb */ 133 if (mbytes > 508) 134 mbytes = 508; 135 136 rdmsr(MSR_K6_WHCR, l, h); 137 if ((l&0x0000FFFF) == 0) { 138 unsigned long flags; 139 l = (1<<0)|((mbytes/4)<<1); 140 local_irq_save(flags); 141 wbinvd(); 142 wrmsr(MSR_K6_WHCR, l, h); 143 local_irq_restore(flags); 144 printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n", 145 mbytes); 146 } 147 break; 148 } 149 150 if ((c->x86_model == 8 && c->x86_mask > 7) || 151 c->x86_model == 9 || c->x86_model == 13) { 152 /* The more serious chips .. */ 153 154 if (mbytes > 4092) 155 mbytes = 4092; 156 157 rdmsr(MSR_K6_WHCR, l, h); 158 if ((l&0xFFFF0000) == 0) { 159 unsigned long flags; 160 l = ((mbytes>>2)<<22)|(1<<16); 161 local_irq_save(flags); 162 wbinvd(); 163 wrmsr(MSR_K6_WHCR, l, h); 164 local_irq_restore(flags); 165 printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n", 166 mbytes); 167 } 168 169 /* Set MTRR capability flag if appropriate */ 170 if (c->x86_model == 13 || c->x86_model == 9 || 171 (c->x86_model == 8 && c->x86_mask >= 8)) 172 set_cpu_cap(c, X86_FEATURE_K6_MTRR); 173 break; 174 } 175 176 if (c->x86_model == 10) { 177 /* AMD Geode LX is model 10 */ 178 /* placeholder for any needed mods */ 179 break; 180 } 181 break; 182 case 6: /* An Athlon/Duron */ 183 184 /* 185 * Bit 15 of Athlon specific MSR 15, needs to be 0 186 * to enable SSE on Palomino/Morgan/Barton CPU's. 187 * If the BIOS didn't enable it already, enable it here. 188 */ 189 if (c->x86_model >= 6 && c->x86_model <= 10) { 190 if (!cpu_has(c, X86_FEATURE_XMM)) { 191 printk(KERN_INFO "Enabling disabled K7/SSE Support.\n"); 192 rdmsr(MSR_K7_HWCR, l, h); 193 l &= ~0x00008000; 194 wrmsr(MSR_K7_HWCR, l, h); 195 set_cpu_cap(c, X86_FEATURE_XMM); 196 } 197 } 198 199 /* 200 * It's been determined by AMD that Athlons since model 8 stepping 1 201 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx 202 * As per AMD technical note 27212 0.2 203 */ 204 if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) { 205 rdmsr(MSR_K7_CLK_CTL, l, h); 206 if ((l & 0xfff00000) != 0x20000000) { 207 printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l, 208 ((l & 0x000fffff)|0x20000000)); 209 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); 210 } 211 } 212 break; 213 } 214 215 switch (c->x86) { 216 case 15: 217 /* Use K8 tuning for Fam10h and Fam11h */ 218 case 0x10: 219 case 0x11: 220 set_cpu_cap(c, X86_FEATURE_K8); 221 break; 222 case 6: 223 set_cpu_cap(c, X86_FEATURE_K7); 224 break; 225 } 226 if (c->x86 >= 6) 227 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK); 228 229 display_cacheinfo(c); 230 231 if (cpuid_eax(0x80000000) >= 0x80000008) 232 c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1; 233 234 #ifdef CONFIG_X86_HT 235 /* 236 * On a AMD multi core setup the lower bits of the APIC id 237 * distinguish the cores. 238 */ 239 if (c->x86_max_cores > 1) { 240 int cpu = smp_processor_id(); 241 unsigned bits = (cpuid_ecx(0x80000008) >> 12) & 0xf; 242 243 if (bits == 0) { 244 while ((1 << bits) < c->x86_max_cores) 245 bits++; 246 } 247 c->cpu_core_id = c->phys_proc_id & ((1<<bits)-1); 248 c->phys_proc_id >>= bits; 249 printk(KERN_INFO "CPU %d(%d) -> Core %d\n", 250 cpu, c->x86_max_cores, c->cpu_core_id); 251 } 252 #endif 253 254 if (cpuid_eax(0x80000000) >= 0x80000006) { 255 if ((c->x86 == 0x10) && (cpuid_edx(0x80000006) & 0xf000)) 256 num_cache_leaves = 4; 257 else 258 num_cache_leaves = 3; 259 } 260 261 /* K6s reports MCEs but don't actually have all the MSRs */ 262 if (c->x86 < 6) 263 clear_cpu_cap(c, X86_FEATURE_MCE); 264 265 if (cpu_has_xmm2) 266 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); 267 } 268 269 static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, unsigned int size) 270 { 271 /* AMD errata T13 (order #21922) */ 272 if ((c->x86 == 6)) { 273 if (c->x86_model == 3 && c->x86_mask == 0) /* Duron Rev A0 */ 274 size = 64; 275 if (c->x86_model == 4 && 276 (c->x86_mask == 0 || c->x86_mask == 1)) /* Tbird rev A1/A2 */ 277 size = 256; 278 } 279 return size; 280 } 281 282 static struct cpu_dev amd_cpu_dev __cpuinitdata = { 283 .c_vendor = "AMD", 284 .c_ident = { "AuthenticAMD" }, 285 .c_models = { 286 { .vendor = X86_VENDOR_AMD, .family = 4, .model_names = 287 { 288 [3] = "486 DX/2", 289 [7] = "486 DX/2-WB", 290 [8] = "486 DX/4", 291 [9] = "486 DX/4-WB", 292 [14] = "Am5x86-WT", 293 [15] = "Am5x86-WB" 294 } 295 }, 296 }, 297 .c_early_init = early_init_amd, 298 .c_init = init_amd, 299 .c_size_cache = amd_size_cache, 300 }; 301 302 cpu_vendor_dev_register(X86_VENDOR_AMD, &amd_cpu_dev); 303