1 #include <linux/export.h> 2 #include <linux/bitops.h> 3 #include <linux/elf.h> 4 #include <linux/mm.h> 5 6 #include <linux/io.h> 7 #include <linux/sched.h> 8 #include <linux/random.h> 9 #include <asm/processor.h> 10 #include <asm/apic.h> 11 #include <asm/cpu.h> 12 #include <asm/smp.h> 13 #include <asm/pci-direct.h> 14 #include <asm/delay.h> 15 16 #ifdef CONFIG_X86_64 17 # include <asm/mmconfig.h> 18 # include <asm/cacheflush.h> 19 #endif 20 21 #include "cpu.h" 22 23 static const int amd_erratum_383[]; 24 static const int amd_erratum_400[]; 25 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum); 26 27 /* 28 * nodes_per_socket: Stores the number of nodes per socket. 29 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX 30 * Node Identifiers[10:8] 31 */ 32 static u32 nodes_per_socket = 1; 33 34 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) 35 { 36 u32 gprs[8] = { 0 }; 37 int err; 38 39 WARN_ONCE((boot_cpu_data.x86 != 0xf), 40 "%s should only be used on K8!\n", __func__); 41 42 gprs[1] = msr; 43 gprs[7] = 0x9c5a203a; 44 45 err = rdmsr_safe_regs(gprs); 46 47 *p = gprs[0] | ((u64)gprs[2] << 32); 48 49 return err; 50 } 51 52 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val) 53 { 54 u32 gprs[8] = { 0 }; 55 56 WARN_ONCE((boot_cpu_data.x86 != 0xf), 57 "%s should only be used on K8!\n", __func__); 58 59 gprs[0] = (u32)val; 60 gprs[1] = msr; 61 gprs[2] = val >> 32; 62 gprs[7] = 0x9c5a203a; 63 64 return wrmsr_safe_regs(gprs); 65 } 66 67 /* 68 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause 69 * misexecution of code under Linux. Owners of such processors should 70 * contact AMD for precise details and a CPU swap. 71 * 72 * See http://www.multimania.com/poulot/k6bug.html 73 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6" 74 * (Publication # 21266 Issue Date: August 1998) 75 * 76 * The following test is erm.. interesting. AMD neglected to up 77 * the chip setting when fixing the bug but they also tweaked some 78 * performance at the same time.. 79 */ 80 81 extern __visible void vide(void); 82 __asm__(".globl vide\n" 83 ".type vide, @function\n" 84 ".align 4\n" 85 "vide: ret\n"); 86 87 static void init_amd_k5(struct cpuinfo_x86 *c) 88 { 89 #ifdef CONFIG_X86_32 90 /* 91 * General Systems BIOSen alias the cpu frequency registers 92 * of the Elan at 0x000df000. Unfortunately, one of the Linux 93 * drivers subsequently pokes it, and changes the CPU speed. 94 * Workaround : Remove the unneeded alias. 95 */ 96 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ 97 #define CBAR_ENB (0x80000000) 98 #define CBAR_KEY (0X000000CB) 99 if (c->x86_model == 9 || c->x86_model == 10) { 100 if (inl(CBAR) & CBAR_ENB) 101 outl(0 | CBAR_KEY, CBAR); 102 } 103 #endif 104 } 105 106 static void init_amd_k6(struct cpuinfo_x86 *c) 107 { 108 #ifdef CONFIG_X86_32 109 u32 l, h; 110 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT); 111 112 if (c->x86_model < 6) { 113 /* Based on AMD doc 20734R - June 2000 */ 114 if (c->x86_model == 0) { 115 clear_cpu_cap(c, X86_FEATURE_APIC); 116 set_cpu_cap(c, X86_FEATURE_PGE); 117 } 118 return; 119 } 120 121 if (c->x86_model == 6 && c->x86_mask == 1) { 122 const int K6_BUG_LOOP = 1000000; 123 int n; 124 void (*f_vide)(void); 125 u64 d, d2; 126 127 pr_info("AMD K6 stepping B detected - "); 128 129 /* 130 * It looks like AMD fixed the 2.6.2 bug and improved indirect 131 * calls at the same time. 132 */ 133 134 n = K6_BUG_LOOP; 135 f_vide = vide; 136 d = rdtsc(); 137 while (n--) 138 f_vide(); 139 d2 = rdtsc(); 140 d = d2-d; 141 142 if (d > 20*K6_BUG_LOOP) 143 pr_cont("system stability may be impaired when more than 32 MB are used.\n"); 144 else 145 pr_cont("probably OK (after B9730xxxx).\n"); 146 } 147 148 /* K6 with old style WHCR */ 149 if (c->x86_model < 8 || 150 (c->x86_model == 8 && c->x86_mask < 8)) { 151 /* We can only write allocate on the low 508Mb */ 152 if (mbytes > 508) 153 mbytes = 508; 154 155 rdmsr(MSR_K6_WHCR, l, h); 156 if ((l&0x0000FFFF) == 0) { 157 unsigned long flags; 158 l = (1<<0)|((mbytes/4)<<1); 159 local_irq_save(flags); 160 wbinvd(); 161 wrmsr(MSR_K6_WHCR, l, h); 162 local_irq_restore(flags); 163 pr_info("Enabling old style K6 write allocation for %d Mb\n", 164 mbytes); 165 } 166 return; 167 } 168 169 if ((c->x86_model == 8 && c->x86_mask > 7) || 170 c->x86_model == 9 || c->x86_model == 13) { 171 /* The more serious chips .. */ 172 173 if (mbytes > 4092) 174 mbytes = 4092; 175 176 rdmsr(MSR_K6_WHCR, l, h); 177 if ((l&0xFFFF0000) == 0) { 178 unsigned long flags; 179 l = ((mbytes>>2)<<22)|(1<<16); 180 local_irq_save(flags); 181 wbinvd(); 182 wrmsr(MSR_K6_WHCR, l, h); 183 local_irq_restore(flags); 184 pr_info("Enabling new style K6 write allocation for %d Mb\n", 185 mbytes); 186 } 187 188 return; 189 } 190 191 if (c->x86_model == 10) { 192 /* AMD Geode LX is model 10 */ 193 /* placeholder for any needed mods */ 194 return; 195 } 196 #endif 197 } 198 199 static void init_amd_k7(struct cpuinfo_x86 *c) 200 { 201 #ifdef CONFIG_X86_32 202 u32 l, h; 203 204 /* 205 * Bit 15 of Athlon specific MSR 15, needs to be 0 206 * to enable SSE on Palomino/Morgan/Barton CPU's. 207 * If the BIOS didn't enable it already, enable it here. 208 */ 209 if (c->x86_model >= 6 && c->x86_model <= 10) { 210 if (!cpu_has(c, X86_FEATURE_XMM)) { 211 pr_info("Enabling disabled K7/SSE Support.\n"); 212 msr_clear_bit(MSR_K7_HWCR, 15); 213 set_cpu_cap(c, X86_FEATURE_XMM); 214 } 215 } 216 217 /* 218 * It's been determined by AMD that Athlons since model 8 stepping 1 219 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx 220 * As per AMD technical note 27212 0.2 221 */ 222 if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) { 223 rdmsr(MSR_K7_CLK_CTL, l, h); 224 if ((l & 0xfff00000) != 0x20000000) { 225 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", 226 l, ((l & 0x000fffff)|0x20000000)); 227 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); 228 } 229 } 230 231 set_cpu_cap(c, X86_FEATURE_K7); 232 233 /* calling is from identify_secondary_cpu() ? */ 234 if (!c->cpu_index) 235 return; 236 237 /* 238 * Certain Athlons might work (for various values of 'work') in SMP 239 * but they are not certified as MP capable. 240 */ 241 /* Athlon 660/661 is valid. */ 242 if ((c->x86_model == 6) && ((c->x86_mask == 0) || 243 (c->x86_mask == 1))) 244 return; 245 246 /* Duron 670 is valid */ 247 if ((c->x86_model == 7) && (c->x86_mask == 0)) 248 return; 249 250 /* 251 * Athlon 662, Duron 671, and Athlon >model 7 have capability 252 * bit. It's worth noting that the A5 stepping (662) of some 253 * Athlon XP's have the MP bit set. 254 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for 255 * more. 256 */ 257 if (((c->x86_model == 6) && (c->x86_mask >= 2)) || 258 ((c->x86_model == 7) && (c->x86_mask >= 1)) || 259 (c->x86_model > 7)) 260 if (cpu_has(c, X86_FEATURE_MP)) 261 return; 262 263 /* If we get here, not a certified SMP capable AMD system. */ 264 265 /* 266 * Don't taint if we are running SMP kernel on a single non-MP 267 * approved Athlon 268 */ 269 WARN_ONCE(1, "WARNING: This combination of AMD" 270 " processors is not suitable for SMP.\n"); 271 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); 272 #endif 273 } 274 275 #ifdef CONFIG_NUMA 276 /* 277 * To workaround broken NUMA config. Read the comment in 278 * srat_detect_node(). 279 */ 280 static int nearby_node(int apicid) 281 { 282 int i, node; 283 284 for (i = apicid - 1; i >= 0; i--) { 285 node = __apicid_to_node[i]; 286 if (node != NUMA_NO_NODE && node_online(node)) 287 return node; 288 } 289 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { 290 node = __apicid_to_node[i]; 291 if (node != NUMA_NO_NODE && node_online(node)) 292 return node; 293 } 294 return first_node(node_online_map); /* Shouldn't happen */ 295 } 296 #endif 297 298 /* 299 * Fixup core topology information for 300 * (1) AMD multi-node processors 301 * Assumption: Number of cores in each internal node is the same. 302 * (2) AMD processors supporting compute units 303 */ 304 #ifdef CONFIG_SMP 305 static void amd_get_topology(struct cpuinfo_x86 *c) 306 { 307 u8 node_id; 308 int cpu = smp_processor_id(); 309 310 /* get information required for multi-node processors */ 311 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 312 u32 eax, ebx, ecx, edx; 313 314 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); 315 316 node_id = ecx & 0xff; 317 smp_num_siblings = ((ebx >> 8) & 0xff) + 1; 318 319 if (c->x86 == 0x15) 320 c->cu_id = ebx & 0xff; 321 322 if (c->x86 >= 0x17) { 323 c->cpu_core_id = ebx & 0xff; 324 325 if (smp_num_siblings > 1) 326 c->x86_max_cores /= smp_num_siblings; 327 } 328 329 /* 330 * We may have multiple LLCs if L3 caches exist, so check if we 331 * have an L3 cache by looking at the L3 cache CPUID leaf. 332 */ 333 if (cpuid_edx(0x80000006)) { 334 if (c->x86 == 0x17) { 335 /* 336 * LLC is at the core complex level. 337 * Core complex id is ApicId[3]. 338 */ 339 per_cpu(cpu_llc_id, cpu) = c->apicid >> 3; 340 } else { 341 /* LLC is at the node level. */ 342 per_cpu(cpu_llc_id, cpu) = node_id; 343 } 344 } 345 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { 346 u64 value; 347 348 rdmsrl(MSR_FAM10H_NODE_ID, value); 349 node_id = value & 7; 350 351 per_cpu(cpu_llc_id, cpu) = node_id; 352 } else 353 return; 354 355 /* fixup multi-node processor information */ 356 if (nodes_per_socket > 1) { 357 u32 cus_per_node; 358 359 set_cpu_cap(c, X86_FEATURE_AMD_DCM); 360 cus_per_node = c->x86_max_cores / nodes_per_socket; 361 362 /* core id has to be in the [0 .. cores_per_node - 1] range */ 363 c->cpu_core_id %= cus_per_node; 364 } 365 } 366 #endif 367 368 /* 369 * On a AMD dual core setup the lower bits of the APIC id distinguish the cores. 370 * Assumes number of cores is a power of two. 371 */ 372 static void amd_detect_cmp(struct cpuinfo_x86 *c) 373 { 374 #ifdef CONFIG_SMP 375 unsigned bits; 376 int cpu = smp_processor_id(); 377 378 bits = c->x86_coreid_bits; 379 /* Low order bits define the core id (index of core in socket) */ 380 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1); 381 /* Convert the initial APIC ID into the socket ID */ 382 c->phys_proc_id = c->initial_apicid >> bits; 383 /* use socket ID also for last level cache */ 384 per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; 385 amd_get_topology(c); 386 #endif 387 } 388 389 u16 amd_get_nb_id(int cpu) 390 { 391 u16 id = 0; 392 #ifdef CONFIG_SMP 393 id = per_cpu(cpu_llc_id, cpu); 394 #endif 395 return id; 396 } 397 EXPORT_SYMBOL_GPL(amd_get_nb_id); 398 399 u32 amd_get_nodes_per_socket(void) 400 { 401 return nodes_per_socket; 402 } 403 EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket); 404 405 static void srat_detect_node(struct cpuinfo_x86 *c) 406 { 407 #ifdef CONFIG_NUMA 408 int cpu = smp_processor_id(); 409 int node; 410 unsigned apicid = c->apicid; 411 412 node = numa_cpu_node(cpu); 413 if (node == NUMA_NO_NODE) 414 node = per_cpu(cpu_llc_id, cpu); 415 416 /* 417 * On multi-fabric platform (e.g. Numascale NumaChip) a 418 * platform-specific handler needs to be called to fixup some 419 * IDs of the CPU. 420 */ 421 if (x86_cpuinit.fixup_cpu_id) 422 x86_cpuinit.fixup_cpu_id(c, node); 423 424 if (!node_online(node)) { 425 /* 426 * Two possibilities here: 427 * 428 * - The CPU is missing memory and no node was created. In 429 * that case try picking one from a nearby CPU. 430 * 431 * - The APIC IDs differ from the HyperTransport node IDs 432 * which the K8 northbridge parsing fills in. Assume 433 * they are all increased by a constant offset, but in 434 * the same order as the HT nodeids. If that doesn't 435 * result in a usable node fall back to the path for the 436 * previous case. 437 * 438 * This workaround operates directly on the mapping between 439 * APIC ID and NUMA node, assuming certain relationship 440 * between APIC ID, HT node ID and NUMA topology. As going 441 * through CPU mapping may alter the outcome, directly 442 * access __apicid_to_node[]. 443 */ 444 int ht_nodeid = c->initial_apicid; 445 446 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE) 447 node = __apicid_to_node[ht_nodeid]; 448 /* Pick a nearby node */ 449 if (!node_online(node)) 450 node = nearby_node(apicid); 451 } 452 numa_set_node(cpu, node); 453 #endif 454 } 455 456 static void early_init_amd_mc(struct cpuinfo_x86 *c) 457 { 458 #ifdef CONFIG_SMP 459 unsigned bits, ecx; 460 461 /* Multi core CPU? */ 462 if (c->extended_cpuid_level < 0x80000008) 463 return; 464 465 ecx = cpuid_ecx(0x80000008); 466 467 c->x86_max_cores = (ecx & 0xff) + 1; 468 469 /* CPU telling us the core id bits shift? */ 470 bits = (ecx >> 12) & 0xF; 471 472 /* Otherwise recompute */ 473 if (bits == 0) { 474 while ((1 << bits) < c->x86_max_cores) 475 bits++; 476 } 477 478 c->x86_coreid_bits = bits; 479 #endif 480 } 481 482 static void bsp_init_amd(struct cpuinfo_x86 *c) 483 { 484 485 #ifdef CONFIG_X86_64 486 if (c->x86 >= 0xf) { 487 unsigned long long tseg; 488 489 /* 490 * Split up direct mapping around the TSEG SMM area. 491 * Don't do it for gbpages because there seems very little 492 * benefit in doing so. 493 */ 494 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) { 495 unsigned long pfn = tseg >> PAGE_SHIFT; 496 497 pr_debug("tseg: %010llx\n", tseg); 498 if (pfn_range_is_mapped(pfn, pfn + 1)) 499 set_memory_4k((unsigned long)__va(tseg), 1); 500 } 501 } 502 #endif 503 504 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { 505 506 if (c->x86 > 0x10 || 507 (c->x86 == 0x10 && c->x86_model >= 0x2)) { 508 u64 val; 509 510 rdmsrl(MSR_K7_HWCR, val); 511 if (!(val & BIT(24))) 512 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n"); 513 } 514 } 515 516 if (c->x86 == 0x15) { 517 unsigned long upperbit; 518 u32 cpuid, assoc; 519 520 cpuid = cpuid_edx(0x80000005); 521 assoc = cpuid >> 16 & 0xff; 522 upperbit = ((cpuid >> 24) << 10) / assoc; 523 524 va_align.mask = (upperbit - 1) & PAGE_MASK; 525 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64; 526 527 /* A random value per boot for bit slice [12:upper_bit) */ 528 va_align.bits = get_random_int() & va_align.mask; 529 } 530 531 if (cpu_has(c, X86_FEATURE_MWAITX)) 532 use_mwaitx_delay(); 533 534 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 535 u32 ecx; 536 537 ecx = cpuid_ecx(0x8000001e); 538 nodes_per_socket = ((ecx >> 8) & 7) + 1; 539 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) { 540 u64 value; 541 542 rdmsrl(MSR_FAM10H_NODE_ID, value); 543 nodes_per_socket = ((value >> 3) & 7) + 1; 544 } 545 } 546 547 static void early_init_amd(struct cpuinfo_x86 *c) 548 { 549 early_init_amd_mc(c); 550 551 /* 552 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 553 * with P/T states and does not stop in deep C-states 554 */ 555 if (c->x86_power & (1 << 8)) { 556 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 557 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 558 if (check_tsc_unstable()) 559 clear_sched_clock_stable(); 560 } else { 561 clear_sched_clock_stable(); 562 } 563 564 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */ 565 if (c->x86_power & BIT(12)) 566 set_cpu_cap(c, X86_FEATURE_ACC_POWER); 567 568 #ifdef CONFIG_X86_64 569 set_cpu_cap(c, X86_FEATURE_SYSCALL32); 570 #else 571 /* Set MTRR capability flag if appropriate */ 572 if (c->x86 == 5) 573 if (c->x86_model == 13 || c->x86_model == 9 || 574 (c->x86_model == 8 && c->x86_mask >= 8)) 575 set_cpu_cap(c, X86_FEATURE_K6_MTRR); 576 #endif 577 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) 578 /* 579 * ApicID can always be treated as an 8-bit value for AMD APIC versions 580 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we 581 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families 582 * after 16h. 583 */ 584 if (boot_cpu_has(X86_FEATURE_APIC)) { 585 if (c->x86 > 0x16) 586 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 587 else if (c->x86 >= 0xf) { 588 /* check CPU config space for extended APIC ID */ 589 unsigned int val; 590 591 val = read_pci_config(0, 24, 0, 0x68); 592 if ((val >> 17 & 0x3) == 0x3) 593 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 594 } 595 } 596 #endif 597 598 /* 599 * This is only needed to tell the kernel whether to use VMCALL 600 * and VMMCALL. VMMCALL is never executed except under virt, so 601 * we can set it unconditionally. 602 */ 603 set_cpu_cap(c, X86_FEATURE_VMMCALL); 604 605 /* F16h erratum 793, CVE-2013-6885 */ 606 if (c->x86 == 0x16 && c->x86_model <= 0xf) 607 msr_set_bit(MSR_AMD64_LS_CFG, 15); 608 609 /* 610 * Check whether the machine is affected by erratum 400. This is 611 * used to select the proper idle routine and to enable the check 612 * whether the machine is affected in arch_post_acpi_init(), which 613 * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check. 614 */ 615 if (cpu_has_amd_erratum(c, amd_erratum_400)) 616 set_cpu_bug(c, X86_BUG_AMD_E400); 617 } 618 619 static void init_amd_k8(struct cpuinfo_x86 *c) 620 { 621 u32 level; 622 u64 value; 623 624 /* On C+ stepping K8 rep microcode works well for copy/memset */ 625 level = cpuid_eax(1); 626 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) 627 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 628 629 /* 630 * Some BIOSes incorrectly force this feature, but only K8 revision D 631 * (model = 0x14) and later actually support it. 632 * (AMD Erratum #110, docId: 25759). 633 */ 634 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) { 635 clear_cpu_cap(c, X86_FEATURE_LAHF_LM); 636 if (!rdmsrl_amd_safe(0xc001100d, &value)) { 637 value &= ~BIT_64(32); 638 wrmsrl_amd_safe(0xc001100d, value); 639 } 640 } 641 642 if (!c->x86_model_id[0]) 643 strcpy(c->x86_model_id, "Hammer"); 644 645 #ifdef CONFIG_SMP 646 /* 647 * Disable TLB flush filter by setting HWCR.FFDIS on K8 648 * bit 6 of msr C001_0015 649 * 650 * Errata 63 for SH-B3 steppings 651 * Errata 122 for all steppings (F+ have it disabled by default) 652 */ 653 msr_set_bit(MSR_K7_HWCR, 6); 654 #endif 655 set_cpu_bug(c, X86_BUG_SWAPGS_FENCE); 656 } 657 658 static void init_amd_gh(struct cpuinfo_x86 *c) 659 { 660 #ifdef CONFIG_X86_64 661 /* do this for boot cpu */ 662 if (c == &boot_cpu_data) 663 check_enable_amd_mmconf_dmi(); 664 665 fam10h_check_enable_mmcfg(); 666 #endif 667 668 /* 669 * Disable GART TLB Walk Errors on Fam10h. We do this here because this 670 * is always needed when GART is enabled, even in a kernel which has no 671 * MCE support built in. BIOS should disable GartTlbWlk Errors already. 672 * If it doesn't, we do it here as suggested by the BKDG. 673 * 674 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012 675 */ 676 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10); 677 678 /* 679 * On family 10h BIOS may not have properly enabled WC+ support, causing 680 * it to be converted to CD memtype. This may result in performance 681 * degradation for certain nested-paging guests. Prevent this conversion 682 * by clearing bit 24 in MSR_AMD64_BU_CFG2. 683 * 684 * NOTE: we want to use the _safe accessors so as not to #GP kvm 685 * guests on older kvm hosts. 686 */ 687 msr_clear_bit(MSR_AMD64_BU_CFG2, 24); 688 689 if (cpu_has_amd_erratum(c, amd_erratum_383)) 690 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH); 691 } 692 693 #define MSR_AMD64_DE_CFG 0xC0011029 694 695 static void init_amd_ln(struct cpuinfo_x86 *c) 696 { 697 /* 698 * Apply erratum 665 fix unconditionally so machines without a BIOS 699 * fix work. 700 */ 701 msr_set_bit(MSR_AMD64_DE_CFG, 31); 702 } 703 704 static void init_amd_bd(struct cpuinfo_x86 *c) 705 { 706 u64 value; 707 708 /* re-enable TopologyExtensions if switched off by BIOS */ 709 if ((c->x86_model >= 0x10) && (c->x86_model <= 0x6f) && 710 !cpu_has(c, X86_FEATURE_TOPOEXT)) { 711 712 if (msr_set_bit(0xc0011005, 54) > 0) { 713 rdmsrl(0xc0011005, value); 714 if (value & BIT_64(54)) { 715 set_cpu_cap(c, X86_FEATURE_TOPOEXT); 716 pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n"); 717 } 718 } 719 } 720 721 /* 722 * The way access filter has a performance penalty on some workloads. 723 * Disable it on the affected CPUs. 724 */ 725 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) { 726 if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) { 727 value |= 0x1E; 728 wrmsrl_safe(MSR_F15H_IC_CFG, value); 729 } 730 } 731 } 732 733 static void init_amd(struct cpuinfo_x86 *c) 734 { 735 u32 dummy; 736 737 early_init_amd(c); 738 739 /* 740 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 741 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 742 */ 743 clear_cpu_cap(c, 0*32+31); 744 745 if (c->x86 >= 0x10) 746 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 747 748 /* get apicid instead of initial apic id from cpuid */ 749 c->apicid = hard_smp_processor_id(); 750 751 /* K6s reports MCEs but don't actually have all the MSRs */ 752 if (c->x86 < 6) 753 clear_cpu_cap(c, X86_FEATURE_MCE); 754 755 switch (c->x86) { 756 case 4: init_amd_k5(c); break; 757 case 5: init_amd_k6(c); break; 758 case 6: init_amd_k7(c); break; 759 case 0xf: init_amd_k8(c); break; 760 case 0x10: init_amd_gh(c); break; 761 case 0x12: init_amd_ln(c); break; 762 case 0x15: init_amd_bd(c); break; 763 } 764 765 /* Enable workaround for FXSAVE leak */ 766 if (c->x86 >= 6) 767 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK); 768 769 cpu_detect_cache_sizes(c); 770 771 /* Multi core CPU? */ 772 if (c->extended_cpuid_level >= 0x80000008) { 773 amd_detect_cmp(c); 774 srat_detect_node(c); 775 } 776 777 #ifdef CONFIG_X86_32 778 detect_ht(c); 779 #endif 780 781 init_amd_cacheinfo(c); 782 783 if (c->x86 >= 0xf) 784 set_cpu_cap(c, X86_FEATURE_K8); 785 786 if (cpu_has(c, X86_FEATURE_XMM2)) { 787 /* MFENCE stops RDTSC speculation */ 788 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); 789 } 790 791 /* 792 * Family 0x12 and above processors have APIC timer 793 * running in deep C states. 794 */ 795 if (c->x86 > 0x11) 796 set_cpu_cap(c, X86_FEATURE_ARAT); 797 798 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); 799 800 /* 3DNow or LM implies PREFETCHW */ 801 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH)) 802 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM)) 803 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH); 804 805 /* AMD CPUs don't reset SS attributes on SYSRET */ 806 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); 807 } 808 809 #ifdef CONFIG_X86_32 810 static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size) 811 { 812 /* AMD errata T13 (order #21922) */ 813 if ((c->x86 == 6)) { 814 /* Duron Rev A0 */ 815 if (c->x86_model == 3 && c->x86_mask == 0) 816 size = 64; 817 /* Tbird rev A1/A2 */ 818 if (c->x86_model == 4 && 819 (c->x86_mask == 0 || c->x86_mask == 1)) 820 size = 256; 821 } 822 return size; 823 } 824 #endif 825 826 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) 827 { 828 u32 ebx, eax, ecx, edx; 829 u16 mask = 0xfff; 830 831 if (c->x86 < 0xf) 832 return; 833 834 if (c->extended_cpuid_level < 0x80000006) 835 return; 836 837 cpuid(0x80000006, &eax, &ebx, &ecx, &edx); 838 839 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask; 840 tlb_lli_4k[ENTRIES] = ebx & mask; 841 842 /* 843 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB 844 * characteristics from the CPUID function 0x80000005 instead. 845 */ 846 if (c->x86 == 0xf) { 847 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 848 mask = 0xff; 849 } 850 851 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 852 if (!((eax >> 16) & mask)) 853 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff; 854 else 855 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask; 856 857 /* a 4M entry uses two 2M entries */ 858 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1; 859 860 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 861 if (!(eax & mask)) { 862 /* Erratum 658 */ 863 if (c->x86 == 0x15 && c->x86_model <= 0x1f) { 864 tlb_lli_2m[ENTRIES] = 1024; 865 } else { 866 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 867 tlb_lli_2m[ENTRIES] = eax & 0xff; 868 } 869 } else 870 tlb_lli_2m[ENTRIES] = eax & mask; 871 872 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1; 873 } 874 875 static const struct cpu_dev amd_cpu_dev = { 876 .c_vendor = "AMD", 877 .c_ident = { "AuthenticAMD" }, 878 #ifdef CONFIG_X86_32 879 .legacy_models = { 880 { .family = 4, .model_names = 881 { 882 [3] = "486 DX/2", 883 [7] = "486 DX/2-WB", 884 [8] = "486 DX/4", 885 [9] = "486 DX/4-WB", 886 [14] = "Am5x86-WT", 887 [15] = "Am5x86-WB" 888 } 889 }, 890 }, 891 .legacy_cache_size = amd_size_cache, 892 #endif 893 .c_early_init = early_init_amd, 894 .c_detect_tlb = cpu_detect_tlb_amd, 895 .c_bsp_init = bsp_init_amd, 896 .c_init = init_amd, 897 .c_x86_vendor = X86_VENDOR_AMD, 898 }; 899 900 cpu_dev_register(amd_cpu_dev); 901 902 /* 903 * AMD errata checking 904 * 905 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or 906 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that 907 * have an OSVW id assigned, which it takes as first argument. Both take a 908 * variable number of family-specific model-stepping ranges created by 909 * AMD_MODEL_RANGE(). 910 * 911 * Example: 912 * 913 * const int amd_erratum_319[] = 914 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), 915 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), 916 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); 917 */ 918 919 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 } 920 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 } 921 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \ 922 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end)) 923 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff) 924 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff) 925 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff) 926 927 static const int amd_erratum_400[] = 928 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), 929 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); 930 931 static const int amd_erratum_383[] = 932 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); 933 934 935 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum) 936 { 937 int osvw_id = *erratum++; 938 u32 range; 939 u32 ms; 940 941 if (osvw_id >= 0 && osvw_id < 65536 && 942 cpu_has(cpu, X86_FEATURE_OSVW)) { 943 u64 osvw_len; 944 945 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); 946 if (osvw_id < osvw_len) { 947 u64 osvw_bits; 948 949 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), 950 osvw_bits); 951 return osvw_bits & (1ULL << (osvw_id & 0x3f)); 952 } 953 } 954 955 /* OSVW unavailable or ID unknown, match family-model-stepping range */ 956 ms = (cpu->x86_model << 4) | cpu->x86_mask; 957 while ((range = *erratum++)) 958 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) && 959 (ms >= AMD_MODEL_RANGE_START(range)) && 960 (ms <= AMD_MODEL_RANGE_END(range))) 961 return true; 962 963 return false; 964 } 965 966 void set_dr_addr_mask(unsigned long mask, int dr) 967 { 968 if (!boot_cpu_has(X86_FEATURE_BPEXT)) 969 return; 970 971 switch (dr) { 972 case 0: 973 wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0); 974 break; 975 case 1: 976 case 2: 977 case 3: 978 wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0); 979 break; 980 default: 981 break; 982 } 983 } 984