1 // SPDX-License-Identifier: GPL-2.0-only 2 #include <linux/export.h> 3 #include <linux/bitops.h> 4 #include <linux/elf.h> 5 #include <linux/mm.h> 6 7 #include <linux/io.h> 8 #include <linux/sched.h> 9 #include <linux/sched/clock.h> 10 #include <linux/random.h> 11 #include <linux/topology.h> 12 #include <asm/processor.h> 13 #include <asm/apic.h> 14 #include <asm/cacheinfo.h> 15 #include <asm/cpu.h> 16 #include <asm/spec-ctrl.h> 17 #include <asm/smp.h> 18 #include <asm/numa.h> 19 #include <asm/pci-direct.h> 20 #include <asm/delay.h> 21 #include <asm/debugreg.h> 22 #include <asm/resctrl.h> 23 24 #ifdef CONFIG_X86_64 25 # include <asm/mmconfig.h> 26 #endif 27 28 #include "cpu.h" 29 30 /* 31 * nodes_per_socket: Stores the number of nodes per socket. 32 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX 33 * Node Identifiers[10:8] 34 */ 35 static u32 nodes_per_socket = 1; 36 37 /* 38 * AMD errata checking 39 * 40 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or 41 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that 42 * have an OSVW id assigned, which it takes as first argument. Both take a 43 * variable number of family-specific model-stepping ranges created by 44 * AMD_MODEL_RANGE(). 45 * 46 * Example: 47 * 48 * const int amd_erratum_319[] = 49 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), 50 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), 51 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); 52 */ 53 54 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 } 55 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 } 56 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \ 57 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end)) 58 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff) 59 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff) 60 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff) 61 62 static const int amd_erratum_400[] = 63 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), 64 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); 65 66 static const int amd_erratum_383[] = 67 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); 68 69 /* #1054: Instructions Retired Performance Counter May Be Inaccurate */ 70 static const int amd_erratum_1054[] = 71 AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf)); 72 73 static const int amd_zenbleed[] = 74 AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0x30, 0x0, 0x4f, 0xf), 75 AMD_MODEL_RANGE(0x17, 0x60, 0x0, 0x7f, 0xf), 76 AMD_MODEL_RANGE(0x17, 0xa0, 0x0, 0xaf, 0xf)); 77 78 static const int amd_div0[] = 79 AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0x00, 0x0, 0x2f, 0xf), 80 AMD_MODEL_RANGE(0x17, 0x50, 0x0, 0x5f, 0xf)); 81 82 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum) 83 { 84 int osvw_id = *erratum++; 85 u32 range; 86 u32 ms; 87 88 if (osvw_id >= 0 && osvw_id < 65536 && 89 cpu_has(cpu, X86_FEATURE_OSVW)) { 90 u64 osvw_len; 91 92 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); 93 if (osvw_id < osvw_len) { 94 u64 osvw_bits; 95 96 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), 97 osvw_bits); 98 return osvw_bits & (1ULL << (osvw_id & 0x3f)); 99 } 100 } 101 102 /* OSVW unavailable or ID unknown, match family-model-stepping range */ 103 ms = (cpu->x86_model << 4) | cpu->x86_stepping; 104 while ((range = *erratum++)) 105 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) && 106 (ms >= AMD_MODEL_RANGE_START(range)) && 107 (ms <= AMD_MODEL_RANGE_END(range))) 108 return true; 109 110 return false; 111 } 112 113 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) 114 { 115 u32 gprs[8] = { 0 }; 116 int err; 117 118 WARN_ONCE((boot_cpu_data.x86 != 0xf), 119 "%s should only be used on K8!\n", __func__); 120 121 gprs[1] = msr; 122 gprs[7] = 0x9c5a203a; 123 124 err = rdmsr_safe_regs(gprs); 125 126 *p = gprs[0] | ((u64)gprs[2] << 32); 127 128 return err; 129 } 130 131 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val) 132 { 133 u32 gprs[8] = { 0 }; 134 135 WARN_ONCE((boot_cpu_data.x86 != 0xf), 136 "%s should only be used on K8!\n", __func__); 137 138 gprs[0] = (u32)val; 139 gprs[1] = msr; 140 gprs[2] = val >> 32; 141 gprs[7] = 0x9c5a203a; 142 143 return wrmsr_safe_regs(gprs); 144 } 145 146 /* 147 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause 148 * misexecution of code under Linux. Owners of such processors should 149 * contact AMD for precise details and a CPU swap. 150 * 151 * See http://www.multimania.com/poulot/k6bug.html 152 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6" 153 * (Publication # 21266 Issue Date: August 1998) 154 * 155 * The following test is erm.. interesting. AMD neglected to up 156 * the chip setting when fixing the bug but they also tweaked some 157 * performance at the same time.. 158 */ 159 160 #ifdef CONFIG_X86_32 161 extern __visible void vide(void); 162 __asm__(".text\n" 163 ".globl vide\n" 164 ".type vide, @function\n" 165 ".align 4\n" 166 "vide: ret\n"); 167 #endif 168 169 static void init_amd_k5(struct cpuinfo_x86 *c) 170 { 171 #ifdef CONFIG_X86_32 172 /* 173 * General Systems BIOSen alias the cpu frequency registers 174 * of the Elan at 0x000df000. Unfortunately, one of the Linux 175 * drivers subsequently pokes it, and changes the CPU speed. 176 * Workaround : Remove the unneeded alias. 177 */ 178 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ 179 #define CBAR_ENB (0x80000000) 180 #define CBAR_KEY (0X000000CB) 181 if (c->x86_model == 9 || c->x86_model == 10) { 182 if (inl(CBAR) & CBAR_ENB) 183 outl(0 | CBAR_KEY, CBAR); 184 } 185 #endif 186 } 187 188 static void init_amd_k6(struct cpuinfo_x86 *c) 189 { 190 #ifdef CONFIG_X86_32 191 u32 l, h; 192 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT); 193 194 if (c->x86_model < 6) { 195 /* Based on AMD doc 20734R - June 2000 */ 196 if (c->x86_model == 0) { 197 clear_cpu_cap(c, X86_FEATURE_APIC); 198 set_cpu_cap(c, X86_FEATURE_PGE); 199 } 200 return; 201 } 202 203 if (c->x86_model == 6 && c->x86_stepping == 1) { 204 const int K6_BUG_LOOP = 1000000; 205 int n; 206 void (*f_vide)(void); 207 u64 d, d2; 208 209 pr_info("AMD K6 stepping B detected - "); 210 211 /* 212 * It looks like AMD fixed the 2.6.2 bug and improved indirect 213 * calls at the same time. 214 */ 215 216 n = K6_BUG_LOOP; 217 f_vide = vide; 218 OPTIMIZER_HIDE_VAR(f_vide); 219 d = rdtsc(); 220 while (n--) 221 f_vide(); 222 d2 = rdtsc(); 223 d = d2-d; 224 225 if (d > 20*K6_BUG_LOOP) 226 pr_cont("system stability may be impaired when more than 32 MB are used.\n"); 227 else 228 pr_cont("probably OK (after B9730xxxx).\n"); 229 } 230 231 /* K6 with old style WHCR */ 232 if (c->x86_model < 8 || 233 (c->x86_model == 8 && c->x86_stepping < 8)) { 234 /* We can only write allocate on the low 508Mb */ 235 if (mbytes > 508) 236 mbytes = 508; 237 238 rdmsr(MSR_K6_WHCR, l, h); 239 if ((l&0x0000FFFF) == 0) { 240 unsigned long flags; 241 l = (1<<0)|((mbytes/4)<<1); 242 local_irq_save(flags); 243 wbinvd(); 244 wrmsr(MSR_K6_WHCR, l, h); 245 local_irq_restore(flags); 246 pr_info("Enabling old style K6 write allocation for %d Mb\n", 247 mbytes); 248 } 249 return; 250 } 251 252 if ((c->x86_model == 8 && c->x86_stepping > 7) || 253 c->x86_model == 9 || c->x86_model == 13) { 254 /* The more serious chips .. */ 255 256 if (mbytes > 4092) 257 mbytes = 4092; 258 259 rdmsr(MSR_K6_WHCR, l, h); 260 if ((l&0xFFFF0000) == 0) { 261 unsigned long flags; 262 l = ((mbytes>>2)<<22)|(1<<16); 263 local_irq_save(flags); 264 wbinvd(); 265 wrmsr(MSR_K6_WHCR, l, h); 266 local_irq_restore(flags); 267 pr_info("Enabling new style K6 write allocation for %d Mb\n", 268 mbytes); 269 } 270 271 return; 272 } 273 274 if (c->x86_model == 10) { 275 /* AMD Geode LX is model 10 */ 276 /* placeholder for any needed mods */ 277 return; 278 } 279 #endif 280 } 281 282 static void init_amd_k7(struct cpuinfo_x86 *c) 283 { 284 #ifdef CONFIG_X86_32 285 u32 l, h; 286 287 /* 288 * Bit 15 of Athlon specific MSR 15, needs to be 0 289 * to enable SSE on Palomino/Morgan/Barton CPU's. 290 * If the BIOS didn't enable it already, enable it here. 291 */ 292 if (c->x86_model >= 6 && c->x86_model <= 10) { 293 if (!cpu_has(c, X86_FEATURE_XMM)) { 294 pr_info("Enabling disabled K7/SSE Support.\n"); 295 msr_clear_bit(MSR_K7_HWCR, 15); 296 set_cpu_cap(c, X86_FEATURE_XMM); 297 } 298 } 299 300 /* 301 * It's been determined by AMD that Athlons since model 8 stepping 1 302 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx 303 * As per AMD technical note 27212 0.2 304 */ 305 if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) { 306 rdmsr(MSR_K7_CLK_CTL, l, h); 307 if ((l & 0xfff00000) != 0x20000000) { 308 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", 309 l, ((l & 0x000fffff)|0x20000000)); 310 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); 311 } 312 } 313 314 /* calling is from identify_secondary_cpu() ? */ 315 if (!c->cpu_index) 316 return; 317 318 /* 319 * Certain Athlons might work (for various values of 'work') in SMP 320 * but they are not certified as MP capable. 321 */ 322 /* Athlon 660/661 is valid. */ 323 if ((c->x86_model == 6) && ((c->x86_stepping == 0) || 324 (c->x86_stepping == 1))) 325 return; 326 327 /* Duron 670 is valid */ 328 if ((c->x86_model == 7) && (c->x86_stepping == 0)) 329 return; 330 331 /* 332 * Athlon 662, Duron 671, and Athlon >model 7 have capability 333 * bit. It's worth noting that the A5 stepping (662) of some 334 * Athlon XP's have the MP bit set. 335 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for 336 * more. 337 */ 338 if (((c->x86_model == 6) && (c->x86_stepping >= 2)) || 339 ((c->x86_model == 7) && (c->x86_stepping >= 1)) || 340 (c->x86_model > 7)) 341 if (cpu_has(c, X86_FEATURE_MP)) 342 return; 343 344 /* If we get here, not a certified SMP capable AMD system. */ 345 346 /* 347 * Don't taint if we are running SMP kernel on a single non-MP 348 * approved Athlon 349 */ 350 WARN_ONCE(1, "WARNING: This combination of AMD" 351 " processors is not suitable for SMP.\n"); 352 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); 353 #endif 354 } 355 356 #ifdef CONFIG_NUMA 357 /* 358 * To workaround broken NUMA config. Read the comment in 359 * srat_detect_node(). 360 */ 361 static int nearby_node(int apicid) 362 { 363 int i, node; 364 365 for (i = apicid - 1; i >= 0; i--) { 366 node = __apicid_to_node[i]; 367 if (node != NUMA_NO_NODE && node_online(node)) 368 return node; 369 } 370 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { 371 node = __apicid_to_node[i]; 372 if (node != NUMA_NO_NODE && node_online(node)) 373 return node; 374 } 375 return first_node(node_online_map); /* Shouldn't happen */ 376 } 377 #endif 378 379 /* 380 * Fix up cpu_core_id for pre-F17h systems to be in the 381 * [0 .. cores_per_node - 1] range. Not really needed but 382 * kept so as not to break existing setups. 383 */ 384 static void legacy_fixup_core_id(struct cpuinfo_x86 *c) 385 { 386 u32 cus_per_node; 387 388 if (c->x86 >= 0x17) 389 return; 390 391 cus_per_node = c->x86_max_cores / nodes_per_socket; 392 c->cpu_core_id %= cus_per_node; 393 } 394 395 /* 396 * Fixup core topology information for 397 * (1) AMD multi-node processors 398 * Assumption: Number of cores in each internal node is the same. 399 * (2) AMD processors supporting compute units 400 */ 401 static void amd_get_topology(struct cpuinfo_x86 *c) 402 { 403 int cpu = smp_processor_id(); 404 405 /* get information required for multi-node processors */ 406 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 407 int err; 408 u32 eax, ebx, ecx, edx; 409 410 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); 411 412 c->cpu_die_id = ecx & 0xff; 413 414 if (c->x86 == 0x15) 415 c->cu_id = ebx & 0xff; 416 417 if (c->x86 >= 0x17) { 418 c->cpu_core_id = ebx & 0xff; 419 420 if (smp_num_siblings > 1) 421 c->x86_max_cores /= smp_num_siblings; 422 } 423 424 /* 425 * In case leaf B is available, use it to derive 426 * topology information. 427 */ 428 err = detect_extended_topology(c); 429 if (!err) 430 c->x86_coreid_bits = get_count_order(c->x86_max_cores); 431 432 cacheinfo_amd_init_llc_id(c, cpu); 433 434 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { 435 u64 value; 436 437 rdmsrl(MSR_FAM10H_NODE_ID, value); 438 c->cpu_die_id = value & 7; 439 440 per_cpu(cpu_llc_id, cpu) = c->cpu_die_id; 441 } else 442 return; 443 444 if (nodes_per_socket > 1) { 445 set_cpu_cap(c, X86_FEATURE_AMD_DCM); 446 legacy_fixup_core_id(c); 447 } 448 } 449 450 /* 451 * On a AMD dual core setup the lower bits of the APIC id distinguish the cores. 452 * Assumes number of cores is a power of two. 453 */ 454 static void amd_detect_cmp(struct cpuinfo_x86 *c) 455 { 456 unsigned bits; 457 int cpu = smp_processor_id(); 458 459 bits = c->x86_coreid_bits; 460 /* Low order bits define the core id (index of core in socket) */ 461 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1); 462 /* Convert the initial APIC ID into the socket ID */ 463 c->phys_proc_id = c->initial_apicid >> bits; 464 /* use socket ID also for last level cache */ 465 per_cpu(cpu_llc_id, cpu) = c->cpu_die_id = c->phys_proc_id; 466 } 467 468 u32 amd_get_nodes_per_socket(void) 469 { 470 return nodes_per_socket; 471 } 472 EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket); 473 474 static void srat_detect_node(struct cpuinfo_x86 *c) 475 { 476 #ifdef CONFIG_NUMA 477 int cpu = smp_processor_id(); 478 int node; 479 unsigned apicid = c->apicid; 480 481 node = numa_cpu_node(cpu); 482 if (node == NUMA_NO_NODE) 483 node = get_llc_id(cpu); 484 485 /* 486 * On multi-fabric platform (e.g. Numascale NumaChip) a 487 * platform-specific handler needs to be called to fixup some 488 * IDs of the CPU. 489 */ 490 if (x86_cpuinit.fixup_cpu_id) 491 x86_cpuinit.fixup_cpu_id(c, node); 492 493 if (!node_online(node)) { 494 /* 495 * Two possibilities here: 496 * 497 * - The CPU is missing memory and no node was created. In 498 * that case try picking one from a nearby CPU. 499 * 500 * - The APIC IDs differ from the HyperTransport node IDs 501 * which the K8 northbridge parsing fills in. Assume 502 * they are all increased by a constant offset, but in 503 * the same order as the HT nodeids. If that doesn't 504 * result in a usable node fall back to the path for the 505 * previous case. 506 * 507 * This workaround operates directly on the mapping between 508 * APIC ID and NUMA node, assuming certain relationship 509 * between APIC ID, HT node ID and NUMA topology. As going 510 * through CPU mapping may alter the outcome, directly 511 * access __apicid_to_node[]. 512 */ 513 int ht_nodeid = c->initial_apicid; 514 515 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE) 516 node = __apicid_to_node[ht_nodeid]; 517 /* Pick a nearby node */ 518 if (!node_online(node)) 519 node = nearby_node(apicid); 520 } 521 numa_set_node(cpu, node); 522 #endif 523 } 524 525 static void early_init_amd_mc(struct cpuinfo_x86 *c) 526 { 527 #ifdef CONFIG_SMP 528 unsigned bits, ecx; 529 530 /* Multi core CPU? */ 531 if (c->extended_cpuid_level < 0x80000008) 532 return; 533 534 ecx = cpuid_ecx(0x80000008); 535 536 c->x86_max_cores = (ecx & 0xff) + 1; 537 538 /* CPU telling us the core id bits shift? */ 539 bits = (ecx >> 12) & 0xF; 540 541 /* Otherwise recompute */ 542 if (bits == 0) { 543 while ((1 << bits) < c->x86_max_cores) 544 bits++; 545 } 546 547 c->x86_coreid_bits = bits; 548 #endif 549 } 550 551 static void bsp_init_amd(struct cpuinfo_x86 *c) 552 { 553 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { 554 555 if (c->x86 > 0x10 || 556 (c->x86 == 0x10 && c->x86_model >= 0x2)) { 557 u64 val; 558 559 rdmsrl(MSR_K7_HWCR, val); 560 if (!(val & BIT(24))) 561 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n"); 562 } 563 } 564 565 if (c->x86 == 0x15) { 566 unsigned long upperbit; 567 u32 cpuid, assoc; 568 569 cpuid = cpuid_edx(0x80000005); 570 assoc = cpuid >> 16 & 0xff; 571 upperbit = ((cpuid >> 24) << 10) / assoc; 572 573 va_align.mask = (upperbit - 1) & PAGE_MASK; 574 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64; 575 576 /* A random value per boot for bit slice [12:upper_bit) */ 577 va_align.bits = get_random_u32() & va_align.mask; 578 } 579 580 if (cpu_has(c, X86_FEATURE_MWAITX)) 581 use_mwaitx_delay(); 582 583 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 584 u32 ecx; 585 586 ecx = cpuid_ecx(0x8000001e); 587 __max_die_per_package = nodes_per_socket = ((ecx >> 8) & 7) + 1; 588 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) { 589 u64 value; 590 591 rdmsrl(MSR_FAM10H_NODE_ID, value); 592 __max_die_per_package = nodes_per_socket = ((value >> 3) & 7) + 1; 593 } 594 595 if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) && 596 !boot_cpu_has(X86_FEATURE_VIRT_SSBD) && 597 c->x86 >= 0x15 && c->x86 <= 0x17) { 598 unsigned int bit; 599 600 switch (c->x86) { 601 case 0x15: bit = 54; break; 602 case 0x16: bit = 33; break; 603 case 0x17: bit = 10; break; 604 default: return; 605 } 606 /* 607 * Try to cache the base value so further operations can 608 * avoid RMW. If that faults, do not enable SSBD. 609 */ 610 if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) { 611 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD); 612 setup_force_cpu_cap(X86_FEATURE_SSBD); 613 x86_amd_ls_cfg_ssbd_mask = 1ULL << bit; 614 } 615 } 616 617 resctrl_cpu_detect(c); 618 } 619 620 static void early_detect_mem_encrypt(struct cpuinfo_x86 *c) 621 { 622 u64 msr; 623 624 /* 625 * BIOS support is required for SME and SEV. 626 * For SME: If BIOS has enabled SME then adjust x86_phys_bits by 627 * the SME physical address space reduction value. 628 * If BIOS has not enabled SME then don't advertise the 629 * SME feature (set in scattered.c). 630 * If the kernel has not enabled SME via any means then 631 * don't advertise the SME feature. 632 * For SEV: If BIOS has not enabled SEV then don't advertise the 633 * SEV and SEV_ES feature (set in scattered.c). 634 * 635 * In all cases, since support for SME and SEV requires long mode, 636 * don't advertise the feature under CONFIG_X86_32. 637 */ 638 if (cpu_has(c, X86_FEATURE_SME) || cpu_has(c, X86_FEATURE_SEV)) { 639 /* Check if memory encryption is enabled */ 640 rdmsrl(MSR_AMD64_SYSCFG, msr); 641 if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT)) 642 goto clear_all; 643 644 /* 645 * Always adjust physical address bits. Even though this 646 * will be a value above 32-bits this is still done for 647 * CONFIG_X86_32 so that accurate values are reported. 648 */ 649 c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f; 650 651 if (IS_ENABLED(CONFIG_X86_32)) 652 goto clear_all; 653 654 if (!sme_me_mask) 655 setup_clear_cpu_cap(X86_FEATURE_SME); 656 657 rdmsrl(MSR_K7_HWCR, msr); 658 if (!(msr & MSR_K7_HWCR_SMMLOCK)) 659 goto clear_sev; 660 661 return; 662 663 clear_all: 664 setup_clear_cpu_cap(X86_FEATURE_SME); 665 clear_sev: 666 setup_clear_cpu_cap(X86_FEATURE_SEV); 667 setup_clear_cpu_cap(X86_FEATURE_SEV_ES); 668 } 669 } 670 671 static void early_init_amd(struct cpuinfo_x86 *c) 672 { 673 u64 value; 674 u32 dummy; 675 676 early_init_amd_mc(c); 677 678 if (c->x86 >= 0xf) 679 set_cpu_cap(c, X86_FEATURE_K8); 680 681 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); 682 683 /* 684 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 685 * with P/T states and does not stop in deep C-states 686 */ 687 if (c->x86_power & (1 << 8)) { 688 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 689 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 690 } 691 692 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */ 693 if (c->x86_power & BIT(12)) 694 set_cpu_cap(c, X86_FEATURE_ACC_POWER); 695 696 /* Bit 14 indicates the Runtime Average Power Limit interface. */ 697 if (c->x86_power & BIT(14)) 698 set_cpu_cap(c, X86_FEATURE_RAPL); 699 700 #ifdef CONFIG_X86_64 701 set_cpu_cap(c, X86_FEATURE_SYSCALL32); 702 #else 703 /* Set MTRR capability flag if appropriate */ 704 if (c->x86 == 5) 705 if (c->x86_model == 13 || c->x86_model == 9 || 706 (c->x86_model == 8 && c->x86_stepping >= 8)) 707 set_cpu_cap(c, X86_FEATURE_K6_MTRR); 708 #endif 709 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) 710 /* 711 * ApicID can always be treated as an 8-bit value for AMD APIC versions 712 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we 713 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families 714 * after 16h. 715 */ 716 if (boot_cpu_has(X86_FEATURE_APIC)) { 717 if (c->x86 > 0x16) 718 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 719 else if (c->x86 >= 0xf) { 720 /* check CPU config space for extended APIC ID */ 721 unsigned int val; 722 723 val = read_pci_config(0, 24, 0, 0x68); 724 if ((val >> 17 & 0x3) == 0x3) 725 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 726 } 727 } 728 #endif 729 730 /* 731 * This is only needed to tell the kernel whether to use VMCALL 732 * and VMMCALL. VMMCALL is never executed except under virt, so 733 * we can set it unconditionally. 734 */ 735 set_cpu_cap(c, X86_FEATURE_VMMCALL); 736 737 /* F16h erratum 793, CVE-2013-6885 */ 738 if (c->x86 == 0x16 && c->x86_model <= 0xf) 739 msr_set_bit(MSR_AMD64_LS_CFG, 15); 740 741 /* 742 * Check whether the machine is affected by erratum 400. This is 743 * used to select the proper idle routine and to enable the check 744 * whether the machine is affected in arch_post_acpi_init(), which 745 * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check. 746 */ 747 if (cpu_has_amd_erratum(c, amd_erratum_400)) 748 set_cpu_bug(c, X86_BUG_AMD_E400); 749 750 early_detect_mem_encrypt(c); 751 752 /* Re-enable TopologyExtensions if switched off by BIOS */ 753 if (c->x86 == 0x15 && 754 (c->x86_model >= 0x10 && c->x86_model <= 0x6f) && 755 !cpu_has(c, X86_FEATURE_TOPOEXT)) { 756 757 if (msr_set_bit(0xc0011005, 54) > 0) { 758 rdmsrl(0xc0011005, value); 759 if (value & BIT_64(54)) { 760 set_cpu_cap(c, X86_FEATURE_TOPOEXT); 761 pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n"); 762 } 763 } 764 } 765 766 if (cpu_has(c, X86_FEATURE_TOPOEXT)) 767 smp_num_siblings = ((cpuid_ebx(0x8000001e) >> 8) & 0xff) + 1; 768 } 769 770 static void init_amd_k8(struct cpuinfo_x86 *c) 771 { 772 u32 level; 773 u64 value; 774 775 /* On C+ stepping K8 rep microcode works well for copy/memset */ 776 level = cpuid_eax(1); 777 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) 778 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 779 780 /* 781 * Some BIOSes incorrectly force this feature, but only K8 revision D 782 * (model = 0x14) and later actually support it. 783 * (AMD Erratum #110, docId: 25759). 784 */ 785 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) { 786 clear_cpu_cap(c, X86_FEATURE_LAHF_LM); 787 if (!rdmsrl_amd_safe(0xc001100d, &value)) { 788 value &= ~BIT_64(32); 789 wrmsrl_amd_safe(0xc001100d, value); 790 } 791 } 792 793 if (!c->x86_model_id[0]) 794 strcpy(c->x86_model_id, "Hammer"); 795 796 #ifdef CONFIG_SMP 797 /* 798 * Disable TLB flush filter by setting HWCR.FFDIS on K8 799 * bit 6 of msr C001_0015 800 * 801 * Errata 63 for SH-B3 steppings 802 * Errata 122 for all steppings (F+ have it disabled by default) 803 */ 804 msr_set_bit(MSR_K7_HWCR, 6); 805 #endif 806 set_cpu_bug(c, X86_BUG_SWAPGS_FENCE); 807 } 808 809 static void init_amd_gh(struct cpuinfo_x86 *c) 810 { 811 #ifdef CONFIG_MMCONF_FAM10H 812 /* do this for boot cpu */ 813 if (c == &boot_cpu_data) 814 check_enable_amd_mmconf_dmi(); 815 816 fam10h_check_enable_mmcfg(); 817 #endif 818 819 /* 820 * Disable GART TLB Walk Errors on Fam10h. We do this here because this 821 * is always needed when GART is enabled, even in a kernel which has no 822 * MCE support built in. BIOS should disable GartTlbWlk Errors already. 823 * If it doesn't, we do it here as suggested by the BKDG. 824 * 825 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012 826 */ 827 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10); 828 829 /* 830 * On family 10h BIOS may not have properly enabled WC+ support, causing 831 * it to be converted to CD memtype. This may result in performance 832 * degradation for certain nested-paging guests. Prevent this conversion 833 * by clearing bit 24 in MSR_AMD64_BU_CFG2. 834 * 835 * NOTE: we want to use the _safe accessors so as not to #GP kvm 836 * guests on older kvm hosts. 837 */ 838 msr_clear_bit(MSR_AMD64_BU_CFG2, 24); 839 840 if (cpu_has_amd_erratum(c, amd_erratum_383)) 841 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH); 842 } 843 844 static void init_amd_ln(struct cpuinfo_x86 *c) 845 { 846 /* 847 * Apply erratum 665 fix unconditionally so machines without a BIOS 848 * fix work. 849 */ 850 msr_set_bit(MSR_AMD64_DE_CFG, 31); 851 } 852 853 static bool rdrand_force; 854 855 static int __init rdrand_cmdline(char *str) 856 { 857 if (!str) 858 return -EINVAL; 859 860 if (!strcmp(str, "force")) 861 rdrand_force = true; 862 else 863 return -EINVAL; 864 865 return 0; 866 } 867 early_param("rdrand", rdrand_cmdline); 868 869 static void clear_rdrand_cpuid_bit(struct cpuinfo_x86 *c) 870 { 871 /* 872 * Saving of the MSR used to hide the RDRAND support during 873 * suspend/resume is done by arch/x86/power/cpu.c, which is 874 * dependent on CONFIG_PM_SLEEP. 875 */ 876 if (!IS_ENABLED(CONFIG_PM_SLEEP)) 877 return; 878 879 /* 880 * The self-test can clear X86_FEATURE_RDRAND, so check for 881 * RDRAND support using the CPUID function directly. 882 */ 883 if (!(cpuid_ecx(1) & BIT(30)) || rdrand_force) 884 return; 885 886 msr_clear_bit(MSR_AMD64_CPUID_FN_1, 62); 887 888 /* 889 * Verify that the CPUID change has occurred in case the kernel is 890 * running virtualized and the hypervisor doesn't support the MSR. 891 */ 892 if (cpuid_ecx(1) & BIT(30)) { 893 pr_info_once("BIOS may not properly restore RDRAND after suspend, but hypervisor does not support hiding RDRAND via CPUID.\n"); 894 return; 895 } 896 897 clear_cpu_cap(c, X86_FEATURE_RDRAND); 898 pr_info_once("BIOS may not properly restore RDRAND after suspend, hiding RDRAND via CPUID. Use rdrand=force to reenable.\n"); 899 } 900 901 static void init_amd_jg(struct cpuinfo_x86 *c) 902 { 903 /* 904 * Some BIOS implementations do not restore proper RDRAND support 905 * across suspend and resume. Check on whether to hide the RDRAND 906 * instruction support via CPUID. 907 */ 908 clear_rdrand_cpuid_bit(c); 909 } 910 911 static void init_amd_bd(struct cpuinfo_x86 *c) 912 { 913 u64 value; 914 915 /* 916 * The way access filter has a performance penalty on some workloads. 917 * Disable it on the affected CPUs. 918 */ 919 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) { 920 if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) { 921 value |= 0x1E; 922 wrmsrl_safe(MSR_F15H_IC_CFG, value); 923 } 924 } 925 926 /* 927 * Some BIOS implementations do not restore proper RDRAND support 928 * across suspend and resume. Check on whether to hide the RDRAND 929 * instruction support via CPUID. 930 */ 931 clear_rdrand_cpuid_bit(c); 932 } 933 934 void init_spectral_chicken(struct cpuinfo_x86 *c) 935 { 936 #ifdef CONFIG_CPU_UNRET_ENTRY 937 u64 value; 938 939 /* 940 * On Zen2 we offer this chicken (bit) on the altar of Speculation. 941 * 942 * This suppresses speculation from the middle of a basic block, i.e. it 943 * suppresses non-branch predictions. 944 * 945 * We use STIBP as a heuristic to filter out Zen2 from the rest of F17H 946 */ 947 if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && cpu_has(c, X86_FEATURE_AMD_STIBP)) { 948 if (!rdmsrl_safe(MSR_ZEN2_SPECTRAL_CHICKEN, &value)) { 949 value |= MSR_ZEN2_SPECTRAL_CHICKEN_BIT; 950 wrmsrl_safe(MSR_ZEN2_SPECTRAL_CHICKEN, value); 951 } 952 } 953 #endif 954 /* 955 * Work around Erratum 1386. The XSAVES instruction malfunctions in 956 * certain circumstances on Zen1/2 uarch, and not all parts have had 957 * updated microcode at the time of writing (March 2023). 958 * 959 * Affected parts all have no supervisor XSAVE states, meaning that 960 * the XSAVEC instruction (which works fine) is equivalent. 961 */ 962 clear_cpu_cap(c, X86_FEATURE_XSAVES); 963 } 964 965 static void init_amd_zn(struct cpuinfo_x86 *c) 966 { 967 set_cpu_cap(c, X86_FEATURE_ZEN); 968 969 #ifdef CONFIG_NUMA 970 node_reclaim_distance = 32; 971 #endif 972 973 /* Fix up CPUID bits, but only if not virtualised. */ 974 if (!cpu_has(c, X86_FEATURE_HYPERVISOR)) { 975 976 /* Erratum 1076: CPB feature bit not being set in CPUID. */ 977 if (!cpu_has(c, X86_FEATURE_CPB)) 978 set_cpu_cap(c, X86_FEATURE_CPB); 979 980 /* 981 * Zen3 (Fam19 model < 0x10) parts are not susceptible to 982 * Branch Type Confusion, but predate the allocation of the 983 * BTC_NO bit. 984 */ 985 if (c->x86 == 0x19 && !cpu_has(c, X86_FEATURE_BTC_NO)) 986 set_cpu_cap(c, X86_FEATURE_BTC_NO); 987 } 988 } 989 990 static bool cpu_has_zenbleed_microcode(void) 991 { 992 u32 good_rev = 0; 993 994 switch (boot_cpu_data.x86_model) { 995 case 0x30 ... 0x3f: good_rev = 0x0830107a; break; 996 case 0x60 ... 0x67: good_rev = 0x0860010b; break; 997 case 0x68 ... 0x6f: good_rev = 0x08608105; break; 998 case 0x70 ... 0x7f: good_rev = 0x08701032; break; 999 case 0xa0 ... 0xaf: good_rev = 0x08a00008; break; 1000 1001 default: 1002 return false; 1003 break; 1004 } 1005 1006 if (boot_cpu_data.microcode < good_rev) 1007 return false; 1008 1009 return true; 1010 } 1011 1012 static void zenbleed_check(struct cpuinfo_x86 *c) 1013 { 1014 if (!cpu_has_amd_erratum(c, amd_zenbleed)) 1015 return; 1016 1017 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) 1018 return; 1019 1020 if (!cpu_has(c, X86_FEATURE_AVX)) 1021 return; 1022 1023 if (!cpu_has_zenbleed_microcode()) { 1024 pr_notice_once("Zenbleed: please update your microcode for the most optimal fix\n"); 1025 msr_set_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT); 1026 } else { 1027 msr_clear_bit(MSR_AMD64_DE_CFG, MSR_AMD64_DE_CFG_ZEN2_FP_BACKUP_FIX_BIT); 1028 } 1029 } 1030 1031 static void init_amd(struct cpuinfo_x86 *c) 1032 { 1033 early_init_amd(c); 1034 1035 /* 1036 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 1037 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 1038 */ 1039 clear_cpu_cap(c, 0*32+31); 1040 1041 if (c->x86 >= 0x10) 1042 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 1043 1044 /* AMD FSRM also implies FSRS */ 1045 if (cpu_has(c, X86_FEATURE_FSRM)) 1046 set_cpu_cap(c, X86_FEATURE_FSRS); 1047 1048 /* get apicid instead of initial apic id from cpuid */ 1049 c->apicid = hard_smp_processor_id(); 1050 1051 /* K6s reports MCEs but don't actually have all the MSRs */ 1052 if (c->x86 < 6) 1053 clear_cpu_cap(c, X86_FEATURE_MCE); 1054 1055 switch (c->x86) { 1056 case 4: init_amd_k5(c); break; 1057 case 5: init_amd_k6(c); break; 1058 case 6: init_amd_k7(c); break; 1059 case 0xf: init_amd_k8(c); break; 1060 case 0x10: init_amd_gh(c); break; 1061 case 0x12: init_amd_ln(c); break; 1062 case 0x15: init_amd_bd(c); break; 1063 case 0x16: init_amd_jg(c); break; 1064 case 0x17: init_spectral_chicken(c); 1065 fallthrough; 1066 case 0x19: init_amd_zn(c); break; 1067 } 1068 1069 /* 1070 * Enable workaround for FXSAVE leak on CPUs 1071 * without a XSaveErPtr feature 1072 */ 1073 if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR))) 1074 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK); 1075 1076 cpu_detect_cache_sizes(c); 1077 1078 amd_detect_cmp(c); 1079 amd_get_topology(c); 1080 srat_detect_node(c); 1081 1082 init_amd_cacheinfo(c); 1083 1084 if (!cpu_has(c, X86_FEATURE_LFENCE_RDTSC) && cpu_has(c, X86_FEATURE_XMM2)) { 1085 /* 1086 * Use LFENCE for execution serialization. On families which 1087 * don't have that MSR, LFENCE is already serializing. 1088 * msr_set_bit() uses the safe accessors, too, even if the MSR 1089 * is not present. 1090 */ 1091 msr_set_bit(MSR_AMD64_DE_CFG, 1092 MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT); 1093 1094 /* A serializing LFENCE stops RDTSC speculation */ 1095 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 1096 } 1097 1098 /* 1099 * Family 0x12 and above processors have APIC timer 1100 * running in deep C states. 1101 */ 1102 if (c->x86 > 0x11) 1103 set_cpu_cap(c, X86_FEATURE_ARAT); 1104 1105 /* 3DNow or LM implies PREFETCHW */ 1106 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH)) 1107 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM)) 1108 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH); 1109 1110 /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */ 1111 if (!cpu_feature_enabled(X86_FEATURE_XENPV)) 1112 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); 1113 1114 /* 1115 * Turn on the Instructions Retired free counter on machines not 1116 * susceptible to erratum #1054 "Instructions Retired Performance 1117 * Counter May Be Inaccurate". 1118 */ 1119 if (cpu_has(c, X86_FEATURE_IRPERF) && 1120 !cpu_has_amd_erratum(c, amd_erratum_1054)) 1121 msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT); 1122 1123 check_null_seg_clears_base(c); 1124 1125 /* 1126 * Make sure EFER[AIBRSE - Automatic IBRS Enable] is set. The APs are brought up 1127 * using the trampoline code and as part of it, MSR_EFER gets prepared there in 1128 * order to be replicated onto them. Regardless, set it here again, if not set, 1129 * to protect against any future refactoring/code reorganization which might 1130 * miss setting this important bit. 1131 */ 1132 if (spectre_v2_in_eibrs_mode(spectre_v2_enabled) && 1133 cpu_has(c, X86_FEATURE_AUTOIBRS)) 1134 WARN_ON_ONCE(msr_set_bit(MSR_EFER, _EFER_AUTOIBRS)); 1135 1136 zenbleed_check(c); 1137 1138 if (cpu_has_amd_erratum(c, amd_div0)) { 1139 pr_notice_once("AMD Zen1 DIV0 bug detected. Disable SMT for full protection.\n"); 1140 setup_force_cpu_bug(X86_BUG_DIV0); 1141 } 1142 } 1143 1144 #ifdef CONFIG_X86_32 1145 static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size) 1146 { 1147 /* AMD errata T13 (order #21922) */ 1148 if (c->x86 == 6) { 1149 /* Duron Rev A0 */ 1150 if (c->x86_model == 3 && c->x86_stepping == 0) 1151 size = 64; 1152 /* Tbird rev A1/A2 */ 1153 if (c->x86_model == 4 && 1154 (c->x86_stepping == 0 || c->x86_stepping == 1)) 1155 size = 256; 1156 } 1157 return size; 1158 } 1159 #endif 1160 1161 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) 1162 { 1163 u32 ebx, eax, ecx, edx; 1164 u16 mask = 0xfff; 1165 1166 if (c->x86 < 0xf) 1167 return; 1168 1169 if (c->extended_cpuid_level < 0x80000006) 1170 return; 1171 1172 cpuid(0x80000006, &eax, &ebx, &ecx, &edx); 1173 1174 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask; 1175 tlb_lli_4k[ENTRIES] = ebx & mask; 1176 1177 /* 1178 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB 1179 * characteristics from the CPUID function 0x80000005 instead. 1180 */ 1181 if (c->x86 == 0xf) { 1182 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 1183 mask = 0xff; 1184 } 1185 1186 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 1187 if (!((eax >> 16) & mask)) 1188 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff; 1189 else 1190 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask; 1191 1192 /* a 4M entry uses two 2M entries */ 1193 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1; 1194 1195 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 1196 if (!(eax & mask)) { 1197 /* Erratum 658 */ 1198 if (c->x86 == 0x15 && c->x86_model <= 0x1f) { 1199 tlb_lli_2m[ENTRIES] = 1024; 1200 } else { 1201 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 1202 tlb_lli_2m[ENTRIES] = eax & 0xff; 1203 } 1204 } else 1205 tlb_lli_2m[ENTRIES] = eax & mask; 1206 1207 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1; 1208 } 1209 1210 static const struct cpu_dev amd_cpu_dev = { 1211 .c_vendor = "AMD", 1212 .c_ident = { "AuthenticAMD" }, 1213 #ifdef CONFIG_X86_32 1214 .legacy_models = { 1215 { .family = 4, .model_names = 1216 { 1217 [3] = "486 DX/2", 1218 [7] = "486 DX/2-WB", 1219 [8] = "486 DX/4", 1220 [9] = "486 DX/4-WB", 1221 [14] = "Am5x86-WT", 1222 [15] = "Am5x86-WB" 1223 } 1224 }, 1225 }, 1226 .legacy_cache_size = amd_size_cache, 1227 #endif 1228 .c_early_init = early_init_amd, 1229 .c_detect_tlb = cpu_detect_tlb_amd, 1230 .c_bsp_init = bsp_init_amd, 1231 .c_init = init_amd, 1232 .c_x86_vendor = X86_VENDOR_AMD, 1233 }; 1234 1235 cpu_dev_register(amd_cpu_dev); 1236 1237 static DEFINE_PER_CPU_READ_MOSTLY(unsigned long[4], amd_dr_addr_mask); 1238 1239 static unsigned int amd_msr_dr_addr_masks[] = { 1240 MSR_F16H_DR0_ADDR_MASK, 1241 MSR_F16H_DR1_ADDR_MASK, 1242 MSR_F16H_DR1_ADDR_MASK + 1, 1243 MSR_F16H_DR1_ADDR_MASK + 2 1244 }; 1245 1246 void amd_set_dr_addr_mask(unsigned long mask, unsigned int dr) 1247 { 1248 int cpu = smp_processor_id(); 1249 1250 if (!cpu_feature_enabled(X86_FEATURE_BPEXT)) 1251 return; 1252 1253 if (WARN_ON_ONCE(dr >= ARRAY_SIZE(amd_msr_dr_addr_masks))) 1254 return; 1255 1256 if (per_cpu(amd_dr_addr_mask, cpu)[dr] == mask) 1257 return; 1258 1259 wrmsr(amd_msr_dr_addr_masks[dr], mask, 0); 1260 per_cpu(amd_dr_addr_mask, cpu)[dr] = mask; 1261 } 1262 1263 unsigned long amd_get_dr_addr_mask(unsigned int dr) 1264 { 1265 if (!cpu_feature_enabled(X86_FEATURE_BPEXT)) 1266 return 0; 1267 1268 if (WARN_ON_ONCE(dr >= ARRAY_SIZE(amd_msr_dr_addr_masks))) 1269 return 0; 1270 1271 return per_cpu(amd_dr_addr_mask[dr], smp_processor_id()); 1272 } 1273 EXPORT_SYMBOL_GPL(amd_get_dr_addr_mask); 1274 1275 u32 amd_get_highest_perf(void) 1276 { 1277 struct cpuinfo_x86 *c = &boot_cpu_data; 1278 1279 if (c->x86 == 0x17 && ((c->x86_model >= 0x30 && c->x86_model < 0x40) || 1280 (c->x86_model >= 0x70 && c->x86_model < 0x80))) 1281 return 166; 1282 1283 if (c->x86 == 0x19 && ((c->x86_model >= 0x20 && c->x86_model < 0x30) || 1284 (c->x86_model >= 0x40 && c->x86_model < 0x70))) 1285 return 166; 1286 1287 return 255; 1288 } 1289 EXPORT_SYMBOL_GPL(amd_get_highest_perf); 1290 1291 static void zenbleed_check_cpu(void *unused) 1292 { 1293 struct cpuinfo_x86 *c = &cpu_data(smp_processor_id()); 1294 1295 zenbleed_check(c); 1296 } 1297 1298 void amd_check_microcode(void) 1299 { 1300 on_each_cpu(zenbleed_check_cpu, NULL, 1); 1301 } 1302 1303 bool cpu_has_ibpb_brtype_microcode(void) 1304 { 1305 switch (boot_cpu_data.x86) { 1306 /* Zen1/2 IBPB flushes branch type predictions too. */ 1307 case 0x17: 1308 return boot_cpu_has(X86_FEATURE_AMD_IBPB); 1309 case 0x19: 1310 /* Poke the MSR bit on Zen3/4 to check its presence. */ 1311 if (!wrmsrl_safe(MSR_IA32_PRED_CMD, PRED_CMD_SBPB)) { 1312 setup_force_cpu_cap(X86_FEATURE_SBPB); 1313 return true; 1314 } else { 1315 return false; 1316 } 1317 default: 1318 return false; 1319 } 1320 } 1321 1322 /* 1323 * Issue a DIV 0/1 insn to clear any division data from previous DIV 1324 * operations. 1325 */ 1326 void noinstr amd_clear_divider(void) 1327 { 1328 asm volatile(ALTERNATIVE("", "div %2\n\t", X86_BUG_DIV0) 1329 :: "a" (0), "d" (0), "r" (1)); 1330 } 1331