1 #include <linux/init.h> 2 #include <linux/bitops.h> 3 #include <linux/mm.h> 4 #include <asm/io.h> 5 #include <asm/processor.h> 6 #include <asm/apic.h> 7 8 #include <mach_apic.h> 9 #include "cpu.h" 10 11 /* 12 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause 13 * misexecution of code under Linux. Owners of such processors should 14 * contact AMD for precise details and a CPU swap. 15 * 16 * See http://www.multimania.com/poulot/k6bug.html 17 * http://www.amd.com/K6/k6docs/revgd.html 18 * 19 * The following test is erm.. interesting. AMD neglected to up 20 * the chip setting when fixing the bug but they also tweaked some 21 * performance at the same time.. 22 */ 23 24 extern void vide(void); 25 __asm__(".align 4\nvide: ret"); 26 27 static void __cpuinit early_init_amd(struct cpuinfo_x86 *c) 28 { 29 if (cpuid_eax(0x80000000) >= 0x80000007) { 30 c->x86_power = cpuid_edx(0x80000007); 31 if (c->x86_power & (1<<8)) 32 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 33 } 34 35 /* Set MTRR capability flag if appropriate */ 36 if (c->x86_model == 13 || c->x86_model == 9 || 37 (c->x86_model == 8 && c->x86_mask >= 8)) 38 set_cpu_cap(c, X86_FEATURE_K6_MTRR); 39 } 40 41 static void __cpuinit init_amd(struct cpuinfo_x86 *c) 42 { 43 u32 l, h; 44 int mbytes = num_physpages >> (20-PAGE_SHIFT); 45 int r; 46 47 #ifdef CONFIG_SMP 48 unsigned long long value; 49 50 /* 51 * Disable TLB flush filter by setting HWCR.FFDIS on K8 52 * bit 6 of msr C001_0015 53 * 54 * Errata 63 for SH-B3 steppings 55 * Errata 122 for all steppings (F+ have it disabled by default) 56 */ 57 if (c->x86 == 15) { 58 rdmsrl(MSR_K7_HWCR, value); 59 value |= 1 << 6; 60 wrmsrl(MSR_K7_HWCR, value); 61 } 62 #endif 63 64 early_init_amd(c); 65 66 /* 67 * FIXME: We should handle the K5 here. Set up the write 68 * range and also turn on MSR 83 bits 4 and 31 (write alloc, 69 * no bus pipeline) 70 */ 71 72 /* 73 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 74 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 75 */ 76 clear_cpu_cap(c, 0*32+31); 77 78 r = get_model_name(c); 79 80 switch (c->x86) { 81 case 4: 82 /* 83 * General Systems BIOSen alias the cpu frequency registers 84 * of the Elan at 0x000df000. Unfortuantly, one of the Linux 85 * drivers subsequently pokes it, and changes the CPU speed. 86 * Workaround : Remove the unneeded alias. 87 */ 88 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ 89 #define CBAR_ENB (0x80000000) 90 #define CBAR_KEY (0X000000CB) 91 if (c->x86_model == 9 || c->x86_model == 10) { 92 if (inl (CBAR) & CBAR_ENB) 93 outl (0 | CBAR_KEY, CBAR); 94 } 95 break; 96 case 5: 97 if (c->x86_model < 6) { 98 /* Based on AMD doc 20734R - June 2000 */ 99 if (c->x86_model == 0) { 100 clear_cpu_cap(c, X86_FEATURE_APIC); 101 set_cpu_cap(c, X86_FEATURE_PGE); 102 } 103 break; 104 } 105 106 if (c->x86_model == 6 && c->x86_mask == 1) { 107 const int K6_BUG_LOOP = 1000000; 108 int n; 109 void (*f_vide)(void); 110 unsigned long d, d2; 111 112 printk(KERN_INFO "AMD K6 stepping B detected - "); 113 114 /* 115 * It looks like AMD fixed the 2.6.2 bug and improved indirect 116 * calls at the same time. 117 */ 118 119 n = K6_BUG_LOOP; 120 f_vide = vide; 121 rdtscl(d); 122 while (n--) 123 f_vide(); 124 rdtscl(d2); 125 d = d2-d; 126 127 if (d > 20*K6_BUG_LOOP) 128 printk("system stability may be impaired when more than 32 MB are used.\n"); 129 else 130 printk("probably OK (after B9730xxxx).\n"); 131 printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n"); 132 } 133 134 /* K6 with old style WHCR */ 135 if (c->x86_model < 8 || 136 (c->x86_model == 8 && c->x86_mask < 8)) { 137 /* We can only write allocate on the low 508Mb */ 138 if (mbytes > 508) 139 mbytes = 508; 140 141 rdmsr(MSR_K6_WHCR, l, h); 142 if ((l&0x0000FFFF) == 0) { 143 unsigned long flags; 144 l = (1<<0)|((mbytes/4)<<1); 145 local_irq_save(flags); 146 wbinvd(); 147 wrmsr(MSR_K6_WHCR, l, h); 148 local_irq_restore(flags); 149 printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n", 150 mbytes); 151 } 152 break; 153 } 154 155 if ((c->x86_model == 8 && c->x86_mask > 7) || 156 c->x86_model == 9 || c->x86_model == 13) { 157 /* The more serious chips .. */ 158 159 if (mbytes > 4092) 160 mbytes = 4092; 161 162 rdmsr(MSR_K6_WHCR, l, h); 163 if ((l&0xFFFF0000) == 0) { 164 unsigned long flags; 165 l = ((mbytes>>2)<<22)|(1<<16); 166 local_irq_save(flags); 167 wbinvd(); 168 wrmsr(MSR_K6_WHCR, l, h); 169 local_irq_restore(flags); 170 printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n", 171 mbytes); 172 } 173 174 break; 175 } 176 177 if (c->x86_model == 10) { 178 /* AMD Geode LX is model 10 */ 179 /* placeholder for any needed mods */ 180 break; 181 } 182 break; 183 case 6: /* An Athlon/Duron */ 184 185 /* 186 * Bit 15 of Athlon specific MSR 15, needs to be 0 187 * to enable SSE on Palomino/Morgan/Barton CPU's. 188 * If the BIOS didn't enable it already, enable it here. 189 */ 190 if (c->x86_model >= 6 && c->x86_model <= 10) { 191 if (!cpu_has(c, X86_FEATURE_XMM)) { 192 printk(KERN_INFO "Enabling disabled K7/SSE Support.\n"); 193 rdmsr(MSR_K7_HWCR, l, h); 194 l &= ~0x00008000; 195 wrmsr(MSR_K7_HWCR, l, h); 196 set_cpu_cap(c, X86_FEATURE_XMM); 197 } 198 } 199 200 /* 201 * It's been determined by AMD that Athlons since model 8 stepping 1 202 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx 203 * As per AMD technical note 27212 0.2 204 */ 205 if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) { 206 rdmsr(MSR_K7_CLK_CTL, l, h); 207 if ((l & 0xfff00000) != 0x20000000) { 208 printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l, 209 ((l & 0x000fffff)|0x20000000)); 210 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); 211 } 212 } 213 break; 214 } 215 216 switch (c->x86) { 217 case 15: 218 /* Use K8 tuning for Fam10h and Fam11h */ 219 case 0x10: 220 case 0x11: 221 set_cpu_cap(c, X86_FEATURE_K8); 222 break; 223 case 6: 224 set_cpu_cap(c, X86_FEATURE_K7); 225 break; 226 } 227 if (c->x86 >= 6) 228 set_cpu_cap(c, X86_FEATURE_FXSAVE_LEAK); 229 230 display_cacheinfo(c); 231 232 if (cpuid_eax(0x80000000) >= 0x80000008) 233 c->x86_max_cores = (cpuid_ecx(0x80000008) & 0xff) + 1; 234 235 #ifdef CONFIG_X86_HT 236 /* 237 * On a AMD multi core setup the lower bits of the APIC id 238 * distinguish the cores. 239 */ 240 if (c->x86_max_cores > 1) { 241 int cpu = smp_processor_id(); 242 unsigned bits = (cpuid_ecx(0x80000008) >> 12) & 0xf; 243 244 if (bits == 0) { 245 while ((1 << bits) < c->x86_max_cores) 246 bits++; 247 } 248 c->cpu_core_id = c->phys_proc_id & ((1<<bits)-1); 249 c->phys_proc_id >>= bits; 250 printk(KERN_INFO "CPU %d(%d) -> Core %d\n", 251 cpu, c->x86_max_cores, c->cpu_core_id); 252 } 253 #endif 254 255 if (cpuid_eax(0x80000000) >= 0x80000006) { 256 if ((c->x86 == 0x10) && (cpuid_edx(0x80000006) & 0xf000)) 257 num_cache_leaves = 4; 258 else 259 num_cache_leaves = 3; 260 } 261 262 /* K6s reports MCEs but don't actually have all the MSRs */ 263 if (c->x86 < 6) 264 clear_cpu_cap(c, X86_FEATURE_MCE); 265 266 if (cpu_has_xmm2) 267 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); 268 } 269 270 static unsigned int __cpuinit amd_size_cache(struct cpuinfo_x86 *c, unsigned int size) 271 { 272 /* AMD errata T13 (order #21922) */ 273 if ((c->x86 == 6)) { 274 if (c->x86_model == 3 && c->x86_mask == 0) /* Duron Rev A0 */ 275 size = 64; 276 if (c->x86_model == 4 && 277 (c->x86_mask == 0 || c->x86_mask == 1)) /* Tbird rev A1/A2 */ 278 size = 256; 279 } 280 return size; 281 } 282 283 static struct cpu_dev amd_cpu_dev __cpuinitdata = { 284 .c_vendor = "AMD", 285 .c_ident = { "AuthenticAMD" }, 286 .c_models = { 287 { .vendor = X86_VENDOR_AMD, .family = 4, .model_names = 288 { 289 [3] = "486 DX/2", 290 [7] = "486 DX/2-WB", 291 [8] = "486 DX/4", 292 [9] = "486 DX/4-WB", 293 [14] = "Am5x86-WT", 294 [15] = "Am5x86-WB" 295 } 296 }, 297 }, 298 .c_early_init = early_init_amd, 299 .c_init = init_amd, 300 .c_size_cache = amd_size_cache, 301 }; 302 303 cpu_vendor_dev_register(X86_VENDOR_AMD, &amd_cpu_dev); 304