1 #include <linux/export.h> 2 #include <linux/bitops.h> 3 #include <linux/elf.h> 4 #include <linux/mm.h> 5 6 #include <linux/io.h> 7 #include <linux/sched.h> 8 #include <linux/sched/clock.h> 9 #include <linux/random.h> 10 #include <asm/processor.h> 11 #include <asm/apic.h> 12 #include <asm/cpu.h> 13 #include <asm/smp.h> 14 #include <asm/pci-direct.h> 15 #include <asm/delay.h> 16 17 #ifdef CONFIG_X86_64 18 # include <asm/mmconfig.h> 19 # include <asm/cacheflush.h> 20 #endif 21 22 #include "cpu.h" 23 24 static const int amd_erratum_383[]; 25 static const int amd_erratum_400[]; 26 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum); 27 28 /* 29 * nodes_per_socket: Stores the number of nodes per socket. 30 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX 31 * Node Identifiers[10:8] 32 */ 33 static u32 nodes_per_socket = 1; 34 35 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) 36 { 37 u32 gprs[8] = { 0 }; 38 int err; 39 40 WARN_ONCE((boot_cpu_data.x86 != 0xf), 41 "%s should only be used on K8!\n", __func__); 42 43 gprs[1] = msr; 44 gprs[7] = 0x9c5a203a; 45 46 err = rdmsr_safe_regs(gprs); 47 48 *p = gprs[0] | ((u64)gprs[2] << 32); 49 50 return err; 51 } 52 53 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val) 54 { 55 u32 gprs[8] = { 0 }; 56 57 WARN_ONCE((boot_cpu_data.x86 != 0xf), 58 "%s should only be used on K8!\n", __func__); 59 60 gprs[0] = (u32)val; 61 gprs[1] = msr; 62 gprs[2] = val >> 32; 63 gprs[7] = 0x9c5a203a; 64 65 return wrmsr_safe_regs(gprs); 66 } 67 68 /* 69 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause 70 * misexecution of code under Linux. Owners of such processors should 71 * contact AMD for precise details and a CPU swap. 72 * 73 * See http://www.multimania.com/poulot/k6bug.html 74 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6" 75 * (Publication # 21266 Issue Date: August 1998) 76 * 77 * The following test is erm.. interesting. AMD neglected to up 78 * the chip setting when fixing the bug but they also tweaked some 79 * performance at the same time.. 80 */ 81 82 extern __visible void vide(void); 83 __asm__(".globl vide\n" 84 ".type vide, @function\n" 85 ".align 4\n" 86 "vide: ret\n"); 87 88 static void init_amd_k5(struct cpuinfo_x86 *c) 89 { 90 #ifdef CONFIG_X86_32 91 /* 92 * General Systems BIOSen alias the cpu frequency registers 93 * of the Elan at 0x000df000. Unfortunately, one of the Linux 94 * drivers subsequently pokes it, and changes the CPU speed. 95 * Workaround : Remove the unneeded alias. 96 */ 97 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ 98 #define CBAR_ENB (0x80000000) 99 #define CBAR_KEY (0X000000CB) 100 if (c->x86_model == 9 || c->x86_model == 10) { 101 if (inl(CBAR) & CBAR_ENB) 102 outl(0 | CBAR_KEY, CBAR); 103 } 104 #endif 105 } 106 107 static void init_amd_k6(struct cpuinfo_x86 *c) 108 { 109 #ifdef CONFIG_X86_32 110 u32 l, h; 111 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT); 112 113 if (c->x86_model < 6) { 114 /* Based on AMD doc 20734R - June 2000 */ 115 if (c->x86_model == 0) { 116 clear_cpu_cap(c, X86_FEATURE_APIC); 117 set_cpu_cap(c, X86_FEATURE_PGE); 118 } 119 return; 120 } 121 122 if (c->x86_model == 6 && c->x86_mask == 1) { 123 const int K6_BUG_LOOP = 1000000; 124 int n; 125 void (*f_vide)(void); 126 u64 d, d2; 127 128 pr_info("AMD K6 stepping B detected - "); 129 130 /* 131 * It looks like AMD fixed the 2.6.2 bug and improved indirect 132 * calls at the same time. 133 */ 134 135 n = K6_BUG_LOOP; 136 f_vide = vide; 137 d = rdtsc(); 138 while (n--) 139 f_vide(); 140 d2 = rdtsc(); 141 d = d2-d; 142 143 if (d > 20*K6_BUG_LOOP) 144 pr_cont("system stability may be impaired when more than 32 MB are used.\n"); 145 else 146 pr_cont("probably OK (after B9730xxxx).\n"); 147 } 148 149 /* K6 with old style WHCR */ 150 if (c->x86_model < 8 || 151 (c->x86_model == 8 && c->x86_mask < 8)) { 152 /* We can only write allocate on the low 508Mb */ 153 if (mbytes > 508) 154 mbytes = 508; 155 156 rdmsr(MSR_K6_WHCR, l, h); 157 if ((l&0x0000FFFF) == 0) { 158 unsigned long flags; 159 l = (1<<0)|((mbytes/4)<<1); 160 local_irq_save(flags); 161 wbinvd(); 162 wrmsr(MSR_K6_WHCR, l, h); 163 local_irq_restore(flags); 164 pr_info("Enabling old style K6 write allocation for %d Mb\n", 165 mbytes); 166 } 167 return; 168 } 169 170 if ((c->x86_model == 8 && c->x86_mask > 7) || 171 c->x86_model == 9 || c->x86_model == 13) { 172 /* The more serious chips .. */ 173 174 if (mbytes > 4092) 175 mbytes = 4092; 176 177 rdmsr(MSR_K6_WHCR, l, h); 178 if ((l&0xFFFF0000) == 0) { 179 unsigned long flags; 180 l = ((mbytes>>2)<<22)|(1<<16); 181 local_irq_save(flags); 182 wbinvd(); 183 wrmsr(MSR_K6_WHCR, l, h); 184 local_irq_restore(flags); 185 pr_info("Enabling new style K6 write allocation for %d Mb\n", 186 mbytes); 187 } 188 189 return; 190 } 191 192 if (c->x86_model == 10) { 193 /* AMD Geode LX is model 10 */ 194 /* placeholder for any needed mods */ 195 return; 196 } 197 #endif 198 } 199 200 static void init_amd_k7(struct cpuinfo_x86 *c) 201 { 202 #ifdef CONFIG_X86_32 203 u32 l, h; 204 205 /* 206 * Bit 15 of Athlon specific MSR 15, needs to be 0 207 * to enable SSE on Palomino/Morgan/Barton CPU's. 208 * If the BIOS didn't enable it already, enable it here. 209 */ 210 if (c->x86_model >= 6 && c->x86_model <= 10) { 211 if (!cpu_has(c, X86_FEATURE_XMM)) { 212 pr_info("Enabling disabled K7/SSE Support.\n"); 213 msr_clear_bit(MSR_K7_HWCR, 15); 214 set_cpu_cap(c, X86_FEATURE_XMM); 215 } 216 } 217 218 /* 219 * It's been determined by AMD that Athlons since model 8 stepping 1 220 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx 221 * As per AMD technical note 27212 0.2 222 */ 223 if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) { 224 rdmsr(MSR_K7_CLK_CTL, l, h); 225 if ((l & 0xfff00000) != 0x20000000) { 226 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", 227 l, ((l & 0x000fffff)|0x20000000)); 228 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); 229 } 230 } 231 232 set_cpu_cap(c, X86_FEATURE_K7); 233 234 /* calling is from identify_secondary_cpu() ? */ 235 if (!c->cpu_index) 236 return; 237 238 /* 239 * Certain Athlons might work (for various values of 'work') in SMP 240 * but they are not certified as MP capable. 241 */ 242 /* Athlon 660/661 is valid. */ 243 if ((c->x86_model == 6) && ((c->x86_mask == 0) || 244 (c->x86_mask == 1))) 245 return; 246 247 /* Duron 670 is valid */ 248 if ((c->x86_model == 7) && (c->x86_mask == 0)) 249 return; 250 251 /* 252 * Athlon 662, Duron 671, and Athlon >model 7 have capability 253 * bit. It's worth noting that the A5 stepping (662) of some 254 * Athlon XP's have the MP bit set. 255 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for 256 * more. 257 */ 258 if (((c->x86_model == 6) && (c->x86_mask >= 2)) || 259 ((c->x86_model == 7) && (c->x86_mask >= 1)) || 260 (c->x86_model > 7)) 261 if (cpu_has(c, X86_FEATURE_MP)) 262 return; 263 264 /* If we get here, not a certified SMP capable AMD system. */ 265 266 /* 267 * Don't taint if we are running SMP kernel on a single non-MP 268 * approved Athlon 269 */ 270 WARN_ONCE(1, "WARNING: This combination of AMD" 271 " processors is not suitable for SMP.\n"); 272 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); 273 #endif 274 } 275 276 #ifdef CONFIG_NUMA 277 /* 278 * To workaround broken NUMA config. Read the comment in 279 * srat_detect_node(). 280 */ 281 static int nearby_node(int apicid) 282 { 283 int i, node; 284 285 for (i = apicid - 1; i >= 0; i--) { 286 node = __apicid_to_node[i]; 287 if (node != NUMA_NO_NODE && node_online(node)) 288 return node; 289 } 290 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { 291 node = __apicid_to_node[i]; 292 if (node != NUMA_NO_NODE && node_online(node)) 293 return node; 294 } 295 return first_node(node_online_map); /* Shouldn't happen */ 296 } 297 #endif 298 299 /* 300 * Fixup core topology information for 301 * (1) AMD multi-node processors 302 * Assumption: Number of cores in each internal node is the same. 303 * (2) AMD processors supporting compute units 304 */ 305 #ifdef CONFIG_SMP 306 static void amd_get_topology(struct cpuinfo_x86 *c) 307 { 308 u8 node_id; 309 int cpu = smp_processor_id(); 310 311 /* get information required for multi-node processors */ 312 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 313 u32 eax, ebx, ecx, edx; 314 315 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); 316 317 node_id = ecx & 0xff; 318 smp_num_siblings = ((ebx >> 8) & 0xff) + 1; 319 320 if (c->x86 == 0x15) 321 c->cu_id = ebx & 0xff; 322 323 if (c->x86 >= 0x17) { 324 c->cpu_core_id = ebx & 0xff; 325 326 if (smp_num_siblings > 1) 327 c->x86_max_cores /= smp_num_siblings; 328 } 329 330 /* 331 * We may have multiple LLCs if L3 caches exist, so check if we 332 * have an L3 cache by looking at the L3 cache CPUID leaf. 333 */ 334 if (cpuid_edx(0x80000006)) { 335 if (c->x86 == 0x17) { 336 /* 337 * LLC is at the core complex level. 338 * Core complex id is ApicId[3]. 339 */ 340 per_cpu(cpu_llc_id, cpu) = c->apicid >> 3; 341 } else { 342 /* LLC is at the node level. */ 343 per_cpu(cpu_llc_id, cpu) = node_id; 344 } 345 } 346 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { 347 u64 value; 348 349 rdmsrl(MSR_FAM10H_NODE_ID, value); 350 node_id = value & 7; 351 352 per_cpu(cpu_llc_id, cpu) = node_id; 353 } else 354 return; 355 356 /* fixup multi-node processor information */ 357 if (nodes_per_socket > 1) { 358 u32 cus_per_node; 359 360 set_cpu_cap(c, X86_FEATURE_AMD_DCM); 361 cus_per_node = c->x86_max_cores / nodes_per_socket; 362 363 /* core id has to be in the [0 .. cores_per_node - 1] range */ 364 c->cpu_core_id %= cus_per_node; 365 } 366 } 367 #endif 368 369 /* 370 * On a AMD dual core setup the lower bits of the APIC id distinguish the cores. 371 * Assumes number of cores is a power of two. 372 */ 373 static void amd_detect_cmp(struct cpuinfo_x86 *c) 374 { 375 #ifdef CONFIG_SMP 376 unsigned bits; 377 int cpu = smp_processor_id(); 378 379 bits = c->x86_coreid_bits; 380 /* Low order bits define the core id (index of core in socket) */ 381 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1); 382 /* Convert the initial APIC ID into the socket ID */ 383 c->phys_proc_id = c->initial_apicid >> bits; 384 /* use socket ID also for last level cache */ 385 per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; 386 amd_get_topology(c); 387 #endif 388 } 389 390 u16 amd_get_nb_id(int cpu) 391 { 392 u16 id = 0; 393 #ifdef CONFIG_SMP 394 id = per_cpu(cpu_llc_id, cpu); 395 #endif 396 return id; 397 } 398 EXPORT_SYMBOL_GPL(amd_get_nb_id); 399 400 u32 amd_get_nodes_per_socket(void) 401 { 402 return nodes_per_socket; 403 } 404 EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket); 405 406 static void srat_detect_node(struct cpuinfo_x86 *c) 407 { 408 #ifdef CONFIG_NUMA 409 int cpu = smp_processor_id(); 410 int node; 411 unsigned apicid = c->apicid; 412 413 node = numa_cpu_node(cpu); 414 if (node == NUMA_NO_NODE) 415 node = per_cpu(cpu_llc_id, cpu); 416 417 /* 418 * On multi-fabric platform (e.g. Numascale NumaChip) a 419 * platform-specific handler needs to be called to fixup some 420 * IDs of the CPU. 421 */ 422 if (x86_cpuinit.fixup_cpu_id) 423 x86_cpuinit.fixup_cpu_id(c, node); 424 425 if (!node_online(node)) { 426 /* 427 * Two possibilities here: 428 * 429 * - The CPU is missing memory and no node was created. In 430 * that case try picking one from a nearby CPU. 431 * 432 * - The APIC IDs differ from the HyperTransport node IDs 433 * which the K8 northbridge parsing fills in. Assume 434 * they are all increased by a constant offset, but in 435 * the same order as the HT nodeids. If that doesn't 436 * result in a usable node fall back to the path for the 437 * previous case. 438 * 439 * This workaround operates directly on the mapping between 440 * APIC ID and NUMA node, assuming certain relationship 441 * between APIC ID, HT node ID and NUMA topology. As going 442 * through CPU mapping may alter the outcome, directly 443 * access __apicid_to_node[]. 444 */ 445 int ht_nodeid = c->initial_apicid; 446 447 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE) 448 node = __apicid_to_node[ht_nodeid]; 449 /* Pick a nearby node */ 450 if (!node_online(node)) 451 node = nearby_node(apicid); 452 } 453 numa_set_node(cpu, node); 454 #endif 455 } 456 457 static void early_init_amd_mc(struct cpuinfo_x86 *c) 458 { 459 #ifdef CONFIG_SMP 460 unsigned bits, ecx; 461 462 /* Multi core CPU? */ 463 if (c->extended_cpuid_level < 0x80000008) 464 return; 465 466 ecx = cpuid_ecx(0x80000008); 467 468 c->x86_max_cores = (ecx & 0xff) + 1; 469 470 /* CPU telling us the core id bits shift? */ 471 bits = (ecx >> 12) & 0xF; 472 473 /* Otherwise recompute */ 474 if (bits == 0) { 475 while ((1 << bits) < c->x86_max_cores) 476 bits++; 477 } 478 479 c->x86_coreid_bits = bits; 480 #endif 481 } 482 483 static void bsp_init_amd(struct cpuinfo_x86 *c) 484 { 485 486 #ifdef CONFIG_X86_64 487 if (c->x86 >= 0xf) { 488 unsigned long long tseg; 489 490 /* 491 * Split up direct mapping around the TSEG SMM area. 492 * Don't do it for gbpages because there seems very little 493 * benefit in doing so. 494 */ 495 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) { 496 unsigned long pfn = tseg >> PAGE_SHIFT; 497 498 pr_debug("tseg: %010llx\n", tseg); 499 if (pfn_range_is_mapped(pfn, pfn + 1)) 500 set_memory_4k((unsigned long)__va(tseg), 1); 501 } 502 } 503 #endif 504 505 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { 506 507 if (c->x86 > 0x10 || 508 (c->x86 == 0x10 && c->x86_model >= 0x2)) { 509 u64 val; 510 511 rdmsrl(MSR_K7_HWCR, val); 512 if (!(val & BIT(24))) 513 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n"); 514 } 515 } 516 517 if (c->x86 == 0x15) { 518 unsigned long upperbit; 519 u32 cpuid, assoc; 520 521 cpuid = cpuid_edx(0x80000005); 522 assoc = cpuid >> 16 & 0xff; 523 upperbit = ((cpuid >> 24) << 10) / assoc; 524 525 va_align.mask = (upperbit - 1) & PAGE_MASK; 526 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64; 527 528 /* A random value per boot for bit slice [12:upper_bit) */ 529 va_align.bits = get_random_int() & va_align.mask; 530 } 531 532 if (cpu_has(c, X86_FEATURE_MWAITX)) 533 use_mwaitx_delay(); 534 535 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 536 u32 ecx; 537 538 ecx = cpuid_ecx(0x8000001e); 539 nodes_per_socket = ((ecx >> 8) & 7) + 1; 540 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) { 541 u64 value; 542 543 rdmsrl(MSR_FAM10H_NODE_ID, value); 544 nodes_per_socket = ((value >> 3) & 7) + 1; 545 } 546 } 547 548 static void early_init_amd(struct cpuinfo_x86 *c) 549 { 550 early_init_amd_mc(c); 551 552 /* 553 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 554 * with P/T states and does not stop in deep C-states 555 */ 556 if (c->x86_power & (1 << 8)) { 557 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 558 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 559 if (check_tsc_unstable()) 560 clear_sched_clock_stable(); 561 } else { 562 clear_sched_clock_stable(); 563 } 564 565 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */ 566 if (c->x86_power & BIT(12)) 567 set_cpu_cap(c, X86_FEATURE_ACC_POWER); 568 569 #ifdef CONFIG_X86_64 570 set_cpu_cap(c, X86_FEATURE_SYSCALL32); 571 #else 572 /* Set MTRR capability flag if appropriate */ 573 if (c->x86 == 5) 574 if (c->x86_model == 13 || c->x86_model == 9 || 575 (c->x86_model == 8 && c->x86_mask >= 8)) 576 set_cpu_cap(c, X86_FEATURE_K6_MTRR); 577 #endif 578 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) 579 /* 580 * ApicID can always be treated as an 8-bit value for AMD APIC versions 581 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we 582 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families 583 * after 16h. 584 */ 585 if (boot_cpu_has(X86_FEATURE_APIC)) { 586 if (c->x86 > 0x16) 587 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 588 else if (c->x86 >= 0xf) { 589 /* check CPU config space for extended APIC ID */ 590 unsigned int val; 591 592 val = read_pci_config(0, 24, 0, 0x68); 593 if ((val >> 17 & 0x3) == 0x3) 594 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 595 } 596 } 597 #endif 598 599 /* 600 * This is only needed to tell the kernel whether to use VMCALL 601 * and VMMCALL. VMMCALL is never executed except under virt, so 602 * we can set it unconditionally. 603 */ 604 set_cpu_cap(c, X86_FEATURE_VMMCALL); 605 606 /* F16h erratum 793, CVE-2013-6885 */ 607 if (c->x86 == 0x16 && c->x86_model <= 0xf) 608 msr_set_bit(MSR_AMD64_LS_CFG, 15); 609 610 /* 611 * Check whether the machine is affected by erratum 400. This is 612 * used to select the proper idle routine and to enable the check 613 * whether the machine is affected in arch_post_acpi_init(), which 614 * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check. 615 */ 616 if (cpu_has_amd_erratum(c, amd_erratum_400)) 617 set_cpu_bug(c, X86_BUG_AMD_E400); 618 } 619 620 static void init_amd_k8(struct cpuinfo_x86 *c) 621 { 622 u32 level; 623 u64 value; 624 625 /* On C+ stepping K8 rep microcode works well for copy/memset */ 626 level = cpuid_eax(1); 627 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) 628 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 629 630 /* 631 * Some BIOSes incorrectly force this feature, but only K8 revision D 632 * (model = 0x14) and later actually support it. 633 * (AMD Erratum #110, docId: 25759). 634 */ 635 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) { 636 clear_cpu_cap(c, X86_FEATURE_LAHF_LM); 637 if (!rdmsrl_amd_safe(0xc001100d, &value)) { 638 value &= ~BIT_64(32); 639 wrmsrl_amd_safe(0xc001100d, value); 640 } 641 } 642 643 if (!c->x86_model_id[0]) 644 strcpy(c->x86_model_id, "Hammer"); 645 646 #ifdef CONFIG_SMP 647 /* 648 * Disable TLB flush filter by setting HWCR.FFDIS on K8 649 * bit 6 of msr C001_0015 650 * 651 * Errata 63 for SH-B3 steppings 652 * Errata 122 for all steppings (F+ have it disabled by default) 653 */ 654 msr_set_bit(MSR_K7_HWCR, 6); 655 #endif 656 set_cpu_bug(c, X86_BUG_SWAPGS_FENCE); 657 } 658 659 static void init_amd_gh(struct cpuinfo_x86 *c) 660 { 661 #ifdef CONFIG_X86_64 662 /* do this for boot cpu */ 663 if (c == &boot_cpu_data) 664 check_enable_amd_mmconf_dmi(); 665 666 fam10h_check_enable_mmcfg(); 667 #endif 668 669 /* 670 * Disable GART TLB Walk Errors on Fam10h. We do this here because this 671 * is always needed when GART is enabled, even in a kernel which has no 672 * MCE support built in. BIOS should disable GartTlbWlk Errors already. 673 * If it doesn't, we do it here as suggested by the BKDG. 674 * 675 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012 676 */ 677 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10); 678 679 /* 680 * On family 10h BIOS may not have properly enabled WC+ support, causing 681 * it to be converted to CD memtype. This may result in performance 682 * degradation for certain nested-paging guests. Prevent this conversion 683 * by clearing bit 24 in MSR_AMD64_BU_CFG2. 684 * 685 * NOTE: we want to use the _safe accessors so as not to #GP kvm 686 * guests on older kvm hosts. 687 */ 688 msr_clear_bit(MSR_AMD64_BU_CFG2, 24); 689 690 if (cpu_has_amd_erratum(c, amd_erratum_383)) 691 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH); 692 } 693 694 #define MSR_AMD64_DE_CFG 0xC0011029 695 696 static void init_amd_ln(struct cpuinfo_x86 *c) 697 { 698 /* 699 * Apply erratum 665 fix unconditionally so machines without a BIOS 700 * fix work. 701 */ 702 msr_set_bit(MSR_AMD64_DE_CFG, 31); 703 } 704 705 static void init_amd_bd(struct cpuinfo_x86 *c) 706 { 707 u64 value; 708 709 /* re-enable TopologyExtensions if switched off by BIOS */ 710 if ((c->x86_model >= 0x10) && (c->x86_model <= 0x6f) && 711 !cpu_has(c, X86_FEATURE_TOPOEXT)) { 712 713 if (msr_set_bit(0xc0011005, 54) > 0) { 714 rdmsrl(0xc0011005, value); 715 if (value & BIT_64(54)) { 716 set_cpu_cap(c, X86_FEATURE_TOPOEXT); 717 pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n"); 718 } 719 } 720 } 721 722 /* 723 * The way access filter has a performance penalty on some workloads. 724 * Disable it on the affected CPUs. 725 */ 726 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) { 727 if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) { 728 value |= 0x1E; 729 wrmsrl_safe(MSR_F15H_IC_CFG, value); 730 } 731 } 732 } 733 734 static void init_amd(struct cpuinfo_x86 *c) 735 { 736 u32 dummy; 737 738 early_init_amd(c); 739 740 /* 741 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 742 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 743 */ 744 clear_cpu_cap(c, 0*32+31); 745 746 if (c->x86 >= 0x10) 747 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 748 749 /* get apicid instead of initial apic id from cpuid */ 750 c->apicid = hard_smp_processor_id(); 751 752 /* K6s reports MCEs but don't actually have all the MSRs */ 753 if (c->x86 < 6) 754 clear_cpu_cap(c, X86_FEATURE_MCE); 755 756 switch (c->x86) { 757 case 4: init_amd_k5(c); break; 758 case 5: init_amd_k6(c); break; 759 case 6: init_amd_k7(c); break; 760 case 0xf: init_amd_k8(c); break; 761 case 0x10: init_amd_gh(c); break; 762 case 0x12: init_amd_ln(c); break; 763 case 0x15: init_amd_bd(c); break; 764 } 765 766 /* Enable workaround for FXSAVE leak */ 767 if (c->x86 >= 6) 768 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK); 769 770 cpu_detect_cache_sizes(c); 771 772 /* Multi core CPU? */ 773 if (c->extended_cpuid_level >= 0x80000008) { 774 amd_detect_cmp(c); 775 srat_detect_node(c); 776 } 777 778 #ifdef CONFIG_X86_32 779 detect_ht(c); 780 #endif 781 782 init_amd_cacheinfo(c); 783 784 if (c->x86 >= 0xf) 785 set_cpu_cap(c, X86_FEATURE_K8); 786 787 if (cpu_has(c, X86_FEATURE_XMM2)) { 788 /* MFENCE stops RDTSC speculation */ 789 set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC); 790 } 791 792 /* 793 * Family 0x12 and above processors have APIC timer 794 * running in deep C states. 795 */ 796 if (c->x86 > 0x11) 797 set_cpu_cap(c, X86_FEATURE_ARAT); 798 799 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); 800 801 /* 3DNow or LM implies PREFETCHW */ 802 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH)) 803 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM)) 804 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH); 805 806 /* AMD CPUs don't reset SS attributes on SYSRET */ 807 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); 808 } 809 810 #ifdef CONFIG_X86_32 811 static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size) 812 { 813 /* AMD errata T13 (order #21922) */ 814 if ((c->x86 == 6)) { 815 /* Duron Rev A0 */ 816 if (c->x86_model == 3 && c->x86_mask == 0) 817 size = 64; 818 /* Tbird rev A1/A2 */ 819 if (c->x86_model == 4 && 820 (c->x86_mask == 0 || c->x86_mask == 1)) 821 size = 256; 822 } 823 return size; 824 } 825 #endif 826 827 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) 828 { 829 u32 ebx, eax, ecx, edx; 830 u16 mask = 0xfff; 831 832 if (c->x86 < 0xf) 833 return; 834 835 if (c->extended_cpuid_level < 0x80000006) 836 return; 837 838 cpuid(0x80000006, &eax, &ebx, &ecx, &edx); 839 840 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask; 841 tlb_lli_4k[ENTRIES] = ebx & mask; 842 843 /* 844 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB 845 * characteristics from the CPUID function 0x80000005 instead. 846 */ 847 if (c->x86 == 0xf) { 848 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 849 mask = 0xff; 850 } 851 852 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 853 if (!((eax >> 16) & mask)) 854 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff; 855 else 856 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask; 857 858 /* a 4M entry uses two 2M entries */ 859 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1; 860 861 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 862 if (!(eax & mask)) { 863 /* Erratum 658 */ 864 if (c->x86 == 0x15 && c->x86_model <= 0x1f) { 865 tlb_lli_2m[ENTRIES] = 1024; 866 } else { 867 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 868 tlb_lli_2m[ENTRIES] = eax & 0xff; 869 } 870 } else 871 tlb_lli_2m[ENTRIES] = eax & mask; 872 873 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1; 874 } 875 876 static const struct cpu_dev amd_cpu_dev = { 877 .c_vendor = "AMD", 878 .c_ident = { "AuthenticAMD" }, 879 #ifdef CONFIG_X86_32 880 .legacy_models = { 881 { .family = 4, .model_names = 882 { 883 [3] = "486 DX/2", 884 [7] = "486 DX/2-WB", 885 [8] = "486 DX/4", 886 [9] = "486 DX/4-WB", 887 [14] = "Am5x86-WT", 888 [15] = "Am5x86-WB" 889 } 890 }, 891 }, 892 .legacy_cache_size = amd_size_cache, 893 #endif 894 .c_early_init = early_init_amd, 895 .c_detect_tlb = cpu_detect_tlb_amd, 896 .c_bsp_init = bsp_init_amd, 897 .c_init = init_amd, 898 .c_x86_vendor = X86_VENDOR_AMD, 899 }; 900 901 cpu_dev_register(amd_cpu_dev); 902 903 /* 904 * AMD errata checking 905 * 906 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or 907 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that 908 * have an OSVW id assigned, which it takes as first argument. Both take a 909 * variable number of family-specific model-stepping ranges created by 910 * AMD_MODEL_RANGE(). 911 * 912 * Example: 913 * 914 * const int amd_erratum_319[] = 915 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), 916 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), 917 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); 918 */ 919 920 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 } 921 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 } 922 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \ 923 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end)) 924 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff) 925 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff) 926 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff) 927 928 static const int amd_erratum_400[] = 929 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), 930 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); 931 932 static const int amd_erratum_383[] = 933 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); 934 935 936 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum) 937 { 938 int osvw_id = *erratum++; 939 u32 range; 940 u32 ms; 941 942 if (osvw_id >= 0 && osvw_id < 65536 && 943 cpu_has(cpu, X86_FEATURE_OSVW)) { 944 u64 osvw_len; 945 946 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); 947 if (osvw_id < osvw_len) { 948 u64 osvw_bits; 949 950 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), 951 osvw_bits); 952 return osvw_bits & (1ULL << (osvw_id & 0x3f)); 953 } 954 } 955 956 /* OSVW unavailable or ID unknown, match family-model-stepping range */ 957 ms = (cpu->x86_model << 4) | cpu->x86_mask; 958 while ((range = *erratum++)) 959 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) && 960 (ms >= AMD_MODEL_RANGE_START(range)) && 961 (ms <= AMD_MODEL_RANGE_END(range))) 962 return true; 963 964 return false; 965 } 966 967 void set_dr_addr_mask(unsigned long mask, int dr) 968 { 969 if (!boot_cpu_has(X86_FEATURE_BPEXT)) 970 return; 971 972 switch (dr) { 973 case 0: 974 wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0); 975 break; 976 case 1: 977 case 2: 978 case 3: 979 wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0); 980 break; 981 default: 982 break; 983 } 984 } 985