xref: /openbmc/linux/arch/x86/kernel/cpu/amd.c (revision 0edbfea5)
1 #include <linux/export.h>
2 #include <linux/bitops.h>
3 #include <linux/elf.h>
4 #include <linux/mm.h>
5 
6 #include <linux/io.h>
7 #include <linux/sched.h>
8 #include <linux/random.h>
9 #include <asm/processor.h>
10 #include <asm/apic.h>
11 #include <asm/cpu.h>
12 #include <asm/smp.h>
13 #include <asm/pci-direct.h>
14 #include <asm/delay.h>
15 
16 #ifdef CONFIG_X86_64
17 # include <asm/mmconfig.h>
18 # include <asm/cacheflush.h>
19 #endif
20 
21 #include "cpu.h"
22 
23 /*
24  * nodes_per_socket: Stores the number of nodes per socket.
25  * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX
26  * Node Identifiers[10:8]
27  */
28 static u32 nodes_per_socket = 1;
29 
30 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
31 {
32 	u32 gprs[8] = { 0 };
33 	int err;
34 
35 	WARN_ONCE((boot_cpu_data.x86 != 0xf),
36 		  "%s should only be used on K8!\n", __func__);
37 
38 	gprs[1] = msr;
39 	gprs[7] = 0x9c5a203a;
40 
41 	err = rdmsr_safe_regs(gprs);
42 
43 	*p = gprs[0] | ((u64)gprs[2] << 32);
44 
45 	return err;
46 }
47 
48 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val)
49 {
50 	u32 gprs[8] = { 0 };
51 
52 	WARN_ONCE((boot_cpu_data.x86 != 0xf),
53 		  "%s should only be used on K8!\n", __func__);
54 
55 	gprs[0] = (u32)val;
56 	gprs[1] = msr;
57 	gprs[2] = val >> 32;
58 	gprs[7] = 0x9c5a203a;
59 
60 	return wrmsr_safe_regs(gprs);
61 }
62 
63 /*
64  *	B step AMD K6 before B 9730xxxx have hardware bugs that can cause
65  *	misexecution of code under Linux. Owners of such processors should
66  *	contact AMD for precise details and a CPU swap.
67  *
68  *	See	http://www.multimania.com/poulot/k6bug.html
69  *	and	section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
70  *		(Publication # 21266  Issue Date: August 1998)
71  *
72  *	The following test is erm.. interesting. AMD neglected to up
73  *	the chip setting when fixing the bug but they also tweaked some
74  *	performance at the same time..
75  */
76 
77 extern __visible void vide(void);
78 __asm__(".globl vide\n"
79 	".type vide, @function\n"
80 	".align 4\n"
81 	"vide: ret\n");
82 
83 static void init_amd_k5(struct cpuinfo_x86 *c)
84 {
85 #ifdef CONFIG_X86_32
86 /*
87  * General Systems BIOSen alias the cpu frequency registers
88  * of the Elan at 0x000df000. Unfortunately, one of the Linux
89  * drivers subsequently pokes it, and changes the CPU speed.
90  * Workaround : Remove the unneeded alias.
91  */
92 #define CBAR		(0xfffc) /* Configuration Base Address  (32-bit) */
93 #define CBAR_ENB	(0x80000000)
94 #define CBAR_KEY	(0X000000CB)
95 	if (c->x86_model == 9 || c->x86_model == 10) {
96 		if (inl(CBAR) & CBAR_ENB)
97 			outl(0 | CBAR_KEY, CBAR);
98 	}
99 #endif
100 }
101 
102 static void init_amd_k6(struct cpuinfo_x86 *c)
103 {
104 #ifdef CONFIG_X86_32
105 	u32 l, h;
106 	int mbytes = get_num_physpages() >> (20-PAGE_SHIFT);
107 
108 	if (c->x86_model < 6) {
109 		/* Based on AMD doc 20734R - June 2000 */
110 		if (c->x86_model == 0) {
111 			clear_cpu_cap(c, X86_FEATURE_APIC);
112 			set_cpu_cap(c, X86_FEATURE_PGE);
113 		}
114 		return;
115 	}
116 
117 	if (c->x86_model == 6 && c->x86_mask == 1) {
118 		const int K6_BUG_LOOP = 1000000;
119 		int n;
120 		void (*f_vide)(void);
121 		u64 d, d2;
122 
123 		pr_info("AMD K6 stepping B detected - ");
124 
125 		/*
126 		 * It looks like AMD fixed the 2.6.2 bug and improved indirect
127 		 * calls at the same time.
128 		 */
129 
130 		n = K6_BUG_LOOP;
131 		f_vide = vide;
132 		d = rdtsc();
133 		while (n--)
134 			f_vide();
135 		d2 = rdtsc();
136 		d = d2-d;
137 
138 		if (d > 20*K6_BUG_LOOP)
139 			pr_cont("system stability may be impaired when more than 32 MB are used.\n");
140 		else
141 			pr_cont("probably OK (after B9730xxxx).\n");
142 	}
143 
144 	/* K6 with old style WHCR */
145 	if (c->x86_model < 8 ||
146 	   (c->x86_model == 8 && c->x86_mask < 8)) {
147 		/* We can only write allocate on the low 508Mb */
148 		if (mbytes > 508)
149 			mbytes = 508;
150 
151 		rdmsr(MSR_K6_WHCR, l, h);
152 		if ((l&0x0000FFFF) == 0) {
153 			unsigned long flags;
154 			l = (1<<0)|((mbytes/4)<<1);
155 			local_irq_save(flags);
156 			wbinvd();
157 			wrmsr(MSR_K6_WHCR, l, h);
158 			local_irq_restore(flags);
159 			pr_info("Enabling old style K6 write allocation for %d Mb\n",
160 				mbytes);
161 		}
162 		return;
163 	}
164 
165 	if ((c->x86_model == 8 && c->x86_mask > 7) ||
166 	     c->x86_model == 9 || c->x86_model == 13) {
167 		/* The more serious chips .. */
168 
169 		if (mbytes > 4092)
170 			mbytes = 4092;
171 
172 		rdmsr(MSR_K6_WHCR, l, h);
173 		if ((l&0xFFFF0000) == 0) {
174 			unsigned long flags;
175 			l = ((mbytes>>2)<<22)|(1<<16);
176 			local_irq_save(flags);
177 			wbinvd();
178 			wrmsr(MSR_K6_WHCR, l, h);
179 			local_irq_restore(flags);
180 			pr_info("Enabling new style K6 write allocation for %d Mb\n",
181 				mbytes);
182 		}
183 
184 		return;
185 	}
186 
187 	if (c->x86_model == 10) {
188 		/* AMD Geode LX is model 10 */
189 		/* placeholder for any needed mods */
190 		return;
191 	}
192 #endif
193 }
194 
195 static void init_amd_k7(struct cpuinfo_x86 *c)
196 {
197 #ifdef CONFIG_X86_32
198 	u32 l, h;
199 
200 	/*
201 	 * Bit 15 of Athlon specific MSR 15, needs to be 0
202 	 * to enable SSE on Palomino/Morgan/Barton CPU's.
203 	 * If the BIOS didn't enable it already, enable it here.
204 	 */
205 	if (c->x86_model >= 6 && c->x86_model <= 10) {
206 		if (!cpu_has(c, X86_FEATURE_XMM)) {
207 			pr_info("Enabling disabled K7/SSE Support.\n");
208 			msr_clear_bit(MSR_K7_HWCR, 15);
209 			set_cpu_cap(c, X86_FEATURE_XMM);
210 		}
211 	}
212 
213 	/*
214 	 * It's been determined by AMD that Athlons since model 8 stepping 1
215 	 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx
216 	 * As per AMD technical note 27212 0.2
217 	 */
218 	if ((c->x86_model == 8 && c->x86_mask >= 1) || (c->x86_model > 8)) {
219 		rdmsr(MSR_K7_CLK_CTL, l, h);
220 		if ((l & 0xfff00000) != 0x20000000) {
221 			pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n",
222 				l, ((l & 0x000fffff)|0x20000000));
223 			wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h);
224 		}
225 	}
226 
227 	set_cpu_cap(c, X86_FEATURE_K7);
228 
229 	/* calling is from identify_secondary_cpu() ? */
230 	if (!c->cpu_index)
231 		return;
232 
233 	/*
234 	 * Certain Athlons might work (for various values of 'work') in SMP
235 	 * but they are not certified as MP capable.
236 	 */
237 	/* Athlon 660/661 is valid. */
238 	if ((c->x86_model == 6) && ((c->x86_mask == 0) ||
239 	    (c->x86_mask == 1)))
240 		return;
241 
242 	/* Duron 670 is valid */
243 	if ((c->x86_model == 7) && (c->x86_mask == 0))
244 		return;
245 
246 	/*
247 	 * Athlon 662, Duron 671, and Athlon >model 7 have capability
248 	 * bit. It's worth noting that the A5 stepping (662) of some
249 	 * Athlon XP's have the MP bit set.
250 	 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for
251 	 * more.
252 	 */
253 	if (((c->x86_model == 6) && (c->x86_mask >= 2)) ||
254 	    ((c->x86_model == 7) && (c->x86_mask >= 1)) ||
255 	     (c->x86_model > 7))
256 		if (cpu_has(c, X86_FEATURE_MP))
257 			return;
258 
259 	/* If we get here, not a certified SMP capable AMD system. */
260 
261 	/*
262 	 * Don't taint if we are running SMP kernel on a single non-MP
263 	 * approved Athlon
264 	 */
265 	WARN_ONCE(1, "WARNING: This combination of AMD"
266 		" processors is not suitable for SMP.\n");
267 	add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
268 #endif
269 }
270 
271 #ifdef CONFIG_NUMA
272 /*
273  * To workaround broken NUMA config.  Read the comment in
274  * srat_detect_node().
275  */
276 static int nearby_node(int apicid)
277 {
278 	int i, node;
279 
280 	for (i = apicid - 1; i >= 0; i--) {
281 		node = __apicid_to_node[i];
282 		if (node != NUMA_NO_NODE && node_online(node))
283 			return node;
284 	}
285 	for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
286 		node = __apicid_to_node[i];
287 		if (node != NUMA_NO_NODE && node_online(node))
288 			return node;
289 	}
290 	return first_node(node_online_map); /* Shouldn't happen */
291 }
292 #endif
293 
294 /*
295  * Fixup core topology information for
296  * (1) AMD multi-node processors
297  *     Assumption: Number of cores in each internal node is the same.
298  * (2) AMD processors supporting compute units
299  */
300 #ifdef CONFIG_SMP
301 static void amd_get_topology(struct cpuinfo_x86 *c)
302 {
303 	u8 node_id;
304 	int cpu = smp_processor_id();
305 
306 	/* get information required for multi-node processors */
307 	if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
308 		u32 eax, ebx, ecx, edx;
309 
310 		cpuid(0x8000001e, &eax, &ebx, &ecx, &edx);
311 		node_id = ecx & 7;
312 
313 		/* get compute unit information */
314 		smp_num_siblings = ((ebx >> 8) & 3) + 1;
315 		c->x86_max_cores /= smp_num_siblings;
316 		c->cpu_core_id = ebx & 0xff;
317 	} else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
318 		u64 value;
319 
320 		rdmsrl(MSR_FAM10H_NODE_ID, value);
321 		node_id = value & 7;
322 	} else
323 		return;
324 
325 	/* fixup multi-node processor information */
326 	if (nodes_per_socket > 1) {
327 		u32 cus_per_node;
328 
329 		set_cpu_cap(c, X86_FEATURE_AMD_DCM);
330 		cus_per_node = c->x86_max_cores / nodes_per_socket;
331 
332 		/* store NodeID, use llc_shared_map to store sibling info */
333 		per_cpu(cpu_llc_id, cpu) = node_id;
334 
335 		/* core id has to be in the [0 .. cores_per_node - 1] range */
336 		c->cpu_core_id %= cus_per_node;
337 	}
338 }
339 #endif
340 
341 /*
342  * On a AMD dual core setup the lower bits of the APIC id distinguish the cores.
343  * Assumes number of cores is a power of two.
344  */
345 static void amd_detect_cmp(struct cpuinfo_x86 *c)
346 {
347 #ifdef CONFIG_SMP
348 	unsigned bits;
349 	int cpu = smp_processor_id();
350 	unsigned int socket_id, core_complex_id;
351 
352 	bits = c->x86_coreid_bits;
353 	/* Low order bits define the core id (index of core in socket) */
354 	c->cpu_core_id = c->initial_apicid & ((1 << bits)-1);
355 	/* Convert the initial APIC ID into the socket ID */
356 	c->phys_proc_id = c->initial_apicid >> bits;
357 	/* use socket ID also for last level cache */
358 	per_cpu(cpu_llc_id, cpu) = c->phys_proc_id;
359 	amd_get_topology(c);
360 
361 	/*
362 	 * Fix percpu cpu_llc_id here as LLC topology is different
363 	 * for Fam17h systems.
364 	 */
365 	 if (c->x86 != 0x17 || !cpuid_edx(0x80000006))
366 		return;
367 
368 	socket_id	= (c->apicid >> bits) - 1;
369 	core_complex_id	= (c->apicid & ((1 << bits) - 1)) >> 3;
370 
371 	per_cpu(cpu_llc_id, cpu) = (socket_id << 3) | core_complex_id;
372 #endif
373 }
374 
375 u16 amd_get_nb_id(int cpu)
376 {
377 	u16 id = 0;
378 #ifdef CONFIG_SMP
379 	id = per_cpu(cpu_llc_id, cpu);
380 #endif
381 	return id;
382 }
383 EXPORT_SYMBOL_GPL(amd_get_nb_id);
384 
385 u32 amd_get_nodes_per_socket(void)
386 {
387 	return nodes_per_socket;
388 }
389 EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket);
390 
391 static void srat_detect_node(struct cpuinfo_x86 *c)
392 {
393 #ifdef CONFIG_NUMA
394 	int cpu = smp_processor_id();
395 	int node;
396 	unsigned apicid = c->apicid;
397 
398 	node = numa_cpu_node(cpu);
399 	if (node == NUMA_NO_NODE)
400 		node = per_cpu(cpu_llc_id, cpu);
401 
402 	/*
403 	 * On multi-fabric platform (e.g. Numascale NumaChip) a
404 	 * platform-specific handler needs to be called to fixup some
405 	 * IDs of the CPU.
406 	 */
407 	if (x86_cpuinit.fixup_cpu_id)
408 		x86_cpuinit.fixup_cpu_id(c, node);
409 
410 	if (!node_online(node)) {
411 		/*
412 		 * Two possibilities here:
413 		 *
414 		 * - The CPU is missing memory and no node was created.  In
415 		 *   that case try picking one from a nearby CPU.
416 		 *
417 		 * - The APIC IDs differ from the HyperTransport node IDs
418 		 *   which the K8 northbridge parsing fills in.  Assume
419 		 *   they are all increased by a constant offset, but in
420 		 *   the same order as the HT nodeids.  If that doesn't
421 		 *   result in a usable node fall back to the path for the
422 		 *   previous case.
423 		 *
424 		 * This workaround operates directly on the mapping between
425 		 * APIC ID and NUMA node, assuming certain relationship
426 		 * between APIC ID, HT node ID and NUMA topology.  As going
427 		 * through CPU mapping may alter the outcome, directly
428 		 * access __apicid_to_node[].
429 		 */
430 		int ht_nodeid = c->initial_apicid;
431 
432 		if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
433 			node = __apicid_to_node[ht_nodeid];
434 		/* Pick a nearby node */
435 		if (!node_online(node))
436 			node = nearby_node(apicid);
437 	}
438 	numa_set_node(cpu, node);
439 #endif
440 }
441 
442 static void early_init_amd_mc(struct cpuinfo_x86 *c)
443 {
444 #ifdef CONFIG_SMP
445 	unsigned bits, ecx;
446 
447 	/* Multi core CPU? */
448 	if (c->extended_cpuid_level < 0x80000008)
449 		return;
450 
451 	ecx = cpuid_ecx(0x80000008);
452 
453 	c->x86_max_cores = (ecx & 0xff) + 1;
454 
455 	/* CPU telling us the core id bits shift? */
456 	bits = (ecx >> 12) & 0xF;
457 
458 	/* Otherwise recompute */
459 	if (bits == 0) {
460 		while ((1 << bits) < c->x86_max_cores)
461 			bits++;
462 	}
463 
464 	c->x86_coreid_bits = bits;
465 #endif
466 }
467 
468 static void bsp_init_amd(struct cpuinfo_x86 *c)
469 {
470 
471 #ifdef CONFIG_X86_64
472 	if (c->x86 >= 0xf) {
473 		unsigned long long tseg;
474 
475 		/*
476 		 * Split up direct mapping around the TSEG SMM area.
477 		 * Don't do it for gbpages because there seems very little
478 		 * benefit in doing so.
479 		 */
480 		if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) {
481 			unsigned long pfn = tseg >> PAGE_SHIFT;
482 
483 			pr_debug("tseg: %010llx\n", tseg);
484 			if (pfn_range_is_mapped(pfn, pfn + 1))
485 				set_memory_4k((unsigned long)__va(tseg), 1);
486 		}
487 	}
488 #endif
489 
490 	if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
491 
492 		if (c->x86 > 0x10 ||
493 		    (c->x86 == 0x10 && c->x86_model >= 0x2)) {
494 			u64 val;
495 
496 			rdmsrl(MSR_K7_HWCR, val);
497 			if (!(val & BIT(24)))
498 				pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n");
499 		}
500 	}
501 
502 	if (c->x86 == 0x15) {
503 		unsigned long upperbit;
504 		u32 cpuid, assoc;
505 
506 		cpuid	 = cpuid_edx(0x80000005);
507 		assoc	 = cpuid >> 16 & 0xff;
508 		upperbit = ((cpuid >> 24) << 10) / assoc;
509 
510 		va_align.mask	  = (upperbit - 1) & PAGE_MASK;
511 		va_align.flags    = ALIGN_VA_32 | ALIGN_VA_64;
512 
513 		/* A random value per boot for bit slice [12:upper_bit) */
514 		va_align.bits = get_random_int() & va_align.mask;
515 	}
516 
517 	if (cpu_has(c, X86_FEATURE_MWAITX))
518 		use_mwaitx_delay();
519 
520 	if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
521 		u32 ecx;
522 
523 		ecx = cpuid_ecx(0x8000001e);
524 		nodes_per_socket = ((ecx >> 8) & 7) + 1;
525 	} else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) {
526 		u64 value;
527 
528 		rdmsrl(MSR_FAM10H_NODE_ID, value);
529 		nodes_per_socket = ((value >> 3) & 7) + 1;
530 	}
531 }
532 
533 static void early_init_amd(struct cpuinfo_x86 *c)
534 {
535 	early_init_amd_mc(c);
536 
537 	/*
538 	 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
539 	 * with P/T states and does not stop in deep C-states
540 	 */
541 	if (c->x86_power & (1 << 8)) {
542 		set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
543 		set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
544 		if (!check_tsc_unstable())
545 			set_sched_clock_stable();
546 	}
547 
548 	/* Bit 12 of 8000_0007 edx is accumulated power mechanism. */
549 	if (c->x86_power & BIT(12))
550 		set_cpu_cap(c, X86_FEATURE_ACC_POWER);
551 
552 #ifdef CONFIG_X86_64
553 	set_cpu_cap(c, X86_FEATURE_SYSCALL32);
554 #else
555 	/*  Set MTRR capability flag if appropriate */
556 	if (c->x86 == 5)
557 		if (c->x86_model == 13 || c->x86_model == 9 ||
558 		    (c->x86_model == 8 && c->x86_mask >= 8))
559 			set_cpu_cap(c, X86_FEATURE_K6_MTRR);
560 #endif
561 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
562 	/*
563 	 * ApicID can always be treated as an 8-bit value for AMD APIC versions
564 	 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we
565 	 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families
566 	 * after 16h.
567 	 */
568 	if (boot_cpu_has(X86_FEATURE_APIC)) {
569 		if (c->x86 > 0x16)
570 			set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
571 		else if (c->x86 >= 0xf) {
572 			/* check CPU config space for extended APIC ID */
573 			unsigned int val;
574 
575 			val = read_pci_config(0, 24, 0, 0x68);
576 			if ((val >> 17 & 0x3) == 0x3)
577 				set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
578 		}
579 	}
580 #endif
581 
582 	/*
583 	 * This is only needed to tell the kernel whether to use VMCALL
584 	 * and VMMCALL.  VMMCALL is never executed except under virt, so
585 	 * we can set it unconditionally.
586 	 */
587 	set_cpu_cap(c, X86_FEATURE_VMMCALL);
588 
589 	/* F16h erratum 793, CVE-2013-6885 */
590 	if (c->x86 == 0x16 && c->x86_model <= 0xf)
591 		msr_set_bit(MSR_AMD64_LS_CFG, 15);
592 }
593 
594 static const int amd_erratum_383[];
595 static const int amd_erratum_400[];
596 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum);
597 
598 static void init_amd_k8(struct cpuinfo_x86 *c)
599 {
600 	u32 level;
601 	u64 value;
602 
603 	/* On C+ stepping K8 rep microcode works well for copy/memset */
604 	level = cpuid_eax(1);
605 	if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58)
606 		set_cpu_cap(c, X86_FEATURE_REP_GOOD);
607 
608 	/*
609 	 * Some BIOSes incorrectly force this feature, but only K8 revision D
610 	 * (model = 0x14) and later actually support it.
611 	 * (AMD Erratum #110, docId: 25759).
612 	 */
613 	if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) {
614 		clear_cpu_cap(c, X86_FEATURE_LAHF_LM);
615 		if (!rdmsrl_amd_safe(0xc001100d, &value)) {
616 			value &= ~BIT_64(32);
617 			wrmsrl_amd_safe(0xc001100d, value);
618 		}
619 	}
620 
621 	if (!c->x86_model_id[0])
622 		strcpy(c->x86_model_id, "Hammer");
623 
624 #ifdef CONFIG_SMP
625 	/*
626 	 * Disable TLB flush filter by setting HWCR.FFDIS on K8
627 	 * bit 6 of msr C001_0015
628 	 *
629 	 * Errata 63 for SH-B3 steppings
630 	 * Errata 122 for all steppings (F+ have it disabled by default)
631 	 */
632 	msr_set_bit(MSR_K7_HWCR, 6);
633 #endif
634 	set_cpu_bug(c, X86_BUG_SWAPGS_FENCE);
635 }
636 
637 static void init_amd_gh(struct cpuinfo_x86 *c)
638 {
639 #ifdef CONFIG_X86_64
640 	/* do this for boot cpu */
641 	if (c == &boot_cpu_data)
642 		check_enable_amd_mmconf_dmi();
643 
644 	fam10h_check_enable_mmcfg();
645 #endif
646 
647 	/*
648 	 * Disable GART TLB Walk Errors on Fam10h. We do this here because this
649 	 * is always needed when GART is enabled, even in a kernel which has no
650 	 * MCE support built in. BIOS should disable GartTlbWlk Errors already.
651 	 * If it doesn't, we do it here as suggested by the BKDG.
652 	 *
653 	 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012
654 	 */
655 	msr_set_bit(MSR_AMD64_MCx_MASK(4), 10);
656 
657 	/*
658 	 * On family 10h BIOS may not have properly enabled WC+ support, causing
659 	 * it to be converted to CD memtype. This may result in performance
660 	 * degradation for certain nested-paging guests. Prevent this conversion
661 	 * by clearing bit 24 in MSR_AMD64_BU_CFG2.
662 	 *
663 	 * NOTE: we want to use the _safe accessors so as not to #GP kvm
664 	 * guests on older kvm hosts.
665 	 */
666 	msr_clear_bit(MSR_AMD64_BU_CFG2, 24);
667 
668 	if (cpu_has_amd_erratum(c, amd_erratum_383))
669 		set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
670 }
671 
672 static void init_amd_bd(struct cpuinfo_x86 *c)
673 {
674 	u64 value;
675 
676 	/* re-enable TopologyExtensions if switched off by BIOS */
677 	if ((c->x86_model >= 0x10) && (c->x86_model <= 0x1f) &&
678 	    !cpu_has(c, X86_FEATURE_TOPOEXT)) {
679 
680 		if (msr_set_bit(0xc0011005, 54) > 0) {
681 			rdmsrl(0xc0011005, value);
682 			if (value & BIT_64(54)) {
683 				set_cpu_cap(c, X86_FEATURE_TOPOEXT);
684 				pr_info(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n");
685 			}
686 		}
687 	}
688 
689 	/*
690 	 * The way access filter has a performance penalty on some workloads.
691 	 * Disable it on the affected CPUs.
692 	 */
693 	if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) {
694 		if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) {
695 			value |= 0x1E;
696 			wrmsrl_safe(MSR_F15H_IC_CFG, value);
697 		}
698 	}
699 }
700 
701 static void init_amd(struct cpuinfo_x86 *c)
702 {
703 	u32 dummy;
704 
705 	early_init_amd(c);
706 
707 	/*
708 	 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
709 	 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
710 	 */
711 	clear_cpu_cap(c, 0*32+31);
712 
713 	if (c->x86 >= 0x10)
714 		set_cpu_cap(c, X86_FEATURE_REP_GOOD);
715 
716 	/* get apicid instead of initial apic id from cpuid */
717 	c->apicid = hard_smp_processor_id();
718 
719 	/* K6s reports MCEs but don't actually have all the MSRs */
720 	if (c->x86 < 6)
721 		clear_cpu_cap(c, X86_FEATURE_MCE);
722 
723 	switch (c->x86) {
724 	case 4:    init_amd_k5(c); break;
725 	case 5:    init_amd_k6(c); break;
726 	case 6:	   init_amd_k7(c); break;
727 	case 0xf:  init_amd_k8(c); break;
728 	case 0x10: init_amd_gh(c); break;
729 	case 0x15: init_amd_bd(c); break;
730 	}
731 
732 	/* Enable workaround for FXSAVE leak */
733 	if (c->x86 >= 6)
734 		set_cpu_bug(c, X86_BUG_FXSAVE_LEAK);
735 
736 	cpu_detect_cache_sizes(c);
737 
738 	/* Multi core CPU? */
739 	if (c->extended_cpuid_level >= 0x80000008) {
740 		amd_detect_cmp(c);
741 		srat_detect_node(c);
742 	}
743 
744 #ifdef CONFIG_X86_32
745 	detect_ht(c);
746 #endif
747 
748 	init_amd_cacheinfo(c);
749 
750 	if (c->x86 >= 0xf)
751 		set_cpu_cap(c, X86_FEATURE_K8);
752 
753 	if (cpu_has(c, X86_FEATURE_XMM2)) {
754 		/* MFENCE stops RDTSC speculation */
755 		set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
756 	}
757 
758 	/*
759 	 * Family 0x12 and above processors have APIC timer
760 	 * running in deep C states.
761 	 */
762 	if (c->x86 > 0x11)
763 		set_cpu_cap(c, X86_FEATURE_ARAT);
764 
765 	if (cpu_has_amd_erratum(c, amd_erratum_400))
766 		set_cpu_bug(c, X86_BUG_AMD_APIC_C1E);
767 
768 	rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
769 
770 	/* 3DNow or LM implies PREFETCHW */
771 	if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH))
772 		if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM))
773 			set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH);
774 
775 	/* AMD CPUs don't reset SS attributes on SYSRET */
776 	set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
777 }
778 
779 #ifdef CONFIG_X86_32
780 static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size)
781 {
782 	/* AMD errata T13 (order #21922) */
783 	if ((c->x86 == 6)) {
784 		/* Duron Rev A0 */
785 		if (c->x86_model == 3 && c->x86_mask == 0)
786 			size = 64;
787 		/* Tbird rev A1/A2 */
788 		if (c->x86_model == 4 &&
789 			(c->x86_mask == 0 || c->x86_mask == 1))
790 			size = 256;
791 	}
792 	return size;
793 }
794 #endif
795 
796 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c)
797 {
798 	u32 ebx, eax, ecx, edx;
799 	u16 mask = 0xfff;
800 
801 	if (c->x86 < 0xf)
802 		return;
803 
804 	if (c->extended_cpuid_level < 0x80000006)
805 		return;
806 
807 	cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
808 
809 	tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask;
810 	tlb_lli_4k[ENTRIES] = ebx & mask;
811 
812 	/*
813 	 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB
814 	 * characteristics from the CPUID function 0x80000005 instead.
815 	 */
816 	if (c->x86 == 0xf) {
817 		cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
818 		mask = 0xff;
819 	}
820 
821 	/* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
822 	if (!((eax >> 16) & mask))
823 		tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff;
824 	else
825 		tlb_lld_2m[ENTRIES] = (eax >> 16) & mask;
826 
827 	/* a 4M entry uses two 2M entries */
828 	tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1;
829 
830 	/* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
831 	if (!(eax & mask)) {
832 		/* Erratum 658 */
833 		if (c->x86 == 0x15 && c->x86_model <= 0x1f) {
834 			tlb_lli_2m[ENTRIES] = 1024;
835 		} else {
836 			cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
837 			tlb_lli_2m[ENTRIES] = eax & 0xff;
838 		}
839 	} else
840 		tlb_lli_2m[ENTRIES] = eax & mask;
841 
842 	tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
843 }
844 
845 static const struct cpu_dev amd_cpu_dev = {
846 	.c_vendor	= "AMD",
847 	.c_ident	= { "AuthenticAMD" },
848 #ifdef CONFIG_X86_32
849 	.legacy_models = {
850 		{ .family = 4, .model_names =
851 		  {
852 			  [3] = "486 DX/2",
853 			  [7] = "486 DX/2-WB",
854 			  [8] = "486 DX/4",
855 			  [9] = "486 DX/4-WB",
856 			  [14] = "Am5x86-WT",
857 			  [15] = "Am5x86-WB"
858 		  }
859 		},
860 	},
861 	.legacy_cache_size = amd_size_cache,
862 #endif
863 	.c_early_init   = early_init_amd,
864 	.c_detect_tlb	= cpu_detect_tlb_amd,
865 	.c_bsp_init	= bsp_init_amd,
866 	.c_init		= init_amd,
867 	.c_x86_vendor	= X86_VENDOR_AMD,
868 };
869 
870 cpu_dev_register(amd_cpu_dev);
871 
872 /*
873  * AMD errata checking
874  *
875  * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or
876  * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that
877  * have an OSVW id assigned, which it takes as first argument. Both take a
878  * variable number of family-specific model-stepping ranges created by
879  * AMD_MODEL_RANGE().
880  *
881  * Example:
882  *
883  * const int amd_erratum_319[] =
884  *	AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2),
885  *			   AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0),
886  *			   AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0));
887  */
888 
889 #define AMD_LEGACY_ERRATUM(...)		{ -1, __VA_ARGS__, 0 }
890 #define AMD_OSVW_ERRATUM(osvw_id, ...)	{ osvw_id, __VA_ARGS__, 0 }
891 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \
892 	((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end))
893 #define AMD_MODEL_RANGE_FAMILY(range)	(((range) >> 24) & 0xff)
894 #define AMD_MODEL_RANGE_START(range)	(((range) >> 12) & 0xfff)
895 #define AMD_MODEL_RANGE_END(range)	((range) & 0xfff)
896 
897 static const int amd_erratum_400[] =
898 	AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),
899 			    AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf));
900 
901 static const int amd_erratum_383[] =
902 	AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf));
903 
904 
905 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
906 {
907 	int osvw_id = *erratum++;
908 	u32 range;
909 	u32 ms;
910 
911 	if (osvw_id >= 0 && osvw_id < 65536 &&
912 	    cpu_has(cpu, X86_FEATURE_OSVW)) {
913 		u64 osvw_len;
914 
915 		rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len);
916 		if (osvw_id < osvw_len) {
917 			u64 osvw_bits;
918 
919 			rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6),
920 			    osvw_bits);
921 			return osvw_bits & (1ULL << (osvw_id & 0x3f));
922 		}
923 	}
924 
925 	/* OSVW unavailable or ID unknown, match family-model-stepping range */
926 	ms = (cpu->x86_model << 4) | cpu->x86_mask;
927 	while ((range = *erratum++))
928 		if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) &&
929 		    (ms >= AMD_MODEL_RANGE_START(range)) &&
930 		    (ms <= AMD_MODEL_RANGE_END(range)))
931 			return true;
932 
933 	return false;
934 }
935 
936 void set_dr_addr_mask(unsigned long mask, int dr)
937 {
938 	if (!boot_cpu_has(X86_FEATURE_BPEXT))
939 		return;
940 
941 	switch (dr) {
942 	case 0:
943 		wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0);
944 		break;
945 	case 1:
946 	case 2:
947 	case 3:
948 		wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0);
949 		break;
950 	default:
951 		break;
952 	}
953 }
954