1 // SPDX-License-Identifier: GPL-2.0-only 2 #include <linux/export.h> 3 #include <linux/bitops.h> 4 #include <linux/elf.h> 5 #include <linux/mm.h> 6 7 #include <linux/io.h> 8 #include <linux/sched.h> 9 #include <linux/sched/clock.h> 10 #include <linux/random.h> 11 #include <linux/topology.h> 12 #include <asm/processor.h> 13 #include <asm/apic.h> 14 #include <asm/cacheinfo.h> 15 #include <asm/cpu.h> 16 #include <asm/spec-ctrl.h> 17 #include <asm/smp.h> 18 #include <asm/pci-direct.h> 19 #include <asm/delay.h> 20 #include <asm/debugreg.h> 21 #include <asm/resctrl.h> 22 23 #ifdef CONFIG_X86_64 24 # include <asm/mmconfig.h> 25 # include <asm/set_memory.h> 26 #endif 27 28 #include "cpu.h" 29 30 static const int amd_erratum_383[]; 31 static const int amd_erratum_400[]; 32 static const int amd_erratum_1054[]; 33 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum); 34 35 /* 36 * nodes_per_socket: Stores the number of nodes per socket. 37 * Refer to Fam15h Models 00-0fh BKDG - CPUID Fn8000_001E_ECX 38 * Node Identifiers[10:8] 39 */ 40 static u32 nodes_per_socket = 1; 41 42 static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p) 43 { 44 u32 gprs[8] = { 0 }; 45 int err; 46 47 WARN_ONCE((boot_cpu_data.x86 != 0xf), 48 "%s should only be used on K8!\n", __func__); 49 50 gprs[1] = msr; 51 gprs[7] = 0x9c5a203a; 52 53 err = rdmsr_safe_regs(gprs); 54 55 *p = gprs[0] | ((u64)gprs[2] << 32); 56 57 return err; 58 } 59 60 static inline int wrmsrl_amd_safe(unsigned msr, unsigned long long val) 61 { 62 u32 gprs[8] = { 0 }; 63 64 WARN_ONCE((boot_cpu_data.x86 != 0xf), 65 "%s should only be used on K8!\n", __func__); 66 67 gprs[0] = (u32)val; 68 gprs[1] = msr; 69 gprs[2] = val >> 32; 70 gprs[7] = 0x9c5a203a; 71 72 return wrmsr_safe_regs(gprs); 73 } 74 75 /* 76 * B step AMD K6 before B 9730xxxx have hardware bugs that can cause 77 * misexecution of code under Linux. Owners of such processors should 78 * contact AMD for precise details and a CPU swap. 79 * 80 * See http://www.multimania.com/poulot/k6bug.html 81 * and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6" 82 * (Publication # 21266 Issue Date: August 1998) 83 * 84 * The following test is erm.. interesting. AMD neglected to up 85 * the chip setting when fixing the bug but they also tweaked some 86 * performance at the same time.. 87 */ 88 89 #ifdef CONFIG_X86_32 90 extern __visible void vide(void); 91 __asm__(".text\n" 92 ".globl vide\n" 93 ".type vide, @function\n" 94 ".align 4\n" 95 "vide: ret\n"); 96 #endif 97 98 static void init_amd_k5(struct cpuinfo_x86 *c) 99 { 100 #ifdef CONFIG_X86_32 101 /* 102 * General Systems BIOSen alias the cpu frequency registers 103 * of the Elan at 0x000df000. Unfortunately, one of the Linux 104 * drivers subsequently pokes it, and changes the CPU speed. 105 * Workaround : Remove the unneeded alias. 106 */ 107 #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ 108 #define CBAR_ENB (0x80000000) 109 #define CBAR_KEY (0X000000CB) 110 if (c->x86_model == 9 || c->x86_model == 10) { 111 if (inl(CBAR) & CBAR_ENB) 112 outl(0 | CBAR_KEY, CBAR); 113 } 114 #endif 115 } 116 117 static void init_amd_k6(struct cpuinfo_x86 *c) 118 { 119 #ifdef CONFIG_X86_32 120 u32 l, h; 121 int mbytes = get_num_physpages() >> (20-PAGE_SHIFT); 122 123 if (c->x86_model < 6) { 124 /* Based on AMD doc 20734R - June 2000 */ 125 if (c->x86_model == 0) { 126 clear_cpu_cap(c, X86_FEATURE_APIC); 127 set_cpu_cap(c, X86_FEATURE_PGE); 128 } 129 return; 130 } 131 132 if (c->x86_model == 6 && c->x86_stepping == 1) { 133 const int K6_BUG_LOOP = 1000000; 134 int n; 135 void (*f_vide)(void); 136 u64 d, d2; 137 138 pr_info("AMD K6 stepping B detected - "); 139 140 /* 141 * It looks like AMD fixed the 2.6.2 bug and improved indirect 142 * calls at the same time. 143 */ 144 145 n = K6_BUG_LOOP; 146 f_vide = vide; 147 OPTIMIZER_HIDE_VAR(f_vide); 148 d = rdtsc(); 149 while (n--) 150 f_vide(); 151 d2 = rdtsc(); 152 d = d2-d; 153 154 if (d > 20*K6_BUG_LOOP) 155 pr_cont("system stability may be impaired when more than 32 MB are used.\n"); 156 else 157 pr_cont("probably OK (after B9730xxxx).\n"); 158 } 159 160 /* K6 with old style WHCR */ 161 if (c->x86_model < 8 || 162 (c->x86_model == 8 && c->x86_stepping < 8)) { 163 /* We can only write allocate on the low 508Mb */ 164 if (mbytes > 508) 165 mbytes = 508; 166 167 rdmsr(MSR_K6_WHCR, l, h); 168 if ((l&0x0000FFFF) == 0) { 169 unsigned long flags; 170 l = (1<<0)|((mbytes/4)<<1); 171 local_irq_save(flags); 172 wbinvd(); 173 wrmsr(MSR_K6_WHCR, l, h); 174 local_irq_restore(flags); 175 pr_info("Enabling old style K6 write allocation for %d Mb\n", 176 mbytes); 177 } 178 return; 179 } 180 181 if ((c->x86_model == 8 && c->x86_stepping > 7) || 182 c->x86_model == 9 || c->x86_model == 13) { 183 /* The more serious chips .. */ 184 185 if (mbytes > 4092) 186 mbytes = 4092; 187 188 rdmsr(MSR_K6_WHCR, l, h); 189 if ((l&0xFFFF0000) == 0) { 190 unsigned long flags; 191 l = ((mbytes>>2)<<22)|(1<<16); 192 local_irq_save(flags); 193 wbinvd(); 194 wrmsr(MSR_K6_WHCR, l, h); 195 local_irq_restore(flags); 196 pr_info("Enabling new style K6 write allocation for %d Mb\n", 197 mbytes); 198 } 199 200 return; 201 } 202 203 if (c->x86_model == 10) { 204 /* AMD Geode LX is model 10 */ 205 /* placeholder for any needed mods */ 206 return; 207 } 208 #endif 209 } 210 211 static void init_amd_k7(struct cpuinfo_x86 *c) 212 { 213 #ifdef CONFIG_X86_32 214 u32 l, h; 215 216 /* 217 * Bit 15 of Athlon specific MSR 15, needs to be 0 218 * to enable SSE on Palomino/Morgan/Barton CPU's. 219 * If the BIOS didn't enable it already, enable it here. 220 */ 221 if (c->x86_model >= 6 && c->x86_model <= 10) { 222 if (!cpu_has(c, X86_FEATURE_XMM)) { 223 pr_info("Enabling disabled K7/SSE Support.\n"); 224 msr_clear_bit(MSR_K7_HWCR, 15); 225 set_cpu_cap(c, X86_FEATURE_XMM); 226 } 227 } 228 229 /* 230 * It's been determined by AMD that Athlons since model 8 stepping 1 231 * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx 232 * As per AMD technical note 27212 0.2 233 */ 234 if ((c->x86_model == 8 && c->x86_stepping >= 1) || (c->x86_model > 8)) { 235 rdmsr(MSR_K7_CLK_CTL, l, h); 236 if ((l & 0xfff00000) != 0x20000000) { 237 pr_info("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", 238 l, ((l & 0x000fffff)|0x20000000)); 239 wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); 240 } 241 } 242 243 /* calling is from identify_secondary_cpu() ? */ 244 if (!c->cpu_index) 245 return; 246 247 /* 248 * Certain Athlons might work (for various values of 'work') in SMP 249 * but they are not certified as MP capable. 250 */ 251 /* Athlon 660/661 is valid. */ 252 if ((c->x86_model == 6) && ((c->x86_stepping == 0) || 253 (c->x86_stepping == 1))) 254 return; 255 256 /* Duron 670 is valid */ 257 if ((c->x86_model == 7) && (c->x86_stepping == 0)) 258 return; 259 260 /* 261 * Athlon 662, Duron 671, and Athlon >model 7 have capability 262 * bit. It's worth noting that the A5 stepping (662) of some 263 * Athlon XP's have the MP bit set. 264 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for 265 * more. 266 */ 267 if (((c->x86_model == 6) && (c->x86_stepping >= 2)) || 268 ((c->x86_model == 7) && (c->x86_stepping >= 1)) || 269 (c->x86_model > 7)) 270 if (cpu_has(c, X86_FEATURE_MP)) 271 return; 272 273 /* If we get here, not a certified SMP capable AMD system. */ 274 275 /* 276 * Don't taint if we are running SMP kernel on a single non-MP 277 * approved Athlon 278 */ 279 WARN_ONCE(1, "WARNING: This combination of AMD" 280 " processors is not suitable for SMP.\n"); 281 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE); 282 #endif 283 } 284 285 #ifdef CONFIG_NUMA 286 /* 287 * To workaround broken NUMA config. Read the comment in 288 * srat_detect_node(). 289 */ 290 static int nearby_node(int apicid) 291 { 292 int i, node; 293 294 for (i = apicid - 1; i >= 0; i--) { 295 node = __apicid_to_node[i]; 296 if (node != NUMA_NO_NODE && node_online(node)) 297 return node; 298 } 299 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) { 300 node = __apicid_to_node[i]; 301 if (node != NUMA_NO_NODE && node_online(node)) 302 return node; 303 } 304 return first_node(node_online_map); /* Shouldn't happen */ 305 } 306 #endif 307 308 /* 309 * Fix up cpu_core_id for pre-F17h systems to be in the 310 * [0 .. cores_per_node - 1] range. Not really needed but 311 * kept so as not to break existing setups. 312 */ 313 static void legacy_fixup_core_id(struct cpuinfo_x86 *c) 314 { 315 u32 cus_per_node; 316 317 if (c->x86 >= 0x17) 318 return; 319 320 cus_per_node = c->x86_max_cores / nodes_per_socket; 321 c->cpu_core_id %= cus_per_node; 322 } 323 324 /* 325 * Fixup core topology information for 326 * (1) AMD multi-node processors 327 * Assumption: Number of cores in each internal node is the same. 328 * (2) AMD processors supporting compute units 329 */ 330 static void amd_get_topology(struct cpuinfo_x86 *c) 331 { 332 u8 node_id; 333 int cpu = smp_processor_id(); 334 335 /* get information required for multi-node processors */ 336 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 337 int err; 338 u32 eax, ebx, ecx, edx; 339 340 cpuid(0x8000001e, &eax, &ebx, &ecx, &edx); 341 342 node_id = ecx & 0xff; 343 344 if (c->x86 == 0x15) 345 c->cu_id = ebx & 0xff; 346 347 if (c->x86 >= 0x17) { 348 c->cpu_core_id = ebx & 0xff; 349 350 if (smp_num_siblings > 1) 351 c->x86_max_cores /= smp_num_siblings; 352 } 353 354 /* 355 * In case leaf B is available, use it to derive 356 * topology information. 357 */ 358 err = detect_extended_topology(c); 359 if (!err) 360 c->x86_coreid_bits = get_count_order(c->x86_max_cores); 361 362 cacheinfo_amd_init_llc_id(c, cpu, node_id); 363 364 } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) { 365 u64 value; 366 367 rdmsrl(MSR_FAM10H_NODE_ID, value); 368 node_id = value & 7; 369 370 per_cpu(cpu_llc_id, cpu) = node_id; 371 } else 372 return; 373 374 if (nodes_per_socket > 1) { 375 set_cpu_cap(c, X86_FEATURE_AMD_DCM); 376 legacy_fixup_core_id(c); 377 } 378 } 379 380 /* 381 * On a AMD dual core setup the lower bits of the APIC id distinguish the cores. 382 * Assumes number of cores is a power of two. 383 */ 384 static void amd_detect_cmp(struct cpuinfo_x86 *c) 385 { 386 unsigned bits; 387 int cpu = smp_processor_id(); 388 389 bits = c->x86_coreid_bits; 390 /* Low order bits define the core id (index of core in socket) */ 391 c->cpu_core_id = c->initial_apicid & ((1 << bits)-1); 392 /* Convert the initial APIC ID into the socket ID */ 393 c->phys_proc_id = c->initial_apicid >> bits; 394 /* use socket ID also for last level cache */ 395 per_cpu(cpu_llc_id, cpu) = c->phys_proc_id; 396 } 397 398 static void amd_detect_ppin(struct cpuinfo_x86 *c) 399 { 400 unsigned long long val; 401 402 if (!cpu_has(c, X86_FEATURE_AMD_PPIN)) 403 return; 404 405 /* When PPIN is defined in CPUID, still need to check PPIN_CTL MSR */ 406 if (rdmsrl_safe(MSR_AMD_PPIN_CTL, &val)) 407 goto clear_ppin; 408 409 /* PPIN is locked in disabled mode, clear feature bit */ 410 if ((val & 3UL) == 1UL) 411 goto clear_ppin; 412 413 /* If PPIN is disabled, try to enable it */ 414 if (!(val & 2UL)) { 415 wrmsrl_safe(MSR_AMD_PPIN_CTL, val | 2UL); 416 rdmsrl_safe(MSR_AMD_PPIN_CTL, &val); 417 } 418 419 /* If PPIN_EN bit is 1, return from here; otherwise fall through */ 420 if (val & 2UL) 421 return; 422 423 clear_ppin: 424 clear_cpu_cap(c, X86_FEATURE_AMD_PPIN); 425 } 426 427 u16 amd_get_nb_id(int cpu) 428 { 429 return per_cpu(cpu_llc_id, cpu); 430 } 431 EXPORT_SYMBOL_GPL(amd_get_nb_id); 432 433 u32 amd_get_nodes_per_socket(void) 434 { 435 return nodes_per_socket; 436 } 437 EXPORT_SYMBOL_GPL(amd_get_nodes_per_socket); 438 439 static void srat_detect_node(struct cpuinfo_x86 *c) 440 { 441 #ifdef CONFIG_NUMA 442 int cpu = smp_processor_id(); 443 int node; 444 unsigned apicid = c->apicid; 445 446 node = numa_cpu_node(cpu); 447 if (node == NUMA_NO_NODE) 448 node = per_cpu(cpu_llc_id, cpu); 449 450 /* 451 * On multi-fabric platform (e.g. Numascale NumaChip) a 452 * platform-specific handler needs to be called to fixup some 453 * IDs of the CPU. 454 */ 455 if (x86_cpuinit.fixup_cpu_id) 456 x86_cpuinit.fixup_cpu_id(c, node); 457 458 if (!node_online(node)) { 459 /* 460 * Two possibilities here: 461 * 462 * - The CPU is missing memory and no node was created. In 463 * that case try picking one from a nearby CPU. 464 * 465 * - The APIC IDs differ from the HyperTransport node IDs 466 * which the K8 northbridge parsing fills in. Assume 467 * they are all increased by a constant offset, but in 468 * the same order as the HT nodeids. If that doesn't 469 * result in a usable node fall back to the path for the 470 * previous case. 471 * 472 * This workaround operates directly on the mapping between 473 * APIC ID and NUMA node, assuming certain relationship 474 * between APIC ID, HT node ID and NUMA topology. As going 475 * through CPU mapping may alter the outcome, directly 476 * access __apicid_to_node[]. 477 */ 478 int ht_nodeid = c->initial_apicid; 479 480 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE) 481 node = __apicid_to_node[ht_nodeid]; 482 /* Pick a nearby node */ 483 if (!node_online(node)) 484 node = nearby_node(apicid); 485 } 486 numa_set_node(cpu, node); 487 #endif 488 } 489 490 static void early_init_amd_mc(struct cpuinfo_x86 *c) 491 { 492 #ifdef CONFIG_SMP 493 unsigned bits, ecx; 494 495 /* Multi core CPU? */ 496 if (c->extended_cpuid_level < 0x80000008) 497 return; 498 499 ecx = cpuid_ecx(0x80000008); 500 501 c->x86_max_cores = (ecx & 0xff) + 1; 502 503 /* CPU telling us the core id bits shift? */ 504 bits = (ecx >> 12) & 0xF; 505 506 /* Otherwise recompute */ 507 if (bits == 0) { 508 while ((1 << bits) < c->x86_max_cores) 509 bits++; 510 } 511 512 c->x86_coreid_bits = bits; 513 #endif 514 } 515 516 static void bsp_init_amd(struct cpuinfo_x86 *c) 517 { 518 519 #ifdef CONFIG_X86_64 520 if (c->x86 >= 0xf) { 521 unsigned long long tseg; 522 523 /* 524 * Split up direct mapping around the TSEG SMM area. 525 * Don't do it for gbpages because there seems very little 526 * benefit in doing so. 527 */ 528 if (!rdmsrl_safe(MSR_K8_TSEG_ADDR, &tseg)) { 529 unsigned long pfn = tseg >> PAGE_SHIFT; 530 531 pr_debug("tseg: %010llx\n", tseg); 532 if (pfn_range_is_mapped(pfn, pfn + 1)) 533 set_memory_4k((unsigned long)__va(tseg), 1); 534 } 535 } 536 #endif 537 538 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) { 539 540 if (c->x86 > 0x10 || 541 (c->x86 == 0x10 && c->x86_model >= 0x2)) { 542 u64 val; 543 544 rdmsrl(MSR_K7_HWCR, val); 545 if (!(val & BIT(24))) 546 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n"); 547 } 548 } 549 550 if (c->x86 == 0x15) { 551 unsigned long upperbit; 552 u32 cpuid, assoc; 553 554 cpuid = cpuid_edx(0x80000005); 555 assoc = cpuid >> 16 & 0xff; 556 upperbit = ((cpuid >> 24) << 10) / assoc; 557 558 va_align.mask = (upperbit - 1) & PAGE_MASK; 559 va_align.flags = ALIGN_VA_32 | ALIGN_VA_64; 560 561 /* A random value per boot for bit slice [12:upper_bit) */ 562 va_align.bits = get_random_int() & va_align.mask; 563 } 564 565 if (cpu_has(c, X86_FEATURE_MWAITX)) 566 use_mwaitx_delay(); 567 568 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 569 u32 ecx; 570 571 ecx = cpuid_ecx(0x8000001e); 572 nodes_per_socket = ((ecx >> 8) & 7) + 1; 573 } else if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) { 574 u64 value; 575 576 rdmsrl(MSR_FAM10H_NODE_ID, value); 577 nodes_per_socket = ((value >> 3) & 7) + 1; 578 } 579 580 if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) && 581 !boot_cpu_has(X86_FEATURE_VIRT_SSBD) && 582 c->x86 >= 0x15 && c->x86 <= 0x17) { 583 unsigned int bit; 584 585 switch (c->x86) { 586 case 0x15: bit = 54; break; 587 case 0x16: bit = 33; break; 588 case 0x17: bit = 10; break; 589 default: return; 590 } 591 /* 592 * Try to cache the base value so further operations can 593 * avoid RMW. If that faults, do not enable SSBD. 594 */ 595 if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) { 596 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD); 597 setup_force_cpu_cap(X86_FEATURE_SSBD); 598 x86_amd_ls_cfg_ssbd_mask = 1ULL << bit; 599 } 600 } 601 602 resctrl_cpu_detect(c); 603 } 604 605 static void early_detect_mem_encrypt(struct cpuinfo_x86 *c) 606 { 607 u64 msr; 608 609 /* 610 * BIOS support is required for SME and SEV. 611 * For SME: If BIOS has enabled SME then adjust x86_phys_bits by 612 * the SME physical address space reduction value. 613 * If BIOS has not enabled SME then don't advertise the 614 * SME feature (set in scattered.c). 615 * For SEV: If BIOS has not enabled SEV then don't advertise the 616 * SEV feature (set in scattered.c). 617 * 618 * In all cases, since support for SME and SEV requires long mode, 619 * don't advertise the feature under CONFIG_X86_32. 620 */ 621 if (cpu_has(c, X86_FEATURE_SME) || cpu_has(c, X86_FEATURE_SEV)) { 622 /* Check if memory encryption is enabled */ 623 rdmsrl(MSR_K8_SYSCFG, msr); 624 if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT)) 625 goto clear_all; 626 627 /* 628 * Always adjust physical address bits. Even though this 629 * will be a value above 32-bits this is still done for 630 * CONFIG_X86_32 so that accurate values are reported. 631 */ 632 c->x86_phys_bits -= (cpuid_ebx(0x8000001f) >> 6) & 0x3f; 633 634 if (IS_ENABLED(CONFIG_X86_32)) 635 goto clear_all; 636 637 rdmsrl(MSR_K7_HWCR, msr); 638 if (!(msr & MSR_K7_HWCR_SMMLOCK)) 639 goto clear_sev; 640 641 return; 642 643 clear_all: 644 setup_clear_cpu_cap(X86_FEATURE_SME); 645 clear_sev: 646 setup_clear_cpu_cap(X86_FEATURE_SEV); 647 } 648 } 649 650 static void early_init_amd(struct cpuinfo_x86 *c) 651 { 652 u64 value; 653 u32 dummy; 654 655 early_init_amd_mc(c); 656 657 #ifdef CONFIG_X86_32 658 if (c->x86 == 6) 659 set_cpu_cap(c, X86_FEATURE_K7); 660 #endif 661 662 if (c->x86 >= 0xf) 663 set_cpu_cap(c, X86_FEATURE_K8); 664 665 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy); 666 667 /* 668 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate 669 * with P/T states and does not stop in deep C-states 670 */ 671 if (c->x86_power & (1 << 8)) { 672 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); 673 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC); 674 } 675 676 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */ 677 if (c->x86_power & BIT(12)) 678 set_cpu_cap(c, X86_FEATURE_ACC_POWER); 679 680 #ifdef CONFIG_X86_64 681 set_cpu_cap(c, X86_FEATURE_SYSCALL32); 682 #else 683 /* Set MTRR capability flag if appropriate */ 684 if (c->x86 == 5) 685 if (c->x86_model == 13 || c->x86_model == 9 || 686 (c->x86_model == 8 && c->x86_stepping >= 8)) 687 set_cpu_cap(c, X86_FEATURE_K6_MTRR); 688 #endif 689 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI) 690 /* 691 * ApicID can always be treated as an 8-bit value for AMD APIC versions 692 * >= 0x10, but even old K8s came out of reset with version 0x10. So, we 693 * can safely set X86_FEATURE_EXTD_APICID unconditionally for families 694 * after 16h. 695 */ 696 if (boot_cpu_has(X86_FEATURE_APIC)) { 697 if (c->x86 > 0x16) 698 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 699 else if (c->x86 >= 0xf) { 700 /* check CPU config space for extended APIC ID */ 701 unsigned int val; 702 703 val = read_pci_config(0, 24, 0, 0x68); 704 if ((val >> 17 & 0x3) == 0x3) 705 set_cpu_cap(c, X86_FEATURE_EXTD_APICID); 706 } 707 } 708 #endif 709 710 /* 711 * This is only needed to tell the kernel whether to use VMCALL 712 * and VMMCALL. VMMCALL is never executed except under virt, so 713 * we can set it unconditionally. 714 */ 715 set_cpu_cap(c, X86_FEATURE_VMMCALL); 716 717 /* F16h erratum 793, CVE-2013-6885 */ 718 if (c->x86 == 0x16 && c->x86_model <= 0xf) 719 msr_set_bit(MSR_AMD64_LS_CFG, 15); 720 721 /* 722 * Check whether the machine is affected by erratum 400. This is 723 * used to select the proper idle routine and to enable the check 724 * whether the machine is affected in arch_post_acpi_init(), which 725 * sets the X86_BUG_AMD_APIC_C1E bug depending on the MSR check. 726 */ 727 if (cpu_has_amd_erratum(c, amd_erratum_400)) 728 set_cpu_bug(c, X86_BUG_AMD_E400); 729 730 early_detect_mem_encrypt(c); 731 732 /* Re-enable TopologyExtensions if switched off by BIOS */ 733 if (c->x86 == 0x15 && 734 (c->x86_model >= 0x10 && c->x86_model <= 0x6f) && 735 !cpu_has(c, X86_FEATURE_TOPOEXT)) { 736 737 if (msr_set_bit(0xc0011005, 54) > 0) { 738 rdmsrl(0xc0011005, value); 739 if (value & BIT_64(54)) { 740 set_cpu_cap(c, X86_FEATURE_TOPOEXT); 741 pr_info_once(FW_INFO "CPU: Re-enabling disabled Topology Extensions Support.\n"); 742 } 743 } 744 } 745 746 if (cpu_has(c, X86_FEATURE_TOPOEXT)) 747 smp_num_siblings = ((cpuid_ebx(0x8000001e) >> 8) & 0xff) + 1; 748 } 749 750 static void init_amd_k8(struct cpuinfo_x86 *c) 751 { 752 u32 level; 753 u64 value; 754 755 /* On C+ stepping K8 rep microcode works well for copy/memset */ 756 level = cpuid_eax(1); 757 if ((level >= 0x0f48 && level < 0x0f50) || level >= 0x0f58) 758 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 759 760 /* 761 * Some BIOSes incorrectly force this feature, but only K8 revision D 762 * (model = 0x14) and later actually support it. 763 * (AMD Erratum #110, docId: 25759). 764 */ 765 if (c->x86_model < 0x14 && cpu_has(c, X86_FEATURE_LAHF_LM)) { 766 clear_cpu_cap(c, X86_FEATURE_LAHF_LM); 767 if (!rdmsrl_amd_safe(0xc001100d, &value)) { 768 value &= ~BIT_64(32); 769 wrmsrl_amd_safe(0xc001100d, value); 770 } 771 } 772 773 if (!c->x86_model_id[0]) 774 strcpy(c->x86_model_id, "Hammer"); 775 776 #ifdef CONFIG_SMP 777 /* 778 * Disable TLB flush filter by setting HWCR.FFDIS on K8 779 * bit 6 of msr C001_0015 780 * 781 * Errata 63 for SH-B3 steppings 782 * Errata 122 for all steppings (F+ have it disabled by default) 783 */ 784 msr_set_bit(MSR_K7_HWCR, 6); 785 #endif 786 set_cpu_bug(c, X86_BUG_SWAPGS_FENCE); 787 } 788 789 static void init_amd_gh(struct cpuinfo_x86 *c) 790 { 791 #ifdef CONFIG_MMCONF_FAM10H 792 /* do this for boot cpu */ 793 if (c == &boot_cpu_data) 794 check_enable_amd_mmconf_dmi(); 795 796 fam10h_check_enable_mmcfg(); 797 #endif 798 799 /* 800 * Disable GART TLB Walk Errors on Fam10h. We do this here because this 801 * is always needed when GART is enabled, even in a kernel which has no 802 * MCE support built in. BIOS should disable GartTlbWlk Errors already. 803 * If it doesn't, we do it here as suggested by the BKDG. 804 * 805 * Fixes: https://bugzilla.kernel.org/show_bug.cgi?id=33012 806 */ 807 msr_set_bit(MSR_AMD64_MCx_MASK(4), 10); 808 809 /* 810 * On family 10h BIOS may not have properly enabled WC+ support, causing 811 * it to be converted to CD memtype. This may result in performance 812 * degradation for certain nested-paging guests. Prevent this conversion 813 * by clearing bit 24 in MSR_AMD64_BU_CFG2. 814 * 815 * NOTE: we want to use the _safe accessors so as not to #GP kvm 816 * guests on older kvm hosts. 817 */ 818 msr_clear_bit(MSR_AMD64_BU_CFG2, 24); 819 820 if (cpu_has_amd_erratum(c, amd_erratum_383)) 821 set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH); 822 } 823 824 #define MSR_AMD64_DE_CFG 0xC0011029 825 826 static void init_amd_ln(struct cpuinfo_x86 *c) 827 { 828 /* 829 * Apply erratum 665 fix unconditionally so machines without a BIOS 830 * fix work. 831 */ 832 msr_set_bit(MSR_AMD64_DE_CFG, 31); 833 } 834 835 static bool rdrand_force; 836 837 static int __init rdrand_cmdline(char *str) 838 { 839 if (!str) 840 return -EINVAL; 841 842 if (!strcmp(str, "force")) 843 rdrand_force = true; 844 else 845 return -EINVAL; 846 847 return 0; 848 } 849 early_param("rdrand", rdrand_cmdline); 850 851 static void clear_rdrand_cpuid_bit(struct cpuinfo_x86 *c) 852 { 853 /* 854 * Saving of the MSR used to hide the RDRAND support during 855 * suspend/resume is done by arch/x86/power/cpu.c, which is 856 * dependent on CONFIG_PM_SLEEP. 857 */ 858 if (!IS_ENABLED(CONFIG_PM_SLEEP)) 859 return; 860 861 /* 862 * The nordrand option can clear X86_FEATURE_RDRAND, so check for 863 * RDRAND support using the CPUID function directly. 864 */ 865 if (!(cpuid_ecx(1) & BIT(30)) || rdrand_force) 866 return; 867 868 msr_clear_bit(MSR_AMD64_CPUID_FN_1, 62); 869 870 /* 871 * Verify that the CPUID change has occurred in case the kernel is 872 * running virtualized and the hypervisor doesn't support the MSR. 873 */ 874 if (cpuid_ecx(1) & BIT(30)) { 875 pr_info_once("BIOS may not properly restore RDRAND after suspend, but hypervisor does not support hiding RDRAND via CPUID.\n"); 876 return; 877 } 878 879 clear_cpu_cap(c, X86_FEATURE_RDRAND); 880 pr_info_once("BIOS may not properly restore RDRAND after suspend, hiding RDRAND via CPUID. Use rdrand=force to reenable.\n"); 881 } 882 883 static void init_amd_jg(struct cpuinfo_x86 *c) 884 { 885 /* 886 * Some BIOS implementations do not restore proper RDRAND support 887 * across suspend and resume. Check on whether to hide the RDRAND 888 * instruction support via CPUID. 889 */ 890 clear_rdrand_cpuid_bit(c); 891 } 892 893 static void init_amd_bd(struct cpuinfo_x86 *c) 894 { 895 u64 value; 896 897 /* 898 * The way access filter has a performance penalty on some workloads. 899 * Disable it on the affected CPUs. 900 */ 901 if ((c->x86_model >= 0x02) && (c->x86_model < 0x20)) { 902 if (!rdmsrl_safe(MSR_F15H_IC_CFG, &value) && !(value & 0x1E)) { 903 value |= 0x1E; 904 wrmsrl_safe(MSR_F15H_IC_CFG, value); 905 } 906 } 907 908 /* 909 * Some BIOS implementations do not restore proper RDRAND support 910 * across suspend and resume. Check on whether to hide the RDRAND 911 * instruction support via CPUID. 912 */ 913 clear_rdrand_cpuid_bit(c); 914 } 915 916 static void init_amd_zn(struct cpuinfo_x86 *c) 917 { 918 set_cpu_cap(c, X86_FEATURE_ZEN); 919 920 #ifdef CONFIG_NUMA 921 node_reclaim_distance = 32; 922 #endif 923 924 /* 925 * Fix erratum 1076: CPB feature bit not being set in CPUID. 926 * Always set it, except when running under a hypervisor. 927 */ 928 if (!cpu_has(c, X86_FEATURE_HYPERVISOR) && !cpu_has(c, X86_FEATURE_CPB)) 929 set_cpu_cap(c, X86_FEATURE_CPB); 930 } 931 932 static void init_amd(struct cpuinfo_x86 *c) 933 { 934 early_init_amd(c); 935 936 /* 937 * Bit 31 in normal CPUID used for nonstandard 3DNow ID; 938 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway 939 */ 940 clear_cpu_cap(c, 0*32+31); 941 942 if (c->x86 >= 0x10) 943 set_cpu_cap(c, X86_FEATURE_REP_GOOD); 944 945 /* get apicid instead of initial apic id from cpuid */ 946 c->apicid = hard_smp_processor_id(); 947 948 /* K6s reports MCEs but don't actually have all the MSRs */ 949 if (c->x86 < 6) 950 clear_cpu_cap(c, X86_FEATURE_MCE); 951 952 switch (c->x86) { 953 case 4: init_amd_k5(c); break; 954 case 5: init_amd_k6(c); break; 955 case 6: init_amd_k7(c); break; 956 case 0xf: init_amd_k8(c); break; 957 case 0x10: init_amd_gh(c); break; 958 case 0x12: init_amd_ln(c); break; 959 case 0x15: init_amd_bd(c); break; 960 case 0x16: init_amd_jg(c); break; 961 case 0x17: fallthrough; 962 case 0x19: init_amd_zn(c); break; 963 } 964 965 /* 966 * Enable workaround for FXSAVE leak on CPUs 967 * without a XSaveErPtr feature 968 */ 969 if ((c->x86 >= 6) && (!cpu_has(c, X86_FEATURE_XSAVEERPTR))) 970 set_cpu_bug(c, X86_BUG_FXSAVE_LEAK); 971 972 cpu_detect_cache_sizes(c); 973 974 amd_detect_cmp(c); 975 amd_get_topology(c); 976 srat_detect_node(c); 977 amd_detect_ppin(c); 978 979 init_amd_cacheinfo(c); 980 981 if (cpu_has(c, X86_FEATURE_XMM2)) { 982 /* 983 * Use LFENCE for execution serialization. On families which 984 * don't have that MSR, LFENCE is already serializing. 985 * msr_set_bit() uses the safe accessors, too, even if the MSR 986 * is not present. 987 */ 988 msr_set_bit(MSR_F10H_DECFG, 989 MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT); 990 991 /* A serializing LFENCE stops RDTSC speculation */ 992 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC); 993 } 994 995 /* 996 * Family 0x12 and above processors have APIC timer 997 * running in deep C states. 998 */ 999 if (c->x86 > 0x11) 1000 set_cpu_cap(c, X86_FEATURE_ARAT); 1001 1002 /* 3DNow or LM implies PREFETCHW */ 1003 if (!cpu_has(c, X86_FEATURE_3DNOWPREFETCH)) 1004 if (cpu_has(c, X86_FEATURE_3DNOW) || cpu_has(c, X86_FEATURE_LM)) 1005 set_cpu_cap(c, X86_FEATURE_3DNOWPREFETCH); 1006 1007 /* AMD CPUs don't reset SS attributes on SYSRET, Xen does. */ 1008 if (!cpu_has(c, X86_FEATURE_XENPV)) 1009 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS); 1010 1011 /* 1012 * Turn on the Instructions Retired free counter on machines not 1013 * susceptible to erratum #1054 "Instructions Retired Performance 1014 * Counter May Be Inaccurate". 1015 */ 1016 if (cpu_has(c, X86_FEATURE_IRPERF) && 1017 !cpu_has_amd_erratum(c, amd_erratum_1054)) 1018 msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_IRPERF_EN_BIT); 1019 } 1020 1021 #ifdef CONFIG_X86_32 1022 static unsigned int amd_size_cache(struct cpuinfo_x86 *c, unsigned int size) 1023 { 1024 /* AMD errata T13 (order #21922) */ 1025 if (c->x86 == 6) { 1026 /* Duron Rev A0 */ 1027 if (c->x86_model == 3 && c->x86_stepping == 0) 1028 size = 64; 1029 /* Tbird rev A1/A2 */ 1030 if (c->x86_model == 4 && 1031 (c->x86_stepping == 0 || c->x86_stepping == 1)) 1032 size = 256; 1033 } 1034 return size; 1035 } 1036 #endif 1037 1038 static void cpu_detect_tlb_amd(struct cpuinfo_x86 *c) 1039 { 1040 u32 ebx, eax, ecx, edx; 1041 u16 mask = 0xfff; 1042 1043 if (c->x86 < 0xf) 1044 return; 1045 1046 if (c->extended_cpuid_level < 0x80000006) 1047 return; 1048 1049 cpuid(0x80000006, &eax, &ebx, &ecx, &edx); 1050 1051 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask; 1052 tlb_lli_4k[ENTRIES] = ebx & mask; 1053 1054 /* 1055 * K8 doesn't have 2M/4M entries in the L2 TLB so read out the L1 TLB 1056 * characteristics from the CPUID function 0x80000005 instead. 1057 */ 1058 if (c->x86 == 0xf) { 1059 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 1060 mask = 0xff; 1061 } 1062 1063 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 1064 if (!((eax >> 16) & mask)) 1065 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff; 1066 else 1067 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask; 1068 1069 /* a 4M entry uses two 2M entries */ 1070 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1; 1071 1072 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */ 1073 if (!(eax & mask)) { 1074 /* Erratum 658 */ 1075 if (c->x86 == 0x15 && c->x86_model <= 0x1f) { 1076 tlb_lli_2m[ENTRIES] = 1024; 1077 } else { 1078 cpuid(0x80000005, &eax, &ebx, &ecx, &edx); 1079 tlb_lli_2m[ENTRIES] = eax & 0xff; 1080 } 1081 } else 1082 tlb_lli_2m[ENTRIES] = eax & mask; 1083 1084 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1; 1085 } 1086 1087 static const struct cpu_dev amd_cpu_dev = { 1088 .c_vendor = "AMD", 1089 .c_ident = { "AuthenticAMD" }, 1090 #ifdef CONFIG_X86_32 1091 .legacy_models = { 1092 { .family = 4, .model_names = 1093 { 1094 [3] = "486 DX/2", 1095 [7] = "486 DX/2-WB", 1096 [8] = "486 DX/4", 1097 [9] = "486 DX/4-WB", 1098 [14] = "Am5x86-WT", 1099 [15] = "Am5x86-WB" 1100 } 1101 }, 1102 }, 1103 .legacy_cache_size = amd_size_cache, 1104 #endif 1105 .c_early_init = early_init_amd, 1106 .c_detect_tlb = cpu_detect_tlb_amd, 1107 .c_bsp_init = bsp_init_amd, 1108 .c_init = init_amd, 1109 .c_x86_vendor = X86_VENDOR_AMD, 1110 }; 1111 1112 cpu_dev_register(amd_cpu_dev); 1113 1114 /* 1115 * AMD errata checking 1116 * 1117 * Errata are defined as arrays of ints using the AMD_LEGACY_ERRATUM() or 1118 * AMD_OSVW_ERRATUM() macros. The latter is intended for newer errata that 1119 * have an OSVW id assigned, which it takes as first argument. Both take a 1120 * variable number of family-specific model-stepping ranges created by 1121 * AMD_MODEL_RANGE(). 1122 * 1123 * Example: 1124 * 1125 * const int amd_erratum_319[] = 1126 * AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0x4, 0x2), 1127 * AMD_MODEL_RANGE(0x10, 0x8, 0x0, 0x8, 0x0), 1128 * AMD_MODEL_RANGE(0x10, 0x9, 0x0, 0x9, 0x0)); 1129 */ 1130 1131 #define AMD_LEGACY_ERRATUM(...) { -1, __VA_ARGS__, 0 } 1132 #define AMD_OSVW_ERRATUM(osvw_id, ...) { osvw_id, __VA_ARGS__, 0 } 1133 #define AMD_MODEL_RANGE(f, m_start, s_start, m_end, s_end) \ 1134 ((f << 24) | (m_start << 16) | (s_start << 12) | (m_end << 4) | (s_end)) 1135 #define AMD_MODEL_RANGE_FAMILY(range) (((range) >> 24) & 0xff) 1136 #define AMD_MODEL_RANGE_START(range) (((range) >> 12) & 0xfff) 1137 #define AMD_MODEL_RANGE_END(range) ((range) & 0xfff) 1138 1139 static const int amd_erratum_400[] = 1140 AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf), 1141 AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf)); 1142 1143 static const int amd_erratum_383[] = 1144 AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0, 0, 0xff, 0xf)); 1145 1146 /* #1054: Instructions Retired Performance Counter May Be Inaccurate */ 1147 static const int amd_erratum_1054[] = 1148 AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0, 0, 0x2f, 0xf)); 1149 1150 static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum) 1151 { 1152 int osvw_id = *erratum++; 1153 u32 range; 1154 u32 ms; 1155 1156 if (osvw_id >= 0 && osvw_id < 65536 && 1157 cpu_has(cpu, X86_FEATURE_OSVW)) { 1158 u64 osvw_len; 1159 1160 rdmsrl(MSR_AMD64_OSVW_ID_LENGTH, osvw_len); 1161 if (osvw_id < osvw_len) { 1162 u64 osvw_bits; 1163 1164 rdmsrl(MSR_AMD64_OSVW_STATUS + (osvw_id >> 6), 1165 osvw_bits); 1166 return osvw_bits & (1ULL << (osvw_id & 0x3f)); 1167 } 1168 } 1169 1170 /* OSVW unavailable or ID unknown, match family-model-stepping range */ 1171 ms = (cpu->x86_model << 4) | cpu->x86_stepping; 1172 while ((range = *erratum++)) 1173 if ((cpu->x86 == AMD_MODEL_RANGE_FAMILY(range)) && 1174 (ms >= AMD_MODEL_RANGE_START(range)) && 1175 (ms <= AMD_MODEL_RANGE_END(range))) 1176 return true; 1177 1178 return false; 1179 } 1180 1181 void set_dr_addr_mask(unsigned long mask, int dr) 1182 { 1183 if (!boot_cpu_has(X86_FEATURE_BPEXT)) 1184 return; 1185 1186 switch (dr) { 1187 case 0: 1188 wrmsr(MSR_F16H_DR0_ADDR_MASK, mask, 0); 1189 break; 1190 case 1: 1191 case 2: 1192 case 3: 1193 wrmsr(MSR_F16H_DR1_ADDR_MASK - 1 + dr, mask, 0); 1194 break; 1195 default: 1196 break; 1197 } 1198 } 1199