1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * SGI UV APIC functions (note: not an Intel compatible APIC) 7 * 8 * Copyright (C) 2007-2010 Silicon Graphics, Inc. All rights reserved. 9 */ 10 #include <linux/cpumask.h> 11 #include <linux/hardirq.h> 12 #include <linux/proc_fs.h> 13 #include <linux/threads.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/string.h> 17 #include <linux/ctype.h> 18 #include <linux/sched.h> 19 #include <linux/timer.h> 20 #include <linux/slab.h> 21 #include <linux/cpu.h> 22 #include <linux/init.h> 23 #include <linux/io.h> 24 #include <linux/pci.h> 25 #include <linux/kdebug.h> 26 #include <linux/delay.h> 27 #include <linux/crash_dump.h> 28 29 #include <asm/uv/uv_mmrs.h> 30 #include <asm/uv/uv_hub.h> 31 #include <asm/current.h> 32 #include <asm/pgtable.h> 33 #include <asm/uv/bios.h> 34 #include <asm/uv/uv.h> 35 #include <asm/apic.h> 36 #include <asm/ipi.h> 37 #include <asm/smp.h> 38 #include <asm/x86_init.h> 39 #include <asm/emergency-restart.h> 40 #include <asm/nmi.h> 41 42 /* BMC sets a bit this MMR non-zero before sending an NMI */ 43 #define UVH_NMI_MMR UVH_SCRATCH5 44 #define UVH_NMI_MMR_CLEAR (UVH_NMI_MMR + 8) 45 #define UV_NMI_PENDING_MASK (1UL << 63) 46 DEFINE_PER_CPU(unsigned long, cpu_last_nmi_count); 47 48 DEFINE_PER_CPU(int, x2apic_extra_bits); 49 50 #define PR_DEVEL(fmt, args...) pr_devel("%s: " fmt, __func__, args) 51 52 static enum uv_system_type uv_system_type; 53 static u64 gru_start_paddr, gru_end_paddr; 54 static union uvh_apicid uvh_apicid; 55 int uv_min_hub_revision_id; 56 EXPORT_SYMBOL_GPL(uv_min_hub_revision_id); 57 unsigned int uv_apicid_hibits; 58 EXPORT_SYMBOL_GPL(uv_apicid_hibits); 59 static DEFINE_SPINLOCK(uv_nmi_lock); 60 61 static struct apic apic_x2apic_uv_x; 62 63 static unsigned long __init uv_early_read_mmr(unsigned long addr) 64 { 65 unsigned long val, *mmr; 66 67 mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr)); 68 val = *mmr; 69 early_iounmap(mmr, sizeof(*mmr)); 70 return val; 71 } 72 73 static inline bool is_GRU_range(u64 start, u64 end) 74 { 75 return start >= gru_start_paddr && end <= gru_end_paddr; 76 } 77 78 static bool uv_is_untracked_pat_range(u64 start, u64 end) 79 { 80 return is_ISA_range(start, end) || is_GRU_range(start, end); 81 } 82 83 static int __init early_get_pnodeid(void) 84 { 85 union uvh_node_id_u node_id; 86 union uvh_rh_gam_config_mmr_u m_n_config; 87 int pnode; 88 89 /* Currently, all blades have same revision number */ 90 node_id.v = uv_early_read_mmr(UVH_NODE_ID); 91 m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR); 92 uv_min_hub_revision_id = node_id.s.revision; 93 94 if (node_id.s.part_number == UV2_HUB_PART_NUMBER) 95 uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1; 96 if (node_id.s.part_number == UV2_HUB_PART_NUMBER_X) 97 uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1; 98 99 uv_hub_info->hub_revision = uv_min_hub_revision_id; 100 pnode = (node_id.s.node_id >> 1) & ((1 << m_n_config.s.n_skt) - 1); 101 return pnode; 102 } 103 104 static void __init early_get_apic_pnode_shift(void) 105 { 106 uvh_apicid.v = uv_early_read_mmr(UVH_APICID); 107 if (!uvh_apicid.v) 108 /* 109 * Old bios, use default value 110 */ 111 uvh_apicid.s.pnode_shift = UV_APIC_PNODE_SHIFT; 112 } 113 114 /* 115 * Add an extra bit as dictated by bios to the destination apicid of 116 * interrupts potentially passing through the UV HUB. This prevents 117 * a deadlock between interrupts and IO port operations. 118 */ 119 static void __init uv_set_apicid_hibit(void) 120 { 121 union uv1h_lb_target_physical_apic_id_mask_u apicid_mask; 122 123 if (is_uv1_hub()) { 124 apicid_mask.v = 125 uv_early_read_mmr(UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK); 126 uv_apicid_hibits = 127 apicid_mask.s1.bit_enables & UV_APICID_HIBIT_MASK; 128 } 129 } 130 131 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id) 132 { 133 int pnodeid, is_uv1, is_uv2; 134 135 is_uv1 = !strcmp(oem_id, "SGI"); 136 is_uv2 = !strcmp(oem_id, "SGI2"); 137 if (is_uv1 || is_uv2) { 138 uv_hub_info->hub_revision = 139 is_uv1 ? UV1_HUB_REVISION_BASE : UV2_HUB_REVISION_BASE; 140 pnodeid = early_get_pnodeid(); 141 early_get_apic_pnode_shift(); 142 x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range; 143 x86_platform.nmi_init = uv_nmi_init; 144 if (!strcmp(oem_table_id, "UVL")) 145 uv_system_type = UV_LEGACY_APIC; 146 else if (!strcmp(oem_table_id, "UVX")) 147 uv_system_type = UV_X2APIC; 148 else if (!strcmp(oem_table_id, "UVH")) { 149 __this_cpu_write(x2apic_extra_bits, 150 pnodeid << uvh_apicid.s.pnode_shift); 151 uv_system_type = UV_NON_UNIQUE_APIC; 152 uv_set_apicid_hibit(); 153 return 1; 154 } 155 } 156 return 0; 157 } 158 159 enum uv_system_type get_uv_system_type(void) 160 { 161 return uv_system_type; 162 } 163 164 int is_uv_system(void) 165 { 166 return uv_system_type != UV_NONE; 167 } 168 EXPORT_SYMBOL_GPL(is_uv_system); 169 170 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); 171 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info); 172 173 struct uv_blade_info *uv_blade_info; 174 EXPORT_SYMBOL_GPL(uv_blade_info); 175 176 short *uv_node_to_blade; 177 EXPORT_SYMBOL_GPL(uv_node_to_blade); 178 179 short *uv_cpu_to_blade; 180 EXPORT_SYMBOL_GPL(uv_cpu_to_blade); 181 182 short uv_possible_blades; 183 EXPORT_SYMBOL_GPL(uv_possible_blades); 184 185 unsigned long sn_rtc_cycles_per_second; 186 EXPORT_SYMBOL(sn_rtc_cycles_per_second); 187 188 static int __cpuinit uv_wakeup_secondary(int phys_apicid, unsigned long start_rip) 189 { 190 #ifdef CONFIG_SMP 191 unsigned long val; 192 int pnode; 193 194 pnode = uv_apicid_to_pnode(phys_apicid); 195 phys_apicid |= uv_apicid_hibits; 196 val = (1UL << UVH_IPI_INT_SEND_SHFT) | 197 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | 198 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | 199 APIC_DM_INIT; 200 uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 201 202 val = (1UL << UVH_IPI_INT_SEND_SHFT) | 203 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | 204 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | 205 APIC_DM_STARTUP; 206 uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 207 208 atomic_set(&init_deasserted, 1); 209 #endif 210 return 0; 211 } 212 213 static void uv_send_IPI_one(int cpu, int vector) 214 { 215 unsigned long apicid; 216 int pnode; 217 218 apicid = per_cpu(x86_cpu_to_apicid, cpu); 219 pnode = uv_apicid_to_pnode(apicid); 220 uv_hub_send_ipi(pnode, apicid, vector); 221 } 222 223 static void uv_send_IPI_mask(const struct cpumask *mask, int vector) 224 { 225 unsigned int cpu; 226 227 for_each_cpu(cpu, mask) 228 uv_send_IPI_one(cpu, vector); 229 } 230 231 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) 232 { 233 unsigned int this_cpu = smp_processor_id(); 234 unsigned int cpu; 235 236 for_each_cpu(cpu, mask) { 237 if (cpu != this_cpu) 238 uv_send_IPI_one(cpu, vector); 239 } 240 } 241 242 static void uv_send_IPI_allbutself(int vector) 243 { 244 unsigned int this_cpu = smp_processor_id(); 245 unsigned int cpu; 246 247 for_each_online_cpu(cpu) { 248 if (cpu != this_cpu) 249 uv_send_IPI_one(cpu, vector); 250 } 251 } 252 253 static void uv_send_IPI_all(int vector) 254 { 255 uv_send_IPI_mask(cpu_online_mask, vector); 256 } 257 258 static int uv_apic_id_valid(int apicid) 259 { 260 return 1; 261 } 262 263 static int uv_apic_id_registered(void) 264 { 265 return 1; 266 } 267 268 static void uv_init_apic_ldr(void) 269 { 270 } 271 272 static int 273 uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 274 const struct cpumask *andmask, 275 unsigned int *apicid) 276 { 277 int unsigned cpu; 278 279 /* 280 * We're using fixed IRQ delivery, can only return one phys APIC ID. 281 * May as well be the first. 282 */ 283 for_each_cpu_and(cpu, cpumask, andmask) { 284 if (cpumask_test_cpu(cpu, cpu_online_mask)) 285 break; 286 } 287 288 if (likely(cpu < nr_cpu_ids)) { 289 *apicid = per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits; 290 return 0; 291 } 292 293 return -EINVAL; 294 } 295 296 static unsigned int x2apic_get_apic_id(unsigned long x) 297 { 298 unsigned int id; 299 300 WARN_ON(preemptible() && num_online_cpus() > 1); 301 id = x | __this_cpu_read(x2apic_extra_bits); 302 303 return id; 304 } 305 306 static unsigned long set_apic_id(unsigned int id) 307 { 308 unsigned long x; 309 310 /* maskout x2apic_extra_bits ? */ 311 x = id; 312 return x; 313 } 314 315 static unsigned int uv_read_apic_id(void) 316 { 317 318 return x2apic_get_apic_id(apic_read(APIC_ID)); 319 } 320 321 static int uv_phys_pkg_id(int initial_apicid, int index_msb) 322 { 323 return uv_read_apic_id() >> index_msb; 324 } 325 326 static void uv_send_IPI_self(int vector) 327 { 328 apic_write(APIC_SELF_IPI, vector); 329 } 330 331 static int uv_probe(void) 332 { 333 return apic == &apic_x2apic_uv_x; 334 } 335 336 static struct apic __refdata apic_x2apic_uv_x = { 337 338 .name = "UV large system", 339 .probe = uv_probe, 340 .acpi_madt_oem_check = uv_acpi_madt_oem_check, 341 .apic_id_valid = uv_apic_id_valid, 342 .apic_id_registered = uv_apic_id_registered, 343 344 .irq_delivery_mode = dest_Fixed, 345 .irq_dest_mode = 0, /* physical */ 346 347 .target_cpus = online_target_cpus, 348 .disable_esr = 0, 349 .dest_logical = APIC_DEST_LOGICAL, 350 .check_apicid_used = NULL, 351 .check_apicid_present = NULL, 352 353 .vector_allocation_domain = default_vector_allocation_domain, 354 .init_apic_ldr = uv_init_apic_ldr, 355 356 .ioapic_phys_id_map = NULL, 357 .setup_apic_routing = NULL, 358 .multi_timer_check = NULL, 359 .cpu_present_to_apicid = default_cpu_present_to_apicid, 360 .apicid_to_cpu_present = NULL, 361 .setup_portio_remap = NULL, 362 .check_phys_apicid_present = default_check_phys_apicid_present, 363 .enable_apic_mode = NULL, 364 .phys_pkg_id = uv_phys_pkg_id, 365 .mps_oem_check = NULL, 366 367 .get_apic_id = x2apic_get_apic_id, 368 .set_apic_id = set_apic_id, 369 .apic_id_mask = 0xFFFFFFFFu, 370 371 .cpu_mask_to_apicid_and = uv_cpu_mask_to_apicid_and, 372 373 .send_IPI_mask = uv_send_IPI_mask, 374 .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself, 375 .send_IPI_allbutself = uv_send_IPI_allbutself, 376 .send_IPI_all = uv_send_IPI_all, 377 .send_IPI_self = uv_send_IPI_self, 378 379 .wakeup_secondary_cpu = uv_wakeup_secondary, 380 .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW, 381 .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH, 382 .wait_for_init_deassert = NULL, 383 .smp_callin_clear_local_apic = NULL, 384 .inquire_remote_apic = NULL, 385 386 .read = native_apic_msr_read, 387 .write = native_apic_msr_write, 388 .eoi_write = native_apic_msr_eoi_write, 389 .icr_read = native_x2apic_icr_read, 390 .icr_write = native_x2apic_icr_write, 391 .wait_icr_idle = native_x2apic_wait_icr_idle, 392 .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle, 393 }; 394 395 static __cpuinit void set_x2apic_extra_bits(int pnode) 396 { 397 __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift); 398 } 399 400 /* 401 * Called on boot cpu. 402 */ 403 static __init int boot_pnode_to_blade(int pnode) 404 { 405 int blade; 406 407 for (blade = 0; blade < uv_num_possible_blades(); blade++) 408 if (pnode == uv_blade_info[blade].pnode) 409 return blade; 410 BUG(); 411 } 412 413 struct redir_addr { 414 unsigned long redirect; 415 unsigned long alias; 416 }; 417 418 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 419 420 static __initdata struct redir_addr redir_addrs[] = { 421 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR}, 422 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR}, 423 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR}, 424 }; 425 426 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size) 427 { 428 union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias; 429 union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect; 430 int i; 431 432 for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) { 433 alias.v = uv_read_local_mmr(redir_addrs[i].alias); 434 if (alias.s.enable && alias.s.base == 0) { 435 *size = (1UL << alias.s.m_alias); 436 redirect.v = uv_read_local_mmr(redir_addrs[i].redirect); 437 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT; 438 return; 439 } 440 } 441 *base = *size = 0; 442 } 443 444 enum map_type {map_wb, map_uc}; 445 446 static __init void map_high(char *id, unsigned long base, int pshift, 447 int bshift, int max_pnode, enum map_type map_type) 448 { 449 unsigned long bytes, paddr; 450 451 paddr = base << pshift; 452 bytes = (1UL << bshift) * (max_pnode + 1); 453 printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, 454 paddr + bytes); 455 if (map_type == map_uc) 456 init_extra_mapping_uc(paddr, bytes); 457 else 458 init_extra_mapping_wb(paddr, bytes); 459 460 } 461 static __init void map_gru_high(int max_pnode) 462 { 463 union uvh_rh_gam_gru_overlay_config_mmr_u gru; 464 int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT; 465 466 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR); 467 if (gru.s.enable) { 468 map_high("GRU", gru.s.base, shift, shift, max_pnode, map_wb); 469 gru_start_paddr = ((u64)gru.s.base << shift); 470 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1); 471 472 } 473 } 474 475 static __init void map_mmr_high(int max_pnode) 476 { 477 union uvh_rh_gam_mmr_overlay_config_mmr_u mmr; 478 int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT; 479 480 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR); 481 if (mmr.s.enable) 482 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc); 483 } 484 485 static __init void map_mmioh_high(int max_pnode) 486 { 487 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh; 488 int shift; 489 490 mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR); 491 if (is_uv1_hub() && mmioh.s1.enable) { 492 shift = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT; 493 map_high("MMIOH", mmioh.s1.base, shift, mmioh.s1.m_io, 494 max_pnode, map_uc); 495 } 496 if (is_uv2_hub() && mmioh.s2.enable) { 497 shift = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT; 498 map_high("MMIOH", mmioh.s2.base, shift, mmioh.s2.m_io, 499 max_pnode, map_uc); 500 } 501 } 502 503 static __init void map_low_mmrs(void) 504 { 505 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE); 506 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE); 507 } 508 509 static __init void uv_rtc_init(void) 510 { 511 long status; 512 u64 ticks_per_sec; 513 514 status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, 515 &ticks_per_sec); 516 if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) { 517 printk(KERN_WARNING 518 "unable to determine platform RTC clock frequency, " 519 "guessing.\n"); 520 /* BIOS gives wrong value for clock freq. so guess */ 521 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL; 522 } else 523 sn_rtc_cycles_per_second = ticks_per_sec; 524 } 525 526 /* 527 * percpu heartbeat timer 528 */ 529 static void uv_heartbeat(unsigned long ignored) 530 { 531 struct timer_list *timer = &uv_hub_info->scir.timer; 532 unsigned char bits = uv_hub_info->scir.state; 533 534 /* flip heartbeat bit */ 535 bits ^= SCIR_CPU_HEARTBEAT; 536 537 /* is this cpu idle? */ 538 if (idle_cpu(raw_smp_processor_id())) 539 bits &= ~SCIR_CPU_ACTIVITY; 540 else 541 bits |= SCIR_CPU_ACTIVITY; 542 543 /* update system controller interface reg */ 544 uv_set_scir_bits(bits); 545 546 /* enable next timer period */ 547 mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL); 548 } 549 550 static void __cpuinit uv_heartbeat_enable(int cpu) 551 { 552 while (!uv_cpu_hub_info(cpu)->scir.enabled) { 553 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer; 554 555 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY); 556 setup_timer(timer, uv_heartbeat, cpu); 557 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL; 558 add_timer_on(timer, cpu); 559 uv_cpu_hub_info(cpu)->scir.enabled = 1; 560 561 /* also ensure that boot cpu is enabled */ 562 cpu = 0; 563 } 564 } 565 566 #ifdef CONFIG_HOTPLUG_CPU 567 static void __cpuinit uv_heartbeat_disable(int cpu) 568 { 569 if (uv_cpu_hub_info(cpu)->scir.enabled) { 570 uv_cpu_hub_info(cpu)->scir.enabled = 0; 571 del_timer(&uv_cpu_hub_info(cpu)->scir.timer); 572 } 573 uv_set_cpu_scir_bits(cpu, 0xff); 574 } 575 576 /* 577 * cpu hotplug notifier 578 */ 579 static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self, 580 unsigned long action, void *hcpu) 581 { 582 long cpu = (long)hcpu; 583 584 switch (action) { 585 case CPU_ONLINE: 586 uv_heartbeat_enable(cpu); 587 break; 588 case CPU_DOWN_PREPARE: 589 uv_heartbeat_disable(cpu); 590 break; 591 default: 592 break; 593 } 594 return NOTIFY_OK; 595 } 596 597 static __init void uv_scir_register_cpu_notifier(void) 598 { 599 hotcpu_notifier(uv_scir_cpu_notify, 0); 600 } 601 602 #else /* !CONFIG_HOTPLUG_CPU */ 603 604 static __init void uv_scir_register_cpu_notifier(void) 605 { 606 } 607 608 static __init int uv_init_heartbeat(void) 609 { 610 int cpu; 611 612 if (is_uv_system()) 613 for_each_online_cpu(cpu) 614 uv_heartbeat_enable(cpu); 615 return 0; 616 } 617 618 late_initcall(uv_init_heartbeat); 619 620 #endif /* !CONFIG_HOTPLUG_CPU */ 621 622 /* Direct Legacy VGA I/O traffic to designated IOH */ 623 int uv_set_vga_state(struct pci_dev *pdev, bool decode, 624 unsigned int command_bits, u32 flags) 625 { 626 int domain, bus, rc; 627 628 PR_DEVEL("devfn %x decode %d cmd %x flags %d\n", 629 pdev->devfn, decode, command_bits, flags); 630 631 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) 632 return 0; 633 634 if ((command_bits & PCI_COMMAND_IO) == 0) 635 return 0; 636 637 domain = pci_domain_nr(pdev->bus); 638 bus = pdev->bus->number; 639 640 rc = uv_bios_set_legacy_vga_target(decode, domain, bus); 641 PR_DEVEL("vga decode %d %x:%x, rc: %d\n", decode, domain, bus, rc); 642 643 return rc; 644 } 645 646 /* 647 * Called on each cpu to initialize the per_cpu UV data area. 648 * FIXME: hotplug not supported yet 649 */ 650 void __cpuinit uv_cpu_init(void) 651 { 652 /* CPU 0 initilization will be done via uv_system_init. */ 653 if (!uv_blade_info) 654 return; 655 656 uv_blade_info[uv_numa_blade_id()].nr_online_cpus++; 657 658 if (get_uv_system_type() == UV_NON_UNIQUE_APIC) 659 set_x2apic_extra_bits(uv_hub_info->pnode); 660 } 661 662 /* 663 * When NMI is received, print a stack trace. 664 */ 665 int uv_handle_nmi(unsigned int reason, struct pt_regs *regs) 666 { 667 unsigned long real_uv_nmi; 668 int bid; 669 670 /* 671 * Each blade has an MMR that indicates when an NMI has been sent 672 * to cpus on the blade. If an NMI is detected, atomically 673 * clear the MMR and update a per-blade NMI count used to 674 * cause each cpu on the blade to notice a new NMI. 675 */ 676 bid = uv_numa_blade_id(); 677 real_uv_nmi = (uv_read_local_mmr(UVH_NMI_MMR) & UV_NMI_PENDING_MASK); 678 679 if (unlikely(real_uv_nmi)) { 680 spin_lock(&uv_blade_info[bid].nmi_lock); 681 real_uv_nmi = (uv_read_local_mmr(UVH_NMI_MMR) & UV_NMI_PENDING_MASK); 682 if (real_uv_nmi) { 683 uv_blade_info[bid].nmi_count++; 684 uv_write_local_mmr(UVH_NMI_MMR_CLEAR, UV_NMI_PENDING_MASK); 685 } 686 spin_unlock(&uv_blade_info[bid].nmi_lock); 687 } 688 689 if (likely(__get_cpu_var(cpu_last_nmi_count) == uv_blade_info[bid].nmi_count)) 690 return NMI_DONE; 691 692 __get_cpu_var(cpu_last_nmi_count) = uv_blade_info[bid].nmi_count; 693 694 /* 695 * Use a lock so only one cpu prints at a time. 696 * This prevents intermixed output. 697 */ 698 spin_lock(&uv_nmi_lock); 699 pr_info("UV NMI stack dump cpu %u:\n", smp_processor_id()); 700 dump_stack(); 701 spin_unlock(&uv_nmi_lock); 702 703 return NMI_HANDLED; 704 } 705 706 void uv_register_nmi_notifier(void) 707 { 708 if (register_nmi_handler(NMI_UNKNOWN, uv_handle_nmi, 0, "uv")) 709 printk(KERN_WARNING "UV NMI handler failed to register\n"); 710 } 711 712 void uv_nmi_init(void) 713 { 714 unsigned int value; 715 716 /* 717 * Unmask NMI on all cpus 718 */ 719 value = apic_read(APIC_LVT1) | APIC_DM_NMI; 720 value &= ~APIC_LVT_MASKED; 721 apic_write(APIC_LVT1, value); 722 } 723 724 void __init uv_system_init(void) 725 { 726 union uvh_rh_gam_config_mmr_u m_n_config; 727 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh; 728 union uvh_node_id_u node_id; 729 unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size; 730 int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val, n_io; 731 int gnode_extra, max_pnode = 0; 732 unsigned long mmr_base, present, paddr; 733 unsigned short pnode_mask, pnode_io_mask; 734 735 printk(KERN_INFO "UV: Found %s hub\n", is_uv1_hub() ? "UV1" : "UV2"); 736 map_low_mmrs(); 737 738 m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR ); 739 m_val = m_n_config.s.m_skt; 740 n_val = m_n_config.s.n_skt; 741 mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR); 742 n_io = is_uv1_hub() ? mmioh.s1.n_io : mmioh.s2.n_io; 743 mmr_base = 744 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) & 745 ~UV_MMR_ENABLE; 746 pnode_mask = (1 << n_val) - 1; 747 pnode_io_mask = (1 << n_io) - 1; 748 749 node_id.v = uv_read_local_mmr(UVH_NODE_ID); 750 gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1; 751 gnode_upper = ((unsigned long)gnode_extra << m_val); 752 printk(KERN_INFO "UV: N %d, M %d, N_IO: %d, gnode_upper 0x%lx, gnode_extra 0x%x, pnode_mask 0x%x, pnode_io_mask 0x%x\n", 753 n_val, m_val, n_io, gnode_upper, gnode_extra, pnode_mask, pnode_io_mask); 754 755 printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base); 756 757 for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) 758 uv_possible_blades += 759 hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8)); 760 761 /* uv_num_possible_blades() is really the hub count */ 762 printk(KERN_INFO "UV: Found %d blades, %d hubs\n", 763 is_uv1_hub() ? uv_num_possible_blades() : 764 (uv_num_possible_blades() + 1) / 2, 765 uv_num_possible_blades()); 766 767 bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades(); 768 uv_blade_info = kzalloc(bytes, GFP_KERNEL); 769 BUG_ON(!uv_blade_info); 770 771 for (blade = 0; blade < uv_num_possible_blades(); blade++) 772 uv_blade_info[blade].memory_nid = -1; 773 774 get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size); 775 776 bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes(); 777 uv_node_to_blade = kmalloc(bytes, GFP_KERNEL); 778 BUG_ON(!uv_node_to_blade); 779 memset(uv_node_to_blade, 255, bytes); 780 781 bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus(); 782 uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL); 783 BUG_ON(!uv_cpu_to_blade); 784 memset(uv_cpu_to_blade, 255, bytes); 785 786 blade = 0; 787 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) { 788 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8); 789 for (j = 0; j < 64; j++) { 790 if (!test_bit(j, &present)) 791 continue; 792 pnode = (i * 64 + j) & pnode_mask; 793 uv_blade_info[blade].pnode = pnode; 794 uv_blade_info[blade].nr_possible_cpus = 0; 795 uv_blade_info[blade].nr_online_cpus = 0; 796 spin_lock_init(&uv_blade_info[blade].nmi_lock); 797 max_pnode = max(pnode, max_pnode); 798 blade++; 799 } 800 } 801 802 uv_bios_init(); 803 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, 804 &sn_region_size, &system_serial_number); 805 uv_rtc_init(); 806 807 for_each_present_cpu(cpu) { 808 int apicid = per_cpu(x86_cpu_to_apicid, cpu); 809 810 nid = cpu_to_node(cpu); 811 /* 812 * apic_pnode_shift must be set before calling uv_apicid_to_pnode(); 813 */ 814 uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask; 815 uv_cpu_hub_info(cpu)->apic_pnode_shift = uvh_apicid.s.pnode_shift; 816 uv_cpu_hub_info(cpu)->hub_revision = uv_hub_info->hub_revision; 817 818 uv_cpu_hub_info(cpu)->m_shift = 64 - m_val; 819 uv_cpu_hub_info(cpu)->n_lshift = is_uv2_1_hub() ? 820 (m_val == 40 ? 40 : 39) : m_val; 821 822 pnode = uv_apicid_to_pnode(apicid); 823 blade = boot_pnode_to_blade(pnode); 824 lcpu = uv_blade_info[blade].nr_possible_cpus; 825 uv_blade_info[blade].nr_possible_cpus++; 826 827 /* Any node on the blade, else will contain -1. */ 828 uv_blade_info[blade].memory_nid = nid; 829 830 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base; 831 uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size; 832 uv_cpu_hub_info(cpu)->m_val = m_val; 833 uv_cpu_hub_info(cpu)->n_val = n_val; 834 uv_cpu_hub_info(cpu)->numa_blade_id = blade; 835 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu; 836 uv_cpu_hub_info(cpu)->pnode = pnode; 837 uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1; 838 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper; 839 uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra; 840 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base; 841 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id; 842 uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid); 843 uv_node_to_blade[nid] = blade; 844 uv_cpu_to_blade[cpu] = blade; 845 } 846 847 /* Add blade/pnode info for nodes without cpus */ 848 for_each_online_node(nid) { 849 if (uv_node_to_blade[nid] >= 0) 850 continue; 851 paddr = node_start_pfn(nid) << PAGE_SHIFT; 852 pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr)); 853 blade = boot_pnode_to_blade(pnode); 854 uv_node_to_blade[nid] = blade; 855 } 856 857 map_gru_high(max_pnode); 858 map_mmr_high(max_pnode); 859 map_mmioh_high(max_pnode & pnode_io_mask); 860 861 uv_cpu_init(); 862 uv_scir_register_cpu_notifier(); 863 uv_register_nmi_notifier(); 864 proc_mkdir("sgi_uv", NULL); 865 866 /* register Legacy VGA I/O redirection handler */ 867 pci_register_set_vga_state(uv_set_vga_state); 868 869 /* 870 * For a kdump kernel the reset must be BOOT_ACPI, not BOOT_EFI, as 871 * EFI is not enabled in the kdump kernel. 872 */ 873 if (is_kdump_kernel()) 874 reboot_type = BOOT_ACPI; 875 } 876 877 apic_driver(apic_x2apic_uv_x); 878