1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * SGI UV APIC functions (note: not an Intel compatible APIC) 7 * 8 * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved. 9 */ 10 #include <linux/cpumask.h> 11 #include <linux/hardirq.h> 12 #include <linux/proc_fs.h> 13 #include <linux/threads.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/string.h> 17 #include <linux/ctype.h> 18 #include <linux/sched.h> 19 #include <linux/timer.h> 20 #include <linux/cpu.h> 21 #include <linux/init.h> 22 #include <linux/io.h> 23 24 #include <asm/uv/uv_mmrs.h> 25 #include <asm/uv/uv_hub.h> 26 #include <asm/current.h> 27 #include <asm/pgtable.h> 28 #include <asm/uv/bios.h> 29 #include <asm/uv/uv.h> 30 #include <asm/apic.h> 31 #include <asm/ipi.h> 32 #include <asm/smp.h> 33 34 DEFINE_PER_CPU(int, x2apic_extra_bits); 35 36 static enum uv_system_type uv_system_type; 37 38 static int early_get_nodeid(void) 39 { 40 union uvh_node_id_u node_id; 41 unsigned long *mmr; 42 43 mmr = early_ioremap(UV_LOCAL_MMR_BASE | UVH_NODE_ID, sizeof(*mmr)); 44 node_id.v = *mmr; 45 early_iounmap(mmr, sizeof(*mmr)); 46 return node_id.s.node_id; 47 } 48 49 static int uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id) 50 { 51 if (!strcmp(oem_id, "SGI")) { 52 if (!strcmp(oem_table_id, "UVL")) 53 uv_system_type = UV_LEGACY_APIC; 54 else if (!strcmp(oem_table_id, "UVX")) 55 uv_system_type = UV_X2APIC; 56 else if (!strcmp(oem_table_id, "UVH")) { 57 __get_cpu_var(x2apic_extra_bits) = 58 early_get_nodeid() << (UV_APIC_PNODE_SHIFT - 1); 59 uv_system_type = UV_NON_UNIQUE_APIC; 60 return 1; 61 } 62 } 63 return 0; 64 } 65 66 enum uv_system_type get_uv_system_type(void) 67 { 68 return uv_system_type; 69 } 70 71 int is_uv_system(void) 72 { 73 return uv_system_type != UV_NONE; 74 } 75 EXPORT_SYMBOL_GPL(is_uv_system); 76 77 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); 78 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info); 79 80 struct uv_blade_info *uv_blade_info; 81 EXPORT_SYMBOL_GPL(uv_blade_info); 82 83 short *uv_node_to_blade; 84 EXPORT_SYMBOL_GPL(uv_node_to_blade); 85 86 short *uv_cpu_to_blade; 87 EXPORT_SYMBOL_GPL(uv_cpu_to_blade); 88 89 short uv_possible_blades; 90 EXPORT_SYMBOL_GPL(uv_possible_blades); 91 92 unsigned long sn_rtc_cycles_per_second; 93 EXPORT_SYMBOL(sn_rtc_cycles_per_second); 94 95 /* Start with all IRQs pointing to boot CPU. IRQ balancing will shift them. */ 96 97 static const struct cpumask *uv_target_cpus(void) 98 { 99 return cpumask_of(0); 100 } 101 102 static void uv_vector_allocation_domain(int cpu, struct cpumask *retmask) 103 { 104 cpumask_clear(retmask); 105 cpumask_set_cpu(cpu, retmask); 106 } 107 108 static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip) 109 { 110 #ifdef CONFIG_SMP 111 unsigned long val; 112 int pnode; 113 114 pnode = uv_apicid_to_pnode(phys_apicid); 115 val = (1UL << UVH_IPI_INT_SEND_SHFT) | 116 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | 117 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | 118 APIC_DM_INIT; 119 uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 120 mdelay(10); 121 122 val = (1UL << UVH_IPI_INT_SEND_SHFT) | 123 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | 124 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | 125 APIC_DM_STARTUP; 126 uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 127 128 atomic_set(&init_deasserted, 1); 129 #endif 130 return 0; 131 } 132 133 static void uv_send_IPI_one(int cpu, int vector) 134 { 135 unsigned long apicid; 136 int pnode; 137 138 apicid = per_cpu(x86_cpu_to_apicid, cpu); 139 pnode = uv_apicid_to_pnode(apicid); 140 uv_hub_send_ipi(pnode, apicid, vector); 141 } 142 143 static void uv_send_IPI_mask(const struct cpumask *mask, int vector) 144 { 145 unsigned int cpu; 146 147 for_each_cpu(cpu, mask) 148 uv_send_IPI_one(cpu, vector); 149 } 150 151 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) 152 { 153 unsigned int this_cpu = smp_processor_id(); 154 unsigned int cpu; 155 156 for_each_cpu(cpu, mask) { 157 if (cpu != this_cpu) 158 uv_send_IPI_one(cpu, vector); 159 } 160 } 161 162 static void uv_send_IPI_allbutself(int vector) 163 { 164 unsigned int this_cpu = smp_processor_id(); 165 unsigned int cpu; 166 167 for_each_online_cpu(cpu) { 168 if (cpu != this_cpu) 169 uv_send_IPI_one(cpu, vector); 170 } 171 } 172 173 static void uv_send_IPI_all(int vector) 174 { 175 uv_send_IPI_mask(cpu_online_mask, vector); 176 } 177 178 static int uv_apic_id_registered(void) 179 { 180 return 1; 181 } 182 183 static void uv_init_apic_ldr(void) 184 { 185 } 186 187 static unsigned int uv_cpu_mask_to_apicid(const struct cpumask *cpumask) 188 { 189 /* 190 * We're using fixed IRQ delivery, can only return one phys APIC ID. 191 * May as well be the first. 192 */ 193 int cpu = cpumask_first(cpumask); 194 195 if ((unsigned)cpu < nr_cpu_ids) 196 return per_cpu(x86_cpu_to_apicid, cpu); 197 else 198 return BAD_APICID; 199 } 200 201 static unsigned int 202 uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 203 const struct cpumask *andmask) 204 { 205 int cpu; 206 207 /* 208 * We're using fixed IRQ delivery, can only return one phys APIC ID. 209 * May as well be the first. 210 */ 211 for_each_cpu_and(cpu, cpumask, andmask) { 212 if (cpumask_test_cpu(cpu, cpu_online_mask)) 213 break; 214 } 215 if (cpu < nr_cpu_ids) 216 return per_cpu(x86_cpu_to_apicid, cpu); 217 218 return BAD_APICID; 219 } 220 221 static unsigned int x2apic_get_apic_id(unsigned long x) 222 { 223 unsigned int id; 224 225 WARN_ON(preemptible() && num_online_cpus() > 1); 226 id = x | __get_cpu_var(x2apic_extra_bits); 227 228 return id; 229 } 230 231 static unsigned long set_apic_id(unsigned int id) 232 { 233 unsigned long x; 234 235 /* maskout x2apic_extra_bits ? */ 236 x = id; 237 return x; 238 } 239 240 static unsigned int uv_read_apic_id(void) 241 { 242 243 return x2apic_get_apic_id(apic_read(APIC_ID)); 244 } 245 246 static int uv_phys_pkg_id(int initial_apicid, int index_msb) 247 { 248 return uv_read_apic_id() >> index_msb; 249 } 250 251 static void uv_send_IPI_self(int vector) 252 { 253 apic_write(APIC_SELF_IPI, vector); 254 } 255 256 struct apic apic_x2apic_uv_x = { 257 258 .name = "UV large system", 259 .probe = NULL, 260 .acpi_madt_oem_check = uv_acpi_madt_oem_check, 261 .apic_id_registered = uv_apic_id_registered, 262 263 .irq_delivery_mode = dest_Fixed, 264 .irq_dest_mode = 1, /* logical */ 265 266 .target_cpus = uv_target_cpus, 267 .disable_esr = 0, 268 .dest_logical = APIC_DEST_LOGICAL, 269 .check_apicid_used = NULL, 270 .check_apicid_present = NULL, 271 272 .vector_allocation_domain = uv_vector_allocation_domain, 273 .init_apic_ldr = uv_init_apic_ldr, 274 275 .ioapic_phys_id_map = NULL, 276 .setup_apic_routing = NULL, 277 .multi_timer_check = NULL, 278 .apicid_to_node = NULL, 279 .cpu_to_logical_apicid = NULL, 280 .cpu_present_to_apicid = default_cpu_present_to_apicid, 281 .apicid_to_cpu_present = NULL, 282 .setup_portio_remap = NULL, 283 .check_phys_apicid_present = default_check_phys_apicid_present, 284 .enable_apic_mode = NULL, 285 .phys_pkg_id = uv_phys_pkg_id, 286 .mps_oem_check = NULL, 287 288 .get_apic_id = x2apic_get_apic_id, 289 .set_apic_id = set_apic_id, 290 .apic_id_mask = 0xFFFFFFFFu, 291 292 .cpu_mask_to_apicid = uv_cpu_mask_to_apicid, 293 .cpu_mask_to_apicid_and = uv_cpu_mask_to_apicid_and, 294 295 .send_IPI_mask = uv_send_IPI_mask, 296 .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself, 297 .send_IPI_allbutself = uv_send_IPI_allbutself, 298 .send_IPI_all = uv_send_IPI_all, 299 .send_IPI_self = uv_send_IPI_self, 300 301 .wakeup_secondary_cpu = uv_wakeup_secondary, 302 .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW, 303 .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH, 304 .wait_for_init_deassert = NULL, 305 .smp_callin_clear_local_apic = NULL, 306 .inquire_remote_apic = NULL, 307 308 .read = native_apic_msr_read, 309 .write = native_apic_msr_write, 310 .icr_read = native_x2apic_icr_read, 311 .icr_write = native_x2apic_icr_write, 312 .wait_icr_idle = native_x2apic_wait_icr_idle, 313 .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle, 314 }; 315 316 static __cpuinit void set_x2apic_extra_bits(int pnode) 317 { 318 __get_cpu_var(x2apic_extra_bits) = (pnode << 6); 319 } 320 321 /* 322 * Called on boot cpu. 323 */ 324 static __init int boot_pnode_to_blade(int pnode) 325 { 326 int blade; 327 328 for (blade = 0; blade < uv_num_possible_blades(); blade++) 329 if (pnode == uv_blade_info[blade].pnode) 330 return blade; 331 BUG(); 332 } 333 334 struct redir_addr { 335 unsigned long redirect; 336 unsigned long alias; 337 }; 338 339 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 340 341 static __initdata struct redir_addr redir_addrs[] = { 342 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG}, 343 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG}, 344 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG}, 345 }; 346 347 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size) 348 { 349 union uvh_si_alias0_overlay_config_u alias; 350 union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect; 351 int i; 352 353 for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) { 354 alias.v = uv_read_local_mmr(redir_addrs[i].alias); 355 if (alias.s.base == 0) { 356 *size = (1UL << alias.s.m_alias); 357 redirect.v = uv_read_local_mmr(redir_addrs[i].redirect); 358 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT; 359 return; 360 } 361 } 362 BUG(); 363 } 364 365 static __init void map_low_mmrs(void) 366 { 367 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE); 368 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE); 369 } 370 371 enum map_type {map_wb, map_uc}; 372 373 static __init void map_high(char *id, unsigned long base, int shift, 374 int max_pnode, enum map_type map_type) 375 { 376 unsigned long bytes, paddr; 377 378 paddr = base << shift; 379 bytes = (1UL << shift) * (max_pnode + 1); 380 printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, 381 paddr + bytes); 382 if (map_type == map_uc) 383 init_extra_mapping_uc(paddr, bytes); 384 else 385 init_extra_mapping_wb(paddr, bytes); 386 387 } 388 static __init void map_gru_high(int max_pnode) 389 { 390 union uvh_rh_gam_gru_overlay_config_mmr_u gru; 391 int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT; 392 393 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR); 394 if (gru.s.enable) 395 map_high("GRU", gru.s.base, shift, max_pnode, map_wb); 396 } 397 398 static __init void map_config_high(int max_pnode) 399 { 400 union uvh_rh_gam_cfg_overlay_config_mmr_u cfg; 401 int shift = UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR_BASE_SHFT; 402 403 cfg.v = uv_read_local_mmr(UVH_RH_GAM_CFG_OVERLAY_CONFIG_MMR); 404 if (cfg.s.enable) 405 map_high("CONFIG", cfg.s.base, shift, max_pnode, map_uc); 406 } 407 408 static __init void map_mmr_high(int max_pnode) 409 { 410 union uvh_rh_gam_mmr_overlay_config_mmr_u mmr; 411 int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT; 412 413 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR); 414 if (mmr.s.enable) 415 map_high("MMR", mmr.s.base, shift, max_pnode, map_uc); 416 } 417 418 static __init void map_mmioh_high(int max_pnode) 419 { 420 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh; 421 int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT; 422 423 mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR); 424 if (mmioh.s.enable) 425 map_high("MMIOH", mmioh.s.base, shift, max_pnode, map_uc); 426 } 427 428 static __init void uv_rtc_init(void) 429 { 430 long status; 431 u64 ticks_per_sec; 432 433 status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, 434 &ticks_per_sec); 435 if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) { 436 printk(KERN_WARNING 437 "unable to determine platform RTC clock frequency, " 438 "guessing.\n"); 439 /* BIOS gives wrong value for clock freq. so guess */ 440 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL; 441 } else 442 sn_rtc_cycles_per_second = ticks_per_sec; 443 } 444 445 /* 446 * percpu heartbeat timer 447 */ 448 static void uv_heartbeat(unsigned long ignored) 449 { 450 struct timer_list *timer = &uv_hub_info->scir.timer; 451 unsigned char bits = uv_hub_info->scir.state; 452 453 /* flip heartbeat bit */ 454 bits ^= SCIR_CPU_HEARTBEAT; 455 456 /* is this cpu idle? */ 457 if (idle_cpu(raw_smp_processor_id())) 458 bits &= ~SCIR_CPU_ACTIVITY; 459 else 460 bits |= SCIR_CPU_ACTIVITY; 461 462 /* update system controller interface reg */ 463 uv_set_scir_bits(bits); 464 465 /* enable next timer period */ 466 mod_timer(timer, jiffies + SCIR_CPU_HB_INTERVAL); 467 } 468 469 static void __cpuinit uv_heartbeat_enable(int cpu) 470 { 471 if (!uv_cpu_hub_info(cpu)->scir.enabled) { 472 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer; 473 474 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY); 475 setup_timer(timer, uv_heartbeat, cpu); 476 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL; 477 add_timer_on(timer, cpu); 478 uv_cpu_hub_info(cpu)->scir.enabled = 1; 479 } 480 481 /* check boot cpu */ 482 if (!uv_cpu_hub_info(0)->scir.enabled) 483 uv_heartbeat_enable(0); 484 } 485 486 #ifdef CONFIG_HOTPLUG_CPU 487 static void __cpuinit uv_heartbeat_disable(int cpu) 488 { 489 if (uv_cpu_hub_info(cpu)->scir.enabled) { 490 uv_cpu_hub_info(cpu)->scir.enabled = 0; 491 del_timer(&uv_cpu_hub_info(cpu)->scir.timer); 492 } 493 uv_set_cpu_scir_bits(cpu, 0xff); 494 } 495 496 /* 497 * cpu hotplug notifier 498 */ 499 static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self, 500 unsigned long action, void *hcpu) 501 { 502 long cpu = (long)hcpu; 503 504 switch (action) { 505 case CPU_ONLINE: 506 uv_heartbeat_enable(cpu); 507 break; 508 case CPU_DOWN_PREPARE: 509 uv_heartbeat_disable(cpu); 510 break; 511 default: 512 break; 513 } 514 return NOTIFY_OK; 515 } 516 517 static __init void uv_scir_register_cpu_notifier(void) 518 { 519 hotcpu_notifier(uv_scir_cpu_notify, 0); 520 } 521 522 #else /* !CONFIG_HOTPLUG_CPU */ 523 524 static __init void uv_scir_register_cpu_notifier(void) 525 { 526 } 527 528 static __init int uv_init_heartbeat(void) 529 { 530 int cpu; 531 532 if (is_uv_system()) 533 for_each_online_cpu(cpu) 534 uv_heartbeat_enable(cpu); 535 return 0; 536 } 537 538 late_initcall(uv_init_heartbeat); 539 540 #endif /* !CONFIG_HOTPLUG_CPU */ 541 542 /* 543 * Called on each cpu to initialize the per_cpu UV data area. 544 * FIXME: hotplug not supported yet 545 */ 546 void __cpuinit uv_cpu_init(void) 547 { 548 /* CPU 0 initilization will be done via uv_system_init. */ 549 if (!uv_blade_info) 550 return; 551 552 uv_blade_info[uv_numa_blade_id()].nr_online_cpus++; 553 554 if (get_uv_system_type() == UV_NON_UNIQUE_APIC) 555 set_x2apic_extra_bits(uv_hub_info->pnode); 556 } 557 558 559 void __init uv_system_init(void) 560 { 561 union uvh_si_addr_map_config_u m_n_config; 562 union uvh_node_id_u node_id; 563 unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size; 564 int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val; 565 int max_pnode = 0; 566 unsigned long mmr_base, present, paddr; 567 unsigned short pnode_mask; 568 569 map_low_mmrs(); 570 571 m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG); 572 m_val = m_n_config.s.m_skt; 573 n_val = m_n_config.s.n_skt; 574 mmr_base = 575 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) & 576 ~UV_MMR_ENABLE; 577 printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base); 578 579 for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) 580 uv_possible_blades += 581 hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8)); 582 printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades()); 583 584 bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades(); 585 uv_blade_info = kmalloc(bytes, GFP_KERNEL); 586 587 get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size); 588 589 bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes(); 590 uv_node_to_blade = kmalloc(bytes, GFP_KERNEL); 591 memset(uv_node_to_blade, 255, bytes); 592 593 bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus(); 594 uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL); 595 memset(uv_cpu_to_blade, 255, bytes); 596 597 blade = 0; 598 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) { 599 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8); 600 for (j = 0; j < 64; j++) { 601 if (!test_bit(j, &present)) 602 continue; 603 uv_blade_info[blade].pnode = (i * 64 + j); 604 uv_blade_info[blade].nr_possible_cpus = 0; 605 uv_blade_info[blade].nr_online_cpus = 0; 606 blade++; 607 } 608 } 609 610 pnode_mask = (1 << n_val) - 1; 611 node_id.v = uv_read_local_mmr(UVH_NODE_ID); 612 gnode_upper = (((unsigned long)node_id.s.node_id) & 613 ~((1 << n_val) - 1)) << m_val; 614 615 uv_bios_init(); 616 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, 617 &sn_coherency_id, &sn_region_size); 618 uv_rtc_init(); 619 620 for_each_present_cpu(cpu) { 621 nid = cpu_to_node(cpu); 622 pnode = uv_apicid_to_pnode(per_cpu(x86_cpu_to_apicid, cpu)); 623 blade = boot_pnode_to_blade(pnode); 624 lcpu = uv_blade_info[blade].nr_possible_cpus; 625 uv_blade_info[blade].nr_possible_cpus++; 626 627 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base; 628 uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size; 629 uv_cpu_hub_info(cpu)->m_val = m_val; 630 uv_cpu_hub_info(cpu)->n_val = m_val; 631 uv_cpu_hub_info(cpu)->numa_blade_id = blade; 632 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu; 633 uv_cpu_hub_info(cpu)->pnode = pnode; 634 uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask; 635 uv_cpu_hub_info(cpu)->gpa_mask = (1 << (m_val + n_val)) - 1; 636 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper; 637 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base; 638 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id; 639 uv_cpu_hub_info(cpu)->scir.offset = SCIR_LOCAL_MMR_BASE + lcpu; 640 uv_node_to_blade[nid] = blade; 641 uv_cpu_to_blade[cpu] = blade; 642 max_pnode = max(pnode, max_pnode); 643 644 printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, " 645 "lcpu %d, blade %d\n", 646 cpu, per_cpu(x86_cpu_to_apicid, cpu), pnode, nid, 647 lcpu, blade); 648 } 649 650 /* Add blade/pnode info for nodes without cpus */ 651 for_each_online_node(nid) { 652 if (uv_node_to_blade[nid] >= 0) 653 continue; 654 paddr = node_start_pfn(nid) << PAGE_SHIFT; 655 paddr = uv_soc_phys_ram_to_gpa(paddr); 656 pnode = (paddr >> m_val) & pnode_mask; 657 blade = boot_pnode_to_blade(pnode); 658 uv_node_to_blade[nid] = blade; 659 } 660 661 map_gru_high(max_pnode); 662 map_mmr_high(max_pnode); 663 map_config_high(max_pnode); 664 map_mmioh_high(max_pnode); 665 666 uv_cpu_init(); 667 uv_scir_register_cpu_notifier(); 668 proc_mkdir("sgi_uv", NULL); 669 } 670