1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * SGI UV APIC functions (note: not an Intel compatible APIC) 7 * 8 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved. 9 */ 10 #include <linux/cpumask.h> 11 #include <linux/hardirq.h> 12 #include <linux/proc_fs.h> 13 #include <linux/threads.h> 14 #include <linux/kernel.h> 15 #include <linux/export.h> 16 #include <linux/string.h> 17 #include <linux/ctype.h> 18 #include <linux/sched.h> 19 #include <linux/timer.h> 20 #include <linux/slab.h> 21 #include <linux/cpu.h> 22 #include <linux/init.h> 23 #include <linux/io.h> 24 #include <linux/pci.h> 25 #include <linux/kdebug.h> 26 #include <linux/delay.h> 27 #include <linux/crash_dump.h> 28 #include <linux/reboot.h> 29 30 #include <asm/uv/uv_mmrs.h> 31 #include <asm/uv/uv_hub.h> 32 #include <asm/current.h> 33 #include <asm/pgtable.h> 34 #include <asm/uv/bios.h> 35 #include <asm/uv/uv.h> 36 #include <asm/apic.h> 37 #include <asm/ipi.h> 38 #include <asm/smp.h> 39 #include <asm/x86_init.h> 40 #include <asm/nmi.h> 41 42 DEFINE_PER_CPU(int, x2apic_extra_bits); 43 44 static enum uv_system_type uv_system_type; 45 static bool uv_hubless_system; 46 static u64 gru_start_paddr, gru_end_paddr; 47 static u64 gru_dist_base, gru_first_node_paddr = -1LL, gru_last_node_paddr; 48 static u64 gru_dist_lmask, gru_dist_umask; 49 static union uvh_apicid uvh_apicid; 50 51 /* Information derived from CPUID: */ 52 static struct { 53 unsigned int apicid_shift; 54 unsigned int apicid_mask; 55 unsigned int socketid_shift; /* aka pnode_shift for UV1/2/3 */ 56 unsigned int pnode_mask; 57 unsigned int gpa_shift; 58 unsigned int gnode_shift; 59 } uv_cpuid; 60 61 int uv_min_hub_revision_id; 62 EXPORT_SYMBOL_GPL(uv_min_hub_revision_id); 63 64 unsigned int uv_apicid_hibits; 65 EXPORT_SYMBOL_GPL(uv_apicid_hibits); 66 67 static struct apic apic_x2apic_uv_x; 68 static struct uv_hub_info_s uv_hub_info_node0; 69 70 /* Set this to use hardware error handler instead of kernel panic: */ 71 static int disable_uv_undefined_panic = 1; 72 73 unsigned long uv_undefined(char *str) 74 { 75 if (likely(!disable_uv_undefined_panic)) 76 panic("UV: error: undefined MMR: %s\n", str); 77 else 78 pr_crit("UV: error: undefined MMR: %s\n", str); 79 80 /* Cause a machine fault: */ 81 return ~0ul; 82 } 83 EXPORT_SYMBOL(uv_undefined); 84 85 static unsigned long __init uv_early_read_mmr(unsigned long addr) 86 { 87 unsigned long val, *mmr; 88 89 mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr)); 90 val = *mmr; 91 early_iounmap(mmr, sizeof(*mmr)); 92 93 return val; 94 } 95 96 static inline bool is_GRU_range(u64 start, u64 end) 97 { 98 if (gru_dist_base) { 99 u64 su = start & gru_dist_umask; /* Upper (incl pnode) bits */ 100 u64 sl = start & gru_dist_lmask; /* Base offset bits */ 101 u64 eu = end & gru_dist_umask; 102 u64 el = end & gru_dist_lmask; 103 104 /* Must reside completely within a single GRU range: */ 105 return (sl == gru_dist_base && el == gru_dist_base && 106 su >= gru_first_node_paddr && 107 su <= gru_last_node_paddr && 108 eu == su); 109 } else { 110 return start >= gru_start_paddr && end <= gru_end_paddr; 111 } 112 } 113 114 static bool uv_is_untracked_pat_range(u64 start, u64 end) 115 { 116 return is_ISA_range(start, end) || is_GRU_range(start, end); 117 } 118 119 static int __init early_get_pnodeid(void) 120 { 121 union uvh_node_id_u node_id; 122 union uvh_rh_gam_config_mmr_u m_n_config; 123 int pnode; 124 125 /* Currently, all blades have same revision number */ 126 node_id.v = uv_early_read_mmr(UVH_NODE_ID); 127 m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR); 128 uv_min_hub_revision_id = node_id.s.revision; 129 130 switch (node_id.s.part_number) { 131 case UV2_HUB_PART_NUMBER: 132 case UV2_HUB_PART_NUMBER_X: 133 uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1; 134 break; 135 case UV3_HUB_PART_NUMBER: 136 case UV3_HUB_PART_NUMBER_X: 137 uv_min_hub_revision_id += UV3_HUB_REVISION_BASE; 138 break; 139 case UV4_HUB_PART_NUMBER: 140 uv_min_hub_revision_id += UV4_HUB_REVISION_BASE - 1; 141 uv_cpuid.gnode_shift = 2; /* min partition is 4 sockets */ 142 break; 143 } 144 145 uv_hub_info->hub_revision = uv_min_hub_revision_id; 146 uv_cpuid.pnode_mask = (1 << m_n_config.s.n_skt) - 1; 147 pnode = (node_id.s.node_id >> 1) & uv_cpuid.pnode_mask; 148 uv_cpuid.gpa_shift = 46; /* Default unless changed */ 149 150 pr_info("UV: rev:%d part#:%x nodeid:%04x n_skt:%d pnmsk:%x pn:%x\n", 151 node_id.s.revision, node_id.s.part_number, node_id.s.node_id, 152 m_n_config.s.n_skt, uv_cpuid.pnode_mask, pnode); 153 return pnode; 154 } 155 156 /* [Copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */ 157 158 #define SMT_LEVEL 0 /* Leaf 0xb SMT level */ 159 #define INVALID_TYPE 0 /* Leaf 0xb sub-leaf types */ 160 #define SMT_TYPE 1 161 #define CORE_TYPE 2 162 #define LEAFB_SUBTYPE(ecx) (((ecx) >> 8) & 0xff) 163 #define BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f) 164 165 static void set_x2apic_bits(void) 166 { 167 unsigned int eax, ebx, ecx, edx, sub_index; 168 unsigned int sid_shift; 169 170 cpuid(0, &eax, &ebx, &ecx, &edx); 171 if (eax < 0xb) { 172 pr_info("UV: CPU does not have CPUID.11\n"); 173 return; 174 } 175 176 cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx); 177 if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) { 178 pr_info("UV: CPUID.11 not implemented\n"); 179 return; 180 } 181 182 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax); 183 sub_index = 1; 184 do { 185 cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx); 186 if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) { 187 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax); 188 break; 189 } 190 sub_index++; 191 } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE); 192 193 uv_cpuid.apicid_shift = 0; 194 uv_cpuid.apicid_mask = (~(-1 << sid_shift)); 195 uv_cpuid.socketid_shift = sid_shift; 196 } 197 198 static void __init early_get_apic_socketid_shift(void) 199 { 200 if (is_uv2_hub() || is_uv3_hub()) 201 uvh_apicid.v = uv_early_read_mmr(UVH_APICID); 202 203 set_x2apic_bits(); 204 205 pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n", uv_cpuid.apicid_shift, uv_cpuid.apicid_mask); 206 pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n", uv_cpuid.socketid_shift, uv_cpuid.pnode_mask); 207 } 208 209 /* 210 * Add an extra bit as dictated by bios to the destination apicid of 211 * interrupts potentially passing through the UV HUB. This prevents 212 * a deadlock between interrupts and IO port operations. 213 */ 214 static void __init uv_set_apicid_hibit(void) 215 { 216 union uv1h_lb_target_physical_apic_id_mask_u apicid_mask; 217 218 if (is_uv1_hub()) { 219 apicid_mask.v = uv_early_read_mmr(UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK); 220 uv_apicid_hibits = apicid_mask.s1.bit_enables & UV_APICID_HIBIT_MASK; 221 } 222 } 223 224 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id) 225 { 226 int pnodeid; 227 int uv_apic; 228 229 if (strncmp(oem_id, "SGI", 3) != 0) { 230 if (strncmp(oem_id, "NSGI", 4) == 0) { 231 uv_hubless_system = true; 232 pr_info("UV: OEM IDs %s/%s, HUBLESS\n", 233 oem_id, oem_table_id); 234 } 235 return 0; 236 } 237 238 if (numa_off) { 239 pr_err("UV: NUMA is off, disabling UV support\n"); 240 return 0; 241 } 242 243 /* Set up early hub type field in uv_hub_info for Node 0 */ 244 uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0; 245 246 /* 247 * Determine UV arch type. 248 * SGI: UV100/1000 249 * SGI2: UV2000/3000 250 * SGI3: UV300 (truncated to 4 chars because of different varieties) 251 * SGI4: UV400 (truncated to 4 chars because of different varieties) 252 */ 253 uv_hub_info->hub_revision = 254 !strncmp(oem_id, "SGI4", 4) ? UV4_HUB_REVISION_BASE : 255 !strncmp(oem_id, "SGI3", 4) ? UV3_HUB_REVISION_BASE : 256 !strcmp(oem_id, "SGI2") ? UV2_HUB_REVISION_BASE : 257 !strcmp(oem_id, "SGI") ? UV1_HUB_REVISION_BASE : 0; 258 259 if (uv_hub_info->hub_revision == 0) 260 goto badbios; 261 262 pnodeid = early_get_pnodeid(); 263 early_get_apic_socketid_shift(); 264 265 x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range; 266 x86_platform.nmi_init = uv_nmi_init; 267 268 if (!strcmp(oem_table_id, "UVX")) { 269 /* This is the most common hardware variant: */ 270 uv_system_type = UV_X2APIC; 271 uv_apic = 0; 272 273 } else if (!strcmp(oem_table_id, "UVH")) { 274 /* Only UV1 systems: */ 275 uv_system_type = UV_NON_UNIQUE_APIC; 276 __this_cpu_write(x2apic_extra_bits, pnodeid << uvh_apicid.s.pnode_shift); 277 uv_set_apicid_hibit(); 278 uv_apic = 1; 279 280 } else if (!strcmp(oem_table_id, "UVL")) { 281 /* Only used for very small systems: */ 282 uv_system_type = UV_LEGACY_APIC; 283 uv_apic = 0; 284 285 } else { 286 goto badbios; 287 } 288 289 pr_info("UV: OEM IDs %s/%s, System/HUB Types %d/%d, uv_apic %d\n", oem_id, oem_table_id, uv_system_type, uv_min_hub_revision_id, uv_apic); 290 291 return uv_apic; 292 293 badbios: 294 pr_err("UV: OEM_ID:%s OEM_TABLE_ID:%s\n", oem_id, oem_table_id); 295 pr_err("Current BIOS not supported, update kernel and/or BIOS\n"); 296 BUG(); 297 } 298 299 enum uv_system_type get_uv_system_type(void) 300 { 301 return uv_system_type; 302 } 303 304 int is_uv_system(void) 305 { 306 return uv_system_type != UV_NONE; 307 } 308 EXPORT_SYMBOL_GPL(is_uv_system); 309 310 int is_uv_hubless(void) 311 { 312 return uv_hubless_system; 313 } 314 EXPORT_SYMBOL_GPL(is_uv_hubless); 315 316 void **__uv_hub_info_list; 317 EXPORT_SYMBOL_GPL(__uv_hub_info_list); 318 319 DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info); 320 EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info); 321 322 short uv_possible_blades; 323 EXPORT_SYMBOL_GPL(uv_possible_blades); 324 325 unsigned long sn_rtc_cycles_per_second; 326 EXPORT_SYMBOL(sn_rtc_cycles_per_second); 327 328 /* The following values are used for the per node hub info struct */ 329 static __initdata unsigned short *_node_to_pnode; 330 static __initdata unsigned short _min_socket, _max_socket; 331 static __initdata unsigned short _min_pnode, _max_pnode, _gr_table_len; 332 static __initdata struct uv_gam_range_entry *uv_gre_table; 333 static __initdata struct uv_gam_parameters *uv_gp_table; 334 static __initdata unsigned short *_socket_to_node; 335 static __initdata unsigned short *_socket_to_pnode; 336 static __initdata unsigned short *_pnode_to_socket; 337 338 static __initdata struct uv_gam_range_s *_gr_table; 339 340 #define SOCK_EMPTY ((unsigned short)~0) 341 342 extern int uv_hub_info_version(void) 343 { 344 return UV_HUB_INFO_VERSION; 345 } 346 EXPORT_SYMBOL(uv_hub_info_version); 347 348 /* Build GAM range lookup table: */ 349 static __init void build_uv_gr_table(void) 350 { 351 struct uv_gam_range_entry *gre = uv_gre_table; 352 struct uv_gam_range_s *grt; 353 unsigned long last_limit = 0, ram_limit = 0; 354 int bytes, i, sid, lsid = -1, indx = 0, lindx = -1; 355 356 if (!gre) 357 return; 358 359 bytes = _gr_table_len * sizeof(struct uv_gam_range_s); 360 grt = kzalloc(bytes, GFP_KERNEL); 361 BUG_ON(!grt); 362 _gr_table = grt; 363 364 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) { 365 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) { 366 if (!ram_limit) { 367 /* Mark hole between RAM/non-RAM: */ 368 ram_limit = last_limit; 369 last_limit = gre->limit; 370 lsid++; 371 continue; 372 } 373 last_limit = gre->limit; 374 pr_info("UV: extra hole in GAM RE table @%d\n", (int)(gre - uv_gre_table)); 375 continue; 376 } 377 if (_max_socket < gre->sockid) { 378 pr_err("UV: GAM table sockid(%d) too large(>%d) @%d\n", gre->sockid, _max_socket, (int)(gre - uv_gre_table)); 379 continue; 380 } 381 sid = gre->sockid - _min_socket; 382 if (lsid < sid) { 383 /* New range: */ 384 grt = &_gr_table[indx]; 385 grt->base = lindx; 386 grt->nasid = gre->nasid; 387 grt->limit = last_limit = gre->limit; 388 lsid = sid; 389 lindx = indx++; 390 continue; 391 } 392 /* Update range: */ 393 if (lsid == sid && !ram_limit) { 394 /* .. if contiguous: */ 395 if (grt->limit == last_limit) { 396 grt->limit = last_limit = gre->limit; 397 continue; 398 } 399 } 400 /* Non-contiguous RAM range: */ 401 if (!ram_limit) { 402 grt++; 403 grt->base = lindx; 404 grt->nasid = gre->nasid; 405 grt->limit = last_limit = gre->limit; 406 continue; 407 } 408 /* Non-contiguous/non-RAM: */ 409 grt++; 410 /* base is this entry */ 411 grt->base = grt - _gr_table; 412 grt->nasid = gre->nasid; 413 grt->limit = last_limit = gre->limit; 414 lsid++; 415 } 416 417 /* Shorten table if possible */ 418 grt++; 419 i = grt - _gr_table; 420 if (i < _gr_table_len) { 421 void *ret; 422 423 bytes = i * sizeof(struct uv_gam_range_s); 424 ret = krealloc(_gr_table, bytes, GFP_KERNEL); 425 if (ret) { 426 _gr_table = ret; 427 _gr_table_len = i; 428 } 429 } 430 431 /* Display resultant GAM range table: */ 432 for (i = 0, grt = _gr_table; i < _gr_table_len; i++, grt++) { 433 unsigned long start, end; 434 int gb = grt->base; 435 436 start = gb < 0 ? 0 : (unsigned long)_gr_table[gb].limit << UV_GAM_RANGE_SHFT; 437 end = (unsigned long)grt->limit << UV_GAM_RANGE_SHFT; 438 439 pr_info("UV: GAM Range %2d %04x 0x%013lx-0x%013lx (%d)\n", i, grt->nasid, start, end, gb); 440 } 441 } 442 443 static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip) 444 { 445 unsigned long val; 446 int pnode; 447 448 pnode = uv_apicid_to_pnode(phys_apicid); 449 phys_apicid |= uv_apicid_hibits; 450 451 val = (1UL << UVH_IPI_INT_SEND_SHFT) | 452 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | 453 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | 454 APIC_DM_INIT; 455 456 uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 457 458 val = (1UL << UVH_IPI_INT_SEND_SHFT) | 459 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | 460 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | 461 APIC_DM_STARTUP; 462 463 uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 464 465 return 0; 466 } 467 468 static void uv_send_IPI_one(int cpu, int vector) 469 { 470 unsigned long apicid; 471 int pnode; 472 473 apicid = per_cpu(x86_cpu_to_apicid, cpu); 474 pnode = uv_apicid_to_pnode(apicid); 475 uv_hub_send_ipi(pnode, apicid, vector); 476 } 477 478 static void uv_send_IPI_mask(const struct cpumask *mask, int vector) 479 { 480 unsigned int cpu; 481 482 for_each_cpu(cpu, mask) 483 uv_send_IPI_one(cpu, vector); 484 } 485 486 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) 487 { 488 unsigned int this_cpu = smp_processor_id(); 489 unsigned int cpu; 490 491 for_each_cpu(cpu, mask) { 492 if (cpu != this_cpu) 493 uv_send_IPI_one(cpu, vector); 494 } 495 } 496 497 static void uv_send_IPI_allbutself(int vector) 498 { 499 unsigned int this_cpu = smp_processor_id(); 500 unsigned int cpu; 501 502 for_each_online_cpu(cpu) { 503 if (cpu != this_cpu) 504 uv_send_IPI_one(cpu, vector); 505 } 506 } 507 508 static void uv_send_IPI_all(int vector) 509 { 510 uv_send_IPI_mask(cpu_online_mask, vector); 511 } 512 513 static int uv_apic_id_valid(int apicid) 514 { 515 return 1; 516 } 517 518 static int uv_apic_id_registered(void) 519 { 520 return 1; 521 } 522 523 static void uv_init_apic_ldr(void) 524 { 525 } 526 527 static int 528 uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 529 const struct cpumask *andmask, 530 unsigned int *apicid) 531 { 532 int unsigned cpu; 533 534 /* 535 * We're using fixed IRQ delivery, can only return one phys APIC ID. 536 * May as well be the first. 537 */ 538 for_each_cpu_and(cpu, cpumask, andmask) { 539 if (cpumask_test_cpu(cpu, cpu_online_mask)) 540 break; 541 } 542 543 if (likely(cpu < nr_cpu_ids)) { 544 *apicid = per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits; 545 return 0; 546 } 547 548 return -EINVAL; 549 } 550 551 static unsigned int x2apic_get_apic_id(unsigned long x) 552 { 553 unsigned int id; 554 555 WARN_ON(preemptible() && num_online_cpus() > 1); 556 id = x | __this_cpu_read(x2apic_extra_bits); 557 558 return id; 559 } 560 561 static unsigned long set_apic_id(unsigned int id) 562 { 563 /* CHECKME: Do we need to mask out the xapic extra bits? */ 564 return id; 565 } 566 567 static unsigned int uv_read_apic_id(void) 568 { 569 return x2apic_get_apic_id(apic_read(APIC_ID)); 570 } 571 572 static int uv_phys_pkg_id(int initial_apicid, int index_msb) 573 { 574 return uv_read_apic_id() >> index_msb; 575 } 576 577 static void uv_send_IPI_self(int vector) 578 { 579 apic_write(APIC_SELF_IPI, vector); 580 } 581 582 static int uv_probe(void) 583 { 584 return apic == &apic_x2apic_uv_x; 585 } 586 587 static struct apic apic_x2apic_uv_x __ro_after_init = { 588 589 .name = "UV large system", 590 .probe = uv_probe, 591 .acpi_madt_oem_check = uv_acpi_madt_oem_check, 592 .apic_id_valid = uv_apic_id_valid, 593 .apic_id_registered = uv_apic_id_registered, 594 595 .irq_delivery_mode = dest_Fixed, 596 .irq_dest_mode = 0, /* Physical */ 597 598 .target_cpus = online_target_cpus, 599 .disable_esr = 0, 600 .dest_logical = APIC_DEST_LOGICAL, 601 .check_apicid_used = NULL, 602 603 .vector_allocation_domain = default_vector_allocation_domain, 604 .init_apic_ldr = uv_init_apic_ldr, 605 606 .ioapic_phys_id_map = NULL, 607 .setup_apic_routing = NULL, 608 .cpu_present_to_apicid = default_cpu_present_to_apicid, 609 .apicid_to_cpu_present = NULL, 610 .check_phys_apicid_present = default_check_phys_apicid_present, 611 .phys_pkg_id = uv_phys_pkg_id, 612 613 .get_apic_id = x2apic_get_apic_id, 614 .set_apic_id = set_apic_id, 615 616 .cpu_mask_to_apicid_and = uv_cpu_mask_to_apicid_and, 617 618 .send_IPI = uv_send_IPI_one, 619 .send_IPI_mask = uv_send_IPI_mask, 620 .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself, 621 .send_IPI_allbutself = uv_send_IPI_allbutself, 622 .send_IPI_all = uv_send_IPI_all, 623 .send_IPI_self = uv_send_IPI_self, 624 625 .wakeup_secondary_cpu = uv_wakeup_secondary, 626 .inquire_remote_apic = NULL, 627 628 .read = native_apic_msr_read, 629 .write = native_apic_msr_write, 630 .eoi_write = native_apic_msr_eoi_write, 631 .icr_read = native_x2apic_icr_read, 632 .icr_write = native_x2apic_icr_write, 633 .wait_icr_idle = native_x2apic_wait_icr_idle, 634 .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle, 635 }; 636 637 static void set_x2apic_extra_bits(int pnode) 638 { 639 __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift); 640 } 641 642 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH 3 643 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 644 645 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size) 646 { 647 union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias; 648 union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect; 649 unsigned long m_redirect; 650 unsigned long m_overlay; 651 int i; 652 653 for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) { 654 switch (i) { 655 case 0: 656 m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR; 657 m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR; 658 break; 659 case 1: 660 m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR; 661 m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR; 662 break; 663 case 2: 664 m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR; 665 m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR; 666 break; 667 } 668 alias.v = uv_read_local_mmr(m_overlay); 669 if (alias.s.enable && alias.s.base == 0) { 670 *size = (1UL << alias.s.m_alias); 671 redirect.v = uv_read_local_mmr(m_redirect); 672 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT; 673 return; 674 } 675 } 676 *base = *size = 0; 677 } 678 679 enum map_type {map_wb, map_uc}; 680 681 static __init void map_high(char *id, unsigned long base, int pshift, int bshift, int max_pnode, enum map_type map_type) 682 { 683 unsigned long bytes, paddr; 684 685 paddr = base << pshift; 686 bytes = (1UL << bshift) * (max_pnode + 1); 687 if (!paddr) { 688 pr_info("UV: Map %s_HI base address NULL\n", id); 689 return; 690 } 691 pr_debug("UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, paddr + bytes); 692 if (map_type == map_uc) 693 init_extra_mapping_uc(paddr, bytes); 694 else 695 init_extra_mapping_wb(paddr, bytes); 696 } 697 698 static __init void map_gru_distributed(unsigned long c) 699 { 700 union uvh_rh_gam_gru_overlay_config_mmr_u gru; 701 u64 paddr; 702 unsigned long bytes; 703 int nid; 704 705 gru.v = c; 706 707 /* Only base bits 42:28 relevant in dist mode */ 708 gru_dist_base = gru.v & 0x000007fff0000000UL; 709 if (!gru_dist_base) { 710 pr_info("UV: Map GRU_DIST base address NULL\n"); 711 return; 712 } 713 714 bytes = 1UL << UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT; 715 gru_dist_lmask = ((1UL << uv_hub_info->m_val) - 1) & ~(bytes - 1); 716 gru_dist_umask = ~((1UL << uv_hub_info->m_val) - 1); 717 gru_dist_base &= gru_dist_lmask; /* Clear bits above M */ 718 719 for_each_online_node(nid) { 720 paddr = ((u64)uv_node_to_pnode(nid) << uv_hub_info->m_val) | 721 gru_dist_base; 722 init_extra_mapping_wb(paddr, bytes); 723 gru_first_node_paddr = min(paddr, gru_first_node_paddr); 724 gru_last_node_paddr = max(paddr, gru_last_node_paddr); 725 } 726 727 /* Save upper (63:M) bits of address only for is_GRU_range */ 728 gru_first_node_paddr &= gru_dist_umask; 729 gru_last_node_paddr &= gru_dist_umask; 730 731 pr_debug("UV: Map GRU_DIST base 0x%016llx 0x%016llx - 0x%016llx\n", gru_dist_base, gru_first_node_paddr, gru_last_node_paddr); 732 } 733 734 static __init void map_gru_high(int max_pnode) 735 { 736 union uvh_rh_gam_gru_overlay_config_mmr_u gru; 737 int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT; 738 unsigned long mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK; 739 unsigned long base; 740 741 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR); 742 if (!gru.s.enable) { 743 pr_info("UV: GRU disabled\n"); 744 return; 745 } 746 747 if (is_uv3_hub() && gru.s3.mode) { 748 map_gru_distributed(gru.v); 749 return; 750 } 751 752 base = (gru.v & mask) >> shift; 753 map_high("GRU", base, shift, shift, max_pnode, map_wb); 754 gru_start_paddr = ((u64)base << shift); 755 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1); 756 } 757 758 static __init void map_mmr_high(int max_pnode) 759 { 760 union uvh_rh_gam_mmr_overlay_config_mmr_u mmr; 761 int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT; 762 763 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR); 764 if (mmr.s.enable) 765 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc); 766 else 767 pr_info("UV: MMR disabled\n"); 768 } 769 770 /* 771 * This commonality works because both 0 & 1 versions of the MMIOH OVERLAY 772 * and REDIRECT MMR regs are exactly the same on UV3. 773 */ 774 struct mmioh_config { 775 unsigned long overlay; 776 unsigned long redirect; 777 char *id; 778 }; 779 780 static __initdata struct mmioh_config mmiohs[] = { 781 { 782 UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR, 783 UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR, 784 "MMIOH0" 785 }, 786 { 787 UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR, 788 UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR, 789 "MMIOH1" 790 }, 791 }; 792 793 /* UV3 & UV4 have identical MMIOH overlay configs */ 794 static __init void map_mmioh_high_uv3(int index, int min_pnode, int max_pnode) 795 { 796 union uv3h_rh_gam_mmioh_overlay_config0_mmr_u overlay; 797 unsigned long mmr; 798 unsigned long base; 799 int i, n, shift, m_io, max_io; 800 int nasid, lnasid, fi, li; 801 char *id; 802 803 id = mmiohs[index].id; 804 overlay.v = uv_read_local_mmr(mmiohs[index].overlay); 805 806 pr_info("UV: %s overlay 0x%lx base:0x%x m_io:%d\n", id, overlay.v, overlay.s3.base, overlay.s3.m_io); 807 if (!overlay.s3.enable) { 808 pr_info("UV: %s disabled\n", id); 809 return; 810 } 811 812 shift = UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT; 813 base = (unsigned long)overlay.s3.base; 814 m_io = overlay.s3.m_io; 815 mmr = mmiohs[index].redirect; 816 n = UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH; 817 /* Convert to NASID: */ 818 min_pnode *= 2; 819 max_pnode *= 2; 820 max_io = lnasid = fi = li = -1; 821 822 for (i = 0; i < n; i++) { 823 union uv3h_rh_gam_mmioh_redirect_config0_mmr_u redirect; 824 825 redirect.v = uv_read_local_mmr(mmr + i * 8); 826 nasid = redirect.s3.nasid; 827 /* Invalid NASID: */ 828 if (nasid < min_pnode || max_pnode < nasid) 829 nasid = -1; 830 831 if (nasid == lnasid) { 832 li = i; 833 /* Last entry check: */ 834 if (i != n-1) 835 continue; 836 } 837 838 /* Check if we have a cached (or last) redirect to print: */ 839 if (lnasid != -1 || (i == n-1 && nasid != -1)) { 840 unsigned long addr1, addr2; 841 int f, l; 842 843 if (lnasid == -1) { 844 f = l = i; 845 lnasid = nasid; 846 } else { 847 f = fi; 848 l = li; 849 } 850 addr1 = (base << shift) + f * (1ULL << m_io); 851 addr2 = (base << shift) + (l + 1) * (1ULL << m_io); 852 pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n", id, fi, li, lnasid, addr1, addr2); 853 if (max_io < l) 854 max_io = l; 855 } 856 fi = li = i; 857 lnasid = nasid; 858 } 859 860 pr_info("UV: %s base:0x%lx shift:%d M_IO:%d MAX_IO:%d\n", id, base, shift, m_io, max_io); 861 862 if (max_io >= 0) 863 map_high(id, base, shift, m_io, max_io, map_uc); 864 } 865 866 static __init void map_mmioh_high(int min_pnode, int max_pnode) 867 { 868 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh; 869 unsigned long mmr, base; 870 int shift, enable, m_io, n_io; 871 872 if (is_uv3_hub() || is_uv4_hub()) { 873 /* Map both MMIOH regions: */ 874 map_mmioh_high_uv3(0, min_pnode, max_pnode); 875 map_mmioh_high_uv3(1, min_pnode, max_pnode); 876 return; 877 } 878 879 if (is_uv1_hub()) { 880 mmr = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR; 881 shift = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT; 882 mmioh.v = uv_read_local_mmr(mmr); 883 enable = !!mmioh.s1.enable; 884 base = mmioh.s1.base; 885 m_io = mmioh.s1.m_io; 886 n_io = mmioh.s1.n_io; 887 } else if (is_uv2_hub()) { 888 mmr = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR; 889 shift = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT; 890 mmioh.v = uv_read_local_mmr(mmr); 891 enable = !!mmioh.s2.enable; 892 base = mmioh.s2.base; 893 m_io = mmioh.s2.m_io; 894 n_io = mmioh.s2.n_io; 895 } else { 896 return; 897 } 898 899 if (enable) { 900 max_pnode &= (1 << n_io) - 1; 901 pr_info("UV: base:0x%lx shift:%d N_IO:%d M_IO:%d max_pnode:0x%x\n", base, shift, m_io, n_io, max_pnode); 902 map_high("MMIOH", base, shift, m_io, max_pnode, map_uc); 903 } else { 904 pr_info("UV: MMIOH disabled\n"); 905 } 906 } 907 908 static __init void map_low_mmrs(void) 909 { 910 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE); 911 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE); 912 } 913 914 static __init void uv_rtc_init(void) 915 { 916 long status; 917 u64 ticks_per_sec; 918 919 status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec); 920 921 if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) { 922 pr_warn("UV: unable to determine platform RTC clock frequency, guessing.\n"); 923 924 /* BIOS gives wrong value for clock frequency, so guess: */ 925 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL; 926 } else { 927 sn_rtc_cycles_per_second = ticks_per_sec; 928 } 929 } 930 931 /* 932 * percpu heartbeat timer 933 */ 934 static void uv_heartbeat(unsigned long ignored) 935 { 936 struct timer_list *timer = &uv_scir_info->timer; 937 unsigned char bits = uv_scir_info->state; 938 939 /* Flip heartbeat bit: */ 940 bits ^= SCIR_CPU_HEARTBEAT; 941 942 /* Is this CPU idle? */ 943 if (idle_cpu(raw_smp_processor_id())) 944 bits &= ~SCIR_CPU_ACTIVITY; 945 else 946 bits |= SCIR_CPU_ACTIVITY; 947 948 /* Update system controller interface reg: */ 949 uv_set_scir_bits(bits); 950 951 /* Enable next timer period: */ 952 mod_timer(timer, jiffies + SCIR_CPU_HB_INTERVAL); 953 } 954 955 static int uv_heartbeat_enable(unsigned int cpu) 956 { 957 while (!uv_cpu_scir_info(cpu)->enabled) { 958 struct timer_list *timer = &uv_cpu_scir_info(cpu)->timer; 959 960 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY); 961 setup_pinned_timer(timer, uv_heartbeat, cpu); 962 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL; 963 add_timer_on(timer, cpu); 964 uv_cpu_scir_info(cpu)->enabled = 1; 965 966 /* Also ensure that boot CPU is enabled: */ 967 cpu = 0; 968 } 969 return 0; 970 } 971 972 #ifdef CONFIG_HOTPLUG_CPU 973 static int uv_heartbeat_disable(unsigned int cpu) 974 { 975 if (uv_cpu_scir_info(cpu)->enabled) { 976 uv_cpu_scir_info(cpu)->enabled = 0; 977 del_timer(&uv_cpu_scir_info(cpu)->timer); 978 } 979 uv_set_cpu_scir_bits(cpu, 0xff); 980 return 0; 981 } 982 983 static __init void uv_scir_register_cpu_notifier(void) 984 { 985 cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "x86/x2apic-uvx:online", 986 uv_heartbeat_enable, uv_heartbeat_disable); 987 } 988 989 #else /* !CONFIG_HOTPLUG_CPU */ 990 991 static __init void uv_scir_register_cpu_notifier(void) 992 { 993 } 994 995 static __init int uv_init_heartbeat(void) 996 { 997 int cpu; 998 999 if (is_uv_system()) { 1000 for_each_online_cpu(cpu) 1001 uv_heartbeat_enable(cpu); 1002 } 1003 1004 return 0; 1005 } 1006 1007 late_initcall(uv_init_heartbeat); 1008 1009 #endif /* !CONFIG_HOTPLUG_CPU */ 1010 1011 /* Direct Legacy VGA I/O traffic to designated IOH */ 1012 int uv_set_vga_state(struct pci_dev *pdev, bool decode, unsigned int command_bits, u32 flags) 1013 { 1014 int domain, bus, rc; 1015 1016 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) 1017 return 0; 1018 1019 if ((command_bits & PCI_COMMAND_IO) == 0) 1020 return 0; 1021 1022 domain = pci_domain_nr(pdev->bus); 1023 bus = pdev->bus->number; 1024 1025 rc = uv_bios_set_legacy_vga_target(decode, domain, bus); 1026 1027 return rc; 1028 } 1029 1030 /* 1031 * Called on each CPU to initialize the per_cpu UV data area. 1032 * FIXME: hotplug not supported yet 1033 */ 1034 void uv_cpu_init(void) 1035 { 1036 /* CPU 0 initialization will be done via uv_system_init. */ 1037 if (smp_processor_id() == 0) 1038 return; 1039 1040 uv_hub_info->nr_online_cpus++; 1041 1042 if (get_uv_system_type() == UV_NON_UNIQUE_APIC) 1043 set_x2apic_extra_bits(uv_hub_info->pnode); 1044 } 1045 1046 struct mn { 1047 unsigned char m_val; 1048 unsigned char n_val; 1049 unsigned char m_shift; 1050 unsigned char n_lshift; 1051 }; 1052 1053 static void get_mn(struct mn *mnp) 1054 { 1055 union uvh_rh_gam_config_mmr_u m_n_config; 1056 union uv3h_gr0_gam_gr_config_u m_gr_config; 1057 1058 /* Make sure the whole structure is well initialized: */ 1059 memset(mnp, 0, sizeof(*mnp)); 1060 1061 m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR); 1062 mnp->n_val = m_n_config.s.n_skt; 1063 1064 if (is_uv4_hub()) { 1065 mnp->m_val = 0; 1066 mnp->n_lshift = 0; 1067 } else if (is_uv3_hub()) { 1068 mnp->m_val = m_n_config.s3.m_skt; 1069 m_gr_config.v = uv_read_local_mmr(UV3H_GR0_GAM_GR_CONFIG); 1070 mnp->n_lshift = m_gr_config.s3.m_skt; 1071 } else if (is_uv2_hub()) { 1072 mnp->m_val = m_n_config.s2.m_skt; 1073 mnp->n_lshift = mnp->m_val == 40 ? 40 : 39; 1074 } else if (is_uv1_hub()) { 1075 mnp->m_val = m_n_config.s1.m_skt; 1076 mnp->n_lshift = mnp->m_val; 1077 } 1078 mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0; 1079 } 1080 1081 void __init uv_init_hub_info(struct uv_hub_info_s *hi) 1082 { 1083 union uvh_node_id_u node_id; 1084 struct mn mn; 1085 1086 get_mn(&mn); 1087 hi->gpa_mask = mn.m_val ? 1088 (1UL << (mn.m_val + mn.n_val)) - 1 : 1089 (1UL << uv_cpuid.gpa_shift) - 1; 1090 1091 hi->m_val = mn.m_val; 1092 hi->n_val = mn.n_val; 1093 hi->m_shift = mn.m_shift; 1094 hi->n_lshift = mn.n_lshift ? mn.n_lshift : 0; 1095 hi->hub_revision = uv_hub_info->hub_revision; 1096 hi->pnode_mask = uv_cpuid.pnode_mask; 1097 hi->min_pnode = _min_pnode; 1098 hi->min_socket = _min_socket; 1099 hi->pnode_to_socket = _pnode_to_socket; 1100 hi->socket_to_node = _socket_to_node; 1101 hi->socket_to_pnode = _socket_to_pnode; 1102 hi->gr_table_len = _gr_table_len; 1103 hi->gr_table = _gr_table; 1104 1105 node_id.v = uv_read_local_mmr(UVH_NODE_ID); 1106 uv_cpuid.gnode_shift = max_t(unsigned int, uv_cpuid.gnode_shift, mn.n_val); 1107 hi->gnode_extra = (node_id.s.node_id & ~((1 << uv_cpuid.gnode_shift) - 1)) >> 1; 1108 hi->gnode_upper = (unsigned long)hi->gnode_extra << mn.m_val; 1109 1110 if (uv_gp_table) { 1111 hi->global_mmr_base = uv_gp_table->mmr_base; 1112 hi->global_mmr_shift = uv_gp_table->mmr_shift; 1113 hi->global_gru_base = uv_gp_table->gru_base; 1114 hi->global_gru_shift = uv_gp_table->gru_shift; 1115 hi->gpa_shift = uv_gp_table->gpa_shift; 1116 hi->gpa_mask = (1UL << hi->gpa_shift) - 1; 1117 } else { 1118 hi->global_mmr_base = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) & ~UV_MMR_ENABLE; 1119 hi->global_mmr_shift = _UV_GLOBAL_MMR64_PNODE_SHIFT; 1120 } 1121 1122 get_lowmem_redirect(&hi->lowmem_remap_base, &hi->lowmem_remap_top); 1123 1124 hi->apic_pnode_shift = uv_cpuid.socketid_shift; 1125 1126 /* Show system specific info: */ 1127 pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n", hi->n_val, hi->m_val, hi->m_shift, hi->n_lshift); 1128 pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n", hi->gpa_mask, hi->gpa_shift, hi->pnode_mask, hi->apic_pnode_shift); 1129 pr_info("UV: mmr_base/shift:0x%lx/%ld gru_base/shift:0x%lx/%ld\n", hi->global_mmr_base, hi->global_mmr_shift, hi->global_gru_base, hi->global_gru_shift); 1130 pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n", hi->gnode_upper, hi->gnode_extra); 1131 } 1132 1133 static void __init decode_gam_params(unsigned long ptr) 1134 { 1135 uv_gp_table = (struct uv_gam_parameters *)ptr; 1136 1137 pr_info("UV: GAM Params...\n"); 1138 pr_info("UV: mmr_base/shift:0x%llx/%d gru_base/shift:0x%llx/%d gpa_shift:%d\n", 1139 uv_gp_table->mmr_base, uv_gp_table->mmr_shift, 1140 uv_gp_table->gru_base, uv_gp_table->gru_shift, 1141 uv_gp_table->gpa_shift); 1142 } 1143 1144 static void __init decode_gam_rng_tbl(unsigned long ptr) 1145 { 1146 struct uv_gam_range_entry *gre = (struct uv_gam_range_entry *)ptr; 1147 unsigned long lgre = 0; 1148 int index = 0; 1149 int sock_min = 999999, pnode_min = 99999; 1150 int sock_max = -1, pnode_max = -1; 1151 1152 uv_gre_table = gre; 1153 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) { 1154 if (!index) { 1155 pr_info("UV: GAM Range Table...\n"); 1156 pr_info("UV: # %20s %14s %5s %4s %5s %3s %2s\n", "Range", "", "Size", "Type", "NASID", "SID", "PN"); 1157 } 1158 pr_info("UV: %2d: 0x%014lx-0x%014lx %5luG %3d %04x %02x %02x\n", 1159 index++, 1160 (unsigned long)lgre << UV_GAM_RANGE_SHFT, 1161 (unsigned long)gre->limit << UV_GAM_RANGE_SHFT, 1162 ((unsigned long)(gre->limit - lgre)) >> 1163 (30 - UV_GAM_RANGE_SHFT), /* 64M -> 1G */ 1164 gre->type, gre->nasid, gre->sockid, gre->pnode); 1165 1166 lgre = gre->limit; 1167 if (sock_min > gre->sockid) 1168 sock_min = gre->sockid; 1169 if (sock_max < gre->sockid) 1170 sock_max = gre->sockid; 1171 if (pnode_min > gre->pnode) 1172 pnode_min = gre->pnode; 1173 if (pnode_max < gre->pnode) 1174 pnode_max = gre->pnode; 1175 } 1176 _min_socket = sock_min; 1177 _max_socket = sock_max; 1178 _min_pnode = pnode_min; 1179 _max_pnode = pnode_max; 1180 _gr_table_len = index; 1181 1182 pr_info("UV: GRT: %d entries, sockets(min:%x,max:%x) pnodes(min:%x,max:%x)\n", index, _min_socket, _max_socket, _min_pnode, _max_pnode); 1183 } 1184 1185 static int __init decode_uv_systab(void) 1186 { 1187 struct uv_systab *st; 1188 int i; 1189 1190 if (uv_hub_info->hub_revision < UV4_HUB_REVISION_BASE) 1191 return 0; /* No extended UVsystab required */ 1192 1193 st = uv_systab; 1194 if ((!st) || (st->revision < UV_SYSTAB_VERSION_UV4_LATEST)) { 1195 int rev = st ? st->revision : 0; 1196 1197 pr_err("UV: BIOS UVsystab version(%x) mismatch, expecting(%x)\n", rev, UV_SYSTAB_VERSION_UV4_LATEST); 1198 pr_err("UV: Cannot support UV operations, switching to generic PC\n"); 1199 uv_system_type = UV_NONE; 1200 1201 return -EINVAL; 1202 } 1203 1204 for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) { 1205 unsigned long ptr = st->entry[i].offset; 1206 1207 if (!ptr) 1208 continue; 1209 1210 ptr = ptr + (unsigned long)st; 1211 1212 switch (st->entry[i].type) { 1213 case UV_SYSTAB_TYPE_GAM_PARAMS: 1214 decode_gam_params(ptr); 1215 break; 1216 1217 case UV_SYSTAB_TYPE_GAM_RNG_TBL: 1218 decode_gam_rng_tbl(ptr); 1219 break; 1220 } 1221 } 1222 return 0; 1223 } 1224 1225 /* 1226 * Set up physical blade translations from UVH_NODE_PRESENT_TABLE 1227 * .. NB: UVH_NODE_PRESENT_TABLE is going away, 1228 * .. being replaced by GAM Range Table 1229 */ 1230 static __init void boot_init_possible_blades(struct uv_hub_info_s *hub_info) 1231 { 1232 int i, uv_pb = 0; 1233 1234 pr_info("UV: NODE_PRESENT_DEPTH = %d\n", UVH_NODE_PRESENT_TABLE_DEPTH); 1235 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) { 1236 unsigned long np; 1237 1238 np = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8); 1239 if (np) 1240 pr_info("UV: NODE_PRESENT(%d) = 0x%016lx\n", i, np); 1241 1242 uv_pb += hweight64(np); 1243 } 1244 if (uv_possible_blades != uv_pb) 1245 uv_possible_blades = uv_pb; 1246 } 1247 1248 static void __init build_socket_tables(void) 1249 { 1250 struct uv_gam_range_entry *gre = uv_gre_table; 1251 int num, nump; 1252 int cpu, i, lnid; 1253 int minsock = _min_socket; 1254 int maxsock = _max_socket; 1255 int minpnode = _min_pnode; 1256 int maxpnode = _max_pnode; 1257 size_t bytes; 1258 1259 if (!gre) { 1260 if (is_uv1_hub() || is_uv2_hub() || is_uv3_hub()) { 1261 pr_info("UV: No UVsystab socket table, ignoring\n"); 1262 return; 1263 } 1264 pr_crit("UV: Error: UVsystab address translations not available!\n"); 1265 BUG(); 1266 } 1267 1268 /* Build socket id -> node id, pnode */ 1269 num = maxsock - minsock + 1; 1270 bytes = num * sizeof(_socket_to_node[0]); 1271 _socket_to_node = kmalloc(bytes, GFP_KERNEL); 1272 _socket_to_pnode = kmalloc(bytes, GFP_KERNEL); 1273 1274 nump = maxpnode - minpnode + 1; 1275 bytes = nump * sizeof(_pnode_to_socket[0]); 1276 _pnode_to_socket = kmalloc(bytes, GFP_KERNEL); 1277 BUG_ON(!_socket_to_node || !_socket_to_pnode || !_pnode_to_socket); 1278 1279 for (i = 0; i < num; i++) 1280 _socket_to_node[i] = _socket_to_pnode[i] = SOCK_EMPTY; 1281 1282 for (i = 0; i < nump; i++) 1283 _pnode_to_socket[i] = SOCK_EMPTY; 1284 1285 /* Fill in pnode/node/addr conversion list values: */ 1286 pr_info("UV: GAM Building socket/pnode conversion tables\n"); 1287 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) { 1288 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) 1289 continue; 1290 i = gre->sockid - minsock; 1291 /* Duplicate: */ 1292 if (_socket_to_pnode[i] != SOCK_EMPTY) 1293 continue; 1294 _socket_to_pnode[i] = gre->pnode; 1295 1296 i = gre->pnode - minpnode; 1297 _pnode_to_socket[i] = gre->sockid; 1298 1299 pr_info("UV: sid:%02x type:%d nasid:%04x pn:%02x pn2s:%2x\n", 1300 gre->sockid, gre->type, gre->nasid, 1301 _socket_to_pnode[gre->sockid - minsock], 1302 _pnode_to_socket[gre->pnode - minpnode]); 1303 } 1304 1305 /* Set socket -> node values: */ 1306 lnid = -1; 1307 for_each_present_cpu(cpu) { 1308 int nid = cpu_to_node(cpu); 1309 int apicid, sockid; 1310 1311 if (lnid == nid) 1312 continue; 1313 lnid = nid; 1314 apicid = per_cpu(x86_cpu_to_apicid, cpu); 1315 sockid = apicid >> uv_cpuid.socketid_shift; 1316 _socket_to_node[sockid - minsock] = nid; 1317 pr_info("UV: sid:%02x: apicid:%04x node:%2d\n", 1318 sockid, apicid, nid); 1319 } 1320 1321 /* Set up physical blade to pnode translation from GAM Range Table: */ 1322 bytes = num_possible_nodes() * sizeof(_node_to_pnode[0]); 1323 _node_to_pnode = kmalloc(bytes, GFP_KERNEL); 1324 BUG_ON(!_node_to_pnode); 1325 1326 for (lnid = 0; lnid < num_possible_nodes(); lnid++) { 1327 unsigned short sockid; 1328 1329 for (sockid = minsock; sockid <= maxsock; sockid++) { 1330 if (lnid == _socket_to_node[sockid - minsock]) { 1331 _node_to_pnode[lnid] = _socket_to_pnode[sockid - minsock]; 1332 break; 1333 } 1334 } 1335 if (sockid > maxsock) { 1336 pr_err("UV: socket for node %d not found!\n", lnid); 1337 BUG(); 1338 } 1339 } 1340 1341 /* 1342 * If socket id == pnode or socket id == node for all nodes, 1343 * system runs faster by removing corresponding conversion table. 1344 */ 1345 pr_info("UV: Checking socket->node/pnode for identity maps\n"); 1346 if (minsock == 0) { 1347 for (i = 0; i < num; i++) 1348 if (_socket_to_node[i] == SOCK_EMPTY || i != _socket_to_node[i]) 1349 break; 1350 if (i >= num) { 1351 kfree(_socket_to_node); 1352 _socket_to_node = NULL; 1353 pr_info("UV: 1:1 socket_to_node table removed\n"); 1354 } 1355 } 1356 if (minsock == minpnode) { 1357 for (i = 0; i < num; i++) 1358 if (_socket_to_pnode[i] != SOCK_EMPTY && 1359 _socket_to_pnode[i] != i + minpnode) 1360 break; 1361 if (i >= num) { 1362 kfree(_socket_to_pnode); 1363 _socket_to_pnode = NULL; 1364 pr_info("UV: 1:1 socket_to_pnode table removed\n"); 1365 } 1366 } 1367 } 1368 1369 static void __init uv_system_init_hub(void) 1370 { 1371 struct uv_hub_info_s hub_info = {0}; 1372 int bytes, cpu, nodeid; 1373 unsigned short min_pnode = 9999, max_pnode = 0; 1374 char *hub = is_uv4_hub() ? "UV400" : 1375 is_uv3_hub() ? "UV300" : 1376 is_uv2_hub() ? "UV2000/3000" : 1377 is_uv1_hub() ? "UV100/1000" : NULL; 1378 1379 if (!hub) { 1380 pr_err("UV: Unknown/unsupported UV hub\n"); 1381 return; 1382 } 1383 pr_info("UV: Found %s hub\n", hub); 1384 1385 map_low_mmrs(); 1386 1387 /* Get uv_systab for decoding: */ 1388 uv_bios_init(); 1389 1390 /* If there's an UVsystab problem then abort UV init: */ 1391 if (decode_uv_systab() < 0) 1392 return; 1393 1394 build_socket_tables(); 1395 build_uv_gr_table(); 1396 uv_init_hub_info(&hub_info); 1397 uv_possible_blades = num_possible_nodes(); 1398 if (!_node_to_pnode) 1399 boot_init_possible_blades(&hub_info); 1400 1401 /* uv_num_possible_blades() is really the hub count: */ 1402 pr_info("UV: Found %d hubs, %d nodes, %d CPUs\n", uv_num_possible_blades(), num_possible_nodes(), num_possible_cpus()); 1403 1404 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, &sn_region_size, &system_serial_number); 1405 hub_info.coherency_domain_number = sn_coherency_id; 1406 uv_rtc_init(); 1407 1408 bytes = sizeof(void *) * uv_num_possible_blades(); 1409 __uv_hub_info_list = kzalloc(bytes, GFP_KERNEL); 1410 BUG_ON(!__uv_hub_info_list); 1411 1412 bytes = sizeof(struct uv_hub_info_s); 1413 for_each_node(nodeid) { 1414 struct uv_hub_info_s *new_hub; 1415 1416 if (__uv_hub_info_list[nodeid]) { 1417 pr_err("UV: Node %d UV HUB already initialized!?\n", nodeid); 1418 BUG(); 1419 } 1420 1421 /* Allocate new per hub info list */ 1422 new_hub = (nodeid == 0) ? &uv_hub_info_node0 : kzalloc_node(bytes, GFP_KERNEL, nodeid); 1423 BUG_ON(!new_hub); 1424 __uv_hub_info_list[nodeid] = new_hub; 1425 new_hub = uv_hub_info_list(nodeid); 1426 BUG_ON(!new_hub); 1427 *new_hub = hub_info; 1428 1429 /* Use information from GAM table if available: */ 1430 if (_node_to_pnode) 1431 new_hub->pnode = _node_to_pnode[nodeid]; 1432 else /* Or fill in during CPU loop: */ 1433 new_hub->pnode = 0xffff; 1434 1435 new_hub->numa_blade_id = uv_node_to_blade_id(nodeid); 1436 new_hub->memory_nid = -1; 1437 new_hub->nr_possible_cpus = 0; 1438 new_hub->nr_online_cpus = 0; 1439 } 1440 1441 /* Initialize per CPU info: */ 1442 for_each_possible_cpu(cpu) { 1443 int apicid = per_cpu(x86_cpu_to_apicid, cpu); 1444 int numa_node_id; 1445 unsigned short pnode; 1446 1447 nodeid = cpu_to_node(cpu); 1448 numa_node_id = numa_cpu_node(cpu); 1449 pnode = uv_apicid_to_pnode(apicid); 1450 1451 uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list(nodeid); 1452 uv_cpu_info_per(cpu)->blade_cpu_id = uv_cpu_hub_info(cpu)->nr_possible_cpus++; 1453 if (uv_cpu_hub_info(cpu)->memory_nid == -1) 1454 uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu); 1455 1456 /* Init memoryless node: */ 1457 if (nodeid != numa_node_id && 1458 uv_hub_info_list(numa_node_id)->pnode == 0xffff) 1459 uv_hub_info_list(numa_node_id)->pnode = pnode; 1460 else if (uv_cpu_hub_info(cpu)->pnode == 0xffff) 1461 uv_cpu_hub_info(cpu)->pnode = pnode; 1462 1463 uv_cpu_scir_info(cpu)->offset = uv_scir_offset(apicid); 1464 } 1465 1466 for_each_node(nodeid) { 1467 unsigned short pnode = uv_hub_info_list(nodeid)->pnode; 1468 1469 /* Add pnode info for pre-GAM list nodes without CPUs: */ 1470 if (pnode == 0xffff) { 1471 unsigned long paddr; 1472 1473 paddr = node_start_pfn(nodeid) << PAGE_SHIFT; 1474 pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr)); 1475 uv_hub_info_list(nodeid)->pnode = pnode; 1476 } 1477 min_pnode = min(pnode, min_pnode); 1478 max_pnode = max(pnode, max_pnode); 1479 pr_info("UV: UVHUB node:%2d pn:%02x nrcpus:%d\n", 1480 nodeid, 1481 uv_hub_info_list(nodeid)->pnode, 1482 uv_hub_info_list(nodeid)->nr_possible_cpus); 1483 } 1484 1485 pr_info("UV: min_pnode:%02x max_pnode:%02x\n", min_pnode, max_pnode); 1486 map_gru_high(max_pnode); 1487 map_mmr_high(max_pnode); 1488 map_mmioh_high(min_pnode, max_pnode); 1489 1490 uv_nmi_setup(); 1491 uv_cpu_init(); 1492 uv_scir_register_cpu_notifier(); 1493 proc_mkdir("sgi_uv", NULL); 1494 1495 /* Register Legacy VGA I/O redirection handler: */ 1496 pci_register_set_vga_state(uv_set_vga_state); 1497 1498 /* 1499 * For a kdump kernel the reset must be BOOT_ACPI, not BOOT_EFI, as 1500 * EFI is not enabled in the kdump kernel: 1501 */ 1502 if (is_kdump_kernel()) 1503 reboot_type = BOOT_ACPI; 1504 } 1505 1506 /* 1507 * There is a small amount of UV specific code needed to initialize a 1508 * UV system that does not have a "UV HUB" (referred to as "hubless"). 1509 */ 1510 void __init uv_system_init(void) 1511 { 1512 if (likely(!is_uv_system() && !is_uv_hubless())) 1513 return; 1514 1515 if (is_uv_system()) 1516 uv_system_init_hub(); 1517 else 1518 uv_nmi_setup_hubless(); 1519 } 1520 1521 apic_driver(apic_x2apic_uv_x); 1522