1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * SGI UV APIC functions (note: not an Intel compatible APIC) 7 * 8 * (C) Copyright 2020 Hewlett Packard Enterprise Development LP 9 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved. 10 */ 11 #include <linux/crash_dump.h> 12 #include <linux/cpuhotplug.h> 13 #include <linux/cpumask.h> 14 #include <linux/proc_fs.h> 15 #include <linux/memory.h> 16 #include <linux/export.h> 17 #include <linux/pci.h> 18 #include <linux/acpi.h> 19 #include <linux/efi.h> 20 21 #include <asm/e820/api.h> 22 #include <asm/uv/uv_mmrs.h> 23 #include <asm/uv/uv_hub.h> 24 #include <asm/uv/bios.h> 25 #include <asm/uv/uv.h> 26 #include <asm/apic.h> 27 28 static enum uv_system_type uv_system_type; 29 static int uv_hubbed_system; 30 static int uv_hubless_system; 31 static u64 gru_start_paddr, gru_end_paddr; 32 static union uvh_apicid uvh_apicid; 33 static int uv_node_id; 34 35 /* Unpack AT/OEM/TABLE ID's to be NULL terminated strings */ 36 static u8 uv_archtype[UV_AT_SIZE]; 37 static u8 oem_id[ACPI_OEM_ID_SIZE + 1]; 38 static u8 oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1]; 39 40 /* Information derived from CPUID and some UV MMRs */ 41 static struct { 42 unsigned int apicid_shift; 43 unsigned int apicid_mask; 44 unsigned int socketid_shift; /* aka pnode_shift for UV2/3 */ 45 unsigned int pnode_mask; 46 unsigned int nasid_shift; 47 unsigned int gpa_shift; 48 unsigned int gnode_shift; 49 unsigned int m_skt; 50 unsigned int n_skt; 51 } uv_cpuid; 52 53 static int uv_min_hub_revision_id; 54 55 static struct apic apic_x2apic_uv_x; 56 static struct uv_hub_info_s uv_hub_info_node0; 57 58 /* Set this to use hardware error handler instead of kernel panic: */ 59 static int disable_uv_undefined_panic = 1; 60 61 unsigned long uv_undefined(char *str) 62 { 63 if (likely(!disable_uv_undefined_panic)) 64 panic("UV: error: undefined MMR: %s\n", str); 65 else 66 pr_crit("UV: error: undefined MMR: %s\n", str); 67 68 /* Cause a machine fault: */ 69 return ~0ul; 70 } 71 EXPORT_SYMBOL(uv_undefined); 72 73 static unsigned long __init uv_early_read_mmr(unsigned long addr) 74 { 75 unsigned long val, *mmr; 76 77 mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr)); 78 val = *mmr; 79 early_iounmap(mmr, sizeof(*mmr)); 80 81 return val; 82 } 83 84 static inline bool is_GRU_range(u64 start, u64 end) 85 { 86 if (!gru_start_paddr) 87 return false; 88 89 return start >= gru_start_paddr && end <= gru_end_paddr; 90 } 91 92 static bool uv_is_untracked_pat_range(u64 start, u64 end) 93 { 94 return is_ISA_range(start, end) || is_GRU_range(start, end); 95 } 96 97 static void __init early_get_pnodeid(void) 98 { 99 int pnode; 100 101 uv_cpuid.m_skt = 0; 102 if (UVH_RH10_GAM_ADDR_MAP_CONFIG) { 103 union uvh_rh10_gam_addr_map_config_u m_n_config; 104 105 m_n_config.v = uv_early_read_mmr(UVH_RH10_GAM_ADDR_MAP_CONFIG); 106 uv_cpuid.n_skt = m_n_config.s.n_skt; 107 uv_cpuid.nasid_shift = 0; 108 } else if (UVH_RH_GAM_ADDR_MAP_CONFIG) { 109 union uvh_rh_gam_addr_map_config_u m_n_config; 110 111 m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_ADDR_MAP_CONFIG); 112 uv_cpuid.n_skt = m_n_config.s.n_skt; 113 if (is_uv(UV3)) 114 uv_cpuid.m_skt = m_n_config.s3.m_skt; 115 if (is_uv(UV2)) 116 uv_cpuid.m_skt = m_n_config.s2.m_skt; 117 uv_cpuid.nasid_shift = 1; 118 } else { 119 unsigned long GAM_ADDR_MAP_CONFIG = 0; 120 121 WARN(GAM_ADDR_MAP_CONFIG == 0, 122 "UV: WARN: GAM_ADDR_MAP_CONFIG is not available\n"); 123 uv_cpuid.n_skt = 0; 124 uv_cpuid.nasid_shift = 0; 125 } 126 127 if (is_uv(UV4|UVY)) 128 uv_cpuid.gnode_shift = 2; /* min partition is 4 sockets */ 129 130 uv_cpuid.pnode_mask = (1 << uv_cpuid.n_skt) - 1; 131 pnode = (uv_node_id >> uv_cpuid.nasid_shift) & uv_cpuid.pnode_mask; 132 uv_cpuid.gpa_shift = 46; /* Default unless changed */ 133 134 pr_info("UV: n_skt:%d pnmsk:%x pn:%x\n", 135 uv_cpuid.n_skt, uv_cpuid.pnode_mask, pnode); 136 } 137 138 /* Running on a UV Hubbed system, determine which UV Hub Type it is */ 139 static int __init early_set_hub_type(void) 140 { 141 union uvh_node_id_u node_id; 142 143 /* 144 * The NODE_ID MMR is always at offset 0. 145 * Contains the chip part # + revision. 146 * Node_id field started with 15 bits, 147 * ... now 7 but upper 8 are masked to 0. 148 * All blades/nodes have the same part # and hub revision. 149 */ 150 node_id.v = uv_early_read_mmr(UVH_NODE_ID); 151 uv_node_id = node_id.sx.node_id; 152 153 switch (node_id.s.part_number) { 154 155 case UV5_HUB_PART_NUMBER: 156 uv_min_hub_revision_id = node_id.s.revision 157 + UV5_HUB_REVISION_BASE; 158 uv_hub_type_set(UV5); 159 break; 160 161 /* UV4/4A only have a revision difference */ 162 case UV4_HUB_PART_NUMBER: 163 uv_min_hub_revision_id = node_id.s.revision 164 + UV4_HUB_REVISION_BASE; 165 uv_hub_type_set(UV4); 166 if (uv_min_hub_revision_id == UV4A_HUB_REVISION_BASE) 167 uv_hub_type_set(UV4|UV4A); 168 break; 169 170 case UV3_HUB_PART_NUMBER: 171 case UV3_HUB_PART_NUMBER_X: 172 uv_min_hub_revision_id = node_id.s.revision 173 + UV3_HUB_REVISION_BASE; 174 uv_hub_type_set(UV3); 175 break; 176 177 case UV2_HUB_PART_NUMBER: 178 case UV2_HUB_PART_NUMBER_X: 179 uv_min_hub_revision_id = node_id.s.revision 180 + UV2_HUB_REVISION_BASE - 1; 181 uv_hub_type_set(UV2); 182 break; 183 184 default: 185 return 0; 186 } 187 188 pr_info("UV: part#:%x rev:%d rev_id:%d UVtype:0x%x\n", 189 node_id.s.part_number, node_id.s.revision, 190 uv_min_hub_revision_id, is_uv(~0)); 191 192 return 1; 193 } 194 195 static void __init uv_tsc_check_sync(void) 196 { 197 u64 mmr; 198 int sync_state; 199 int mmr_shift; 200 char *state; 201 202 /* Different returns from different UV BIOS versions */ 203 mmr = uv_early_read_mmr(UVH_TSC_SYNC_MMR); 204 mmr_shift = 205 is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT; 206 sync_state = (mmr >> mmr_shift) & UVH_TSC_SYNC_MASK; 207 208 /* Check if TSC is valid for all sockets */ 209 switch (sync_state) { 210 case UVH_TSC_SYNC_VALID: 211 state = "in sync"; 212 mark_tsc_async_resets("UV BIOS"); 213 break; 214 215 /* If BIOS state unknown, don't do anything */ 216 case UVH_TSC_SYNC_UNKNOWN: 217 state = "unknown"; 218 break; 219 220 /* Otherwise, BIOS indicates problem with TSC */ 221 default: 222 state = "unstable"; 223 mark_tsc_unstable("UV BIOS"); 224 break; 225 } 226 pr_info("UV: TSC sync state from BIOS:0%d(%s)\n", sync_state, state); 227 } 228 229 /* Selector for (4|4A|5) structs */ 230 #define uvxy_field(sname, field, undef) ( \ 231 is_uv(UV4A) ? sname.s4a.field : \ 232 is_uv(UV4) ? sname.s4.field : \ 233 is_uv(UV3) ? sname.s3.field : \ 234 undef) 235 236 /* [Copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */ 237 238 #define SMT_LEVEL 0 /* Leaf 0xb SMT level */ 239 #define INVALID_TYPE 0 /* Leaf 0xb sub-leaf types */ 240 #define SMT_TYPE 1 241 #define CORE_TYPE 2 242 #define LEAFB_SUBTYPE(ecx) (((ecx) >> 8) & 0xff) 243 #define BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f) 244 245 static void set_x2apic_bits(void) 246 { 247 unsigned int eax, ebx, ecx, edx, sub_index; 248 unsigned int sid_shift; 249 250 cpuid(0, &eax, &ebx, &ecx, &edx); 251 if (eax < 0xb) { 252 pr_info("UV: CPU does not have CPUID.11\n"); 253 return; 254 } 255 256 cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx); 257 if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) { 258 pr_info("UV: CPUID.11 not implemented\n"); 259 return; 260 } 261 262 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax); 263 sub_index = 1; 264 do { 265 cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx); 266 if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) { 267 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax); 268 break; 269 } 270 sub_index++; 271 } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE); 272 273 uv_cpuid.apicid_shift = 0; 274 uv_cpuid.apicid_mask = (~(-1 << sid_shift)); 275 uv_cpuid.socketid_shift = sid_shift; 276 } 277 278 static void __init early_get_apic_socketid_shift(void) 279 { 280 if (is_uv2_hub() || is_uv3_hub()) 281 uvh_apicid.v = uv_early_read_mmr(UVH_APICID); 282 283 set_x2apic_bits(); 284 285 pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n", uv_cpuid.apicid_shift, uv_cpuid.apicid_mask); 286 pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n", uv_cpuid.socketid_shift, uv_cpuid.pnode_mask); 287 } 288 289 static void __init uv_stringify(int len, char *to, char *from) 290 { 291 /* Relies on 'to' being NULL chars so result will be NULL terminated */ 292 strncpy(to, from, len-1); 293 } 294 295 /* Find UV arch type entry in UVsystab */ 296 static unsigned long __init early_find_archtype(struct uv_systab *st) 297 { 298 int i; 299 300 for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) { 301 unsigned long ptr = st->entry[i].offset; 302 303 if (!ptr) 304 continue; 305 ptr += (unsigned long)st; 306 if (st->entry[i].type == UV_SYSTAB_TYPE_ARCH_TYPE) 307 return ptr; 308 } 309 return 0; 310 } 311 312 /* Validate UV arch type field in UVsystab */ 313 static int __init decode_arch_type(unsigned long ptr) 314 { 315 struct uv_arch_type_entry *uv_ate = (struct uv_arch_type_entry *)ptr; 316 int n = strlen(uv_ate->archtype); 317 318 if (n > 0 && n < sizeof(uv_ate->archtype)) { 319 pr_info("UV: UVarchtype received from BIOS\n"); 320 uv_stringify(UV_AT_SIZE, uv_archtype, uv_ate->archtype); 321 return 1; 322 } 323 return 0; 324 } 325 326 /* Determine if UV arch type entry might exist in UVsystab */ 327 static int __init early_get_arch_type(void) 328 { 329 unsigned long uvst_physaddr, uvst_size, ptr; 330 struct uv_systab *st; 331 u32 rev; 332 int ret; 333 334 uvst_physaddr = get_uv_systab_phys(0); 335 if (!uvst_physaddr) 336 return 0; 337 338 st = early_memremap_ro(uvst_physaddr, sizeof(struct uv_systab)); 339 if (!st) { 340 pr_err("UV: Cannot access UVsystab, remap failed\n"); 341 return 0; 342 } 343 344 rev = st->revision; 345 if (rev < UV_SYSTAB_VERSION_UV5) { 346 early_memunmap(st, sizeof(struct uv_systab)); 347 return 0; 348 } 349 350 uvst_size = st->size; 351 early_memunmap(st, sizeof(struct uv_systab)); 352 st = early_memremap_ro(uvst_physaddr, uvst_size); 353 if (!st) { 354 pr_err("UV: Cannot access UVarchtype, remap failed\n"); 355 return 0; 356 } 357 358 ptr = early_find_archtype(st); 359 if (!ptr) { 360 early_memunmap(st, uvst_size); 361 return 0; 362 } 363 364 ret = decode_arch_type(ptr); 365 early_memunmap(st, uvst_size); 366 return ret; 367 } 368 369 static int __init uv_set_system_type(char *_oem_id) 370 { 371 /* Save OEM_ID passed from ACPI MADT */ 372 uv_stringify(sizeof(oem_id), oem_id, _oem_id); 373 374 /* Check if BIOS sent us a UVarchtype */ 375 if (!early_get_arch_type()) 376 377 /* If not use OEM ID for UVarchtype */ 378 uv_stringify(UV_AT_SIZE, uv_archtype, _oem_id); 379 380 /* Check if not hubbed */ 381 if (strncmp(uv_archtype, "SGI", 3) != 0) { 382 383 /* (Not hubbed), check if not hubless */ 384 if (strncmp(uv_archtype, "NSGI", 4) != 0) 385 386 /* (Not hubless), not a UV */ 387 return 0; 388 389 /* UV4 Hubless: CH */ 390 if (strncmp(uv_archtype, "NSGI4", 5) == 0) 391 uv_hubless_system = 0x11; 392 393 /* UV3 Hubless: UV300/MC990X w/o hub */ 394 else 395 uv_hubless_system = 0x9; 396 397 pr_info("UV: OEM IDs %s/%s, SystemType %d, HUBLESS ID %x\n", 398 oem_id, oem_table_id, uv_system_type, uv_hubless_system); 399 return 0; 400 } 401 402 if (numa_off) { 403 pr_err("UV: NUMA is off, disabling UV support\n"); 404 return 0; 405 } 406 407 /* Set hubbed type if true */ 408 uv_hub_info->hub_revision = 409 !strncmp(uv_archtype, "SGI5", 4) ? UV5_HUB_REVISION_BASE : 410 !strncmp(uv_archtype, "SGI4", 4) ? UV4_HUB_REVISION_BASE : 411 !strncmp(uv_archtype, "SGI3", 4) ? UV3_HUB_REVISION_BASE : 412 !strcmp(uv_archtype, "SGI2") ? UV2_HUB_REVISION_BASE : 0; 413 414 switch (uv_hub_info->hub_revision) { 415 case UV5_HUB_REVISION_BASE: 416 uv_hubbed_system = 0x21; 417 uv_hub_type_set(UV5); 418 break; 419 420 case UV4_HUB_REVISION_BASE: 421 uv_hubbed_system = 0x11; 422 uv_hub_type_set(UV4); 423 break; 424 425 case UV3_HUB_REVISION_BASE: 426 uv_hubbed_system = 0x9; 427 uv_hub_type_set(UV3); 428 break; 429 430 case UV2_HUB_REVISION_BASE: 431 uv_hubbed_system = 0x5; 432 uv_hub_type_set(UV2); 433 break; 434 435 default: 436 return 0; 437 } 438 439 /* Get UV hub chip part number & revision */ 440 early_set_hub_type(); 441 442 /* Other UV setup functions */ 443 early_get_pnodeid(); 444 early_get_apic_socketid_shift(); 445 x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range; 446 x86_platform.nmi_init = uv_nmi_init; 447 uv_tsc_check_sync(); 448 449 return 1; 450 } 451 452 /* Called early to probe for the correct APIC driver */ 453 static int __init uv_acpi_madt_oem_check(char *_oem_id, char *_oem_table_id) 454 { 455 /* Set up early hub info fields for Node 0 */ 456 uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0; 457 458 /* If not UV, return. */ 459 if (likely(uv_set_system_type(_oem_id) == 0)) 460 return 0; 461 462 /* Save and Decode OEM Table ID */ 463 uv_stringify(sizeof(oem_table_id), oem_table_id, _oem_table_id); 464 465 /* This is the most common hardware variant, x2apic mode */ 466 if (!strcmp(oem_table_id, "UVX")) 467 uv_system_type = UV_X2APIC; 468 469 /* Only used for very small systems, usually 1 chassis, legacy mode */ 470 else if (!strcmp(oem_table_id, "UVL")) 471 uv_system_type = UV_LEGACY_APIC; 472 473 else 474 goto badbios; 475 476 pr_info("UV: OEM IDs %s/%s, System/UVType %d/0x%x, HUB RevID %d\n", 477 oem_id, oem_table_id, uv_system_type, is_uv(UV_ANY), 478 uv_min_hub_revision_id); 479 480 return 0; 481 482 badbios: 483 pr_err("UV: UVarchtype:%s not supported\n", uv_archtype); 484 BUG(); 485 } 486 487 enum uv_system_type get_uv_system_type(void) 488 { 489 return uv_system_type; 490 } 491 492 int is_uv_system(void) 493 { 494 return uv_system_type != UV_NONE; 495 } 496 EXPORT_SYMBOL_GPL(is_uv_system); 497 498 int is_uv_hubbed(int uvtype) 499 { 500 return (uv_hubbed_system & uvtype); 501 } 502 EXPORT_SYMBOL_GPL(is_uv_hubbed); 503 504 static int is_uv_hubless(int uvtype) 505 { 506 return (uv_hubless_system & uvtype); 507 } 508 509 void **__uv_hub_info_list; 510 EXPORT_SYMBOL_GPL(__uv_hub_info_list); 511 512 DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info); 513 EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info); 514 515 short uv_possible_blades; 516 EXPORT_SYMBOL_GPL(uv_possible_blades); 517 518 unsigned long sn_rtc_cycles_per_second; 519 EXPORT_SYMBOL(sn_rtc_cycles_per_second); 520 521 /* The following values are used for the per node hub info struct */ 522 static __initdata unsigned short *_node_to_pnode; 523 static __initdata unsigned short _min_socket, _max_socket; 524 static __initdata unsigned short _min_pnode, _max_pnode, _gr_table_len; 525 static __initdata struct uv_gam_range_entry *uv_gre_table; 526 static __initdata struct uv_gam_parameters *uv_gp_table; 527 static __initdata unsigned short *_socket_to_node; 528 static __initdata unsigned short *_socket_to_pnode; 529 static __initdata unsigned short *_pnode_to_socket; 530 531 static __initdata struct uv_gam_range_s *_gr_table; 532 533 #define SOCK_EMPTY ((unsigned short)~0) 534 535 /* Default UV memory block size is 2GB */ 536 static unsigned long mem_block_size __initdata = (2UL << 30); 537 538 /* Kernel parameter to specify UV mem block size */ 539 static int __init parse_mem_block_size(char *ptr) 540 { 541 unsigned long size = memparse(ptr, NULL); 542 543 /* Size will be rounded down by set_block_size() below */ 544 mem_block_size = size; 545 return 0; 546 } 547 early_param("uv_memblksize", parse_mem_block_size); 548 549 static __init int adj_blksize(u32 lgre) 550 { 551 unsigned long base = (unsigned long)lgre << UV_GAM_RANGE_SHFT; 552 unsigned long size; 553 554 for (size = mem_block_size; size > MIN_MEMORY_BLOCK_SIZE; size >>= 1) 555 if (IS_ALIGNED(base, size)) 556 break; 557 558 if (size >= mem_block_size) 559 return 0; 560 561 mem_block_size = size; 562 return 1; 563 } 564 565 static __init void set_block_size(void) 566 { 567 unsigned int order = ffs(mem_block_size); 568 569 if (order) { 570 /* adjust for ffs return of 1..64 */ 571 set_memory_block_size_order(order - 1); 572 pr_info("UV: mem_block_size set to 0x%lx\n", mem_block_size); 573 } else { 574 /* bad or zero value, default to 1UL << 31 (2GB) */ 575 pr_err("UV: mem_block_size error with 0x%lx\n", mem_block_size); 576 set_memory_block_size_order(31); 577 } 578 } 579 580 /* Build GAM range lookup table: */ 581 static __init void build_uv_gr_table(void) 582 { 583 struct uv_gam_range_entry *gre = uv_gre_table; 584 struct uv_gam_range_s *grt; 585 unsigned long last_limit = 0, ram_limit = 0; 586 int bytes, i, sid, lsid = -1, indx = 0, lindx = -1; 587 588 if (!gre) 589 return; 590 591 bytes = _gr_table_len * sizeof(struct uv_gam_range_s); 592 grt = kzalloc(bytes, GFP_KERNEL); 593 BUG_ON(!grt); 594 _gr_table = grt; 595 596 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) { 597 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) { 598 if (!ram_limit) { 599 /* Mark hole between RAM/non-RAM: */ 600 ram_limit = last_limit; 601 last_limit = gre->limit; 602 lsid++; 603 continue; 604 } 605 last_limit = gre->limit; 606 pr_info("UV: extra hole in GAM RE table @%d\n", (int)(gre - uv_gre_table)); 607 continue; 608 } 609 if (_max_socket < gre->sockid) { 610 pr_err("UV: GAM table sockid(%d) too large(>%d) @%d\n", gre->sockid, _max_socket, (int)(gre - uv_gre_table)); 611 continue; 612 } 613 sid = gre->sockid - _min_socket; 614 if (lsid < sid) { 615 /* New range: */ 616 grt = &_gr_table[indx]; 617 grt->base = lindx; 618 grt->nasid = gre->nasid; 619 grt->limit = last_limit = gre->limit; 620 lsid = sid; 621 lindx = indx++; 622 continue; 623 } 624 /* Update range: */ 625 if (lsid == sid && !ram_limit) { 626 /* .. if contiguous: */ 627 if (grt->limit == last_limit) { 628 grt->limit = last_limit = gre->limit; 629 continue; 630 } 631 } 632 /* Non-contiguous RAM range: */ 633 if (!ram_limit) { 634 grt++; 635 grt->base = lindx; 636 grt->nasid = gre->nasid; 637 grt->limit = last_limit = gre->limit; 638 continue; 639 } 640 /* Non-contiguous/non-RAM: */ 641 grt++; 642 /* base is this entry */ 643 grt->base = grt - _gr_table; 644 grt->nasid = gre->nasid; 645 grt->limit = last_limit = gre->limit; 646 lsid++; 647 } 648 649 /* Shorten table if possible */ 650 grt++; 651 i = grt - _gr_table; 652 if (i < _gr_table_len) { 653 void *ret; 654 655 bytes = i * sizeof(struct uv_gam_range_s); 656 ret = krealloc(_gr_table, bytes, GFP_KERNEL); 657 if (ret) { 658 _gr_table = ret; 659 _gr_table_len = i; 660 } 661 } 662 663 /* Display resultant GAM range table: */ 664 for (i = 0, grt = _gr_table; i < _gr_table_len; i++, grt++) { 665 unsigned long start, end; 666 int gb = grt->base; 667 668 start = gb < 0 ? 0 : (unsigned long)_gr_table[gb].limit << UV_GAM_RANGE_SHFT; 669 end = (unsigned long)grt->limit << UV_GAM_RANGE_SHFT; 670 671 pr_info("UV: GAM Range %2d %04x 0x%013lx-0x%013lx (%d)\n", i, grt->nasid, start, end, gb); 672 } 673 } 674 675 static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip) 676 { 677 unsigned long val; 678 int pnode; 679 680 pnode = uv_apicid_to_pnode(phys_apicid); 681 682 val = (1UL << UVH_IPI_INT_SEND_SHFT) | 683 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | 684 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | 685 APIC_DM_INIT; 686 687 uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 688 689 val = (1UL << UVH_IPI_INT_SEND_SHFT) | 690 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | 691 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | 692 APIC_DM_STARTUP; 693 694 uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 695 696 return 0; 697 } 698 699 static void uv_send_IPI_one(int cpu, int vector) 700 { 701 unsigned long apicid = per_cpu(x86_cpu_to_apicid, cpu); 702 int pnode = uv_apicid_to_pnode(apicid); 703 unsigned long dmode, val; 704 705 if (vector == NMI_VECTOR) 706 dmode = dest_NMI; 707 else 708 dmode = dest_Fixed; 709 710 val = (1UL << UVH_IPI_INT_SEND_SHFT) | 711 (apicid << UVH_IPI_INT_APIC_ID_SHFT) | 712 (dmode << UVH_IPI_INT_DELIVERY_MODE_SHFT) | 713 (vector << UVH_IPI_INT_VECTOR_SHFT); 714 715 uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 716 } 717 718 static void uv_send_IPI_mask(const struct cpumask *mask, int vector) 719 { 720 unsigned int cpu; 721 722 for_each_cpu(cpu, mask) 723 uv_send_IPI_one(cpu, vector); 724 } 725 726 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) 727 { 728 unsigned int this_cpu = smp_processor_id(); 729 unsigned int cpu; 730 731 for_each_cpu(cpu, mask) { 732 if (cpu != this_cpu) 733 uv_send_IPI_one(cpu, vector); 734 } 735 } 736 737 static void uv_send_IPI_allbutself(int vector) 738 { 739 unsigned int this_cpu = smp_processor_id(); 740 unsigned int cpu; 741 742 for_each_online_cpu(cpu) { 743 if (cpu != this_cpu) 744 uv_send_IPI_one(cpu, vector); 745 } 746 } 747 748 static void uv_send_IPI_all(int vector) 749 { 750 uv_send_IPI_mask(cpu_online_mask, vector); 751 } 752 753 static int uv_apic_id_valid(u32 apicid) 754 { 755 return 1; 756 } 757 758 static int uv_apic_id_registered(void) 759 { 760 return 1; 761 } 762 763 static void uv_init_apic_ldr(void) 764 { 765 } 766 767 static u32 apic_uv_calc_apicid(unsigned int cpu) 768 { 769 return apic_default_calc_apicid(cpu); 770 } 771 772 static unsigned int x2apic_get_apic_id(unsigned long id) 773 { 774 return id; 775 } 776 777 static u32 set_apic_id(unsigned int id) 778 { 779 return id; 780 } 781 782 static unsigned int uv_read_apic_id(void) 783 { 784 return x2apic_get_apic_id(apic_read(APIC_ID)); 785 } 786 787 static int uv_phys_pkg_id(int initial_apicid, int index_msb) 788 { 789 return uv_read_apic_id() >> index_msb; 790 } 791 792 static void uv_send_IPI_self(int vector) 793 { 794 apic_write(APIC_SELF_IPI, vector); 795 } 796 797 static int uv_probe(void) 798 { 799 return apic == &apic_x2apic_uv_x; 800 } 801 802 static struct apic apic_x2apic_uv_x __ro_after_init = { 803 804 .name = "UV large system", 805 .probe = uv_probe, 806 .acpi_madt_oem_check = uv_acpi_madt_oem_check, 807 .apic_id_valid = uv_apic_id_valid, 808 .apic_id_registered = uv_apic_id_registered, 809 810 .irq_delivery_mode = dest_Fixed, 811 .irq_dest_mode = 0, /* Physical */ 812 813 .disable_esr = 0, 814 .dest_logical = APIC_DEST_LOGICAL, 815 .check_apicid_used = NULL, 816 817 .init_apic_ldr = uv_init_apic_ldr, 818 819 .ioapic_phys_id_map = NULL, 820 .setup_apic_routing = NULL, 821 .cpu_present_to_apicid = default_cpu_present_to_apicid, 822 .apicid_to_cpu_present = NULL, 823 .check_phys_apicid_present = default_check_phys_apicid_present, 824 .phys_pkg_id = uv_phys_pkg_id, 825 826 .get_apic_id = x2apic_get_apic_id, 827 .set_apic_id = set_apic_id, 828 829 .calc_dest_apicid = apic_uv_calc_apicid, 830 831 .send_IPI = uv_send_IPI_one, 832 .send_IPI_mask = uv_send_IPI_mask, 833 .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself, 834 .send_IPI_allbutself = uv_send_IPI_allbutself, 835 .send_IPI_all = uv_send_IPI_all, 836 .send_IPI_self = uv_send_IPI_self, 837 838 .wakeup_secondary_cpu = uv_wakeup_secondary, 839 .inquire_remote_apic = NULL, 840 841 .read = native_apic_msr_read, 842 .write = native_apic_msr_write, 843 .eoi_write = native_apic_msr_eoi_write, 844 .icr_read = native_x2apic_icr_read, 845 .icr_write = native_x2apic_icr_write, 846 .wait_icr_idle = native_x2apic_wait_icr_idle, 847 .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle, 848 }; 849 850 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH 3 851 #define DEST_SHIFT UVXH_RH_GAM_ALIAS_0_REDIRECT_CONFIG_DEST_BASE_SHFT 852 853 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size) 854 { 855 union uvh_rh_gam_alias_2_overlay_config_u alias; 856 union uvh_rh_gam_alias_2_redirect_config_u redirect; 857 unsigned long m_redirect; 858 unsigned long m_overlay; 859 int i; 860 861 for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) { 862 switch (i) { 863 case 0: 864 m_redirect = UVH_RH_GAM_ALIAS_0_REDIRECT_CONFIG; 865 m_overlay = UVH_RH_GAM_ALIAS_0_OVERLAY_CONFIG; 866 break; 867 case 1: 868 m_redirect = UVH_RH_GAM_ALIAS_1_REDIRECT_CONFIG; 869 m_overlay = UVH_RH_GAM_ALIAS_1_OVERLAY_CONFIG; 870 break; 871 case 2: 872 m_redirect = UVH_RH_GAM_ALIAS_2_REDIRECT_CONFIG; 873 m_overlay = UVH_RH_GAM_ALIAS_2_OVERLAY_CONFIG; 874 break; 875 } 876 alias.v = uv_read_local_mmr(m_overlay); 877 if (alias.s.enable && alias.s.base == 0) { 878 *size = (1UL << alias.s.m_alias); 879 redirect.v = uv_read_local_mmr(m_redirect); 880 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT; 881 return; 882 } 883 } 884 *base = *size = 0; 885 } 886 887 enum map_type {map_wb, map_uc}; 888 static const char * const mt[] = { "WB", "UC" }; 889 890 static __init void map_high(char *id, unsigned long base, int pshift, int bshift, int max_pnode, enum map_type map_type) 891 { 892 unsigned long bytes, paddr; 893 894 paddr = base << pshift; 895 bytes = (1UL << bshift) * (max_pnode + 1); 896 if (!paddr) { 897 pr_info("UV: Map %s_HI base address NULL\n", id); 898 return; 899 } 900 if (map_type == map_uc) 901 init_extra_mapping_uc(paddr, bytes); 902 else 903 init_extra_mapping_wb(paddr, bytes); 904 905 pr_info("UV: Map %s_HI 0x%lx - 0x%lx %s (%d segments)\n", 906 id, paddr, paddr + bytes, mt[map_type], max_pnode + 1); 907 } 908 909 static __init void map_gru_high(int max_pnode) 910 { 911 union uvh_rh_gam_gru_overlay_config_u gru; 912 unsigned long mask, base; 913 int shift; 914 915 if (UVH_RH_GAM_GRU_OVERLAY_CONFIG) { 916 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG); 917 shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT; 918 mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_MASK; 919 } else if (UVH_RH10_GAM_GRU_OVERLAY_CONFIG) { 920 gru.v = uv_read_local_mmr(UVH_RH10_GAM_GRU_OVERLAY_CONFIG); 921 shift = UVH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT; 922 mask = UVH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_MASK; 923 } else { 924 pr_err("UV: GRU unavailable (no MMR)\n"); 925 return; 926 } 927 928 if (!gru.s.enable) { 929 pr_info("UV: GRU disabled (by BIOS)\n"); 930 return; 931 } 932 933 base = (gru.v & mask) >> shift; 934 map_high("GRU", base, shift, shift, max_pnode, map_wb); 935 gru_start_paddr = ((u64)base << shift); 936 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1); 937 } 938 939 static __init void map_mmr_high(int max_pnode) 940 { 941 unsigned long base; 942 int shift; 943 bool enable; 944 945 if (UVH_RH10_GAM_MMR_OVERLAY_CONFIG) { 946 union uvh_rh10_gam_mmr_overlay_config_u mmr; 947 948 mmr.v = uv_read_local_mmr(UVH_RH10_GAM_MMR_OVERLAY_CONFIG); 949 enable = mmr.s.enable; 950 base = mmr.s.base; 951 shift = UVH_RH10_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT; 952 } else if (UVH_RH_GAM_MMR_OVERLAY_CONFIG) { 953 union uvh_rh_gam_mmr_overlay_config_u mmr; 954 955 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG); 956 enable = mmr.s.enable; 957 base = mmr.s.base; 958 shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT; 959 } else { 960 pr_err("UV:%s:RH_GAM_MMR_OVERLAY_CONFIG MMR undefined?\n", 961 __func__); 962 return; 963 } 964 965 if (enable) 966 map_high("MMR", base, shift, shift, max_pnode, map_uc); 967 else 968 pr_info("UV: MMR disabled\n"); 969 } 970 971 /* Arch specific ENUM cases */ 972 enum mmioh_arch { 973 UV2_MMIOH = -1, 974 UVY_MMIOH0, UVY_MMIOH1, 975 UVX_MMIOH0, UVX_MMIOH1, 976 }; 977 978 /* Calculate and Map MMIOH Regions */ 979 static void __init calc_mmioh_map(enum mmioh_arch index, 980 int min_pnode, int max_pnode, 981 int shift, unsigned long base, int m_io, int n_io) 982 { 983 unsigned long mmr, nasid_mask; 984 int nasid, min_nasid, max_nasid, lnasid, mapped; 985 int i, fi, li, n, max_io; 986 char id[8]; 987 988 /* One (UV2) mapping */ 989 if (index == UV2_MMIOH) { 990 strncpy(id, "MMIOH", sizeof(id)); 991 max_io = max_pnode; 992 mapped = 0; 993 goto map_exit; 994 } 995 996 /* small and large MMIOH mappings */ 997 switch (index) { 998 case UVY_MMIOH0: 999 mmr = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG0; 1000 nasid_mask = UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK; 1001 n = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG0_DEPTH; 1002 min_nasid = min_pnode; 1003 max_nasid = max_pnode; 1004 mapped = 1; 1005 break; 1006 case UVY_MMIOH1: 1007 mmr = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG1; 1008 nasid_mask = UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK; 1009 n = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG1_DEPTH; 1010 min_nasid = min_pnode; 1011 max_nasid = max_pnode; 1012 mapped = 1; 1013 break; 1014 case UVX_MMIOH0: 1015 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0; 1016 nasid_mask = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK; 1017 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_DEPTH; 1018 min_nasid = min_pnode * 2; 1019 max_nasid = max_pnode * 2; 1020 mapped = 1; 1021 break; 1022 case UVX_MMIOH1: 1023 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1; 1024 nasid_mask = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK; 1025 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_DEPTH; 1026 min_nasid = min_pnode * 2; 1027 max_nasid = max_pnode * 2; 1028 mapped = 1; 1029 break; 1030 default: 1031 pr_err("UV:%s:Invalid mapping type:%d\n", __func__, index); 1032 return; 1033 } 1034 1035 /* enum values chosen so (index mod 2) is MMIOH 0/1 (low/high) */ 1036 snprintf(id, sizeof(id), "MMIOH%d", index%2); 1037 1038 max_io = lnasid = fi = li = -1; 1039 for (i = 0; i < n; i++) { 1040 unsigned long m_redirect = mmr + i * 8; 1041 unsigned long redirect = uv_read_local_mmr(m_redirect); 1042 1043 nasid = redirect & nasid_mask; 1044 if (i == 0) 1045 pr_info("UV: %s redirect base 0x%lx(@0x%lx) 0x%04x\n", 1046 id, redirect, m_redirect, nasid); 1047 1048 /* Invalid NASID check */ 1049 if (nasid < min_nasid || max_nasid < nasid) { 1050 pr_err("UV:%s:Invalid NASID:%x (range:%x..%x)\n", 1051 __func__, index, min_nasid, max_nasid); 1052 nasid = -1; 1053 } 1054 1055 if (nasid == lnasid) { 1056 li = i; 1057 /* Last entry check: */ 1058 if (i != n-1) 1059 continue; 1060 } 1061 1062 /* Check if we have a cached (or last) redirect to print: */ 1063 if (lnasid != -1 || (i == n-1 && nasid != -1)) { 1064 unsigned long addr1, addr2; 1065 int f, l; 1066 1067 if (lnasid == -1) { 1068 f = l = i; 1069 lnasid = nasid; 1070 } else { 1071 f = fi; 1072 l = li; 1073 } 1074 addr1 = (base << shift) + f * (1ULL << m_io); 1075 addr2 = (base << shift) + (l + 1) * (1ULL << m_io); 1076 pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n", 1077 id, fi, li, lnasid, addr1, addr2); 1078 if (max_io < l) 1079 max_io = l; 1080 } 1081 fi = li = i; 1082 lnasid = nasid; 1083 } 1084 1085 map_exit: 1086 pr_info("UV: %s base:0x%lx shift:%d m_io:%d max_io:%d max_pnode:0x%x\n", 1087 id, base, shift, m_io, max_io, max_pnode); 1088 1089 if (max_io >= 0 && !mapped) 1090 map_high(id, base, shift, m_io, max_io, map_uc); 1091 } 1092 1093 static __init void map_mmioh_high(int min_pnode, int max_pnode) 1094 { 1095 /* UVY flavor */ 1096 if (UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0) { 1097 union uvh_rh10_gam_mmioh_overlay_config0_u mmioh0; 1098 union uvh_rh10_gam_mmioh_overlay_config1_u mmioh1; 1099 1100 mmioh0.v = uv_read_local_mmr(UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0); 1101 if (unlikely(mmioh0.s.enable == 0)) 1102 pr_info("UV: MMIOH0 disabled\n"); 1103 else 1104 calc_mmioh_map(UVY_MMIOH0, min_pnode, max_pnode, 1105 UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT, 1106 mmioh0.s.base, mmioh0.s.m_io, mmioh0.s.n_io); 1107 1108 mmioh1.v = uv_read_local_mmr(UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1); 1109 if (unlikely(mmioh1.s.enable == 0)) 1110 pr_info("UV: MMIOH1 disabled\n"); 1111 else 1112 calc_mmioh_map(UVY_MMIOH1, min_pnode, max_pnode, 1113 UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT, 1114 mmioh1.s.base, mmioh1.s.m_io, mmioh1.s.n_io); 1115 return; 1116 } 1117 /* UVX flavor */ 1118 if (UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0) { 1119 union uvh_rh_gam_mmioh_overlay_config0_u mmioh0; 1120 union uvh_rh_gam_mmioh_overlay_config1_u mmioh1; 1121 1122 mmioh0.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0); 1123 if (unlikely(mmioh0.s.enable == 0)) 1124 pr_info("UV: MMIOH0 disabled\n"); 1125 else { 1126 unsigned long base = uvxy_field(mmioh0, base, 0); 1127 int m_io = uvxy_field(mmioh0, m_io, 0); 1128 int n_io = uvxy_field(mmioh0, n_io, 0); 1129 1130 calc_mmioh_map(UVX_MMIOH0, min_pnode, max_pnode, 1131 UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT, 1132 base, m_io, n_io); 1133 } 1134 1135 mmioh1.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1); 1136 if (unlikely(mmioh1.s.enable == 0)) 1137 pr_info("UV: MMIOH1 disabled\n"); 1138 else { 1139 unsigned long base = uvxy_field(mmioh1, base, 0); 1140 int m_io = uvxy_field(mmioh1, m_io, 0); 1141 int n_io = uvxy_field(mmioh1, n_io, 0); 1142 1143 calc_mmioh_map(UVX_MMIOH1, min_pnode, max_pnode, 1144 UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT, 1145 base, m_io, n_io); 1146 } 1147 return; 1148 } 1149 1150 /* UV2 flavor */ 1151 if (UVH_RH_GAM_MMIOH_OVERLAY_CONFIG) { 1152 union uvh_rh_gam_mmioh_overlay_config_u mmioh; 1153 1154 mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG); 1155 if (unlikely(mmioh.s2.enable == 0)) 1156 pr_info("UV: MMIOH disabled\n"); 1157 else 1158 calc_mmioh_map(UV2_MMIOH, min_pnode, max_pnode, 1159 UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_BASE_SHFT, 1160 mmioh.s2.base, mmioh.s2.m_io, mmioh.s2.n_io); 1161 return; 1162 } 1163 } 1164 1165 static __init void map_low_mmrs(void) 1166 { 1167 if (UV_GLOBAL_MMR32_BASE) 1168 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE); 1169 1170 if (UV_LOCAL_MMR_BASE) 1171 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE); 1172 } 1173 1174 static __init void uv_rtc_init(void) 1175 { 1176 long status; 1177 u64 ticks_per_sec; 1178 1179 status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec); 1180 1181 if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) { 1182 pr_warn("UV: unable to determine platform RTC clock frequency, guessing.\n"); 1183 1184 /* BIOS gives wrong value for clock frequency, so guess: */ 1185 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL; 1186 } else { 1187 sn_rtc_cycles_per_second = ticks_per_sec; 1188 } 1189 } 1190 1191 /* Direct Legacy VGA I/O traffic to designated IOH */ 1192 static int uv_set_vga_state(struct pci_dev *pdev, bool decode, unsigned int command_bits, u32 flags) 1193 { 1194 int domain, bus, rc; 1195 1196 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) 1197 return 0; 1198 1199 if ((command_bits & PCI_COMMAND_IO) == 0) 1200 return 0; 1201 1202 domain = pci_domain_nr(pdev->bus); 1203 bus = pdev->bus->number; 1204 1205 rc = uv_bios_set_legacy_vga_target(decode, domain, bus); 1206 1207 return rc; 1208 } 1209 1210 /* 1211 * Called on each CPU to initialize the per_cpu UV data area. 1212 * FIXME: hotplug not supported yet 1213 */ 1214 void uv_cpu_init(void) 1215 { 1216 /* CPU 0 initialization will be done via uv_system_init. */ 1217 if (smp_processor_id() == 0) 1218 return; 1219 1220 uv_hub_info->nr_online_cpus++; 1221 } 1222 1223 struct mn { 1224 unsigned char m_val; 1225 unsigned char n_val; 1226 unsigned char m_shift; 1227 unsigned char n_lshift; 1228 }; 1229 1230 /* Initialize caller's MN struct and fill in values */ 1231 static void get_mn(struct mn *mnp) 1232 { 1233 memset(mnp, 0, sizeof(*mnp)); 1234 mnp->n_val = uv_cpuid.n_skt; 1235 if (is_uv(UV4|UVY)) { 1236 mnp->m_val = 0; 1237 mnp->n_lshift = 0; 1238 } else if (is_uv3_hub()) { 1239 union uvyh_gr0_gam_gr_config_u m_gr_config; 1240 1241 mnp->m_val = uv_cpuid.m_skt; 1242 m_gr_config.v = uv_read_local_mmr(UVH_GR0_GAM_GR_CONFIG); 1243 mnp->n_lshift = m_gr_config.s3.m_skt; 1244 } else if (is_uv2_hub()) { 1245 mnp->m_val = uv_cpuid.m_skt; 1246 mnp->n_lshift = mnp->m_val == 40 ? 40 : 39; 1247 } 1248 mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0; 1249 } 1250 1251 static void __init uv_init_hub_info(struct uv_hub_info_s *hi) 1252 { 1253 struct mn mn; 1254 1255 get_mn(&mn); 1256 hi->gpa_mask = mn.m_val ? 1257 (1UL << (mn.m_val + mn.n_val)) - 1 : 1258 (1UL << uv_cpuid.gpa_shift) - 1; 1259 1260 hi->m_val = mn.m_val; 1261 hi->n_val = mn.n_val; 1262 hi->m_shift = mn.m_shift; 1263 hi->n_lshift = mn.n_lshift ? mn.n_lshift : 0; 1264 hi->hub_revision = uv_hub_info->hub_revision; 1265 hi->hub_type = uv_hub_info->hub_type; 1266 hi->pnode_mask = uv_cpuid.pnode_mask; 1267 hi->nasid_shift = uv_cpuid.nasid_shift; 1268 hi->min_pnode = _min_pnode; 1269 hi->min_socket = _min_socket; 1270 hi->pnode_to_socket = _pnode_to_socket; 1271 hi->socket_to_node = _socket_to_node; 1272 hi->socket_to_pnode = _socket_to_pnode; 1273 hi->gr_table_len = _gr_table_len; 1274 hi->gr_table = _gr_table; 1275 1276 uv_cpuid.gnode_shift = max_t(unsigned int, uv_cpuid.gnode_shift, mn.n_val); 1277 hi->gnode_extra = (uv_node_id & ~((1 << uv_cpuid.gnode_shift) - 1)) >> 1; 1278 if (mn.m_val) 1279 hi->gnode_upper = (u64)hi->gnode_extra << mn.m_val; 1280 1281 if (uv_gp_table) { 1282 hi->global_mmr_base = uv_gp_table->mmr_base; 1283 hi->global_mmr_shift = uv_gp_table->mmr_shift; 1284 hi->global_gru_base = uv_gp_table->gru_base; 1285 hi->global_gru_shift = uv_gp_table->gru_shift; 1286 hi->gpa_shift = uv_gp_table->gpa_shift; 1287 hi->gpa_mask = (1UL << hi->gpa_shift) - 1; 1288 } else { 1289 hi->global_mmr_base = 1290 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG) & 1291 ~UV_MMR_ENABLE; 1292 hi->global_mmr_shift = _UV_GLOBAL_MMR64_PNODE_SHIFT; 1293 } 1294 1295 get_lowmem_redirect(&hi->lowmem_remap_base, &hi->lowmem_remap_top); 1296 1297 hi->apic_pnode_shift = uv_cpuid.socketid_shift; 1298 1299 /* Show system specific info: */ 1300 pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n", hi->n_val, hi->m_val, hi->m_shift, hi->n_lshift); 1301 pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n", hi->gpa_mask, hi->gpa_shift, hi->pnode_mask, hi->apic_pnode_shift); 1302 pr_info("UV: mmr_base/shift:0x%lx/%ld\n", hi->global_mmr_base, hi->global_mmr_shift); 1303 if (hi->global_gru_base) 1304 pr_info("UV: gru_base/shift:0x%lx/%ld\n", 1305 hi->global_gru_base, hi->global_gru_shift); 1306 1307 pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n", hi->gnode_upper, hi->gnode_extra); 1308 } 1309 1310 static void __init decode_gam_params(unsigned long ptr) 1311 { 1312 uv_gp_table = (struct uv_gam_parameters *)ptr; 1313 1314 pr_info("UV: GAM Params...\n"); 1315 pr_info("UV: mmr_base/shift:0x%llx/%d gru_base/shift:0x%llx/%d gpa_shift:%d\n", 1316 uv_gp_table->mmr_base, uv_gp_table->mmr_shift, 1317 uv_gp_table->gru_base, uv_gp_table->gru_shift, 1318 uv_gp_table->gpa_shift); 1319 } 1320 1321 static void __init decode_gam_rng_tbl(unsigned long ptr) 1322 { 1323 struct uv_gam_range_entry *gre = (struct uv_gam_range_entry *)ptr; 1324 unsigned long lgre = 0; 1325 int index = 0; 1326 int sock_min = 999999, pnode_min = 99999; 1327 int sock_max = -1, pnode_max = -1; 1328 1329 uv_gre_table = gre; 1330 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) { 1331 unsigned long size = ((unsigned long)(gre->limit - lgre) 1332 << UV_GAM_RANGE_SHFT); 1333 int order = 0; 1334 char suffix[] = " KMGTPE"; 1335 int flag = ' '; 1336 1337 while (size > 9999 && order < sizeof(suffix)) { 1338 size /= 1024; 1339 order++; 1340 } 1341 1342 /* adjust max block size to current range start */ 1343 if (gre->type == 1 || gre->type == 2) 1344 if (adj_blksize(lgre)) 1345 flag = '*'; 1346 1347 if (!index) { 1348 pr_info("UV: GAM Range Table...\n"); 1349 pr_info("UV: # %20s %14s %6s %4s %5s %3s %2s\n", "Range", "", "Size", "Type", "NASID", "SID", "PN"); 1350 } 1351 pr_info("UV: %2d: 0x%014lx-0x%014lx%c %5lu%c %3d %04x %02x %02x\n", 1352 index++, 1353 (unsigned long)lgre << UV_GAM_RANGE_SHFT, 1354 (unsigned long)gre->limit << UV_GAM_RANGE_SHFT, 1355 flag, size, suffix[order], 1356 gre->type, gre->nasid, gre->sockid, gre->pnode); 1357 1358 /* update to next range start */ 1359 lgre = gre->limit; 1360 if (sock_min > gre->sockid) 1361 sock_min = gre->sockid; 1362 if (sock_max < gre->sockid) 1363 sock_max = gre->sockid; 1364 if (pnode_min > gre->pnode) 1365 pnode_min = gre->pnode; 1366 if (pnode_max < gre->pnode) 1367 pnode_max = gre->pnode; 1368 } 1369 _min_socket = sock_min; 1370 _max_socket = sock_max; 1371 _min_pnode = pnode_min; 1372 _max_pnode = pnode_max; 1373 _gr_table_len = index; 1374 1375 pr_info("UV: GRT: %d entries, sockets(min:%x,max:%x) pnodes(min:%x,max:%x)\n", index, _min_socket, _max_socket, _min_pnode, _max_pnode); 1376 } 1377 1378 /* Walk through UVsystab decoding the fields */ 1379 static int __init decode_uv_systab(void) 1380 { 1381 struct uv_systab *st; 1382 int i; 1383 1384 /* Get mapped UVsystab pointer */ 1385 st = uv_systab; 1386 1387 /* If UVsystab is version 1, there is no extended UVsystab */ 1388 if (st && st->revision == UV_SYSTAB_VERSION_1) 1389 return 0; 1390 1391 if ((!st) || (st->revision < UV_SYSTAB_VERSION_UV4_LATEST)) { 1392 int rev = st ? st->revision : 0; 1393 1394 pr_err("UV: BIOS UVsystab mismatch, (%x < %x)\n", 1395 rev, UV_SYSTAB_VERSION_UV4_LATEST); 1396 pr_err("UV: Does not support UV, switch to non-UV x86_64\n"); 1397 uv_system_type = UV_NONE; 1398 1399 return -EINVAL; 1400 } 1401 1402 for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) { 1403 unsigned long ptr = st->entry[i].offset; 1404 1405 if (!ptr) 1406 continue; 1407 1408 /* point to payload */ 1409 ptr += (unsigned long)st; 1410 1411 switch (st->entry[i].type) { 1412 case UV_SYSTAB_TYPE_GAM_PARAMS: 1413 decode_gam_params(ptr); 1414 break; 1415 1416 case UV_SYSTAB_TYPE_GAM_RNG_TBL: 1417 decode_gam_rng_tbl(ptr); 1418 break; 1419 1420 case UV_SYSTAB_TYPE_ARCH_TYPE: 1421 /* already processed in early startup */ 1422 break; 1423 1424 default: 1425 pr_err("UV:%s:Unrecognized UV_SYSTAB_TYPE:%d, skipped\n", 1426 __func__, st->entry[i].type); 1427 break; 1428 } 1429 } 1430 return 0; 1431 } 1432 1433 /* Set up physical blade translations from UVH_NODE_PRESENT_TABLE */ 1434 static __init void boot_init_possible_blades(struct uv_hub_info_s *hub_info) 1435 { 1436 unsigned long np; 1437 int i, uv_pb = 0; 1438 1439 if (UVH_NODE_PRESENT_TABLE) { 1440 pr_info("UV: NODE_PRESENT_DEPTH = %d\n", 1441 UVH_NODE_PRESENT_TABLE_DEPTH); 1442 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) { 1443 np = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8); 1444 pr_info("UV: NODE_PRESENT(%d) = 0x%016lx\n", i, np); 1445 uv_pb += hweight64(np); 1446 } 1447 } 1448 if (UVH_NODE_PRESENT_0) { 1449 np = uv_read_local_mmr(UVH_NODE_PRESENT_0); 1450 pr_info("UV: NODE_PRESENT_0 = 0x%016lx\n", np); 1451 uv_pb += hweight64(np); 1452 } 1453 if (UVH_NODE_PRESENT_1) { 1454 np = uv_read_local_mmr(UVH_NODE_PRESENT_1); 1455 pr_info("UV: NODE_PRESENT_1 = 0x%016lx\n", np); 1456 uv_pb += hweight64(np); 1457 } 1458 if (uv_possible_blades != uv_pb) 1459 uv_possible_blades = uv_pb; 1460 1461 pr_info("UV: number nodes/possible blades %d\n", uv_pb); 1462 } 1463 1464 static void __init build_socket_tables(void) 1465 { 1466 struct uv_gam_range_entry *gre = uv_gre_table; 1467 int num, nump; 1468 int cpu, i, lnid; 1469 int minsock = _min_socket; 1470 int maxsock = _max_socket; 1471 int minpnode = _min_pnode; 1472 int maxpnode = _max_pnode; 1473 size_t bytes; 1474 1475 if (!gre) { 1476 if (is_uv2_hub() || is_uv3_hub()) { 1477 pr_info("UV: No UVsystab socket table, ignoring\n"); 1478 return; 1479 } 1480 pr_err("UV: Error: UVsystab address translations not available!\n"); 1481 BUG(); 1482 } 1483 1484 /* Build socket id -> node id, pnode */ 1485 num = maxsock - minsock + 1; 1486 bytes = num * sizeof(_socket_to_node[0]); 1487 _socket_to_node = kmalloc(bytes, GFP_KERNEL); 1488 _socket_to_pnode = kmalloc(bytes, GFP_KERNEL); 1489 1490 nump = maxpnode - minpnode + 1; 1491 bytes = nump * sizeof(_pnode_to_socket[0]); 1492 _pnode_to_socket = kmalloc(bytes, GFP_KERNEL); 1493 BUG_ON(!_socket_to_node || !_socket_to_pnode || !_pnode_to_socket); 1494 1495 for (i = 0; i < num; i++) 1496 _socket_to_node[i] = _socket_to_pnode[i] = SOCK_EMPTY; 1497 1498 for (i = 0; i < nump; i++) 1499 _pnode_to_socket[i] = SOCK_EMPTY; 1500 1501 /* Fill in pnode/node/addr conversion list values: */ 1502 pr_info("UV: GAM Building socket/pnode conversion tables\n"); 1503 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) { 1504 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) 1505 continue; 1506 i = gre->sockid - minsock; 1507 /* Duplicate: */ 1508 if (_socket_to_pnode[i] != SOCK_EMPTY) 1509 continue; 1510 _socket_to_pnode[i] = gre->pnode; 1511 1512 i = gre->pnode - minpnode; 1513 _pnode_to_socket[i] = gre->sockid; 1514 1515 pr_info("UV: sid:%02x type:%d nasid:%04x pn:%02x pn2s:%2x\n", 1516 gre->sockid, gre->type, gre->nasid, 1517 _socket_to_pnode[gre->sockid - minsock], 1518 _pnode_to_socket[gre->pnode - minpnode]); 1519 } 1520 1521 /* Set socket -> node values: */ 1522 lnid = NUMA_NO_NODE; 1523 for_each_present_cpu(cpu) { 1524 int nid = cpu_to_node(cpu); 1525 int apicid, sockid; 1526 1527 if (lnid == nid) 1528 continue; 1529 lnid = nid; 1530 apicid = per_cpu(x86_cpu_to_apicid, cpu); 1531 sockid = apicid >> uv_cpuid.socketid_shift; 1532 _socket_to_node[sockid - minsock] = nid; 1533 pr_info("UV: sid:%02x: apicid:%04x node:%2d\n", 1534 sockid, apicid, nid); 1535 } 1536 1537 /* Set up physical blade to pnode translation from GAM Range Table: */ 1538 bytes = num_possible_nodes() * sizeof(_node_to_pnode[0]); 1539 _node_to_pnode = kmalloc(bytes, GFP_KERNEL); 1540 BUG_ON(!_node_to_pnode); 1541 1542 for (lnid = 0; lnid < num_possible_nodes(); lnid++) { 1543 unsigned short sockid; 1544 1545 for (sockid = minsock; sockid <= maxsock; sockid++) { 1546 if (lnid == _socket_to_node[sockid - minsock]) { 1547 _node_to_pnode[lnid] = _socket_to_pnode[sockid - minsock]; 1548 break; 1549 } 1550 } 1551 if (sockid > maxsock) { 1552 pr_err("UV: socket for node %d not found!\n", lnid); 1553 BUG(); 1554 } 1555 } 1556 1557 /* 1558 * If socket id == pnode or socket id == node for all nodes, 1559 * system runs faster by removing corresponding conversion table. 1560 */ 1561 pr_info("UV: Checking socket->node/pnode for identity maps\n"); 1562 if (minsock == 0) { 1563 for (i = 0; i < num; i++) 1564 if (_socket_to_node[i] == SOCK_EMPTY || i != _socket_to_node[i]) 1565 break; 1566 if (i >= num) { 1567 kfree(_socket_to_node); 1568 _socket_to_node = NULL; 1569 pr_info("UV: 1:1 socket_to_node table removed\n"); 1570 } 1571 } 1572 if (minsock == minpnode) { 1573 for (i = 0; i < num; i++) 1574 if (_socket_to_pnode[i] != SOCK_EMPTY && 1575 _socket_to_pnode[i] != i + minpnode) 1576 break; 1577 if (i >= num) { 1578 kfree(_socket_to_pnode); 1579 _socket_to_pnode = NULL; 1580 pr_info("UV: 1:1 socket_to_pnode table removed\n"); 1581 } 1582 } 1583 } 1584 1585 /* Check which reboot to use */ 1586 static void check_efi_reboot(void) 1587 { 1588 /* If EFI reboot not available, use ACPI reboot */ 1589 if (!efi_enabled(EFI_BOOT)) 1590 reboot_type = BOOT_ACPI; 1591 } 1592 1593 /* Setup user proc fs files */ 1594 static int __maybe_unused proc_hubbed_show(struct seq_file *file, void *data) 1595 { 1596 seq_printf(file, "0x%x\n", uv_hubbed_system); 1597 return 0; 1598 } 1599 1600 static int __maybe_unused proc_hubless_show(struct seq_file *file, void *data) 1601 { 1602 seq_printf(file, "0x%x\n", uv_hubless_system); 1603 return 0; 1604 } 1605 1606 static int __maybe_unused proc_archtype_show(struct seq_file *file, void *data) 1607 { 1608 seq_printf(file, "%s/%s\n", uv_archtype, oem_table_id); 1609 return 0; 1610 } 1611 1612 static __init void uv_setup_proc_files(int hubless) 1613 { 1614 struct proc_dir_entry *pde; 1615 1616 pde = proc_mkdir(UV_PROC_NODE, NULL); 1617 proc_create_single("archtype", 0, pde, proc_archtype_show); 1618 if (hubless) 1619 proc_create_single("hubless", 0, pde, proc_hubless_show); 1620 else 1621 proc_create_single("hubbed", 0, pde, proc_hubbed_show); 1622 } 1623 1624 /* Initialize UV hubless systems */ 1625 static __init int uv_system_init_hubless(void) 1626 { 1627 int rc; 1628 1629 /* Setup PCH NMI handler */ 1630 uv_nmi_setup_hubless(); 1631 1632 /* Init kernel/BIOS interface */ 1633 rc = uv_bios_init(); 1634 if (rc < 0) 1635 return rc; 1636 1637 /* Process UVsystab */ 1638 rc = decode_uv_systab(); 1639 if (rc < 0) 1640 return rc; 1641 1642 /* Create user access node */ 1643 if (rc >= 0) 1644 uv_setup_proc_files(1); 1645 1646 check_efi_reboot(); 1647 1648 return rc; 1649 } 1650 1651 static void __init uv_system_init_hub(void) 1652 { 1653 struct uv_hub_info_s hub_info = {0}; 1654 int bytes, cpu, nodeid; 1655 unsigned short min_pnode = 9999, max_pnode = 0; 1656 char *hub = is_uv5_hub() ? "UV500" : 1657 is_uv4_hub() ? "UV400" : 1658 is_uv3_hub() ? "UV300" : 1659 is_uv2_hub() ? "UV2000/3000" : NULL; 1660 1661 if (!hub) { 1662 pr_err("UV: Unknown/unsupported UV hub\n"); 1663 return; 1664 } 1665 pr_info("UV: Found %s hub\n", hub); 1666 1667 map_low_mmrs(); 1668 1669 /* Get uv_systab for decoding, setup UV BIOS calls */ 1670 uv_bios_init(); 1671 1672 /* If there's an UVsystab problem then abort UV init: */ 1673 if (decode_uv_systab() < 0) { 1674 pr_err("UV: Mangled UVsystab format\n"); 1675 return; 1676 } 1677 1678 build_socket_tables(); 1679 build_uv_gr_table(); 1680 set_block_size(); 1681 uv_init_hub_info(&hub_info); 1682 uv_possible_blades = num_possible_nodes(); 1683 if (!_node_to_pnode) 1684 boot_init_possible_blades(&hub_info); 1685 1686 /* uv_num_possible_blades() is really the hub count: */ 1687 pr_info("UV: Found %d hubs, %d nodes, %d CPUs\n", uv_num_possible_blades(), num_possible_nodes(), num_possible_cpus()); 1688 1689 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, &sn_region_size, &system_serial_number); 1690 hub_info.coherency_domain_number = sn_coherency_id; 1691 uv_rtc_init(); 1692 1693 bytes = sizeof(void *) * uv_num_possible_blades(); 1694 __uv_hub_info_list = kzalloc(bytes, GFP_KERNEL); 1695 BUG_ON(!__uv_hub_info_list); 1696 1697 bytes = sizeof(struct uv_hub_info_s); 1698 for_each_node(nodeid) { 1699 struct uv_hub_info_s *new_hub; 1700 1701 if (__uv_hub_info_list[nodeid]) { 1702 pr_err("UV: Node %d UV HUB already initialized!?\n", nodeid); 1703 BUG(); 1704 } 1705 1706 /* Allocate new per hub info list */ 1707 new_hub = (nodeid == 0) ? &uv_hub_info_node0 : kzalloc_node(bytes, GFP_KERNEL, nodeid); 1708 BUG_ON(!new_hub); 1709 __uv_hub_info_list[nodeid] = new_hub; 1710 new_hub = uv_hub_info_list(nodeid); 1711 BUG_ON(!new_hub); 1712 *new_hub = hub_info; 1713 1714 /* Use information from GAM table if available: */ 1715 if (_node_to_pnode) 1716 new_hub->pnode = _node_to_pnode[nodeid]; 1717 else /* Or fill in during CPU loop: */ 1718 new_hub->pnode = 0xffff; 1719 1720 new_hub->numa_blade_id = uv_node_to_blade_id(nodeid); 1721 new_hub->memory_nid = NUMA_NO_NODE; 1722 new_hub->nr_possible_cpus = 0; 1723 new_hub->nr_online_cpus = 0; 1724 } 1725 1726 /* Initialize per CPU info: */ 1727 for_each_possible_cpu(cpu) { 1728 int apicid = per_cpu(x86_cpu_to_apicid, cpu); 1729 int numa_node_id; 1730 unsigned short pnode; 1731 1732 nodeid = cpu_to_node(cpu); 1733 numa_node_id = numa_cpu_node(cpu); 1734 pnode = uv_apicid_to_pnode(apicid); 1735 1736 uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list(nodeid); 1737 uv_cpu_info_per(cpu)->blade_cpu_id = uv_cpu_hub_info(cpu)->nr_possible_cpus++; 1738 if (uv_cpu_hub_info(cpu)->memory_nid == NUMA_NO_NODE) 1739 uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu); 1740 1741 /* Init memoryless node: */ 1742 if (nodeid != numa_node_id && 1743 uv_hub_info_list(numa_node_id)->pnode == 0xffff) 1744 uv_hub_info_list(numa_node_id)->pnode = pnode; 1745 else if (uv_cpu_hub_info(cpu)->pnode == 0xffff) 1746 uv_cpu_hub_info(cpu)->pnode = pnode; 1747 } 1748 1749 for_each_node(nodeid) { 1750 unsigned short pnode = uv_hub_info_list(nodeid)->pnode; 1751 1752 /* Add pnode info for pre-GAM list nodes without CPUs: */ 1753 if (pnode == 0xffff) { 1754 unsigned long paddr; 1755 1756 paddr = node_start_pfn(nodeid) << PAGE_SHIFT; 1757 pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr)); 1758 uv_hub_info_list(nodeid)->pnode = pnode; 1759 } 1760 min_pnode = min(pnode, min_pnode); 1761 max_pnode = max(pnode, max_pnode); 1762 pr_info("UV: UVHUB node:%2d pn:%02x nrcpus:%d\n", 1763 nodeid, 1764 uv_hub_info_list(nodeid)->pnode, 1765 uv_hub_info_list(nodeid)->nr_possible_cpus); 1766 } 1767 1768 pr_info("UV: min_pnode:%02x max_pnode:%02x\n", min_pnode, max_pnode); 1769 map_gru_high(max_pnode); 1770 map_mmr_high(max_pnode); 1771 map_mmioh_high(min_pnode, max_pnode); 1772 1773 uv_nmi_setup(); 1774 uv_cpu_init(); 1775 uv_setup_proc_files(0); 1776 1777 /* Register Legacy VGA I/O redirection handler: */ 1778 pci_register_set_vga_state(uv_set_vga_state); 1779 1780 check_efi_reboot(); 1781 } 1782 1783 /* 1784 * There is a different code path needed to initialize a UV system that does 1785 * not have a "UV HUB" (referred to as "hubless"). 1786 */ 1787 void __init uv_system_init(void) 1788 { 1789 if (likely(!is_uv_system() && !is_uv_hubless(1))) 1790 return; 1791 1792 if (is_uv_system()) 1793 uv_system_init_hub(); 1794 else 1795 uv_system_init_hubless(); 1796 } 1797 1798 apic_driver(apic_x2apic_uv_x); 1799