1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * SGI UV APIC functions (note: not an Intel compatible APIC) 7 * 8 * (C) Copyright 2020 Hewlett Packard Enterprise Development LP 9 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved. 10 */ 11 #include <linux/crash_dump.h> 12 #include <linux/cpuhotplug.h> 13 #include <linux/cpumask.h> 14 #include <linux/proc_fs.h> 15 #include <linux/memory.h> 16 #include <linux/export.h> 17 #include <linux/pci.h> 18 #include <linux/acpi.h> 19 #include <linux/efi.h> 20 21 #include <asm/e820/api.h> 22 #include <asm/uv/uv_mmrs.h> 23 #include <asm/uv/uv_hub.h> 24 #include <asm/uv/bios.h> 25 #include <asm/uv/uv.h> 26 #include <asm/apic.h> 27 28 static enum uv_system_type uv_system_type; 29 static int uv_hubbed_system; 30 static int uv_hubless_system; 31 static u64 gru_start_paddr, gru_end_paddr; 32 static union uvh_apicid uvh_apicid; 33 static int uv_node_id; 34 35 /* Unpack AT/OEM/TABLE ID's to be NULL terminated strings */ 36 static u8 uv_archtype[UV_AT_SIZE + 1]; 37 static u8 oem_id[ACPI_OEM_ID_SIZE + 1]; 38 static u8 oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1]; 39 40 /* Information derived from CPUID and some UV MMRs */ 41 static struct { 42 unsigned int apicid_shift; 43 unsigned int apicid_mask; 44 unsigned int socketid_shift; /* aka pnode_shift for UV2/3 */ 45 unsigned int pnode_mask; 46 unsigned int nasid_shift; 47 unsigned int gpa_shift; 48 unsigned int gnode_shift; 49 unsigned int m_skt; 50 unsigned int n_skt; 51 } uv_cpuid; 52 53 static int uv_min_hub_revision_id; 54 55 static struct apic apic_x2apic_uv_x; 56 static struct uv_hub_info_s uv_hub_info_node0; 57 58 /* Set this to use hardware error handler instead of kernel panic: */ 59 static int disable_uv_undefined_panic = 1; 60 61 unsigned long uv_undefined(char *str) 62 { 63 if (likely(!disable_uv_undefined_panic)) 64 panic("UV: error: undefined MMR: %s\n", str); 65 else 66 pr_crit("UV: error: undefined MMR: %s\n", str); 67 68 /* Cause a machine fault: */ 69 return ~0ul; 70 } 71 EXPORT_SYMBOL(uv_undefined); 72 73 static unsigned long __init uv_early_read_mmr(unsigned long addr) 74 { 75 unsigned long val, *mmr; 76 77 mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr)); 78 val = *mmr; 79 early_iounmap(mmr, sizeof(*mmr)); 80 81 return val; 82 } 83 84 static inline bool is_GRU_range(u64 start, u64 end) 85 { 86 if (!gru_start_paddr) 87 return false; 88 89 return start >= gru_start_paddr && end <= gru_end_paddr; 90 } 91 92 static bool uv_is_untracked_pat_range(u64 start, u64 end) 93 { 94 return is_ISA_range(start, end) || is_GRU_range(start, end); 95 } 96 97 static void __init early_get_pnodeid(void) 98 { 99 int pnode; 100 101 uv_cpuid.m_skt = 0; 102 if (UVH_RH10_GAM_ADDR_MAP_CONFIG) { 103 union uvh_rh10_gam_addr_map_config_u m_n_config; 104 105 m_n_config.v = uv_early_read_mmr(UVH_RH10_GAM_ADDR_MAP_CONFIG); 106 uv_cpuid.n_skt = m_n_config.s.n_skt; 107 uv_cpuid.nasid_shift = 0; 108 } else if (UVH_RH_GAM_ADDR_MAP_CONFIG) { 109 union uvh_rh_gam_addr_map_config_u m_n_config; 110 111 m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_ADDR_MAP_CONFIG); 112 uv_cpuid.n_skt = m_n_config.s.n_skt; 113 if (is_uv(UV3)) 114 uv_cpuid.m_skt = m_n_config.s3.m_skt; 115 if (is_uv(UV2)) 116 uv_cpuid.m_skt = m_n_config.s2.m_skt; 117 uv_cpuid.nasid_shift = 1; 118 } else { 119 unsigned long GAM_ADDR_MAP_CONFIG = 0; 120 121 WARN(GAM_ADDR_MAP_CONFIG == 0, 122 "UV: WARN: GAM_ADDR_MAP_CONFIG is not available\n"); 123 uv_cpuid.n_skt = 0; 124 uv_cpuid.nasid_shift = 0; 125 } 126 127 if (is_uv(UV4|UVY)) 128 uv_cpuid.gnode_shift = 2; /* min partition is 4 sockets */ 129 130 uv_cpuid.pnode_mask = (1 << uv_cpuid.n_skt) - 1; 131 pnode = (uv_node_id >> uv_cpuid.nasid_shift) & uv_cpuid.pnode_mask; 132 uv_cpuid.gpa_shift = 46; /* Default unless changed */ 133 134 pr_info("UV: n_skt:%d pnmsk:%x pn:%x\n", 135 uv_cpuid.n_skt, uv_cpuid.pnode_mask, pnode); 136 } 137 138 /* Running on a UV Hubbed system, determine which UV Hub Type it is */ 139 static int __init early_set_hub_type(void) 140 { 141 union uvh_node_id_u node_id; 142 143 /* 144 * The NODE_ID MMR is always at offset 0. 145 * Contains the chip part # + revision. 146 * Node_id field started with 15 bits, 147 * ... now 7 but upper 8 are masked to 0. 148 * All blades/nodes have the same part # and hub revision. 149 */ 150 node_id.v = uv_early_read_mmr(UVH_NODE_ID); 151 uv_node_id = node_id.sx.node_id; 152 153 switch (node_id.s.part_number) { 154 155 case UV5_HUB_PART_NUMBER: 156 uv_min_hub_revision_id = node_id.s.revision 157 + UV5_HUB_REVISION_BASE; 158 uv_hub_type_set(UV5); 159 break; 160 161 /* UV4/4A only have a revision difference */ 162 case UV4_HUB_PART_NUMBER: 163 uv_min_hub_revision_id = node_id.s.revision 164 + UV4_HUB_REVISION_BASE - 1; 165 uv_hub_type_set(UV4); 166 if (uv_min_hub_revision_id == UV4A_HUB_REVISION_BASE) 167 uv_hub_type_set(UV4|UV4A); 168 break; 169 170 case UV3_HUB_PART_NUMBER: 171 case UV3_HUB_PART_NUMBER_X: 172 uv_min_hub_revision_id = node_id.s.revision 173 + UV3_HUB_REVISION_BASE; 174 uv_hub_type_set(UV3); 175 break; 176 177 case UV2_HUB_PART_NUMBER: 178 case UV2_HUB_PART_NUMBER_X: 179 uv_min_hub_revision_id = node_id.s.revision 180 + UV2_HUB_REVISION_BASE - 1; 181 uv_hub_type_set(UV2); 182 break; 183 184 default: 185 return 0; 186 } 187 188 pr_info("UV: part#:%x rev:%d rev_id:%d UVtype:0x%x\n", 189 node_id.s.part_number, node_id.s.revision, 190 uv_min_hub_revision_id, is_uv(~0)); 191 192 return 1; 193 } 194 195 static void __init uv_tsc_check_sync(void) 196 { 197 u64 mmr; 198 int sync_state; 199 int mmr_shift; 200 char *state; 201 202 /* UV5 guarantees synced TSCs; do not zero TSC_ADJUST */ 203 if (!is_uv(UV2|UV3|UV4)) { 204 mark_tsc_async_resets("UV5+"); 205 return; 206 } 207 208 /* UV2,3,4, UV BIOS TSC sync state available */ 209 mmr = uv_early_read_mmr(UVH_TSC_SYNC_MMR); 210 mmr_shift = 211 is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT; 212 sync_state = (mmr >> mmr_shift) & UVH_TSC_SYNC_MASK; 213 214 /* Check if TSC is valid for all sockets */ 215 switch (sync_state) { 216 case UVH_TSC_SYNC_VALID: 217 state = "in sync"; 218 mark_tsc_async_resets("UV BIOS"); 219 break; 220 221 /* If BIOS state unknown, don't do anything */ 222 case UVH_TSC_SYNC_UNKNOWN: 223 state = "unknown"; 224 break; 225 226 /* Otherwise, BIOS indicates problem with TSC */ 227 default: 228 state = "unstable"; 229 mark_tsc_unstable("UV BIOS"); 230 break; 231 } 232 pr_info("UV: TSC sync state from BIOS:0%d(%s)\n", sync_state, state); 233 } 234 235 /* Selector for (4|4A|5) structs */ 236 #define uvxy_field(sname, field, undef) ( \ 237 is_uv(UV4A) ? sname.s4a.field : \ 238 is_uv(UV4) ? sname.s4.field : \ 239 is_uv(UV3) ? sname.s3.field : \ 240 undef) 241 242 /* [Copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */ 243 244 #define SMT_LEVEL 0 /* Leaf 0xb SMT level */ 245 #define INVALID_TYPE 0 /* Leaf 0xb sub-leaf types */ 246 #define SMT_TYPE 1 247 #define CORE_TYPE 2 248 #define LEAFB_SUBTYPE(ecx) (((ecx) >> 8) & 0xff) 249 #define BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f) 250 251 static void set_x2apic_bits(void) 252 { 253 unsigned int eax, ebx, ecx, edx, sub_index; 254 unsigned int sid_shift; 255 256 cpuid(0, &eax, &ebx, &ecx, &edx); 257 if (eax < 0xb) { 258 pr_info("UV: CPU does not have CPUID.11\n"); 259 return; 260 } 261 262 cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx); 263 if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) { 264 pr_info("UV: CPUID.11 not implemented\n"); 265 return; 266 } 267 268 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax); 269 sub_index = 1; 270 do { 271 cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx); 272 if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) { 273 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax); 274 break; 275 } 276 sub_index++; 277 } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE); 278 279 uv_cpuid.apicid_shift = 0; 280 uv_cpuid.apicid_mask = (~(-1 << sid_shift)); 281 uv_cpuid.socketid_shift = sid_shift; 282 } 283 284 static void __init early_get_apic_socketid_shift(void) 285 { 286 if (is_uv2_hub() || is_uv3_hub()) 287 uvh_apicid.v = uv_early_read_mmr(UVH_APICID); 288 289 set_x2apic_bits(); 290 291 pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n", uv_cpuid.apicid_shift, uv_cpuid.apicid_mask); 292 pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n", uv_cpuid.socketid_shift, uv_cpuid.pnode_mask); 293 } 294 295 static void __init uv_stringify(int len, char *to, char *from) 296 { 297 /* Relies on 'to' being NULL chars so result will be NULL terminated */ 298 strncpy(to, from, len-1); 299 300 /* Trim trailing spaces */ 301 (void)strim(to); 302 } 303 304 /* Find UV arch type entry in UVsystab */ 305 static unsigned long __init early_find_archtype(struct uv_systab *st) 306 { 307 int i; 308 309 for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) { 310 unsigned long ptr = st->entry[i].offset; 311 312 if (!ptr) 313 continue; 314 ptr += (unsigned long)st; 315 if (st->entry[i].type == UV_SYSTAB_TYPE_ARCH_TYPE) 316 return ptr; 317 } 318 return 0; 319 } 320 321 /* Validate UV arch type field in UVsystab */ 322 static int __init decode_arch_type(unsigned long ptr) 323 { 324 struct uv_arch_type_entry *uv_ate = (struct uv_arch_type_entry *)ptr; 325 int n = strlen(uv_ate->archtype); 326 327 if (n > 0 && n < sizeof(uv_ate->archtype)) { 328 pr_info("UV: UVarchtype received from BIOS\n"); 329 uv_stringify(sizeof(uv_archtype), uv_archtype, uv_ate->archtype); 330 return 1; 331 } 332 return 0; 333 } 334 335 /* Determine if UV arch type entry might exist in UVsystab */ 336 static int __init early_get_arch_type(void) 337 { 338 unsigned long uvst_physaddr, uvst_size, ptr; 339 struct uv_systab *st; 340 u32 rev; 341 int ret; 342 343 uvst_physaddr = get_uv_systab_phys(0); 344 if (!uvst_physaddr) 345 return 0; 346 347 st = early_memremap_ro(uvst_physaddr, sizeof(struct uv_systab)); 348 if (!st) { 349 pr_err("UV: Cannot access UVsystab, remap failed\n"); 350 return 0; 351 } 352 353 rev = st->revision; 354 if (rev < UV_SYSTAB_VERSION_UV5) { 355 early_memunmap(st, sizeof(struct uv_systab)); 356 return 0; 357 } 358 359 uvst_size = st->size; 360 early_memunmap(st, sizeof(struct uv_systab)); 361 st = early_memremap_ro(uvst_physaddr, uvst_size); 362 if (!st) { 363 pr_err("UV: Cannot access UVarchtype, remap failed\n"); 364 return 0; 365 } 366 367 ptr = early_find_archtype(st); 368 if (!ptr) { 369 early_memunmap(st, uvst_size); 370 return 0; 371 } 372 373 ret = decode_arch_type(ptr); 374 early_memunmap(st, uvst_size); 375 return ret; 376 } 377 378 /* UV system found, check which APIC MODE BIOS already selected */ 379 static void __init early_set_apic_mode(void) 380 { 381 if (x2apic_enabled()) 382 uv_system_type = UV_X2APIC; 383 else 384 uv_system_type = UV_LEGACY_APIC; 385 } 386 387 static int __init uv_set_system_type(char *_oem_id, char *_oem_table_id) 388 { 389 /* Save OEM_ID passed from ACPI MADT */ 390 uv_stringify(sizeof(oem_id), oem_id, _oem_id); 391 392 /* Check if BIOS sent us a UVarchtype */ 393 if (!early_get_arch_type()) 394 395 /* If not use OEM ID for UVarchtype */ 396 uv_stringify(sizeof(uv_archtype), uv_archtype, oem_id); 397 398 /* Check if not hubbed */ 399 if (strncmp(uv_archtype, "SGI", 3) != 0) { 400 401 /* (Not hubbed), check if not hubless */ 402 if (strncmp(uv_archtype, "NSGI", 4) != 0) 403 404 /* (Not hubless), not a UV */ 405 return 0; 406 407 /* Is UV hubless system */ 408 uv_hubless_system = 0x01; 409 410 /* UV5 Hubless */ 411 if (strncmp(uv_archtype, "NSGI5", 5) == 0) 412 uv_hubless_system |= 0x20; 413 414 /* UV4 Hubless: CH */ 415 else if (strncmp(uv_archtype, "NSGI4", 5) == 0) 416 uv_hubless_system |= 0x10; 417 418 /* UV3 Hubless: UV300/MC990X w/o hub */ 419 else 420 uv_hubless_system |= 0x8; 421 422 /* Copy OEM Table ID */ 423 uv_stringify(sizeof(oem_table_id), oem_table_id, _oem_table_id); 424 425 pr_info("UV: OEM IDs %s/%s, SystemType %d, HUBLESS ID %x\n", 426 oem_id, oem_table_id, uv_system_type, uv_hubless_system); 427 428 return 0; 429 } 430 431 if (numa_off) { 432 pr_err("UV: NUMA is off, disabling UV support\n"); 433 return 0; 434 } 435 436 /* Set hubbed type if true */ 437 uv_hub_info->hub_revision = 438 !strncmp(uv_archtype, "SGI5", 4) ? UV5_HUB_REVISION_BASE : 439 !strncmp(uv_archtype, "SGI4", 4) ? UV4_HUB_REVISION_BASE : 440 !strncmp(uv_archtype, "SGI3", 4) ? UV3_HUB_REVISION_BASE : 441 !strcmp(uv_archtype, "SGI2") ? UV2_HUB_REVISION_BASE : 0; 442 443 switch (uv_hub_info->hub_revision) { 444 case UV5_HUB_REVISION_BASE: 445 uv_hubbed_system = 0x21; 446 uv_hub_type_set(UV5); 447 break; 448 449 case UV4_HUB_REVISION_BASE: 450 uv_hubbed_system = 0x11; 451 uv_hub_type_set(UV4); 452 break; 453 454 case UV3_HUB_REVISION_BASE: 455 uv_hubbed_system = 0x9; 456 uv_hub_type_set(UV3); 457 break; 458 459 case UV2_HUB_REVISION_BASE: 460 uv_hubbed_system = 0x5; 461 uv_hub_type_set(UV2); 462 break; 463 464 default: 465 return 0; 466 } 467 468 /* Get UV hub chip part number & revision */ 469 early_set_hub_type(); 470 471 /* Other UV setup functions */ 472 early_set_apic_mode(); 473 early_get_pnodeid(); 474 early_get_apic_socketid_shift(); 475 x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range; 476 x86_platform.nmi_init = uv_nmi_init; 477 uv_tsc_check_sync(); 478 479 return 1; 480 } 481 482 /* Called early to probe for the correct APIC driver */ 483 static int __init uv_acpi_madt_oem_check(char *_oem_id, char *_oem_table_id) 484 { 485 /* Set up early hub info fields for Node 0 */ 486 uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0; 487 488 /* If not UV, return. */ 489 if (uv_set_system_type(_oem_id, _oem_table_id) == 0) 490 return 0; 491 492 /* Save for display of the OEM Table ID */ 493 uv_stringify(sizeof(oem_table_id), oem_table_id, _oem_table_id); 494 495 pr_info("UV: OEM IDs %s/%s, System/UVType %d/0x%x, HUB RevID %d\n", 496 oem_id, oem_table_id, uv_system_type, is_uv(UV_ANY), 497 uv_min_hub_revision_id); 498 499 return 0; 500 } 501 502 enum uv_system_type get_uv_system_type(void) 503 { 504 return uv_system_type; 505 } 506 507 int uv_get_hubless_system(void) 508 { 509 return uv_hubless_system; 510 } 511 EXPORT_SYMBOL_GPL(uv_get_hubless_system); 512 513 ssize_t uv_get_archtype(char *buf, int len) 514 { 515 return scnprintf(buf, len, "%s/%s", uv_archtype, oem_table_id); 516 } 517 EXPORT_SYMBOL_GPL(uv_get_archtype); 518 519 int is_uv_system(void) 520 { 521 return uv_system_type != UV_NONE; 522 } 523 EXPORT_SYMBOL_GPL(is_uv_system); 524 525 int is_uv_hubbed(int uvtype) 526 { 527 return (uv_hubbed_system & uvtype); 528 } 529 EXPORT_SYMBOL_GPL(is_uv_hubbed); 530 531 static int is_uv_hubless(int uvtype) 532 { 533 return (uv_hubless_system & uvtype); 534 } 535 536 void **__uv_hub_info_list; 537 EXPORT_SYMBOL_GPL(__uv_hub_info_list); 538 539 DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info); 540 EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info); 541 542 short uv_possible_blades; 543 EXPORT_SYMBOL_GPL(uv_possible_blades); 544 545 unsigned long sn_rtc_cycles_per_second; 546 EXPORT_SYMBOL(sn_rtc_cycles_per_second); 547 548 /* The following values are used for the per node hub info struct */ 549 static __initdata unsigned short _min_socket, _max_socket; 550 static __initdata unsigned short _min_pnode, _max_pnode, _gr_table_len; 551 static __initdata struct uv_gam_range_entry *uv_gre_table; 552 static __initdata struct uv_gam_parameters *uv_gp_table; 553 static __initdata unsigned short *_socket_to_node; 554 static __initdata unsigned short *_socket_to_pnode; 555 static __initdata unsigned short *_pnode_to_socket; 556 static __initdata unsigned short *_node_to_socket; 557 558 static __initdata struct uv_gam_range_s *_gr_table; 559 560 #define SOCK_EMPTY ((unsigned short)~0) 561 562 /* Default UV memory block size is 2GB */ 563 static unsigned long mem_block_size __initdata = (2UL << 30); 564 565 /* Kernel parameter to specify UV mem block size */ 566 static int __init parse_mem_block_size(char *ptr) 567 { 568 unsigned long size = memparse(ptr, NULL); 569 570 /* Size will be rounded down by set_block_size() below */ 571 mem_block_size = size; 572 return 0; 573 } 574 early_param("uv_memblksize", parse_mem_block_size); 575 576 static __init int adj_blksize(u32 lgre) 577 { 578 unsigned long base = (unsigned long)lgre << UV_GAM_RANGE_SHFT; 579 unsigned long size; 580 581 for (size = mem_block_size; size > MIN_MEMORY_BLOCK_SIZE; size >>= 1) 582 if (IS_ALIGNED(base, size)) 583 break; 584 585 if (size >= mem_block_size) 586 return 0; 587 588 mem_block_size = size; 589 return 1; 590 } 591 592 static __init void set_block_size(void) 593 { 594 unsigned int order = ffs(mem_block_size); 595 596 if (order) { 597 /* adjust for ffs return of 1..64 */ 598 set_memory_block_size_order(order - 1); 599 pr_info("UV: mem_block_size set to 0x%lx\n", mem_block_size); 600 } else { 601 /* bad or zero value, default to 1UL << 31 (2GB) */ 602 pr_err("UV: mem_block_size error with 0x%lx\n", mem_block_size); 603 set_memory_block_size_order(31); 604 } 605 } 606 607 /* Build GAM range lookup table: */ 608 static __init void build_uv_gr_table(void) 609 { 610 struct uv_gam_range_entry *gre = uv_gre_table; 611 struct uv_gam_range_s *grt; 612 unsigned long last_limit = 0, ram_limit = 0; 613 int bytes, i, sid, lsid = -1, indx = 0, lindx = -1; 614 615 if (!gre) 616 return; 617 618 bytes = _gr_table_len * sizeof(struct uv_gam_range_s); 619 grt = kzalloc(bytes, GFP_KERNEL); 620 if (WARN_ON_ONCE(!grt)) 621 return; 622 _gr_table = grt; 623 624 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) { 625 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) { 626 if (!ram_limit) { 627 /* Mark hole between RAM/non-RAM: */ 628 ram_limit = last_limit; 629 last_limit = gre->limit; 630 lsid++; 631 continue; 632 } 633 last_limit = gre->limit; 634 pr_info("UV: extra hole in GAM RE table @%d\n", (int)(gre - uv_gre_table)); 635 continue; 636 } 637 if (_max_socket < gre->sockid) { 638 pr_err("UV: GAM table sockid(%d) too large(>%d) @%d\n", gre->sockid, _max_socket, (int)(gre - uv_gre_table)); 639 continue; 640 } 641 sid = gre->sockid - _min_socket; 642 if (lsid < sid) { 643 /* New range: */ 644 grt = &_gr_table[indx]; 645 grt->base = lindx; 646 grt->nasid = gre->nasid; 647 grt->limit = last_limit = gre->limit; 648 lsid = sid; 649 lindx = indx++; 650 continue; 651 } 652 /* Update range: */ 653 if (lsid == sid && !ram_limit) { 654 /* .. if contiguous: */ 655 if (grt->limit == last_limit) { 656 grt->limit = last_limit = gre->limit; 657 continue; 658 } 659 } 660 /* Non-contiguous RAM range: */ 661 if (!ram_limit) { 662 grt++; 663 grt->base = lindx; 664 grt->nasid = gre->nasid; 665 grt->limit = last_limit = gre->limit; 666 continue; 667 } 668 /* Non-contiguous/non-RAM: */ 669 grt++; 670 /* base is this entry */ 671 grt->base = grt - _gr_table; 672 grt->nasid = gre->nasid; 673 grt->limit = last_limit = gre->limit; 674 lsid++; 675 } 676 677 /* Shorten table if possible */ 678 grt++; 679 i = grt - _gr_table; 680 if (i < _gr_table_len) { 681 void *ret; 682 683 bytes = i * sizeof(struct uv_gam_range_s); 684 ret = krealloc(_gr_table, bytes, GFP_KERNEL); 685 if (ret) { 686 _gr_table = ret; 687 _gr_table_len = i; 688 } 689 } 690 691 /* Display resultant GAM range table: */ 692 for (i = 0, grt = _gr_table; i < _gr_table_len; i++, grt++) { 693 unsigned long start, end; 694 int gb = grt->base; 695 696 start = gb < 0 ? 0 : (unsigned long)_gr_table[gb].limit << UV_GAM_RANGE_SHFT; 697 end = (unsigned long)grt->limit << UV_GAM_RANGE_SHFT; 698 699 pr_info("UV: GAM Range %2d %04x 0x%013lx-0x%013lx (%d)\n", i, grt->nasid, start, end, gb); 700 } 701 } 702 703 static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip) 704 { 705 unsigned long val; 706 int pnode; 707 708 pnode = uv_apicid_to_pnode(phys_apicid); 709 710 val = (1UL << UVH_IPI_INT_SEND_SHFT) | 711 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | 712 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | 713 APIC_DM_INIT; 714 715 uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 716 717 val = (1UL << UVH_IPI_INT_SEND_SHFT) | 718 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | 719 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | 720 APIC_DM_STARTUP; 721 722 uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 723 724 return 0; 725 } 726 727 static void uv_send_IPI_one(int cpu, int vector) 728 { 729 unsigned long apicid = per_cpu(x86_cpu_to_apicid, cpu); 730 int pnode = uv_apicid_to_pnode(apicid); 731 unsigned long dmode, val; 732 733 if (vector == NMI_VECTOR) 734 dmode = APIC_DELIVERY_MODE_NMI; 735 else 736 dmode = APIC_DELIVERY_MODE_FIXED; 737 738 val = (1UL << UVH_IPI_INT_SEND_SHFT) | 739 (apicid << UVH_IPI_INT_APIC_ID_SHFT) | 740 (dmode << UVH_IPI_INT_DELIVERY_MODE_SHFT) | 741 (vector << UVH_IPI_INT_VECTOR_SHFT); 742 743 uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 744 } 745 746 static void uv_send_IPI_mask(const struct cpumask *mask, int vector) 747 { 748 unsigned int cpu; 749 750 for_each_cpu(cpu, mask) 751 uv_send_IPI_one(cpu, vector); 752 } 753 754 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) 755 { 756 unsigned int this_cpu = smp_processor_id(); 757 unsigned int cpu; 758 759 for_each_cpu(cpu, mask) { 760 if (cpu != this_cpu) 761 uv_send_IPI_one(cpu, vector); 762 } 763 } 764 765 static void uv_send_IPI_allbutself(int vector) 766 { 767 unsigned int this_cpu = smp_processor_id(); 768 unsigned int cpu; 769 770 for_each_online_cpu(cpu) { 771 if (cpu != this_cpu) 772 uv_send_IPI_one(cpu, vector); 773 } 774 } 775 776 static void uv_send_IPI_all(int vector) 777 { 778 uv_send_IPI_mask(cpu_online_mask, vector); 779 } 780 781 static int uv_apic_id_valid(u32 apicid) 782 { 783 return 1; 784 } 785 786 static int uv_apic_id_registered(void) 787 { 788 return 1; 789 } 790 791 static void uv_init_apic_ldr(void) 792 { 793 } 794 795 static u32 apic_uv_calc_apicid(unsigned int cpu) 796 { 797 return apic_default_calc_apicid(cpu); 798 } 799 800 static unsigned int x2apic_get_apic_id(unsigned long id) 801 { 802 return id; 803 } 804 805 static u32 set_apic_id(unsigned int id) 806 { 807 return id; 808 } 809 810 static unsigned int uv_read_apic_id(void) 811 { 812 return x2apic_get_apic_id(apic_read(APIC_ID)); 813 } 814 815 static int uv_phys_pkg_id(int initial_apicid, int index_msb) 816 { 817 return uv_read_apic_id() >> index_msb; 818 } 819 820 static void uv_send_IPI_self(int vector) 821 { 822 apic_write(APIC_SELF_IPI, vector); 823 } 824 825 static int uv_probe(void) 826 { 827 return apic == &apic_x2apic_uv_x; 828 } 829 830 static struct apic apic_x2apic_uv_x __ro_after_init = { 831 832 .name = "UV large system", 833 .probe = uv_probe, 834 .acpi_madt_oem_check = uv_acpi_madt_oem_check, 835 .apic_id_valid = uv_apic_id_valid, 836 .apic_id_registered = uv_apic_id_registered, 837 838 .delivery_mode = APIC_DELIVERY_MODE_FIXED, 839 .dest_mode_logical = false, 840 841 .disable_esr = 0, 842 843 .check_apicid_used = NULL, 844 .init_apic_ldr = uv_init_apic_ldr, 845 .ioapic_phys_id_map = NULL, 846 .setup_apic_routing = NULL, 847 .cpu_present_to_apicid = default_cpu_present_to_apicid, 848 .apicid_to_cpu_present = NULL, 849 .check_phys_apicid_present = default_check_phys_apicid_present, 850 .phys_pkg_id = uv_phys_pkg_id, 851 852 .get_apic_id = x2apic_get_apic_id, 853 .set_apic_id = set_apic_id, 854 855 .calc_dest_apicid = apic_uv_calc_apicid, 856 857 .send_IPI = uv_send_IPI_one, 858 .send_IPI_mask = uv_send_IPI_mask, 859 .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself, 860 .send_IPI_allbutself = uv_send_IPI_allbutself, 861 .send_IPI_all = uv_send_IPI_all, 862 .send_IPI_self = uv_send_IPI_self, 863 864 .wakeup_secondary_cpu = uv_wakeup_secondary, 865 .inquire_remote_apic = NULL, 866 867 .read = native_apic_msr_read, 868 .write = native_apic_msr_write, 869 .eoi_write = native_apic_msr_eoi_write, 870 .icr_read = native_x2apic_icr_read, 871 .icr_write = native_x2apic_icr_write, 872 .wait_icr_idle = native_x2apic_wait_icr_idle, 873 .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle, 874 }; 875 876 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH 3 877 #define DEST_SHIFT UVXH_RH_GAM_ALIAS_0_REDIRECT_CONFIG_DEST_BASE_SHFT 878 879 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size) 880 { 881 union uvh_rh_gam_alias_2_overlay_config_u alias; 882 union uvh_rh_gam_alias_2_redirect_config_u redirect; 883 unsigned long m_redirect; 884 unsigned long m_overlay; 885 int i; 886 887 for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) { 888 switch (i) { 889 case 0: 890 m_redirect = UVH_RH_GAM_ALIAS_0_REDIRECT_CONFIG; 891 m_overlay = UVH_RH_GAM_ALIAS_0_OVERLAY_CONFIG; 892 break; 893 case 1: 894 m_redirect = UVH_RH_GAM_ALIAS_1_REDIRECT_CONFIG; 895 m_overlay = UVH_RH_GAM_ALIAS_1_OVERLAY_CONFIG; 896 break; 897 case 2: 898 m_redirect = UVH_RH_GAM_ALIAS_2_REDIRECT_CONFIG; 899 m_overlay = UVH_RH_GAM_ALIAS_2_OVERLAY_CONFIG; 900 break; 901 } 902 alias.v = uv_read_local_mmr(m_overlay); 903 if (alias.s.enable && alias.s.base == 0) { 904 *size = (1UL << alias.s.m_alias); 905 redirect.v = uv_read_local_mmr(m_redirect); 906 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT; 907 return; 908 } 909 } 910 *base = *size = 0; 911 } 912 913 enum map_type {map_wb, map_uc}; 914 static const char * const mt[] = { "WB", "UC" }; 915 916 static __init void map_high(char *id, unsigned long base, int pshift, int bshift, int max_pnode, enum map_type map_type) 917 { 918 unsigned long bytes, paddr; 919 920 paddr = base << pshift; 921 bytes = (1UL << bshift) * (max_pnode + 1); 922 if (!paddr) { 923 pr_info("UV: Map %s_HI base address NULL\n", id); 924 return; 925 } 926 if (map_type == map_uc) 927 init_extra_mapping_uc(paddr, bytes); 928 else 929 init_extra_mapping_wb(paddr, bytes); 930 931 pr_info("UV: Map %s_HI 0x%lx - 0x%lx %s (%d segments)\n", 932 id, paddr, paddr + bytes, mt[map_type], max_pnode + 1); 933 } 934 935 static __init void map_gru_high(int max_pnode) 936 { 937 union uvh_rh_gam_gru_overlay_config_u gru; 938 unsigned long mask, base; 939 int shift; 940 941 if (UVH_RH_GAM_GRU_OVERLAY_CONFIG) { 942 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG); 943 shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT; 944 mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_MASK; 945 } else if (UVH_RH10_GAM_GRU_OVERLAY_CONFIG) { 946 gru.v = uv_read_local_mmr(UVH_RH10_GAM_GRU_OVERLAY_CONFIG); 947 shift = UVH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT; 948 mask = UVH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_MASK; 949 } else { 950 pr_err("UV: GRU unavailable (no MMR)\n"); 951 return; 952 } 953 954 if (!gru.s.enable) { 955 pr_info("UV: GRU disabled (by BIOS)\n"); 956 return; 957 } 958 959 base = (gru.v & mask) >> shift; 960 map_high("GRU", base, shift, shift, max_pnode, map_wb); 961 gru_start_paddr = ((u64)base << shift); 962 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1); 963 } 964 965 static __init void map_mmr_high(int max_pnode) 966 { 967 unsigned long base; 968 int shift; 969 bool enable; 970 971 if (UVH_RH10_GAM_MMR_OVERLAY_CONFIG) { 972 union uvh_rh10_gam_mmr_overlay_config_u mmr; 973 974 mmr.v = uv_read_local_mmr(UVH_RH10_GAM_MMR_OVERLAY_CONFIG); 975 enable = mmr.s.enable; 976 base = mmr.s.base; 977 shift = UVH_RH10_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT; 978 } else if (UVH_RH_GAM_MMR_OVERLAY_CONFIG) { 979 union uvh_rh_gam_mmr_overlay_config_u mmr; 980 981 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG); 982 enable = mmr.s.enable; 983 base = mmr.s.base; 984 shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT; 985 } else { 986 pr_err("UV:%s:RH_GAM_MMR_OVERLAY_CONFIG MMR undefined?\n", 987 __func__); 988 return; 989 } 990 991 if (enable) 992 map_high("MMR", base, shift, shift, max_pnode, map_uc); 993 else 994 pr_info("UV: MMR disabled\n"); 995 } 996 997 /* Arch specific ENUM cases */ 998 enum mmioh_arch { 999 UV2_MMIOH = -1, 1000 UVY_MMIOH0, UVY_MMIOH1, 1001 UVX_MMIOH0, UVX_MMIOH1, 1002 }; 1003 1004 /* Calculate and Map MMIOH Regions */ 1005 static void __init calc_mmioh_map(enum mmioh_arch index, 1006 int min_pnode, int max_pnode, 1007 int shift, unsigned long base, int m_io, int n_io) 1008 { 1009 unsigned long mmr, nasid_mask; 1010 int nasid, min_nasid, max_nasid, lnasid, mapped; 1011 int i, fi, li, n, max_io; 1012 char id[8]; 1013 1014 /* One (UV2) mapping */ 1015 if (index == UV2_MMIOH) { 1016 strncpy(id, "MMIOH", sizeof(id)); 1017 max_io = max_pnode; 1018 mapped = 0; 1019 goto map_exit; 1020 } 1021 1022 /* small and large MMIOH mappings */ 1023 switch (index) { 1024 case UVY_MMIOH0: 1025 mmr = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG0; 1026 nasid_mask = UVYH_RH10_GAM_MMIOH_REDIRECT_CONFIG0_NASID_MASK; 1027 n = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG0_DEPTH; 1028 min_nasid = min_pnode; 1029 max_nasid = max_pnode; 1030 mapped = 1; 1031 break; 1032 case UVY_MMIOH1: 1033 mmr = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG1; 1034 nasid_mask = UVYH_RH10_GAM_MMIOH_REDIRECT_CONFIG1_NASID_MASK; 1035 n = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG1_DEPTH; 1036 min_nasid = min_pnode; 1037 max_nasid = max_pnode; 1038 mapped = 1; 1039 break; 1040 case UVX_MMIOH0: 1041 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0; 1042 nasid_mask = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_NASID_MASK; 1043 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_DEPTH; 1044 min_nasid = min_pnode * 2; 1045 max_nasid = max_pnode * 2; 1046 mapped = 1; 1047 break; 1048 case UVX_MMIOH1: 1049 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1; 1050 nasid_mask = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_NASID_MASK; 1051 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_DEPTH; 1052 min_nasid = min_pnode * 2; 1053 max_nasid = max_pnode * 2; 1054 mapped = 1; 1055 break; 1056 default: 1057 pr_err("UV:%s:Invalid mapping type:%d\n", __func__, index); 1058 return; 1059 } 1060 1061 /* enum values chosen so (index mod 2) is MMIOH 0/1 (low/high) */ 1062 snprintf(id, sizeof(id), "MMIOH%d", index%2); 1063 1064 max_io = lnasid = fi = li = -1; 1065 for (i = 0; i < n; i++) { 1066 unsigned long m_redirect = mmr + i * 8; 1067 unsigned long redirect = uv_read_local_mmr(m_redirect); 1068 1069 nasid = redirect & nasid_mask; 1070 if (i == 0) 1071 pr_info("UV: %s redirect base 0x%lx(@0x%lx) 0x%04x\n", 1072 id, redirect, m_redirect, nasid); 1073 1074 /* Invalid NASID check */ 1075 if (nasid < min_nasid || max_nasid < nasid) { 1076 /* Not an error: unused table entries get "poison" values */ 1077 pr_debug("UV:%s:Invalid NASID(%x):%x (range:%x..%x)\n", 1078 __func__, index, nasid, min_nasid, max_nasid); 1079 nasid = -1; 1080 } 1081 1082 if (nasid == lnasid) { 1083 li = i; 1084 /* Last entry check: */ 1085 if (i != n-1) 1086 continue; 1087 } 1088 1089 /* Check if we have a cached (or last) redirect to print: */ 1090 if (lnasid != -1 || (i == n-1 && nasid != -1)) { 1091 unsigned long addr1, addr2; 1092 int f, l; 1093 1094 if (lnasid == -1) { 1095 f = l = i; 1096 lnasid = nasid; 1097 } else { 1098 f = fi; 1099 l = li; 1100 } 1101 addr1 = (base << shift) + f * (1ULL << m_io); 1102 addr2 = (base << shift) + (l + 1) * (1ULL << m_io); 1103 pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n", 1104 id, fi, li, lnasid, addr1, addr2); 1105 if (max_io < l) 1106 max_io = l; 1107 } 1108 fi = li = i; 1109 lnasid = nasid; 1110 } 1111 1112 map_exit: 1113 pr_info("UV: %s base:0x%lx shift:%d m_io:%d max_io:%d max_pnode:0x%x\n", 1114 id, base, shift, m_io, max_io, max_pnode); 1115 1116 if (max_io >= 0 && !mapped) 1117 map_high(id, base, shift, m_io, max_io, map_uc); 1118 } 1119 1120 static __init void map_mmioh_high(int min_pnode, int max_pnode) 1121 { 1122 /* UVY flavor */ 1123 if (UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0) { 1124 union uvh_rh10_gam_mmioh_overlay_config0_u mmioh0; 1125 union uvh_rh10_gam_mmioh_overlay_config1_u mmioh1; 1126 1127 mmioh0.v = uv_read_local_mmr(UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0); 1128 if (unlikely(mmioh0.s.enable == 0)) 1129 pr_info("UV: MMIOH0 disabled\n"); 1130 else 1131 calc_mmioh_map(UVY_MMIOH0, min_pnode, max_pnode, 1132 UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT, 1133 mmioh0.s.base, mmioh0.s.m_io, mmioh0.s.n_io); 1134 1135 mmioh1.v = uv_read_local_mmr(UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1); 1136 if (unlikely(mmioh1.s.enable == 0)) 1137 pr_info("UV: MMIOH1 disabled\n"); 1138 else 1139 calc_mmioh_map(UVY_MMIOH1, min_pnode, max_pnode, 1140 UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT, 1141 mmioh1.s.base, mmioh1.s.m_io, mmioh1.s.n_io); 1142 return; 1143 } 1144 /* UVX flavor */ 1145 if (UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0) { 1146 union uvh_rh_gam_mmioh_overlay_config0_u mmioh0; 1147 union uvh_rh_gam_mmioh_overlay_config1_u mmioh1; 1148 1149 mmioh0.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0); 1150 if (unlikely(mmioh0.s.enable == 0)) 1151 pr_info("UV: MMIOH0 disabled\n"); 1152 else { 1153 unsigned long base = uvxy_field(mmioh0, base, 0); 1154 int m_io = uvxy_field(mmioh0, m_io, 0); 1155 int n_io = uvxy_field(mmioh0, n_io, 0); 1156 1157 calc_mmioh_map(UVX_MMIOH0, min_pnode, max_pnode, 1158 UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT, 1159 base, m_io, n_io); 1160 } 1161 1162 mmioh1.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1); 1163 if (unlikely(mmioh1.s.enable == 0)) 1164 pr_info("UV: MMIOH1 disabled\n"); 1165 else { 1166 unsigned long base = uvxy_field(mmioh1, base, 0); 1167 int m_io = uvxy_field(mmioh1, m_io, 0); 1168 int n_io = uvxy_field(mmioh1, n_io, 0); 1169 1170 calc_mmioh_map(UVX_MMIOH1, min_pnode, max_pnode, 1171 UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT, 1172 base, m_io, n_io); 1173 } 1174 return; 1175 } 1176 1177 /* UV2 flavor */ 1178 if (UVH_RH_GAM_MMIOH_OVERLAY_CONFIG) { 1179 union uvh_rh_gam_mmioh_overlay_config_u mmioh; 1180 1181 mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG); 1182 if (unlikely(mmioh.s2.enable == 0)) 1183 pr_info("UV: MMIOH disabled\n"); 1184 else 1185 calc_mmioh_map(UV2_MMIOH, min_pnode, max_pnode, 1186 UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_BASE_SHFT, 1187 mmioh.s2.base, mmioh.s2.m_io, mmioh.s2.n_io); 1188 return; 1189 } 1190 } 1191 1192 static __init void map_low_mmrs(void) 1193 { 1194 if (UV_GLOBAL_MMR32_BASE) 1195 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE); 1196 1197 if (UV_LOCAL_MMR_BASE) 1198 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE); 1199 } 1200 1201 static __init void uv_rtc_init(void) 1202 { 1203 long status; 1204 u64 ticks_per_sec; 1205 1206 status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec); 1207 1208 if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) { 1209 pr_warn("UV: unable to determine platform RTC clock frequency, guessing.\n"); 1210 1211 /* BIOS gives wrong value for clock frequency, so guess: */ 1212 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL; 1213 } else { 1214 sn_rtc_cycles_per_second = ticks_per_sec; 1215 } 1216 } 1217 1218 /* Direct Legacy VGA I/O traffic to designated IOH */ 1219 static int uv_set_vga_state(struct pci_dev *pdev, bool decode, unsigned int command_bits, u32 flags) 1220 { 1221 int domain, bus, rc; 1222 1223 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) 1224 return 0; 1225 1226 if ((command_bits & PCI_COMMAND_IO) == 0) 1227 return 0; 1228 1229 domain = pci_domain_nr(pdev->bus); 1230 bus = pdev->bus->number; 1231 1232 rc = uv_bios_set_legacy_vga_target(decode, domain, bus); 1233 1234 return rc; 1235 } 1236 1237 /* 1238 * Called on each CPU to initialize the per_cpu UV data area. 1239 * FIXME: hotplug not supported yet 1240 */ 1241 void uv_cpu_init(void) 1242 { 1243 /* CPU 0 initialization will be done via uv_system_init. */ 1244 if (smp_processor_id() == 0) 1245 return; 1246 1247 uv_hub_info->nr_online_cpus++; 1248 } 1249 1250 struct mn { 1251 unsigned char m_val; 1252 unsigned char n_val; 1253 unsigned char m_shift; 1254 unsigned char n_lshift; 1255 }; 1256 1257 /* Initialize caller's MN struct and fill in values */ 1258 static void get_mn(struct mn *mnp) 1259 { 1260 memset(mnp, 0, sizeof(*mnp)); 1261 mnp->n_val = uv_cpuid.n_skt; 1262 if (is_uv(UV4|UVY)) { 1263 mnp->m_val = 0; 1264 mnp->n_lshift = 0; 1265 } else if (is_uv3_hub()) { 1266 union uvyh_gr0_gam_gr_config_u m_gr_config; 1267 1268 mnp->m_val = uv_cpuid.m_skt; 1269 m_gr_config.v = uv_read_local_mmr(UVH_GR0_GAM_GR_CONFIG); 1270 mnp->n_lshift = m_gr_config.s3.m_skt; 1271 } else if (is_uv2_hub()) { 1272 mnp->m_val = uv_cpuid.m_skt; 1273 mnp->n_lshift = mnp->m_val == 40 ? 40 : 39; 1274 } 1275 mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0; 1276 } 1277 1278 static void __init uv_init_hub_info(struct uv_hub_info_s *hi) 1279 { 1280 struct mn mn; 1281 1282 get_mn(&mn); 1283 hi->gpa_mask = mn.m_val ? 1284 (1UL << (mn.m_val + mn.n_val)) - 1 : 1285 (1UL << uv_cpuid.gpa_shift) - 1; 1286 1287 hi->m_val = mn.m_val; 1288 hi->n_val = mn.n_val; 1289 hi->m_shift = mn.m_shift; 1290 hi->n_lshift = mn.n_lshift ? mn.n_lshift : 0; 1291 hi->hub_revision = uv_hub_info->hub_revision; 1292 hi->hub_type = uv_hub_info->hub_type; 1293 hi->pnode_mask = uv_cpuid.pnode_mask; 1294 hi->nasid_shift = uv_cpuid.nasid_shift; 1295 hi->min_pnode = _min_pnode; 1296 hi->min_socket = _min_socket; 1297 hi->node_to_socket = _node_to_socket; 1298 hi->pnode_to_socket = _pnode_to_socket; 1299 hi->socket_to_node = _socket_to_node; 1300 hi->socket_to_pnode = _socket_to_pnode; 1301 hi->gr_table_len = _gr_table_len; 1302 hi->gr_table = _gr_table; 1303 1304 uv_cpuid.gnode_shift = max_t(unsigned int, uv_cpuid.gnode_shift, mn.n_val); 1305 hi->gnode_extra = (uv_node_id & ~((1 << uv_cpuid.gnode_shift) - 1)) >> 1; 1306 if (mn.m_val) 1307 hi->gnode_upper = (u64)hi->gnode_extra << mn.m_val; 1308 1309 if (uv_gp_table) { 1310 hi->global_mmr_base = uv_gp_table->mmr_base; 1311 hi->global_mmr_shift = uv_gp_table->mmr_shift; 1312 hi->global_gru_base = uv_gp_table->gru_base; 1313 hi->global_gru_shift = uv_gp_table->gru_shift; 1314 hi->gpa_shift = uv_gp_table->gpa_shift; 1315 hi->gpa_mask = (1UL << hi->gpa_shift) - 1; 1316 } else { 1317 hi->global_mmr_base = 1318 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG) & 1319 ~UV_MMR_ENABLE; 1320 hi->global_mmr_shift = _UV_GLOBAL_MMR64_PNODE_SHIFT; 1321 } 1322 1323 get_lowmem_redirect(&hi->lowmem_remap_base, &hi->lowmem_remap_top); 1324 1325 hi->apic_pnode_shift = uv_cpuid.socketid_shift; 1326 1327 /* Show system specific info: */ 1328 pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n", hi->n_val, hi->m_val, hi->m_shift, hi->n_lshift); 1329 pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n", hi->gpa_mask, hi->gpa_shift, hi->pnode_mask, hi->apic_pnode_shift); 1330 pr_info("UV: mmr_base/shift:0x%lx/%ld\n", hi->global_mmr_base, hi->global_mmr_shift); 1331 if (hi->global_gru_base) 1332 pr_info("UV: gru_base/shift:0x%lx/%ld\n", 1333 hi->global_gru_base, hi->global_gru_shift); 1334 1335 pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n", hi->gnode_upper, hi->gnode_extra); 1336 } 1337 1338 static void __init decode_gam_params(unsigned long ptr) 1339 { 1340 uv_gp_table = (struct uv_gam_parameters *)ptr; 1341 1342 pr_info("UV: GAM Params...\n"); 1343 pr_info("UV: mmr_base/shift:0x%llx/%d gru_base/shift:0x%llx/%d gpa_shift:%d\n", 1344 uv_gp_table->mmr_base, uv_gp_table->mmr_shift, 1345 uv_gp_table->gru_base, uv_gp_table->gru_shift, 1346 uv_gp_table->gpa_shift); 1347 } 1348 1349 static void __init decode_gam_rng_tbl(unsigned long ptr) 1350 { 1351 struct uv_gam_range_entry *gre = (struct uv_gam_range_entry *)ptr; 1352 unsigned long lgre = 0, gend = 0; 1353 int index = 0; 1354 int sock_min = INT_MAX, pnode_min = INT_MAX; 1355 int sock_max = -1, pnode_max = -1; 1356 1357 uv_gre_table = gre; 1358 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) { 1359 unsigned long size = ((unsigned long)(gre->limit - lgre) 1360 << UV_GAM_RANGE_SHFT); 1361 int order = 0; 1362 char suffix[] = " KMGTPE"; 1363 int flag = ' '; 1364 1365 while (size > 9999 && order < sizeof(suffix)) { 1366 size /= 1024; 1367 order++; 1368 } 1369 1370 /* adjust max block size to current range start */ 1371 if (gre->type == 1 || gre->type == 2) 1372 if (adj_blksize(lgre)) 1373 flag = '*'; 1374 1375 if (!index) { 1376 pr_info("UV: GAM Range Table...\n"); 1377 pr_info("UV: # %20s %14s %6s %4s %5s %3s %2s\n", "Range", "", "Size", "Type", "NASID", "SID", "PN"); 1378 } 1379 pr_info("UV: %2d: 0x%014lx-0x%014lx%c %5lu%c %3d %04x %02x %02x\n", 1380 index++, 1381 (unsigned long)lgre << UV_GAM_RANGE_SHFT, 1382 (unsigned long)gre->limit << UV_GAM_RANGE_SHFT, 1383 flag, size, suffix[order], 1384 gre->type, gre->nasid, gre->sockid, gre->pnode); 1385 1386 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) 1387 gend = (unsigned long)gre->limit << UV_GAM_RANGE_SHFT; 1388 1389 /* update to next range start */ 1390 lgre = gre->limit; 1391 if (sock_min > gre->sockid) 1392 sock_min = gre->sockid; 1393 if (sock_max < gre->sockid) 1394 sock_max = gre->sockid; 1395 if (pnode_min > gre->pnode) 1396 pnode_min = gre->pnode; 1397 if (pnode_max < gre->pnode) 1398 pnode_max = gre->pnode; 1399 } 1400 _min_socket = sock_min; 1401 _max_socket = sock_max; 1402 _min_pnode = pnode_min; 1403 _max_pnode = pnode_max; 1404 _gr_table_len = index; 1405 1406 pr_info("UV: GRT: %d entries, sockets(min:%x,max:%x), pnodes(min:%x,max:%x), gap_end(%d)\n", 1407 index, _min_socket, _max_socket, _min_pnode, _max_pnode, fls64(gend)); 1408 } 1409 1410 /* Walk through UVsystab decoding the fields */ 1411 static int __init decode_uv_systab(void) 1412 { 1413 struct uv_systab *st; 1414 int i; 1415 1416 /* Get mapped UVsystab pointer */ 1417 st = uv_systab; 1418 1419 /* If UVsystab is version 1, there is no extended UVsystab */ 1420 if (st && st->revision == UV_SYSTAB_VERSION_1) 1421 return 0; 1422 1423 if ((!st) || (st->revision < UV_SYSTAB_VERSION_UV4_LATEST)) { 1424 int rev = st ? st->revision : 0; 1425 1426 pr_err("UV: BIOS UVsystab mismatch, (%x < %x)\n", 1427 rev, UV_SYSTAB_VERSION_UV4_LATEST); 1428 pr_err("UV: Does not support UV, switch to non-UV x86_64\n"); 1429 uv_system_type = UV_NONE; 1430 1431 return -EINVAL; 1432 } 1433 1434 for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) { 1435 unsigned long ptr = st->entry[i].offset; 1436 1437 if (!ptr) 1438 continue; 1439 1440 /* point to payload */ 1441 ptr += (unsigned long)st; 1442 1443 switch (st->entry[i].type) { 1444 case UV_SYSTAB_TYPE_GAM_PARAMS: 1445 decode_gam_params(ptr); 1446 break; 1447 1448 case UV_SYSTAB_TYPE_GAM_RNG_TBL: 1449 decode_gam_rng_tbl(ptr); 1450 break; 1451 1452 case UV_SYSTAB_TYPE_ARCH_TYPE: 1453 /* already processed in early startup */ 1454 break; 1455 1456 default: 1457 pr_err("UV:%s:Unrecognized UV_SYSTAB_TYPE:%d, skipped\n", 1458 __func__, st->entry[i].type); 1459 break; 1460 } 1461 } 1462 return 0; 1463 } 1464 1465 /* 1466 * Given a bitmask 'bits' representing presnt blades, numbered 1467 * starting at 'base', masking off unused high bits of blade number 1468 * with 'mask', update the minimum and maximum blade numbers that we 1469 * have found. (Masking with 'mask' necessary because of BIOS 1470 * treatment of system partitioning when creating this table we are 1471 * interpreting.) 1472 */ 1473 static inline void blade_update_min_max(unsigned long bits, int base, int mask, int *min, int *max) 1474 { 1475 int first, last; 1476 1477 if (!bits) 1478 return; 1479 first = (base + __ffs(bits)) & mask; 1480 last = (base + __fls(bits)) & mask; 1481 1482 if (*min > first) 1483 *min = first; 1484 if (*max < last) 1485 *max = last; 1486 } 1487 1488 /* Set up physical blade translations from UVH_NODE_PRESENT_TABLE */ 1489 static __init void boot_init_possible_blades(struct uv_hub_info_s *hub_info) 1490 { 1491 unsigned long np; 1492 int i, uv_pb = 0; 1493 int sock_min = INT_MAX, sock_max = -1, s_mask; 1494 1495 s_mask = (1 << uv_cpuid.n_skt) - 1; 1496 1497 if (UVH_NODE_PRESENT_TABLE) { 1498 pr_info("UV: NODE_PRESENT_DEPTH = %d\n", 1499 UVH_NODE_PRESENT_TABLE_DEPTH); 1500 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) { 1501 np = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8); 1502 pr_info("UV: NODE_PRESENT(%d) = 0x%016lx\n", i, np); 1503 blade_update_min_max(np, i * 64, s_mask, &sock_min, &sock_max); 1504 } 1505 } 1506 if (UVH_NODE_PRESENT_0) { 1507 np = uv_read_local_mmr(UVH_NODE_PRESENT_0); 1508 pr_info("UV: NODE_PRESENT_0 = 0x%016lx\n", np); 1509 blade_update_min_max(np, 0, s_mask, &sock_min, &sock_max); 1510 } 1511 if (UVH_NODE_PRESENT_1) { 1512 np = uv_read_local_mmr(UVH_NODE_PRESENT_1); 1513 pr_info("UV: NODE_PRESENT_1 = 0x%016lx\n", np); 1514 blade_update_min_max(np, 64, s_mask, &sock_min, &sock_max); 1515 } 1516 1517 /* Only update if we actually found some bits indicating blades present */ 1518 if (sock_max >= sock_min) { 1519 _min_socket = sock_min; 1520 _max_socket = sock_max; 1521 uv_pb = sock_max - sock_min + 1; 1522 } 1523 if (uv_possible_blades != uv_pb) 1524 uv_possible_blades = uv_pb; 1525 1526 pr_info("UV: number nodes/possible blades %d (%d - %d)\n", 1527 uv_pb, sock_min, sock_max); 1528 } 1529 1530 static int __init alloc_conv_table(int num_elem, unsigned short **table) 1531 { 1532 int i; 1533 size_t bytes; 1534 1535 bytes = num_elem * sizeof(*table[0]); 1536 *table = kmalloc(bytes, GFP_KERNEL); 1537 if (WARN_ON_ONCE(!*table)) 1538 return -ENOMEM; 1539 for (i = 0; i < num_elem; i++) 1540 ((unsigned short *)*table)[i] = SOCK_EMPTY; 1541 return 0; 1542 } 1543 1544 /* Remove conversion table if it's 1:1 */ 1545 #define FREE_1_TO_1_TABLE(tbl, min, max, max2) free_1_to_1_table(&tbl, #tbl, min, max, max2) 1546 1547 static void __init free_1_to_1_table(unsigned short **tp, char *tname, int min, int max, int max2) 1548 { 1549 int i; 1550 unsigned short *table = *tp; 1551 1552 if (table == NULL) 1553 return; 1554 if (max != max2) 1555 return; 1556 for (i = 0; i < max; i++) { 1557 if (i != table[i]) 1558 return; 1559 } 1560 kfree(table); 1561 *tp = NULL; 1562 pr_info("UV: %s is 1:1, conversion table removed\n", tname); 1563 } 1564 1565 /* 1566 * Build Socket Tables 1567 * If the number of nodes is >1 per socket, socket to node table will 1568 * contain lowest node number on that socket. 1569 */ 1570 static void __init build_socket_tables(void) 1571 { 1572 struct uv_gam_range_entry *gre = uv_gre_table; 1573 int nums, numn, nump; 1574 int cpu, i, lnid; 1575 int minsock = _min_socket; 1576 int maxsock = _max_socket; 1577 int minpnode = _min_pnode; 1578 int maxpnode = _max_pnode; 1579 1580 if (!gre) { 1581 if (is_uv2_hub() || is_uv3_hub()) { 1582 pr_info("UV: No UVsystab socket table, ignoring\n"); 1583 return; 1584 } 1585 pr_err("UV: Error: UVsystab address translations not available!\n"); 1586 WARN_ON_ONCE(!gre); 1587 return; 1588 } 1589 1590 numn = num_possible_nodes(); 1591 nump = maxpnode - minpnode + 1; 1592 nums = maxsock - minsock + 1; 1593 1594 /* Allocate and clear tables */ 1595 if ((alloc_conv_table(nump, &_pnode_to_socket) < 0) 1596 || (alloc_conv_table(nums, &_socket_to_pnode) < 0) 1597 || (alloc_conv_table(numn, &_node_to_socket) < 0) 1598 || (alloc_conv_table(nums, &_socket_to_node) < 0)) { 1599 kfree(_pnode_to_socket); 1600 kfree(_socket_to_pnode); 1601 kfree(_node_to_socket); 1602 return; 1603 } 1604 1605 /* Fill in pnode/node/addr conversion list values: */ 1606 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) { 1607 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) 1608 continue; 1609 i = gre->sockid - minsock; 1610 if (_socket_to_pnode[i] == SOCK_EMPTY) 1611 _socket_to_pnode[i] = gre->pnode; 1612 1613 i = gre->pnode - minpnode; 1614 if (_pnode_to_socket[i] == SOCK_EMPTY) 1615 _pnode_to_socket[i] = gre->sockid; 1616 1617 pr_info("UV: sid:%02x type:%d nasid:%04x pn:%02x pn2s:%2x\n", 1618 gre->sockid, gre->type, gre->nasid, 1619 _socket_to_pnode[gre->sockid - minsock], 1620 _pnode_to_socket[gre->pnode - minpnode]); 1621 } 1622 1623 /* Set socket -> node values: */ 1624 lnid = NUMA_NO_NODE; 1625 for_each_possible_cpu(cpu) { 1626 int nid = cpu_to_node(cpu); 1627 int apicid, sockid; 1628 1629 if (lnid == nid) 1630 continue; 1631 lnid = nid; 1632 1633 apicid = per_cpu(x86_cpu_to_apicid, cpu); 1634 sockid = apicid >> uv_cpuid.socketid_shift; 1635 1636 if (_socket_to_node[sockid - minsock] == SOCK_EMPTY) 1637 _socket_to_node[sockid - minsock] = nid; 1638 1639 if (_node_to_socket[nid] == SOCK_EMPTY) 1640 _node_to_socket[nid] = sockid; 1641 1642 pr_info("UV: sid:%02x: apicid:%04x socket:%02d node:%03x s2n:%03x\n", 1643 sockid, 1644 apicid, 1645 _node_to_socket[nid], 1646 nid, 1647 _socket_to_node[sockid - minsock]); 1648 } 1649 1650 /* 1651 * If e.g. socket id == pnode for all pnodes, 1652 * system runs faster by removing corresponding conversion table. 1653 */ 1654 FREE_1_TO_1_TABLE(_socket_to_node, _min_socket, nums, numn); 1655 FREE_1_TO_1_TABLE(_node_to_socket, _min_socket, nums, numn); 1656 FREE_1_TO_1_TABLE(_socket_to_pnode, _min_pnode, nums, nump); 1657 FREE_1_TO_1_TABLE(_pnode_to_socket, _min_pnode, nums, nump); 1658 } 1659 1660 /* Check which reboot to use */ 1661 static void check_efi_reboot(void) 1662 { 1663 /* If EFI reboot not available, use ACPI reboot */ 1664 if (!efi_enabled(EFI_BOOT)) 1665 reboot_type = BOOT_ACPI; 1666 } 1667 1668 /* 1669 * User proc fs file handling now deprecated. 1670 * Recommend using /sys/firmware/sgi_uv/... instead. 1671 */ 1672 static int __maybe_unused proc_hubbed_show(struct seq_file *file, void *data) 1673 { 1674 pr_notice_once("%s: using deprecated /proc/sgi_uv/hubbed, use /sys/firmware/sgi_uv/hub_type\n", 1675 current->comm); 1676 seq_printf(file, "0x%x\n", uv_hubbed_system); 1677 return 0; 1678 } 1679 1680 static int __maybe_unused proc_hubless_show(struct seq_file *file, void *data) 1681 { 1682 pr_notice_once("%s: using deprecated /proc/sgi_uv/hubless, use /sys/firmware/sgi_uv/hubless\n", 1683 current->comm); 1684 seq_printf(file, "0x%x\n", uv_hubless_system); 1685 return 0; 1686 } 1687 1688 static int __maybe_unused proc_archtype_show(struct seq_file *file, void *data) 1689 { 1690 pr_notice_once("%s: using deprecated /proc/sgi_uv/archtype, use /sys/firmware/sgi_uv/archtype\n", 1691 current->comm); 1692 seq_printf(file, "%s/%s\n", uv_archtype, oem_table_id); 1693 return 0; 1694 } 1695 1696 static __init void uv_setup_proc_files(int hubless) 1697 { 1698 struct proc_dir_entry *pde; 1699 1700 pde = proc_mkdir(UV_PROC_NODE, NULL); 1701 proc_create_single("archtype", 0, pde, proc_archtype_show); 1702 if (hubless) 1703 proc_create_single("hubless", 0, pde, proc_hubless_show); 1704 else 1705 proc_create_single("hubbed", 0, pde, proc_hubbed_show); 1706 } 1707 1708 /* Initialize UV hubless systems */ 1709 static __init int uv_system_init_hubless(void) 1710 { 1711 int rc; 1712 1713 /* Setup PCH NMI handler */ 1714 uv_nmi_setup_hubless(); 1715 1716 /* Init kernel/BIOS interface */ 1717 rc = uv_bios_init(); 1718 if (rc < 0) 1719 return rc; 1720 1721 /* Process UVsystab */ 1722 rc = decode_uv_systab(); 1723 if (rc < 0) 1724 return rc; 1725 1726 /* Set section block size for current node memory */ 1727 set_block_size(); 1728 1729 /* Create user access node */ 1730 if (rc >= 0) 1731 uv_setup_proc_files(1); 1732 1733 check_efi_reboot(); 1734 1735 return rc; 1736 } 1737 1738 static void __init uv_system_init_hub(void) 1739 { 1740 struct uv_hub_info_s hub_info = {0}; 1741 int bytes, cpu, nodeid, bid; 1742 unsigned short min_pnode = USHRT_MAX, max_pnode = 0; 1743 char *hub = is_uv5_hub() ? "UV500" : 1744 is_uv4_hub() ? "UV400" : 1745 is_uv3_hub() ? "UV300" : 1746 is_uv2_hub() ? "UV2000/3000" : NULL; 1747 struct uv_hub_info_s **uv_hub_info_list_blade; 1748 1749 if (!hub) { 1750 pr_err("UV: Unknown/unsupported UV hub\n"); 1751 return; 1752 } 1753 pr_info("UV: Found %s hub\n", hub); 1754 1755 map_low_mmrs(); 1756 1757 /* Get uv_systab for decoding, setup UV BIOS calls */ 1758 uv_bios_init(); 1759 1760 /* If there's an UVsystab problem then abort UV init: */ 1761 if (decode_uv_systab() < 0) { 1762 pr_err("UV: Mangled UVsystab format\n"); 1763 return; 1764 } 1765 1766 build_socket_tables(); 1767 build_uv_gr_table(); 1768 set_block_size(); 1769 uv_init_hub_info(&hub_info); 1770 /* If UV2 or UV3 may need to get # blades from HW */ 1771 if (is_uv(UV2|UV3) && !uv_gre_table) 1772 boot_init_possible_blades(&hub_info); 1773 else 1774 /* min/max sockets set in decode_gam_rng_tbl */ 1775 uv_possible_blades = (_max_socket - _min_socket) + 1; 1776 1777 /* uv_num_possible_blades() is really the hub count: */ 1778 pr_info("UV: Found %d hubs, %d nodes, %d CPUs\n", uv_num_possible_blades(), num_possible_nodes(), num_possible_cpus()); 1779 1780 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, &sn_region_size, &system_serial_number); 1781 hub_info.coherency_domain_number = sn_coherency_id; 1782 uv_rtc_init(); 1783 1784 /* 1785 * __uv_hub_info_list[] is indexed by node, but there is only 1786 * one hub_info structure per blade. First, allocate one 1787 * structure per blade. Further down we create a per-node 1788 * table (__uv_hub_info_list[]) pointing to hub_info 1789 * structures for the correct blade. 1790 */ 1791 1792 bytes = sizeof(void *) * uv_num_possible_blades(); 1793 uv_hub_info_list_blade = kzalloc(bytes, GFP_KERNEL); 1794 if (WARN_ON_ONCE(!uv_hub_info_list_blade)) 1795 return; 1796 1797 bytes = sizeof(struct uv_hub_info_s); 1798 for_each_possible_blade(bid) { 1799 struct uv_hub_info_s *new_hub; 1800 1801 /* Allocate & fill new per hub info list */ 1802 new_hub = (bid == 0) ? &uv_hub_info_node0 1803 : kzalloc_node(bytes, GFP_KERNEL, uv_blade_to_node(bid)); 1804 if (WARN_ON_ONCE(!new_hub)) { 1805 /* do not kfree() bid 0, which is statically allocated */ 1806 while (--bid > 0) 1807 kfree(uv_hub_info_list_blade[bid]); 1808 kfree(uv_hub_info_list_blade); 1809 return; 1810 } 1811 1812 uv_hub_info_list_blade[bid] = new_hub; 1813 *new_hub = hub_info; 1814 1815 /* Use information from GAM table if available: */ 1816 if (uv_gre_table) 1817 new_hub->pnode = uv_blade_to_pnode(bid); 1818 else /* Or fill in during CPU loop: */ 1819 new_hub->pnode = 0xffff; 1820 1821 new_hub->numa_blade_id = bid; 1822 new_hub->memory_nid = NUMA_NO_NODE; 1823 new_hub->nr_possible_cpus = 0; 1824 new_hub->nr_online_cpus = 0; 1825 } 1826 1827 /* 1828 * Now populate __uv_hub_info_list[] for each node with the 1829 * pointer to the struct for the blade it resides on. 1830 */ 1831 1832 bytes = sizeof(void *) * num_possible_nodes(); 1833 __uv_hub_info_list = kzalloc(bytes, GFP_KERNEL); 1834 if (WARN_ON_ONCE(!__uv_hub_info_list)) { 1835 for_each_possible_blade(bid) 1836 /* bid 0 is statically allocated */ 1837 if (bid != 0) 1838 kfree(uv_hub_info_list_blade[bid]); 1839 kfree(uv_hub_info_list_blade); 1840 return; 1841 } 1842 1843 for_each_node(nodeid) 1844 __uv_hub_info_list[nodeid] = uv_hub_info_list_blade[uv_node_to_blade_id(nodeid)]; 1845 1846 /* Initialize per CPU info: */ 1847 for_each_possible_cpu(cpu) { 1848 int apicid = early_per_cpu(x86_cpu_to_apicid, cpu); 1849 unsigned short bid; 1850 unsigned short pnode; 1851 1852 pnode = uv_apicid_to_pnode(apicid); 1853 bid = uv_pnode_to_socket(pnode) - _min_socket; 1854 1855 uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list_blade[bid]; 1856 uv_cpu_info_per(cpu)->blade_cpu_id = uv_cpu_hub_info(cpu)->nr_possible_cpus++; 1857 if (uv_cpu_hub_info(cpu)->memory_nid == NUMA_NO_NODE) 1858 uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu); 1859 1860 if (uv_cpu_hub_info(cpu)->pnode == 0xffff) 1861 uv_cpu_hub_info(cpu)->pnode = pnode; 1862 } 1863 1864 for_each_possible_blade(bid) { 1865 unsigned short pnode = uv_hub_info_list_blade[bid]->pnode; 1866 1867 if (pnode == 0xffff) 1868 continue; 1869 1870 min_pnode = min(pnode, min_pnode); 1871 max_pnode = max(pnode, max_pnode); 1872 pr_info("UV: HUB:%2d pn:%02x nrcpus:%d\n", 1873 bid, 1874 uv_hub_info_list_blade[bid]->pnode, 1875 uv_hub_info_list_blade[bid]->nr_possible_cpus); 1876 } 1877 1878 pr_info("UV: min_pnode:%02x max_pnode:%02x\n", min_pnode, max_pnode); 1879 map_gru_high(max_pnode); 1880 map_mmr_high(max_pnode); 1881 map_mmioh_high(min_pnode, max_pnode); 1882 1883 kfree(uv_hub_info_list_blade); 1884 uv_hub_info_list_blade = NULL; 1885 1886 uv_nmi_setup(); 1887 uv_cpu_init(); 1888 uv_setup_proc_files(0); 1889 1890 /* Register Legacy VGA I/O redirection handler: */ 1891 pci_register_set_vga_state(uv_set_vga_state); 1892 1893 check_efi_reboot(); 1894 } 1895 1896 /* 1897 * There is a different code path needed to initialize a UV system that does 1898 * not have a "UV HUB" (referred to as "hubless"). 1899 */ 1900 void __init uv_system_init(void) 1901 { 1902 if (likely(!is_uv_system() && !is_uv_hubless(1))) 1903 return; 1904 1905 if (is_uv_system()) 1906 uv_system_init_hub(); 1907 else 1908 uv_system_init_hubless(); 1909 } 1910 1911 apic_driver(apic_x2apic_uv_x); 1912