1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * SGI UV APIC functions (note: not an Intel compatible APIC) 7 * 8 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved. 9 */ 10 #include <linux/cpumask.h> 11 #include <linux/hardirq.h> 12 #include <linux/proc_fs.h> 13 #include <linux/threads.h> 14 #include <linux/kernel.h> 15 #include <linux/export.h> 16 #include <linux/string.h> 17 #include <linux/ctype.h> 18 #include <linux/sched.h> 19 #include <linux/timer.h> 20 #include <linux/slab.h> 21 #include <linux/cpu.h> 22 #include <linux/init.h> 23 #include <linux/io.h> 24 #include <linux/pci.h> 25 #include <linux/kdebug.h> 26 #include <linux/delay.h> 27 #include <linux/crash_dump.h> 28 #include <linux/reboot.h> 29 30 #include <asm/uv/uv_mmrs.h> 31 #include <asm/uv/uv_hub.h> 32 #include <asm/current.h> 33 #include <asm/pgtable.h> 34 #include <asm/uv/bios.h> 35 #include <asm/uv/uv.h> 36 #include <asm/apic.h> 37 #include <asm/e820/api.h> 38 #include <asm/ipi.h> 39 #include <asm/smp.h> 40 #include <asm/x86_init.h> 41 #include <asm/nmi.h> 42 43 DEFINE_PER_CPU(int, x2apic_extra_bits); 44 45 static enum uv_system_type uv_system_type; 46 static bool uv_hubless_system; 47 static u64 gru_start_paddr, gru_end_paddr; 48 static u64 gru_dist_base, gru_first_node_paddr = -1LL, gru_last_node_paddr; 49 static u64 gru_dist_lmask, gru_dist_umask; 50 static union uvh_apicid uvh_apicid; 51 52 /* Information derived from CPUID: */ 53 static struct { 54 unsigned int apicid_shift; 55 unsigned int apicid_mask; 56 unsigned int socketid_shift; /* aka pnode_shift for UV1/2/3 */ 57 unsigned int pnode_mask; 58 unsigned int gpa_shift; 59 unsigned int gnode_shift; 60 } uv_cpuid; 61 62 int uv_min_hub_revision_id; 63 EXPORT_SYMBOL_GPL(uv_min_hub_revision_id); 64 65 unsigned int uv_apicid_hibits; 66 EXPORT_SYMBOL_GPL(uv_apicid_hibits); 67 68 static struct apic apic_x2apic_uv_x; 69 static struct uv_hub_info_s uv_hub_info_node0; 70 71 /* Set this to use hardware error handler instead of kernel panic: */ 72 static int disable_uv_undefined_panic = 1; 73 74 unsigned long uv_undefined(char *str) 75 { 76 if (likely(!disable_uv_undefined_panic)) 77 panic("UV: error: undefined MMR: %s\n", str); 78 else 79 pr_crit("UV: error: undefined MMR: %s\n", str); 80 81 /* Cause a machine fault: */ 82 return ~0ul; 83 } 84 EXPORT_SYMBOL(uv_undefined); 85 86 static unsigned long __init uv_early_read_mmr(unsigned long addr) 87 { 88 unsigned long val, *mmr; 89 90 mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr)); 91 val = *mmr; 92 early_iounmap(mmr, sizeof(*mmr)); 93 94 return val; 95 } 96 97 static inline bool is_GRU_range(u64 start, u64 end) 98 { 99 if (gru_dist_base) { 100 u64 su = start & gru_dist_umask; /* Upper (incl pnode) bits */ 101 u64 sl = start & gru_dist_lmask; /* Base offset bits */ 102 u64 eu = end & gru_dist_umask; 103 u64 el = end & gru_dist_lmask; 104 105 /* Must reside completely within a single GRU range: */ 106 return (sl == gru_dist_base && el == gru_dist_base && 107 su >= gru_first_node_paddr && 108 su <= gru_last_node_paddr && 109 eu == su); 110 } else { 111 return start >= gru_start_paddr && end <= gru_end_paddr; 112 } 113 } 114 115 static bool uv_is_untracked_pat_range(u64 start, u64 end) 116 { 117 return is_ISA_range(start, end) || is_GRU_range(start, end); 118 } 119 120 static int __init early_get_pnodeid(void) 121 { 122 union uvh_node_id_u node_id; 123 union uvh_rh_gam_config_mmr_u m_n_config; 124 int pnode; 125 126 /* Currently, all blades have same revision number */ 127 node_id.v = uv_early_read_mmr(UVH_NODE_ID); 128 m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR); 129 uv_min_hub_revision_id = node_id.s.revision; 130 131 switch (node_id.s.part_number) { 132 case UV2_HUB_PART_NUMBER: 133 case UV2_HUB_PART_NUMBER_X: 134 uv_min_hub_revision_id += UV2_HUB_REVISION_BASE - 1; 135 break; 136 case UV3_HUB_PART_NUMBER: 137 case UV3_HUB_PART_NUMBER_X: 138 uv_min_hub_revision_id += UV3_HUB_REVISION_BASE; 139 break; 140 case UV4_HUB_PART_NUMBER: 141 uv_min_hub_revision_id += UV4_HUB_REVISION_BASE - 1; 142 uv_cpuid.gnode_shift = 2; /* min partition is 4 sockets */ 143 break; 144 } 145 146 uv_hub_info->hub_revision = uv_min_hub_revision_id; 147 uv_cpuid.pnode_mask = (1 << m_n_config.s.n_skt) - 1; 148 pnode = (node_id.s.node_id >> 1) & uv_cpuid.pnode_mask; 149 uv_cpuid.gpa_shift = 46; /* Default unless changed */ 150 151 pr_info("UV: rev:%d part#:%x nodeid:%04x n_skt:%d pnmsk:%x pn:%x\n", 152 node_id.s.revision, node_id.s.part_number, node_id.s.node_id, 153 m_n_config.s.n_skt, uv_cpuid.pnode_mask, pnode); 154 return pnode; 155 } 156 157 static void __init uv_tsc_check_sync(void) 158 { 159 u64 mmr; 160 int sync_state; 161 int mmr_shift; 162 char *state; 163 bool valid; 164 165 /* Accommodate different UV arch BIOSes */ 166 mmr = uv_early_read_mmr(UVH_TSC_SYNC_MMR); 167 mmr_shift = 168 is_uv1_hub() ? 0 : 169 is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT; 170 if (mmr_shift) 171 sync_state = (mmr >> mmr_shift) & UVH_TSC_SYNC_MASK; 172 else 173 sync_state = 0; 174 175 switch (sync_state) { 176 case UVH_TSC_SYNC_VALID: 177 state = "in sync"; 178 valid = true; 179 break; 180 181 case UVH_TSC_SYNC_INVALID: 182 state = "unstable"; 183 valid = false; 184 break; 185 default: 186 state = "unknown: assuming valid"; 187 valid = true; 188 break; 189 } 190 pr_info("UV: TSC sync state from BIOS:0%d(%s)\n", sync_state, state); 191 192 /* Mark flag that says TSC != 0 is valid for socket 0 */ 193 if (valid) 194 mark_tsc_async_resets("UV BIOS"); 195 else 196 mark_tsc_unstable("UV BIOS"); 197 } 198 199 /* [Copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */ 200 201 #define SMT_LEVEL 0 /* Leaf 0xb SMT level */ 202 #define INVALID_TYPE 0 /* Leaf 0xb sub-leaf types */ 203 #define SMT_TYPE 1 204 #define CORE_TYPE 2 205 #define LEAFB_SUBTYPE(ecx) (((ecx) >> 8) & 0xff) 206 #define BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f) 207 208 static void set_x2apic_bits(void) 209 { 210 unsigned int eax, ebx, ecx, edx, sub_index; 211 unsigned int sid_shift; 212 213 cpuid(0, &eax, &ebx, &ecx, &edx); 214 if (eax < 0xb) { 215 pr_info("UV: CPU does not have CPUID.11\n"); 216 return; 217 } 218 219 cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx); 220 if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) { 221 pr_info("UV: CPUID.11 not implemented\n"); 222 return; 223 } 224 225 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax); 226 sub_index = 1; 227 do { 228 cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx); 229 if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) { 230 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax); 231 break; 232 } 233 sub_index++; 234 } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE); 235 236 uv_cpuid.apicid_shift = 0; 237 uv_cpuid.apicid_mask = (~(-1 << sid_shift)); 238 uv_cpuid.socketid_shift = sid_shift; 239 } 240 241 static void __init early_get_apic_socketid_shift(void) 242 { 243 if (is_uv2_hub() || is_uv3_hub()) 244 uvh_apicid.v = uv_early_read_mmr(UVH_APICID); 245 246 set_x2apic_bits(); 247 248 pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n", uv_cpuid.apicid_shift, uv_cpuid.apicid_mask); 249 pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n", uv_cpuid.socketid_shift, uv_cpuid.pnode_mask); 250 } 251 252 /* 253 * Add an extra bit as dictated by bios to the destination apicid of 254 * interrupts potentially passing through the UV HUB. This prevents 255 * a deadlock between interrupts and IO port operations. 256 */ 257 static void __init uv_set_apicid_hibit(void) 258 { 259 union uv1h_lb_target_physical_apic_id_mask_u apicid_mask; 260 261 if (is_uv1_hub()) { 262 apicid_mask.v = uv_early_read_mmr(UV1H_LB_TARGET_PHYSICAL_APIC_ID_MASK); 263 uv_apicid_hibits = apicid_mask.s1.bit_enables & UV_APICID_HIBIT_MASK; 264 } 265 } 266 267 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id) 268 { 269 int pnodeid; 270 int uv_apic; 271 272 if (strncmp(oem_id, "SGI", 3) != 0) { 273 if (strncmp(oem_id, "NSGI", 4) == 0) { 274 uv_hubless_system = true; 275 pr_info("UV: OEM IDs %s/%s, HUBLESS\n", 276 oem_id, oem_table_id); 277 } 278 return 0; 279 } 280 281 if (numa_off) { 282 pr_err("UV: NUMA is off, disabling UV support\n"); 283 return 0; 284 } 285 286 /* Set up early hub type field in uv_hub_info for Node 0 */ 287 uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0; 288 289 /* 290 * Determine UV arch type. 291 * SGI: UV100/1000 292 * SGI2: UV2000/3000 293 * SGI3: UV300 (truncated to 4 chars because of different varieties) 294 * SGI4: UV400 (truncated to 4 chars because of different varieties) 295 */ 296 uv_hub_info->hub_revision = 297 !strncmp(oem_id, "SGI4", 4) ? UV4_HUB_REVISION_BASE : 298 !strncmp(oem_id, "SGI3", 4) ? UV3_HUB_REVISION_BASE : 299 !strcmp(oem_id, "SGI2") ? UV2_HUB_REVISION_BASE : 300 !strcmp(oem_id, "SGI") ? UV1_HUB_REVISION_BASE : 0; 301 302 if (uv_hub_info->hub_revision == 0) 303 goto badbios; 304 305 pnodeid = early_get_pnodeid(); 306 early_get_apic_socketid_shift(); 307 308 x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range; 309 x86_platform.nmi_init = uv_nmi_init; 310 311 if (!strcmp(oem_table_id, "UVX")) { 312 /* This is the most common hardware variant: */ 313 uv_system_type = UV_X2APIC; 314 uv_apic = 0; 315 316 } else if (!strcmp(oem_table_id, "UVH")) { 317 /* Only UV1 systems: */ 318 uv_system_type = UV_NON_UNIQUE_APIC; 319 __this_cpu_write(x2apic_extra_bits, pnodeid << uvh_apicid.s.pnode_shift); 320 uv_set_apicid_hibit(); 321 uv_apic = 1; 322 323 } else if (!strcmp(oem_table_id, "UVL")) { 324 /* Only used for very small systems: */ 325 uv_system_type = UV_LEGACY_APIC; 326 uv_apic = 0; 327 328 } else { 329 goto badbios; 330 } 331 332 pr_info("UV: OEM IDs %s/%s, System/HUB Types %d/%d, uv_apic %d\n", oem_id, oem_table_id, uv_system_type, uv_min_hub_revision_id, uv_apic); 333 uv_tsc_check_sync(); 334 335 return uv_apic; 336 337 badbios: 338 pr_err("UV: OEM_ID:%s OEM_TABLE_ID:%s\n", oem_id, oem_table_id); 339 pr_err("Current BIOS not supported, update kernel and/or BIOS\n"); 340 BUG(); 341 } 342 343 enum uv_system_type get_uv_system_type(void) 344 { 345 return uv_system_type; 346 } 347 348 int is_uv_system(void) 349 { 350 return uv_system_type != UV_NONE; 351 } 352 EXPORT_SYMBOL_GPL(is_uv_system); 353 354 int is_uv_hubless(void) 355 { 356 return uv_hubless_system; 357 } 358 EXPORT_SYMBOL_GPL(is_uv_hubless); 359 360 void **__uv_hub_info_list; 361 EXPORT_SYMBOL_GPL(__uv_hub_info_list); 362 363 DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info); 364 EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info); 365 366 short uv_possible_blades; 367 EXPORT_SYMBOL_GPL(uv_possible_blades); 368 369 unsigned long sn_rtc_cycles_per_second; 370 EXPORT_SYMBOL(sn_rtc_cycles_per_second); 371 372 /* The following values are used for the per node hub info struct */ 373 static __initdata unsigned short *_node_to_pnode; 374 static __initdata unsigned short _min_socket, _max_socket; 375 static __initdata unsigned short _min_pnode, _max_pnode, _gr_table_len; 376 static __initdata struct uv_gam_range_entry *uv_gre_table; 377 static __initdata struct uv_gam_parameters *uv_gp_table; 378 static __initdata unsigned short *_socket_to_node; 379 static __initdata unsigned short *_socket_to_pnode; 380 static __initdata unsigned short *_pnode_to_socket; 381 382 static __initdata struct uv_gam_range_s *_gr_table; 383 384 #define SOCK_EMPTY ((unsigned short)~0) 385 386 extern int uv_hub_info_version(void) 387 { 388 return UV_HUB_INFO_VERSION; 389 } 390 EXPORT_SYMBOL(uv_hub_info_version); 391 392 /* Build GAM range lookup table: */ 393 static __init void build_uv_gr_table(void) 394 { 395 struct uv_gam_range_entry *gre = uv_gre_table; 396 struct uv_gam_range_s *grt; 397 unsigned long last_limit = 0, ram_limit = 0; 398 int bytes, i, sid, lsid = -1, indx = 0, lindx = -1; 399 400 if (!gre) 401 return; 402 403 bytes = _gr_table_len * sizeof(struct uv_gam_range_s); 404 grt = kzalloc(bytes, GFP_KERNEL); 405 BUG_ON(!grt); 406 _gr_table = grt; 407 408 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) { 409 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) { 410 if (!ram_limit) { 411 /* Mark hole between RAM/non-RAM: */ 412 ram_limit = last_limit; 413 last_limit = gre->limit; 414 lsid++; 415 continue; 416 } 417 last_limit = gre->limit; 418 pr_info("UV: extra hole in GAM RE table @%d\n", (int)(gre - uv_gre_table)); 419 continue; 420 } 421 if (_max_socket < gre->sockid) { 422 pr_err("UV: GAM table sockid(%d) too large(>%d) @%d\n", gre->sockid, _max_socket, (int)(gre - uv_gre_table)); 423 continue; 424 } 425 sid = gre->sockid - _min_socket; 426 if (lsid < sid) { 427 /* New range: */ 428 grt = &_gr_table[indx]; 429 grt->base = lindx; 430 grt->nasid = gre->nasid; 431 grt->limit = last_limit = gre->limit; 432 lsid = sid; 433 lindx = indx++; 434 continue; 435 } 436 /* Update range: */ 437 if (lsid == sid && !ram_limit) { 438 /* .. if contiguous: */ 439 if (grt->limit == last_limit) { 440 grt->limit = last_limit = gre->limit; 441 continue; 442 } 443 } 444 /* Non-contiguous RAM range: */ 445 if (!ram_limit) { 446 grt++; 447 grt->base = lindx; 448 grt->nasid = gre->nasid; 449 grt->limit = last_limit = gre->limit; 450 continue; 451 } 452 /* Non-contiguous/non-RAM: */ 453 grt++; 454 /* base is this entry */ 455 grt->base = grt - _gr_table; 456 grt->nasid = gre->nasid; 457 grt->limit = last_limit = gre->limit; 458 lsid++; 459 } 460 461 /* Shorten table if possible */ 462 grt++; 463 i = grt - _gr_table; 464 if (i < _gr_table_len) { 465 void *ret; 466 467 bytes = i * sizeof(struct uv_gam_range_s); 468 ret = krealloc(_gr_table, bytes, GFP_KERNEL); 469 if (ret) { 470 _gr_table = ret; 471 _gr_table_len = i; 472 } 473 } 474 475 /* Display resultant GAM range table: */ 476 for (i = 0, grt = _gr_table; i < _gr_table_len; i++, grt++) { 477 unsigned long start, end; 478 int gb = grt->base; 479 480 start = gb < 0 ? 0 : (unsigned long)_gr_table[gb].limit << UV_GAM_RANGE_SHFT; 481 end = (unsigned long)grt->limit << UV_GAM_RANGE_SHFT; 482 483 pr_info("UV: GAM Range %2d %04x 0x%013lx-0x%013lx (%d)\n", i, grt->nasid, start, end, gb); 484 } 485 } 486 487 static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip) 488 { 489 unsigned long val; 490 int pnode; 491 492 pnode = uv_apicid_to_pnode(phys_apicid); 493 phys_apicid |= uv_apicid_hibits; 494 495 val = (1UL << UVH_IPI_INT_SEND_SHFT) | 496 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | 497 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | 498 APIC_DM_INIT; 499 500 uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 501 502 val = (1UL << UVH_IPI_INT_SEND_SHFT) | 503 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | 504 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | 505 APIC_DM_STARTUP; 506 507 uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 508 509 return 0; 510 } 511 512 static void uv_send_IPI_one(int cpu, int vector) 513 { 514 unsigned long apicid; 515 int pnode; 516 517 apicid = per_cpu(x86_cpu_to_apicid, cpu); 518 pnode = uv_apicid_to_pnode(apicid); 519 uv_hub_send_ipi(pnode, apicid, vector); 520 } 521 522 static void uv_send_IPI_mask(const struct cpumask *mask, int vector) 523 { 524 unsigned int cpu; 525 526 for_each_cpu(cpu, mask) 527 uv_send_IPI_one(cpu, vector); 528 } 529 530 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) 531 { 532 unsigned int this_cpu = smp_processor_id(); 533 unsigned int cpu; 534 535 for_each_cpu(cpu, mask) { 536 if (cpu != this_cpu) 537 uv_send_IPI_one(cpu, vector); 538 } 539 } 540 541 static void uv_send_IPI_allbutself(int vector) 542 { 543 unsigned int this_cpu = smp_processor_id(); 544 unsigned int cpu; 545 546 for_each_online_cpu(cpu) { 547 if (cpu != this_cpu) 548 uv_send_IPI_one(cpu, vector); 549 } 550 } 551 552 static void uv_send_IPI_all(int vector) 553 { 554 uv_send_IPI_mask(cpu_online_mask, vector); 555 } 556 557 static int uv_apic_id_valid(int apicid) 558 { 559 return 1; 560 } 561 562 static int uv_apic_id_registered(void) 563 { 564 return 1; 565 } 566 567 static void uv_init_apic_ldr(void) 568 { 569 } 570 571 static u32 apic_uv_calc_apicid(unsigned int cpu) 572 { 573 return apic_default_calc_apicid(cpu) | uv_apicid_hibits; 574 } 575 576 static unsigned int x2apic_get_apic_id(unsigned long x) 577 { 578 unsigned int id; 579 580 WARN_ON(preemptible() && num_online_cpus() > 1); 581 id = x | __this_cpu_read(x2apic_extra_bits); 582 583 return id; 584 } 585 586 static u32 set_apic_id(unsigned int id) 587 { 588 /* CHECKME: Do we need to mask out the xapic extra bits? */ 589 return id; 590 } 591 592 static unsigned int uv_read_apic_id(void) 593 { 594 return x2apic_get_apic_id(apic_read(APIC_ID)); 595 } 596 597 static int uv_phys_pkg_id(int initial_apicid, int index_msb) 598 { 599 return uv_read_apic_id() >> index_msb; 600 } 601 602 static void uv_send_IPI_self(int vector) 603 { 604 apic_write(APIC_SELF_IPI, vector); 605 } 606 607 static int uv_probe(void) 608 { 609 return apic == &apic_x2apic_uv_x; 610 } 611 612 static struct apic apic_x2apic_uv_x __ro_after_init = { 613 614 .name = "UV large system", 615 .probe = uv_probe, 616 .acpi_madt_oem_check = uv_acpi_madt_oem_check, 617 .apic_id_valid = uv_apic_id_valid, 618 .apic_id_registered = uv_apic_id_registered, 619 620 .irq_delivery_mode = dest_Fixed, 621 .irq_dest_mode = 0, /* Physical */ 622 623 .disable_esr = 0, 624 .dest_logical = APIC_DEST_LOGICAL, 625 .check_apicid_used = NULL, 626 627 .init_apic_ldr = uv_init_apic_ldr, 628 629 .ioapic_phys_id_map = NULL, 630 .setup_apic_routing = NULL, 631 .cpu_present_to_apicid = default_cpu_present_to_apicid, 632 .apicid_to_cpu_present = NULL, 633 .check_phys_apicid_present = default_check_phys_apicid_present, 634 .phys_pkg_id = uv_phys_pkg_id, 635 636 .get_apic_id = x2apic_get_apic_id, 637 .set_apic_id = set_apic_id, 638 639 .calc_dest_apicid = apic_uv_calc_apicid, 640 641 .send_IPI = uv_send_IPI_one, 642 .send_IPI_mask = uv_send_IPI_mask, 643 .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself, 644 .send_IPI_allbutself = uv_send_IPI_allbutself, 645 .send_IPI_all = uv_send_IPI_all, 646 .send_IPI_self = uv_send_IPI_self, 647 648 .wakeup_secondary_cpu = uv_wakeup_secondary, 649 .inquire_remote_apic = NULL, 650 651 .read = native_apic_msr_read, 652 .write = native_apic_msr_write, 653 .eoi_write = native_apic_msr_eoi_write, 654 .icr_read = native_x2apic_icr_read, 655 .icr_write = native_x2apic_icr_write, 656 .wait_icr_idle = native_x2apic_wait_icr_idle, 657 .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle, 658 }; 659 660 static void set_x2apic_extra_bits(int pnode) 661 { 662 __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift); 663 } 664 665 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH 3 666 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 667 668 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size) 669 { 670 union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias; 671 union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect; 672 unsigned long m_redirect; 673 unsigned long m_overlay; 674 int i; 675 676 for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) { 677 switch (i) { 678 case 0: 679 m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR; 680 m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR; 681 break; 682 case 1: 683 m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR; 684 m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR; 685 break; 686 case 2: 687 m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR; 688 m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR; 689 break; 690 } 691 alias.v = uv_read_local_mmr(m_overlay); 692 if (alias.s.enable && alias.s.base == 0) { 693 *size = (1UL << alias.s.m_alias); 694 redirect.v = uv_read_local_mmr(m_redirect); 695 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT; 696 return; 697 } 698 } 699 *base = *size = 0; 700 } 701 702 enum map_type {map_wb, map_uc}; 703 704 static __init void map_high(char *id, unsigned long base, int pshift, int bshift, int max_pnode, enum map_type map_type) 705 { 706 unsigned long bytes, paddr; 707 708 paddr = base << pshift; 709 bytes = (1UL << bshift) * (max_pnode + 1); 710 if (!paddr) { 711 pr_info("UV: Map %s_HI base address NULL\n", id); 712 return; 713 } 714 pr_debug("UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, paddr + bytes); 715 if (map_type == map_uc) 716 init_extra_mapping_uc(paddr, bytes); 717 else 718 init_extra_mapping_wb(paddr, bytes); 719 } 720 721 static __init void map_gru_distributed(unsigned long c) 722 { 723 union uvh_rh_gam_gru_overlay_config_mmr_u gru; 724 u64 paddr; 725 unsigned long bytes; 726 int nid; 727 728 gru.v = c; 729 730 /* Only base bits 42:28 relevant in dist mode */ 731 gru_dist_base = gru.v & 0x000007fff0000000UL; 732 if (!gru_dist_base) { 733 pr_info("UV: Map GRU_DIST base address NULL\n"); 734 return; 735 } 736 737 bytes = 1UL << UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT; 738 gru_dist_lmask = ((1UL << uv_hub_info->m_val) - 1) & ~(bytes - 1); 739 gru_dist_umask = ~((1UL << uv_hub_info->m_val) - 1); 740 gru_dist_base &= gru_dist_lmask; /* Clear bits above M */ 741 742 for_each_online_node(nid) { 743 paddr = ((u64)uv_node_to_pnode(nid) << uv_hub_info->m_val) | 744 gru_dist_base; 745 init_extra_mapping_wb(paddr, bytes); 746 gru_first_node_paddr = min(paddr, gru_first_node_paddr); 747 gru_last_node_paddr = max(paddr, gru_last_node_paddr); 748 } 749 750 /* Save upper (63:M) bits of address only for is_GRU_range */ 751 gru_first_node_paddr &= gru_dist_umask; 752 gru_last_node_paddr &= gru_dist_umask; 753 754 pr_debug("UV: Map GRU_DIST base 0x%016llx 0x%016llx - 0x%016llx\n", gru_dist_base, gru_first_node_paddr, gru_last_node_paddr); 755 } 756 757 static __init void map_gru_high(int max_pnode) 758 { 759 union uvh_rh_gam_gru_overlay_config_mmr_u gru; 760 int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT; 761 unsigned long mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK; 762 unsigned long base; 763 764 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR); 765 if (!gru.s.enable) { 766 pr_info("UV: GRU disabled\n"); 767 return; 768 } 769 770 if (is_uv3_hub() && gru.s3.mode) { 771 map_gru_distributed(gru.v); 772 return; 773 } 774 775 base = (gru.v & mask) >> shift; 776 map_high("GRU", base, shift, shift, max_pnode, map_wb); 777 gru_start_paddr = ((u64)base << shift); 778 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1); 779 } 780 781 static __init void map_mmr_high(int max_pnode) 782 { 783 union uvh_rh_gam_mmr_overlay_config_mmr_u mmr; 784 int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT; 785 786 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR); 787 if (mmr.s.enable) 788 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc); 789 else 790 pr_info("UV: MMR disabled\n"); 791 } 792 793 /* 794 * This commonality works because both 0 & 1 versions of the MMIOH OVERLAY 795 * and REDIRECT MMR regs are exactly the same on UV3. 796 */ 797 struct mmioh_config { 798 unsigned long overlay; 799 unsigned long redirect; 800 char *id; 801 }; 802 803 static __initdata struct mmioh_config mmiohs[] = { 804 { 805 UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR, 806 UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR, 807 "MMIOH0" 808 }, 809 { 810 UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG1_MMR, 811 UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG1_MMR, 812 "MMIOH1" 813 }, 814 }; 815 816 /* UV3 & UV4 have identical MMIOH overlay configs */ 817 static __init void map_mmioh_high_uv3(int index, int min_pnode, int max_pnode) 818 { 819 union uv3h_rh_gam_mmioh_overlay_config0_mmr_u overlay; 820 unsigned long mmr; 821 unsigned long base; 822 int i, n, shift, m_io, max_io; 823 int nasid, lnasid, fi, li; 824 char *id; 825 826 id = mmiohs[index].id; 827 overlay.v = uv_read_local_mmr(mmiohs[index].overlay); 828 829 pr_info("UV: %s overlay 0x%lx base:0x%x m_io:%d\n", id, overlay.v, overlay.s3.base, overlay.s3.m_io); 830 if (!overlay.s3.enable) { 831 pr_info("UV: %s disabled\n", id); 832 return; 833 } 834 835 shift = UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR_BASE_SHFT; 836 base = (unsigned long)overlay.s3.base; 837 m_io = overlay.s3.m_io; 838 mmr = mmiohs[index].redirect; 839 n = UV3H_RH_GAM_MMIOH_REDIRECT_CONFIG0_MMR_DEPTH; 840 /* Convert to NASID: */ 841 min_pnode *= 2; 842 max_pnode *= 2; 843 max_io = lnasid = fi = li = -1; 844 845 for (i = 0; i < n; i++) { 846 union uv3h_rh_gam_mmioh_redirect_config0_mmr_u redirect; 847 848 redirect.v = uv_read_local_mmr(mmr + i * 8); 849 nasid = redirect.s3.nasid; 850 /* Invalid NASID: */ 851 if (nasid < min_pnode || max_pnode < nasid) 852 nasid = -1; 853 854 if (nasid == lnasid) { 855 li = i; 856 /* Last entry check: */ 857 if (i != n-1) 858 continue; 859 } 860 861 /* Check if we have a cached (or last) redirect to print: */ 862 if (lnasid != -1 || (i == n-1 && nasid != -1)) { 863 unsigned long addr1, addr2; 864 int f, l; 865 866 if (lnasid == -1) { 867 f = l = i; 868 lnasid = nasid; 869 } else { 870 f = fi; 871 l = li; 872 } 873 addr1 = (base << shift) + f * (1ULL << m_io); 874 addr2 = (base << shift) + (l + 1) * (1ULL << m_io); 875 pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n", id, fi, li, lnasid, addr1, addr2); 876 if (max_io < l) 877 max_io = l; 878 } 879 fi = li = i; 880 lnasid = nasid; 881 } 882 883 pr_info("UV: %s base:0x%lx shift:%d M_IO:%d MAX_IO:%d\n", id, base, shift, m_io, max_io); 884 885 if (max_io >= 0) 886 map_high(id, base, shift, m_io, max_io, map_uc); 887 } 888 889 static __init void map_mmioh_high(int min_pnode, int max_pnode) 890 { 891 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh; 892 unsigned long mmr, base; 893 int shift, enable, m_io, n_io; 894 895 if (is_uv3_hub() || is_uv4_hub()) { 896 /* Map both MMIOH regions: */ 897 map_mmioh_high_uv3(0, min_pnode, max_pnode); 898 map_mmioh_high_uv3(1, min_pnode, max_pnode); 899 return; 900 } 901 902 if (is_uv1_hub()) { 903 mmr = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR; 904 shift = UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT; 905 mmioh.v = uv_read_local_mmr(mmr); 906 enable = !!mmioh.s1.enable; 907 base = mmioh.s1.base; 908 m_io = mmioh.s1.m_io; 909 n_io = mmioh.s1.n_io; 910 } else if (is_uv2_hub()) { 911 mmr = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR; 912 shift = UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT; 913 mmioh.v = uv_read_local_mmr(mmr); 914 enable = !!mmioh.s2.enable; 915 base = mmioh.s2.base; 916 m_io = mmioh.s2.m_io; 917 n_io = mmioh.s2.n_io; 918 } else { 919 return; 920 } 921 922 if (enable) { 923 max_pnode &= (1 << n_io) - 1; 924 pr_info("UV: base:0x%lx shift:%d N_IO:%d M_IO:%d max_pnode:0x%x\n", base, shift, m_io, n_io, max_pnode); 925 map_high("MMIOH", base, shift, m_io, max_pnode, map_uc); 926 } else { 927 pr_info("UV: MMIOH disabled\n"); 928 } 929 } 930 931 static __init void map_low_mmrs(void) 932 { 933 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE); 934 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE); 935 } 936 937 static __init void uv_rtc_init(void) 938 { 939 long status; 940 u64 ticks_per_sec; 941 942 status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec); 943 944 if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) { 945 pr_warn("UV: unable to determine platform RTC clock frequency, guessing.\n"); 946 947 /* BIOS gives wrong value for clock frequency, so guess: */ 948 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL; 949 } else { 950 sn_rtc_cycles_per_second = ticks_per_sec; 951 } 952 } 953 954 /* 955 * percpu heartbeat timer 956 */ 957 static void uv_heartbeat(struct timer_list *timer) 958 { 959 unsigned char bits = uv_scir_info->state; 960 961 /* Flip heartbeat bit: */ 962 bits ^= SCIR_CPU_HEARTBEAT; 963 964 /* Is this CPU idle? */ 965 if (idle_cpu(raw_smp_processor_id())) 966 bits &= ~SCIR_CPU_ACTIVITY; 967 else 968 bits |= SCIR_CPU_ACTIVITY; 969 970 /* Update system controller interface reg: */ 971 uv_set_scir_bits(bits); 972 973 /* Enable next timer period: */ 974 mod_timer(timer, jiffies + SCIR_CPU_HB_INTERVAL); 975 } 976 977 static int uv_heartbeat_enable(unsigned int cpu) 978 { 979 while (!uv_cpu_scir_info(cpu)->enabled) { 980 struct timer_list *timer = &uv_cpu_scir_info(cpu)->timer; 981 982 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY); 983 timer_setup(timer, uv_heartbeat, TIMER_PINNED); 984 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL; 985 add_timer_on(timer, cpu); 986 uv_cpu_scir_info(cpu)->enabled = 1; 987 988 /* Also ensure that boot CPU is enabled: */ 989 cpu = 0; 990 } 991 return 0; 992 } 993 994 #ifdef CONFIG_HOTPLUG_CPU 995 static int uv_heartbeat_disable(unsigned int cpu) 996 { 997 if (uv_cpu_scir_info(cpu)->enabled) { 998 uv_cpu_scir_info(cpu)->enabled = 0; 999 del_timer(&uv_cpu_scir_info(cpu)->timer); 1000 } 1001 uv_set_cpu_scir_bits(cpu, 0xff); 1002 return 0; 1003 } 1004 1005 static __init void uv_scir_register_cpu_notifier(void) 1006 { 1007 cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "x86/x2apic-uvx:online", 1008 uv_heartbeat_enable, uv_heartbeat_disable); 1009 } 1010 1011 #else /* !CONFIG_HOTPLUG_CPU */ 1012 1013 static __init void uv_scir_register_cpu_notifier(void) 1014 { 1015 } 1016 1017 static __init int uv_init_heartbeat(void) 1018 { 1019 int cpu; 1020 1021 if (is_uv_system()) { 1022 for_each_online_cpu(cpu) 1023 uv_heartbeat_enable(cpu); 1024 } 1025 1026 return 0; 1027 } 1028 1029 late_initcall(uv_init_heartbeat); 1030 1031 #endif /* !CONFIG_HOTPLUG_CPU */ 1032 1033 /* Direct Legacy VGA I/O traffic to designated IOH */ 1034 int uv_set_vga_state(struct pci_dev *pdev, bool decode, unsigned int command_bits, u32 flags) 1035 { 1036 int domain, bus, rc; 1037 1038 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) 1039 return 0; 1040 1041 if ((command_bits & PCI_COMMAND_IO) == 0) 1042 return 0; 1043 1044 domain = pci_domain_nr(pdev->bus); 1045 bus = pdev->bus->number; 1046 1047 rc = uv_bios_set_legacy_vga_target(decode, domain, bus); 1048 1049 return rc; 1050 } 1051 1052 /* 1053 * Called on each CPU to initialize the per_cpu UV data area. 1054 * FIXME: hotplug not supported yet 1055 */ 1056 void uv_cpu_init(void) 1057 { 1058 /* CPU 0 initialization will be done via uv_system_init. */ 1059 if (smp_processor_id() == 0) 1060 return; 1061 1062 uv_hub_info->nr_online_cpus++; 1063 1064 if (get_uv_system_type() == UV_NON_UNIQUE_APIC) 1065 set_x2apic_extra_bits(uv_hub_info->pnode); 1066 } 1067 1068 struct mn { 1069 unsigned char m_val; 1070 unsigned char n_val; 1071 unsigned char m_shift; 1072 unsigned char n_lshift; 1073 }; 1074 1075 static void get_mn(struct mn *mnp) 1076 { 1077 union uvh_rh_gam_config_mmr_u m_n_config; 1078 union uv3h_gr0_gam_gr_config_u m_gr_config; 1079 1080 /* Make sure the whole structure is well initialized: */ 1081 memset(mnp, 0, sizeof(*mnp)); 1082 1083 m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR); 1084 mnp->n_val = m_n_config.s.n_skt; 1085 1086 if (is_uv4_hub()) { 1087 mnp->m_val = 0; 1088 mnp->n_lshift = 0; 1089 } else if (is_uv3_hub()) { 1090 mnp->m_val = m_n_config.s3.m_skt; 1091 m_gr_config.v = uv_read_local_mmr(UV3H_GR0_GAM_GR_CONFIG); 1092 mnp->n_lshift = m_gr_config.s3.m_skt; 1093 } else if (is_uv2_hub()) { 1094 mnp->m_val = m_n_config.s2.m_skt; 1095 mnp->n_lshift = mnp->m_val == 40 ? 40 : 39; 1096 } else if (is_uv1_hub()) { 1097 mnp->m_val = m_n_config.s1.m_skt; 1098 mnp->n_lshift = mnp->m_val; 1099 } 1100 mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0; 1101 } 1102 1103 void __init uv_init_hub_info(struct uv_hub_info_s *hi) 1104 { 1105 union uvh_node_id_u node_id; 1106 struct mn mn; 1107 1108 get_mn(&mn); 1109 hi->gpa_mask = mn.m_val ? 1110 (1UL << (mn.m_val + mn.n_val)) - 1 : 1111 (1UL << uv_cpuid.gpa_shift) - 1; 1112 1113 hi->m_val = mn.m_val; 1114 hi->n_val = mn.n_val; 1115 hi->m_shift = mn.m_shift; 1116 hi->n_lshift = mn.n_lshift ? mn.n_lshift : 0; 1117 hi->hub_revision = uv_hub_info->hub_revision; 1118 hi->pnode_mask = uv_cpuid.pnode_mask; 1119 hi->min_pnode = _min_pnode; 1120 hi->min_socket = _min_socket; 1121 hi->pnode_to_socket = _pnode_to_socket; 1122 hi->socket_to_node = _socket_to_node; 1123 hi->socket_to_pnode = _socket_to_pnode; 1124 hi->gr_table_len = _gr_table_len; 1125 hi->gr_table = _gr_table; 1126 1127 node_id.v = uv_read_local_mmr(UVH_NODE_ID); 1128 uv_cpuid.gnode_shift = max_t(unsigned int, uv_cpuid.gnode_shift, mn.n_val); 1129 hi->gnode_extra = (node_id.s.node_id & ~((1 << uv_cpuid.gnode_shift) - 1)) >> 1; 1130 if (mn.m_val) 1131 hi->gnode_upper = (u64)hi->gnode_extra << mn.m_val; 1132 1133 if (uv_gp_table) { 1134 hi->global_mmr_base = uv_gp_table->mmr_base; 1135 hi->global_mmr_shift = uv_gp_table->mmr_shift; 1136 hi->global_gru_base = uv_gp_table->gru_base; 1137 hi->global_gru_shift = uv_gp_table->gru_shift; 1138 hi->gpa_shift = uv_gp_table->gpa_shift; 1139 hi->gpa_mask = (1UL << hi->gpa_shift) - 1; 1140 } else { 1141 hi->global_mmr_base = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) & ~UV_MMR_ENABLE; 1142 hi->global_mmr_shift = _UV_GLOBAL_MMR64_PNODE_SHIFT; 1143 } 1144 1145 get_lowmem_redirect(&hi->lowmem_remap_base, &hi->lowmem_remap_top); 1146 1147 hi->apic_pnode_shift = uv_cpuid.socketid_shift; 1148 1149 /* Show system specific info: */ 1150 pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n", hi->n_val, hi->m_val, hi->m_shift, hi->n_lshift); 1151 pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n", hi->gpa_mask, hi->gpa_shift, hi->pnode_mask, hi->apic_pnode_shift); 1152 pr_info("UV: mmr_base/shift:0x%lx/%ld gru_base/shift:0x%lx/%ld\n", hi->global_mmr_base, hi->global_mmr_shift, hi->global_gru_base, hi->global_gru_shift); 1153 pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n", hi->gnode_upper, hi->gnode_extra); 1154 } 1155 1156 static void __init decode_gam_params(unsigned long ptr) 1157 { 1158 uv_gp_table = (struct uv_gam_parameters *)ptr; 1159 1160 pr_info("UV: GAM Params...\n"); 1161 pr_info("UV: mmr_base/shift:0x%llx/%d gru_base/shift:0x%llx/%d gpa_shift:%d\n", 1162 uv_gp_table->mmr_base, uv_gp_table->mmr_shift, 1163 uv_gp_table->gru_base, uv_gp_table->gru_shift, 1164 uv_gp_table->gpa_shift); 1165 } 1166 1167 static void __init decode_gam_rng_tbl(unsigned long ptr) 1168 { 1169 struct uv_gam_range_entry *gre = (struct uv_gam_range_entry *)ptr; 1170 unsigned long lgre = 0; 1171 int index = 0; 1172 int sock_min = 999999, pnode_min = 99999; 1173 int sock_max = -1, pnode_max = -1; 1174 1175 uv_gre_table = gre; 1176 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) { 1177 if (!index) { 1178 pr_info("UV: GAM Range Table...\n"); 1179 pr_info("UV: # %20s %14s %5s %4s %5s %3s %2s\n", "Range", "", "Size", "Type", "NASID", "SID", "PN"); 1180 } 1181 pr_info("UV: %2d: 0x%014lx-0x%014lx %5luG %3d %04x %02x %02x\n", 1182 index++, 1183 (unsigned long)lgre << UV_GAM_RANGE_SHFT, 1184 (unsigned long)gre->limit << UV_GAM_RANGE_SHFT, 1185 ((unsigned long)(gre->limit - lgre)) >> 1186 (30 - UV_GAM_RANGE_SHFT), /* 64M -> 1G */ 1187 gre->type, gre->nasid, gre->sockid, gre->pnode); 1188 1189 lgre = gre->limit; 1190 if (sock_min > gre->sockid) 1191 sock_min = gre->sockid; 1192 if (sock_max < gre->sockid) 1193 sock_max = gre->sockid; 1194 if (pnode_min > gre->pnode) 1195 pnode_min = gre->pnode; 1196 if (pnode_max < gre->pnode) 1197 pnode_max = gre->pnode; 1198 } 1199 _min_socket = sock_min; 1200 _max_socket = sock_max; 1201 _min_pnode = pnode_min; 1202 _max_pnode = pnode_max; 1203 _gr_table_len = index; 1204 1205 pr_info("UV: GRT: %d entries, sockets(min:%x,max:%x) pnodes(min:%x,max:%x)\n", index, _min_socket, _max_socket, _min_pnode, _max_pnode); 1206 } 1207 1208 static int __init decode_uv_systab(void) 1209 { 1210 struct uv_systab *st; 1211 int i; 1212 1213 if (uv_hub_info->hub_revision < UV4_HUB_REVISION_BASE) 1214 return 0; /* No extended UVsystab required */ 1215 1216 st = uv_systab; 1217 if ((!st) || (st->revision < UV_SYSTAB_VERSION_UV4_LATEST)) { 1218 int rev = st ? st->revision : 0; 1219 1220 pr_err("UV: BIOS UVsystab version(%x) mismatch, expecting(%x)\n", rev, UV_SYSTAB_VERSION_UV4_LATEST); 1221 pr_err("UV: Cannot support UV operations, switching to generic PC\n"); 1222 uv_system_type = UV_NONE; 1223 1224 return -EINVAL; 1225 } 1226 1227 for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) { 1228 unsigned long ptr = st->entry[i].offset; 1229 1230 if (!ptr) 1231 continue; 1232 1233 ptr = ptr + (unsigned long)st; 1234 1235 switch (st->entry[i].type) { 1236 case UV_SYSTAB_TYPE_GAM_PARAMS: 1237 decode_gam_params(ptr); 1238 break; 1239 1240 case UV_SYSTAB_TYPE_GAM_RNG_TBL: 1241 decode_gam_rng_tbl(ptr); 1242 break; 1243 } 1244 } 1245 return 0; 1246 } 1247 1248 /* 1249 * Set up physical blade translations from UVH_NODE_PRESENT_TABLE 1250 * .. NB: UVH_NODE_PRESENT_TABLE is going away, 1251 * .. being replaced by GAM Range Table 1252 */ 1253 static __init void boot_init_possible_blades(struct uv_hub_info_s *hub_info) 1254 { 1255 int i, uv_pb = 0; 1256 1257 pr_info("UV: NODE_PRESENT_DEPTH = %d\n", UVH_NODE_PRESENT_TABLE_DEPTH); 1258 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) { 1259 unsigned long np; 1260 1261 np = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8); 1262 if (np) 1263 pr_info("UV: NODE_PRESENT(%d) = 0x%016lx\n", i, np); 1264 1265 uv_pb += hweight64(np); 1266 } 1267 if (uv_possible_blades != uv_pb) 1268 uv_possible_blades = uv_pb; 1269 } 1270 1271 static void __init build_socket_tables(void) 1272 { 1273 struct uv_gam_range_entry *gre = uv_gre_table; 1274 int num, nump; 1275 int cpu, i, lnid; 1276 int minsock = _min_socket; 1277 int maxsock = _max_socket; 1278 int minpnode = _min_pnode; 1279 int maxpnode = _max_pnode; 1280 size_t bytes; 1281 1282 if (!gre) { 1283 if (is_uv1_hub() || is_uv2_hub() || is_uv3_hub()) { 1284 pr_info("UV: No UVsystab socket table, ignoring\n"); 1285 return; 1286 } 1287 pr_crit("UV: Error: UVsystab address translations not available!\n"); 1288 BUG(); 1289 } 1290 1291 /* Build socket id -> node id, pnode */ 1292 num = maxsock - minsock + 1; 1293 bytes = num * sizeof(_socket_to_node[0]); 1294 _socket_to_node = kmalloc(bytes, GFP_KERNEL); 1295 _socket_to_pnode = kmalloc(bytes, GFP_KERNEL); 1296 1297 nump = maxpnode - minpnode + 1; 1298 bytes = nump * sizeof(_pnode_to_socket[0]); 1299 _pnode_to_socket = kmalloc(bytes, GFP_KERNEL); 1300 BUG_ON(!_socket_to_node || !_socket_to_pnode || !_pnode_to_socket); 1301 1302 for (i = 0; i < num; i++) 1303 _socket_to_node[i] = _socket_to_pnode[i] = SOCK_EMPTY; 1304 1305 for (i = 0; i < nump; i++) 1306 _pnode_to_socket[i] = SOCK_EMPTY; 1307 1308 /* Fill in pnode/node/addr conversion list values: */ 1309 pr_info("UV: GAM Building socket/pnode conversion tables\n"); 1310 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) { 1311 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) 1312 continue; 1313 i = gre->sockid - minsock; 1314 /* Duplicate: */ 1315 if (_socket_to_pnode[i] != SOCK_EMPTY) 1316 continue; 1317 _socket_to_pnode[i] = gre->pnode; 1318 1319 i = gre->pnode - minpnode; 1320 _pnode_to_socket[i] = gre->sockid; 1321 1322 pr_info("UV: sid:%02x type:%d nasid:%04x pn:%02x pn2s:%2x\n", 1323 gre->sockid, gre->type, gre->nasid, 1324 _socket_to_pnode[gre->sockid - minsock], 1325 _pnode_to_socket[gre->pnode - minpnode]); 1326 } 1327 1328 /* Set socket -> node values: */ 1329 lnid = -1; 1330 for_each_present_cpu(cpu) { 1331 int nid = cpu_to_node(cpu); 1332 int apicid, sockid; 1333 1334 if (lnid == nid) 1335 continue; 1336 lnid = nid; 1337 apicid = per_cpu(x86_cpu_to_apicid, cpu); 1338 sockid = apicid >> uv_cpuid.socketid_shift; 1339 _socket_to_node[sockid - minsock] = nid; 1340 pr_info("UV: sid:%02x: apicid:%04x node:%2d\n", 1341 sockid, apicid, nid); 1342 } 1343 1344 /* Set up physical blade to pnode translation from GAM Range Table: */ 1345 bytes = num_possible_nodes() * sizeof(_node_to_pnode[0]); 1346 _node_to_pnode = kmalloc(bytes, GFP_KERNEL); 1347 BUG_ON(!_node_to_pnode); 1348 1349 for (lnid = 0; lnid < num_possible_nodes(); lnid++) { 1350 unsigned short sockid; 1351 1352 for (sockid = minsock; sockid <= maxsock; sockid++) { 1353 if (lnid == _socket_to_node[sockid - minsock]) { 1354 _node_to_pnode[lnid] = _socket_to_pnode[sockid - minsock]; 1355 break; 1356 } 1357 } 1358 if (sockid > maxsock) { 1359 pr_err("UV: socket for node %d not found!\n", lnid); 1360 BUG(); 1361 } 1362 } 1363 1364 /* 1365 * If socket id == pnode or socket id == node for all nodes, 1366 * system runs faster by removing corresponding conversion table. 1367 */ 1368 pr_info("UV: Checking socket->node/pnode for identity maps\n"); 1369 if (minsock == 0) { 1370 for (i = 0; i < num; i++) 1371 if (_socket_to_node[i] == SOCK_EMPTY || i != _socket_to_node[i]) 1372 break; 1373 if (i >= num) { 1374 kfree(_socket_to_node); 1375 _socket_to_node = NULL; 1376 pr_info("UV: 1:1 socket_to_node table removed\n"); 1377 } 1378 } 1379 if (minsock == minpnode) { 1380 for (i = 0; i < num; i++) 1381 if (_socket_to_pnode[i] != SOCK_EMPTY && 1382 _socket_to_pnode[i] != i + minpnode) 1383 break; 1384 if (i >= num) { 1385 kfree(_socket_to_pnode); 1386 _socket_to_pnode = NULL; 1387 pr_info("UV: 1:1 socket_to_pnode table removed\n"); 1388 } 1389 } 1390 } 1391 1392 static void __init uv_system_init_hub(void) 1393 { 1394 struct uv_hub_info_s hub_info = {0}; 1395 int bytes, cpu, nodeid; 1396 unsigned short min_pnode = 9999, max_pnode = 0; 1397 char *hub = is_uv4_hub() ? "UV400" : 1398 is_uv3_hub() ? "UV300" : 1399 is_uv2_hub() ? "UV2000/3000" : 1400 is_uv1_hub() ? "UV100/1000" : NULL; 1401 1402 if (!hub) { 1403 pr_err("UV: Unknown/unsupported UV hub\n"); 1404 return; 1405 } 1406 pr_info("UV: Found %s hub\n", hub); 1407 1408 map_low_mmrs(); 1409 1410 /* Get uv_systab for decoding: */ 1411 uv_bios_init(); 1412 1413 /* If there's an UVsystab problem then abort UV init: */ 1414 if (decode_uv_systab() < 0) 1415 return; 1416 1417 build_socket_tables(); 1418 build_uv_gr_table(); 1419 uv_init_hub_info(&hub_info); 1420 uv_possible_blades = num_possible_nodes(); 1421 if (!_node_to_pnode) 1422 boot_init_possible_blades(&hub_info); 1423 1424 /* uv_num_possible_blades() is really the hub count: */ 1425 pr_info("UV: Found %d hubs, %d nodes, %d CPUs\n", uv_num_possible_blades(), num_possible_nodes(), num_possible_cpus()); 1426 1427 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, &sn_region_size, &system_serial_number); 1428 hub_info.coherency_domain_number = sn_coherency_id; 1429 uv_rtc_init(); 1430 1431 bytes = sizeof(void *) * uv_num_possible_blades(); 1432 __uv_hub_info_list = kzalloc(bytes, GFP_KERNEL); 1433 BUG_ON(!__uv_hub_info_list); 1434 1435 bytes = sizeof(struct uv_hub_info_s); 1436 for_each_node(nodeid) { 1437 struct uv_hub_info_s *new_hub; 1438 1439 if (__uv_hub_info_list[nodeid]) { 1440 pr_err("UV: Node %d UV HUB already initialized!?\n", nodeid); 1441 BUG(); 1442 } 1443 1444 /* Allocate new per hub info list */ 1445 new_hub = (nodeid == 0) ? &uv_hub_info_node0 : kzalloc_node(bytes, GFP_KERNEL, nodeid); 1446 BUG_ON(!new_hub); 1447 __uv_hub_info_list[nodeid] = new_hub; 1448 new_hub = uv_hub_info_list(nodeid); 1449 BUG_ON(!new_hub); 1450 *new_hub = hub_info; 1451 1452 /* Use information from GAM table if available: */ 1453 if (_node_to_pnode) 1454 new_hub->pnode = _node_to_pnode[nodeid]; 1455 else /* Or fill in during CPU loop: */ 1456 new_hub->pnode = 0xffff; 1457 1458 new_hub->numa_blade_id = uv_node_to_blade_id(nodeid); 1459 new_hub->memory_nid = -1; 1460 new_hub->nr_possible_cpus = 0; 1461 new_hub->nr_online_cpus = 0; 1462 } 1463 1464 /* Initialize per CPU info: */ 1465 for_each_possible_cpu(cpu) { 1466 int apicid = per_cpu(x86_cpu_to_apicid, cpu); 1467 int numa_node_id; 1468 unsigned short pnode; 1469 1470 nodeid = cpu_to_node(cpu); 1471 numa_node_id = numa_cpu_node(cpu); 1472 pnode = uv_apicid_to_pnode(apicid); 1473 1474 uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list(nodeid); 1475 uv_cpu_info_per(cpu)->blade_cpu_id = uv_cpu_hub_info(cpu)->nr_possible_cpus++; 1476 if (uv_cpu_hub_info(cpu)->memory_nid == -1) 1477 uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu); 1478 1479 /* Init memoryless node: */ 1480 if (nodeid != numa_node_id && 1481 uv_hub_info_list(numa_node_id)->pnode == 0xffff) 1482 uv_hub_info_list(numa_node_id)->pnode = pnode; 1483 else if (uv_cpu_hub_info(cpu)->pnode == 0xffff) 1484 uv_cpu_hub_info(cpu)->pnode = pnode; 1485 1486 uv_cpu_scir_info(cpu)->offset = uv_scir_offset(apicid); 1487 } 1488 1489 for_each_node(nodeid) { 1490 unsigned short pnode = uv_hub_info_list(nodeid)->pnode; 1491 1492 /* Add pnode info for pre-GAM list nodes without CPUs: */ 1493 if (pnode == 0xffff) { 1494 unsigned long paddr; 1495 1496 paddr = node_start_pfn(nodeid) << PAGE_SHIFT; 1497 pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr)); 1498 uv_hub_info_list(nodeid)->pnode = pnode; 1499 } 1500 min_pnode = min(pnode, min_pnode); 1501 max_pnode = max(pnode, max_pnode); 1502 pr_info("UV: UVHUB node:%2d pn:%02x nrcpus:%d\n", 1503 nodeid, 1504 uv_hub_info_list(nodeid)->pnode, 1505 uv_hub_info_list(nodeid)->nr_possible_cpus); 1506 } 1507 1508 pr_info("UV: min_pnode:%02x max_pnode:%02x\n", min_pnode, max_pnode); 1509 map_gru_high(max_pnode); 1510 map_mmr_high(max_pnode); 1511 map_mmioh_high(min_pnode, max_pnode); 1512 1513 uv_nmi_setup(); 1514 uv_cpu_init(); 1515 uv_scir_register_cpu_notifier(); 1516 proc_mkdir("sgi_uv", NULL); 1517 1518 /* Register Legacy VGA I/O redirection handler: */ 1519 pci_register_set_vga_state(uv_set_vga_state); 1520 1521 /* 1522 * For a kdump kernel the reset must be BOOT_ACPI, not BOOT_EFI, as 1523 * EFI is not enabled in the kdump kernel: 1524 */ 1525 if (is_kdump_kernel()) 1526 reboot_type = BOOT_ACPI; 1527 } 1528 1529 /* 1530 * There is a small amount of UV specific code needed to initialize a 1531 * UV system that does not have a "UV HUB" (referred to as "hubless"). 1532 */ 1533 void __init uv_system_init(void) 1534 { 1535 if (likely(!is_uv_system() && !is_uv_hubless())) 1536 return; 1537 1538 if (is_uv_system()) 1539 uv_system_init_hub(); 1540 else 1541 uv_nmi_setup_hubless(); 1542 } 1543 1544 apic_driver(apic_x2apic_uv_x); 1545