1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * SGI UV APIC functions (note: not an Intel compatible APIC) 7 * 8 * Copyright (C) 2007-2010 Silicon Graphics, Inc. All rights reserved. 9 */ 10 #include <linux/cpumask.h> 11 #include <linux/hardirq.h> 12 #include <linux/proc_fs.h> 13 #include <linux/threads.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/string.h> 17 #include <linux/ctype.h> 18 #include <linux/sched.h> 19 #include <linux/timer.h> 20 #include <linux/slab.h> 21 #include <linux/cpu.h> 22 #include <linux/init.h> 23 #include <linux/io.h> 24 #include <linux/pci.h> 25 #include <linux/kdebug.h> 26 27 #include <asm/uv/uv_mmrs.h> 28 #include <asm/uv/uv_hub.h> 29 #include <asm/current.h> 30 #include <asm/pgtable.h> 31 #include <asm/uv/bios.h> 32 #include <asm/uv/uv.h> 33 #include <asm/apic.h> 34 #include <asm/ipi.h> 35 #include <asm/smp.h> 36 #include <asm/x86_init.h> 37 38 DEFINE_PER_CPU(int, x2apic_extra_bits); 39 40 #define PR_DEVEL(fmt, args...) pr_devel("%s: " fmt, __func__, args) 41 42 static enum uv_system_type uv_system_type; 43 static u64 gru_start_paddr, gru_end_paddr; 44 static union uvh_apicid uvh_apicid; 45 int uv_min_hub_revision_id; 46 EXPORT_SYMBOL_GPL(uv_min_hub_revision_id); 47 unsigned int uv_apicid_hibits; 48 EXPORT_SYMBOL_GPL(uv_apicid_hibits); 49 static DEFINE_SPINLOCK(uv_nmi_lock); 50 51 static unsigned long __init uv_early_read_mmr(unsigned long addr) 52 { 53 unsigned long val, *mmr; 54 55 mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr)); 56 val = *mmr; 57 early_iounmap(mmr, sizeof(*mmr)); 58 return val; 59 } 60 61 static inline bool is_GRU_range(u64 start, u64 end) 62 { 63 return start >= gru_start_paddr && end <= gru_end_paddr; 64 } 65 66 static bool uv_is_untracked_pat_range(u64 start, u64 end) 67 { 68 return is_ISA_range(start, end) || is_GRU_range(start, end); 69 } 70 71 static int __init early_get_pnodeid(void) 72 { 73 union uvh_node_id_u node_id; 74 union uvh_rh_gam_config_mmr_u m_n_config; 75 int pnode; 76 77 /* Currently, all blades have same revision number */ 78 node_id.v = uv_early_read_mmr(UVH_NODE_ID); 79 m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR); 80 uv_min_hub_revision_id = node_id.s.revision; 81 82 pnode = (node_id.s.node_id >> 1) & ((1 << m_n_config.s.n_skt) - 1); 83 return pnode; 84 } 85 86 static void __init early_get_apic_pnode_shift(void) 87 { 88 uvh_apicid.v = uv_early_read_mmr(UVH_APICID); 89 if (!uvh_apicid.v) 90 /* 91 * Old bios, use default value 92 */ 93 uvh_apicid.s.pnode_shift = UV_APIC_PNODE_SHIFT; 94 } 95 96 /* 97 * Add an extra bit as dictated by bios to the destination apicid of 98 * interrupts potentially passing through the UV HUB. This prevents 99 * a deadlock between interrupts and IO port operations. 100 */ 101 static void __init uv_set_apicid_hibit(void) 102 { 103 union uvh_lb_target_physical_apic_id_mask_u apicid_mask; 104 105 apicid_mask.v = uv_early_read_mmr(UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK); 106 uv_apicid_hibits = apicid_mask.s.bit_enables & UV_APICID_HIBIT_MASK; 107 } 108 109 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id) 110 { 111 int pnodeid; 112 113 if (!strcmp(oem_id, "SGI")) { 114 pnodeid = early_get_pnodeid(); 115 early_get_apic_pnode_shift(); 116 x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range; 117 x86_platform.nmi_init = uv_nmi_init; 118 if (!strcmp(oem_table_id, "UVL")) 119 uv_system_type = UV_LEGACY_APIC; 120 else if (!strcmp(oem_table_id, "UVX")) 121 uv_system_type = UV_X2APIC; 122 else if (!strcmp(oem_table_id, "UVH")) { 123 __this_cpu_write(x2apic_extra_bits, 124 pnodeid << uvh_apicid.s.pnode_shift); 125 uv_system_type = UV_NON_UNIQUE_APIC; 126 uv_set_apicid_hibit(); 127 return 1; 128 } 129 } 130 return 0; 131 } 132 133 enum uv_system_type get_uv_system_type(void) 134 { 135 return uv_system_type; 136 } 137 138 int is_uv_system(void) 139 { 140 return uv_system_type != UV_NONE; 141 } 142 EXPORT_SYMBOL_GPL(is_uv_system); 143 144 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); 145 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info); 146 147 struct uv_blade_info *uv_blade_info; 148 EXPORT_SYMBOL_GPL(uv_blade_info); 149 150 short *uv_node_to_blade; 151 EXPORT_SYMBOL_GPL(uv_node_to_blade); 152 153 short *uv_cpu_to_blade; 154 EXPORT_SYMBOL_GPL(uv_cpu_to_blade); 155 156 short uv_possible_blades; 157 EXPORT_SYMBOL_GPL(uv_possible_blades); 158 159 unsigned long sn_rtc_cycles_per_second; 160 EXPORT_SYMBOL(sn_rtc_cycles_per_second); 161 162 static const struct cpumask *uv_target_cpus(void) 163 { 164 return cpu_online_mask; 165 } 166 167 static void uv_vector_allocation_domain(int cpu, struct cpumask *retmask) 168 { 169 cpumask_clear(retmask); 170 cpumask_set_cpu(cpu, retmask); 171 } 172 173 static int __cpuinit uv_wakeup_secondary(int phys_apicid, unsigned long start_rip) 174 { 175 #ifdef CONFIG_SMP 176 unsigned long val; 177 int pnode; 178 179 pnode = uv_apicid_to_pnode(phys_apicid); 180 phys_apicid |= uv_apicid_hibits; 181 val = (1UL << UVH_IPI_INT_SEND_SHFT) | 182 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | 183 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | 184 APIC_DM_INIT; 185 uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 186 mdelay(10); 187 188 val = (1UL << UVH_IPI_INT_SEND_SHFT) | 189 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | 190 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | 191 APIC_DM_STARTUP; 192 uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 193 194 atomic_set(&init_deasserted, 1); 195 #endif 196 return 0; 197 } 198 199 static void uv_send_IPI_one(int cpu, int vector) 200 { 201 unsigned long apicid; 202 int pnode; 203 204 apicid = per_cpu(x86_cpu_to_apicid, cpu); 205 pnode = uv_apicid_to_pnode(apicid); 206 uv_hub_send_ipi(pnode, apicid, vector); 207 } 208 209 static void uv_send_IPI_mask(const struct cpumask *mask, int vector) 210 { 211 unsigned int cpu; 212 213 for_each_cpu(cpu, mask) 214 uv_send_IPI_one(cpu, vector); 215 } 216 217 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) 218 { 219 unsigned int this_cpu = smp_processor_id(); 220 unsigned int cpu; 221 222 for_each_cpu(cpu, mask) { 223 if (cpu != this_cpu) 224 uv_send_IPI_one(cpu, vector); 225 } 226 } 227 228 static void uv_send_IPI_allbutself(int vector) 229 { 230 unsigned int this_cpu = smp_processor_id(); 231 unsigned int cpu; 232 233 for_each_online_cpu(cpu) { 234 if (cpu != this_cpu) 235 uv_send_IPI_one(cpu, vector); 236 } 237 } 238 239 static void uv_send_IPI_all(int vector) 240 { 241 uv_send_IPI_mask(cpu_online_mask, vector); 242 } 243 244 static int uv_apic_id_registered(void) 245 { 246 return 1; 247 } 248 249 static void uv_init_apic_ldr(void) 250 { 251 } 252 253 static unsigned int uv_cpu_mask_to_apicid(const struct cpumask *cpumask) 254 { 255 /* 256 * We're using fixed IRQ delivery, can only return one phys APIC ID. 257 * May as well be the first. 258 */ 259 int cpu = cpumask_first(cpumask); 260 261 if ((unsigned)cpu < nr_cpu_ids) 262 return per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits; 263 else 264 return BAD_APICID; 265 } 266 267 static unsigned int 268 uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 269 const struct cpumask *andmask) 270 { 271 int cpu; 272 273 /* 274 * We're using fixed IRQ delivery, can only return one phys APIC ID. 275 * May as well be the first. 276 */ 277 for_each_cpu_and(cpu, cpumask, andmask) { 278 if (cpumask_test_cpu(cpu, cpu_online_mask)) 279 break; 280 } 281 return per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits; 282 } 283 284 static unsigned int x2apic_get_apic_id(unsigned long x) 285 { 286 unsigned int id; 287 288 WARN_ON(preemptible() && num_online_cpus() > 1); 289 id = x | __this_cpu_read(x2apic_extra_bits); 290 291 return id; 292 } 293 294 static unsigned long set_apic_id(unsigned int id) 295 { 296 unsigned long x; 297 298 /* maskout x2apic_extra_bits ? */ 299 x = id; 300 return x; 301 } 302 303 static unsigned int uv_read_apic_id(void) 304 { 305 306 return x2apic_get_apic_id(apic_read(APIC_ID)); 307 } 308 309 static int uv_phys_pkg_id(int initial_apicid, int index_msb) 310 { 311 return uv_read_apic_id() >> index_msb; 312 } 313 314 static void uv_send_IPI_self(int vector) 315 { 316 apic_write(APIC_SELF_IPI, vector); 317 } 318 319 struct apic __refdata apic_x2apic_uv_x = { 320 321 .name = "UV large system", 322 .probe = NULL, 323 .acpi_madt_oem_check = uv_acpi_madt_oem_check, 324 .apic_id_registered = uv_apic_id_registered, 325 326 .irq_delivery_mode = dest_Fixed, 327 .irq_dest_mode = 0, /* physical */ 328 329 .target_cpus = uv_target_cpus, 330 .disable_esr = 0, 331 .dest_logical = APIC_DEST_LOGICAL, 332 .check_apicid_used = NULL, 333 .check_apicid_present = NULL, 334 335 .vector_allocation_domain = uv_vector_allocation_domain, 336 .init_apic_ldr = uv_init_apic_ldr, 337 338 .ioapic_phys_id_map = NULL, 339 .setup_apic_routing = NULL, 340 .multi_timer_check = NULL, 341 .cpu_present_to_apicid = default_cpu_present_to_apicid, 342 .apicid_to_cpu_present = NULL, 343 .setup_portio_remap = NULL, 344 .check_phys_apicid_present = default_check_phys_apicid_present, 345 .enable_apic_mode = NULL, 346 .phys_pkg_id = uv_phys_pkg_id, 347 .mps_oem_check = NULL, 348 349 .get_apic_id = x2apic_get_apic_id, 350 .set_apic_id = set_apic_id, 351 .apic_id_mask = 0xFFFFFFFFu, 352 353 .cpu_mask_to_apicid = uv_cpu_mask_to_apicid, 354 .cpu_mask_to_apicid_and = uv_cpu_mask_to_apicid_and, 355 356 .send_IPI_mask = uv_send_IPI_mask, 357 .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself, 358 .send_IPI_allbutself = uv_send_IPI_allbutself, 359 .send_IPI_all = uv_send_IPI_all, 360 .send_IPI_self = uv_send_IPI_self, 361 362 .wakeup_secondary_cpu = uv_wakeup_secondary, 363 .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW, 364 .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH, 365 .wait_for_init_deassert = NULL, 366 .smp_callin_clear_local_apic = NULL, 367 .inquire_remote_apic = NULL, 368 369 .read = native_apic_msr_read, 370 .write = native_apic_msr_write, 371 .icr_read = native_x2apic_icr_read, 372 .icr_write = native_x2apic_icr_write, 373 .wait_icr_idle = native_x2apic_wait_icr_idle, 374 .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle, 375 }; 376 377 static __cpuinit void set_x2apic_extra_bits(int pnode) 378 { 379 __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift); 380 } 381 382 /* 383 * Called on boot cpu. 384 */ 385 static __init int boot_pnode_to_blade(int pnode) 386 { 387 int blade; 388 389 for (blade = 0; blade < uv_num_possible_blades(); blade++) 390 if (pnode == uv_blade_info[blade].pnode) 391 return blade; 392 BUG(); 393 } 394 395 struct redir_addr { 396 unsigned long redirect; 397 unsigned long alias; 398 }; 399 400 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 401 402 static __initdata struct redir_addr redir_addrs[] = { 403 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR}, 404 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR}, 405 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR}, 406 }; 407 408 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size) 409 { 410 union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias; 411 union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect; 412 int i; 413 414 for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) { 415 alias.v = uv_read_local_mmr(redir_addrs[i].alias); 416 if (alias.s.enable && alias.s.base == 0) { 417 *size = (1UL << alias.s.m_alias); 418 redirect.v = uv_read_local_mmr(redir_addrs[i].redirect); 419 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT; 420 return; 421 } 422 } 423 *base = *size = 0; 424 } 425 426 enum map_type {map_wb, map_uc}; 427 428 static __init void map_high(char *id, unsigned long base, int pshift, 429 int bshift, int max_pnode, enum map_type map_type) 430 { 431 unsigned long bytes, paddr; 432 433 paddr = base << pshift; 434 bytes = (1UL << bshift) * (max_pnode + 1); 435 printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr, 436 paddr + bytes); 437 if (map_type == map_uc) 438 init_extra_mapping_uc(paddr, bytes); 439 else 440 init_extra_mapping_wb(paddr, bytes); 441 442 } 443 static __init void map_gru_high(int max_pnode) 444 { 445 union uvh_rh_gam_gru_overlay_config_mmr_u gru; 446 int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT; 447 448 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR); 449 if (gru.s.enable) { 450 map_high("GRU", gru.s.base, shift, shift, max_pnode, map_wb); 451 gru_start_paddr = ((u64)gru.s.base << shift); 452 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1); 453 454 } 455 } 456 457 static __init void map_mmr_high(int max_pnode) 458 { 459 union uvh_rh_gam_mmr_overlay_config_mmr_u mmr; 460 int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT; 461 462 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR); 463 if (mmr.s.enable) 464 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc); 465 } 466 467 static __init void map_mmioh_high(int max_pnode) 468 { 469 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh; 470 int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT; 471 472 mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR); 473 if (mmioh.s.enable) 474 map_high("MMIOH", mmioh.s.base, shift, mmioh.s.m_io, 475 max_pnode, map_uc); 476 } 477 478 static __init void map_low_mmrs(void) 479 { 480 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE); 481 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE); 482 } 483 484 static __init void uv_rtc_init(void) 485 { 486 long status; 487 u64 ticks_per_sec; 488 489 status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, 490 &ticks_per_sec); 491 if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) { 492 printk(KERN_WARNING 493 "unable to determine platform RTC clock frequency, " 494 "guessing.\n"); 495 /* BIOS gives wrong value for clock freq. so guess */ 496 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL; 497 } else 498 sn_rtc_cycles_per_second = ticks_per_sec; 499 } 500 501 /* 502 * percpu heartbeat timer 503 */ 504 static void uv_heartbeat(unsigned long ignored) 505 { 506 struct timer_list *timer = &uv_hub_info->scir.timer; 507 unsigned char bits = uv_hub_info->scir.state; 508 509 /* flip heartbeat bit */ 510 bits ^= SCIR_CPU_HEARTBEAT; 511 512 /* is this cpu idle? */ 513 if (idle_cpu(raw_smp_processor_id())) 514 bits &= ~SCIR_CPU_ACTIVITY; 515 else 516 bits |= SCIR_CPU_ACTIVITY; 517 518 /* update system controller interface reg */ 519 uv_set_scir_bits(bits); 520 521 /* enable next timer period */ 522 mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL); 523 } 524 525 static void __cpuinit uv_heartbeat_enable(int cpu) 526 { 527 while (!uv_cpu_hub_info(cpu)->scir.enabled) { 528 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer; 529 530 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY); 531 setup_timer(timer, uv_heartbeat, cpu); 532 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL; 533 add_timer_on(timer, cpu); 534 uv_cpu_hub_info(cpu)->scir.enabled = 1; 535 536 /* also ensure that boot cpu is enabled */ 537 cpu = 0; 538 } 539 } 540 541 #ifdef CONFIG_HOTPLUG_CPU 542 static void __cpuinit uv_heartbeat_disable(int cpu) 543 { 544 if (uv_cpu_hub_info(cpu)->scir.enabled) { 545 uv_cpu_hub_info(cpu)->scir.enabled = 0; 546 del_timer(&uv_cpu_hub_info(cpu)->scir.timer); 547 } 548 uv_set_cpu_scir_bits(cpu, 0xff); 549 } 550 551 /* 552 * cpu hotplug notifier 553 */ 554 static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self, 555 unsigned long action, void *hcpu) 556 { 557 long cpu = (long)hcpu; 558 559 switch (action) { 560 case CPU_ONLINE: 561 uv_heartbeat_enable(cpu); 562 break; 563 case CPU_DOWN_PREPARE: 564 uv_heartbeat_disable(cpu); 565 break; 566 default: 567 break; 568 } 569 return NOTIFY_OK; 570 } 571 572 static __init void uv_scir_register_cpu_notifier(void) 573 { 574 hotcpu_notifier(uv_scir_cpu_notify, 0); 575 } 576 577 #else /* !CONFIG_HOTPLUG_CPU */ 578 579 static __init void uv_scir_register_cpu_notifier(void) 580 { 581 } 582 583 static __init int uv_init_heartbeat(void) 584 { 585 int cpu; 586 587 if (is_uv_system()) 588 for_each_online_cpu(cpu) 589 uv_heartbeat_enable(cpu); 590 return 0; 591 } 592 593 late_initcall(uv_init_heartbeat); 594 595 #endif /* !CONFIG_HOTPLUG_CPU */ 596 597 /* Direct Legacy VGA I/O traffic to designated IOH */ 598 int uv_set_vga_state(struct pci_dev *pdev, bool decode, 599 unsigned int command_bits, bool change_bridge) 600 { 601 int domain, bus, rc; 602 603 PR_DEVEL("devfn %x decode %d cmd %x chg_brdg %d\n", 604 pdev->devfn, decode, command_bits, change_bridge); 605 606 if (!change_bridge) 607 return 0; 608 609 if ((command_bits & PCI_COMMAND_IO) == 0) 610 return 0; 611 612 domain = pci_domain_nr(pdev->bus); 613 bus = pdev->bus->number; 614 615 rc = uv_bios_set_legacy_vga_target(decode, domain, bus); 616 PR_DEVEL("vga decode %d %x:%x, rc: %d\n", decode, domain, bus, rc); 617 618 return rc; 619 } 620 621 /* 622 * Called on each cpu to initialize the per_cpu UV data area. 623 * FIXME: hotplug not supported yet 624 */ 625 void __cpuinit uv_cpu_init(void) 626 { 627 /* CPU 0 initilization will be done via uv_system_init. */ 628 if (!uv_blade_info) 629 return; 630 631 uv_blade_info[uv_numa_blade_id()].nr_online_cpus++; 632 633 if (get_uv_system_type() == UV_NON_UNIQUE_APIC) 634 set_x2apic_extra_bits(uv_hub_info->pnode); 635 } 636 637 /* 638 * When NMI is received, print a stack trace. 639 */ 640 int uv_handle_nmi(struct notifier_block *self, unsigned long reason, void *data) 641 { 642 if (reason != DIE_NMIUNKNOWN) 643 return NOTIFY_OK; 644 645 if (in_crash_kexec) 646 /* do nothing if entering the crash kernel */ 647 return NOTIFY_OK; 648 /* 649 * Use a lock so only one cpu prints at a time 650 * to prevent intermixed output. 651 */ 652 spin_lock(&uv_nmi_lock); 653 pr_info("NMI stack dump cpu %u:\n", smp_processor_id()); 654 dump_stack(); 655 spin_unlock(&uv_nmi_lock); 656 657 return NOTIFY_STOP; 658 } 659 660 static struct notifier_block uv_dump_stack_nmi_nb = { 661 .notifier_call = uv_handle_nmi 662 }; 663 664 void uv_register_nmi_notifier(void) 665 { 666 if (register_die_notifier(&uv_dump_stack_nmi_nb)) 667 printk(KERN_WARNING "UV NMI handler failed to register\n"); 668 } 669 670 void uv_nmi_init(void) 671 { 672 unsigned int value; 673 674 /* 675 * Unmask NMI on all cpus 676 */ 677 value = apic_read(APIC_LVT1) | APIC_DM_NMI; 678 value &= ~APIC_LVT_MASKED; 679 apic_write(APIC_LVT1, value); 680 } 681 682 void __init uv_system_init(void) 683 { 684 union uvh_rh_gam_config_mmr_u m_n_config; 685 union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh; 686 union uvh_node_id_u node_id; 687 unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size; 688 int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val, n_io; 689 int gnode_extra, max_pnode = 0; 690 unsigned long mmr_base, present, paddr; 691 unsigned short pnode_mask, pnode_io_mask; 692 693 map_low_mmrs(); 694 695 m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR ); 696 m_val = m_n_config.s.m_skt; 697 n_val = m_n_config.s.n_skt; 698 mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR); 699 n_io = mmioh.s.n_io; 700 mmr_base = 701 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) & 702 ~UV_MMR_ENABLE; 703 pnode_mask = (1 << n_val) - 1; 704 pnode_io_mask = (1 << n_io) - 1; 705 706 node_id.v = uv_read_local_mmr(UVH_NODE_ID); 707 gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1; 708 gnode_upper = ((unsigned long)gnode_extra << m_val); 709 printk(KERN_INFO "UV: N %d, M %d, N_IO: %d, gnode_upper 0x%lx, gnode_extra 0x%x, pnode_mask 0x%x, pnode_io_mask 0x%x\n", 710 n_val, m_val, n_io, gnode_upper, gnode_extra, pnode_mask, pnode_io_mask); 711 712 printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base); 713 714 for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) 715 uv_possible_blades += 716 hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8)); 717 printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades()); 718 719 bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades(); 720 uv_blade_info = kmalloc(bytes, GFP_KERNEL); 721 BUG_ON(!uv_blade_info); 722 for (blade = 0; blade < uv_num_possible_blades(); blade++) 723 uv_blade_info[blade].memory_nid = -1; 724 725 get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size); 726 727 bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes(); 728 uv_node_to_blade = kmalloc(bytes, GFP_KERNEL); 729 BUG_ON(!uv_node_to_blade); 730 memset(uv_node_to_blade, 255, bytes); 731 732 bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus(); 733 uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL); 734 BUG_ON(!uv_cpu_to_blade); 735 memset(uv_cpu_to_blade, 255, bytes); 736 737 blade = 0; 738 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) { 739 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8); 740 for (j = 0; j < 64; j++) { 741 if (!test_bit(j, &present)) 742 continue; 743 pnode = (i * 64 + j) & pnode_mask; 744 uv_blade_info[blade].pnode = pnode; 745 uv_blade_info[blade].nr_possible_cpus = 0; 746 uv_blade_info[blade].nr_online_cpus = 0; 747 max_pnode = max(pnode, max_pnode); 748 blade++; 749 } 750 } 751 752 uv_bios_init(); 753 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, 754 &sn_region_size, &system_serial_number); 755 uv_rtc_init(); 756 757 for_each_present_cpu(cpu) { 758 int apicid = per_cpu(x86_cpu_to_apicid, cpu); 759 760 nid = cpu_to_node(cpu); 761 /* 762 * apic_pnode_shift must be set before calling uv_apicid_to_pnode(); 763 */ 764 uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask; 765 uv_cpu_hub_info(cpu)->apic_pnode_shift = uvh_apicid.s.pnode_shift; 766 pnode = uv_apicid_to_pnode(apicid); 767 blade = boot_pnode_to_blade(pnode); 768 lcpu = uv_blade_info[blade].nr_possible_cpus; 769 uv_blade_info[blade].nr_possible_cpus++; 770 771 /* Any node on the blade, else will contain -1. */ 772 uv_blade_info[blade].memory_nid = nid; 773 774 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base; 775 uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size; 776 uv_cpu_hub_info(cpu)->m_val = m_val; 777 uv_cpu_hub_info(cpu)->n_val = n_val; 778 uv_cpu_hub_info(cpu)->numa_blade_id = blade; 779 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu; 780 uv_cpu_hub_info(cpu)->pnode = pnode; 781 uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1; 782 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper; 783 uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra; 784 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base; 785 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id; 786 uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid); 787 uv_node_to_blade[nid] = blade; 788 uv_cpu_to_blade[cpu] = blade; 789 } 790 791 /* Add blade/pnode info for nodes without cpus */ 792 for_each_online_node(nid) { 793 if (uv_node_to_blade[nid] >= 0) 794 continue; 795 paddr = node_start_pfn(nid) << PAGE_SHIFT; 796 paddr = uv_soc_phys_ram_to_gpa(paddr); 797 pnode = (paddr >> m_val) & pnode_mask; 798 blade = boot_pnode_to_blade(pnode); 799 uv_node_to_blade[nid] = blade; 800 } 801 802 map_gru_high(max_pnode); 803 map_mmr_high(max_pnode); 804 map_mmioh_high(max_pnode & pnode_io_mask); 805 806 uv_cpu_init(); 807 uv_scir_register_cpu_notifier(); 808 uv_register_nmi_notifier(); 809 proc_mkdir("sgi_uv", NULL); 810 811 /* register Legacy VGA I/O redirection handler */ 812 pci_register_set_vga_state(uv_set_vga_state); 813 } 814