1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * SGI UV APIC functions (note: not an Intel compatible APIC) 7 * 8 * (C) Copyright 2020 Hewlett Packard Enterprise Development LP 9 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved. 10 */ 11 #include <linux/crash_dump.h> 12 #include <linux/cpuhotplug.h> 13 #include <linux/cpumask.h> 14 #include <linux/proc_fs.h> 15 #include <linux/memory.h> 16 #include <linux/export.h> 17 #include <linux/pci.h> 18 #include <linux/acpi.h> 19 #include <linux/efi.h> 20 21 #include <asm/e820/api.h> 22 #include <asm/uv/uv_mmrs.h> 23 #include <asm/uv/uv_hub.h> 24 #include <asm/uv/bios.h> 25 #include <asm/uv/uv.h> 26 #include <asm/apic.h> 27 28 static enum uv_system_type uv_system_type; 29 static int uv_hubbed_system; 30 static int uv_hubless_system; 31 static u64 gru_start_paddr, gru_end_paddr; 32 static union uvh_apicid uvh_apicid; 33 static int uv_node_id; 34 35 /* Unpack AT/OEM/TABLE ID's to be NULL terminated strings */ 36 static u8 uv_archtype[UV_AT_SIZE + 1]; 37 static u8 oem_id[ACPI_OEM_ID_SIZE + 1]; 38 static u8 oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1]; 39 40 /* Information derived from CPUID and some UV MMRs */ 41 static struct { 42 unsigned int apicid_shift; 43 unsigned int apicid_mask; 44 unsigned int socketid_shift; /* aka pnode_shift for UV2/3 */ 45 unsigned int pnode_mask; 46 unsigned int nasid_shift; 47 unsigned int gpa_shift; 48 unsigned int gnode_shift; 49 unsigned int m_skt; 50 unsigned int n_skt; 51 } uv_cpuid; 52 53 static int uv_min_hub_revision_id; 54 55 static struct apic apic_x2apic_uv_x; 56 static struct uv_hub_info_s uv_hub_info_node0; 57 58 /* Set this to use hardware error handler instead of kernel panic: */ 59 static int disable_uv_undefined_panic = 1; 60 61 unsigned long uv_undefined(char *str) 62 { 63 if (likely(!disable_uv_undefined_panic)) 64 panic("UV: error: undefined MMR: %s\n", str); 65 else 66 pr_crit("UV: error: undefined MMR: %s\n", str); 67 68 /* Cause a machine fault: */ 69 return ~0ul; 70 } 71 EXPORT_SYMBOL(uv_undefined); 72 73 static unsigned long __init uv_early_read_mmr(unsigned long addr) 74 { 75 unsigned long val, *mmr; 76 77 mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr)); 78 val = *mmr; 79 early_iounmap(mmr, sizeof(*mmr)); 80 81 return val; 82 } 83 84 static inline bool is_GRU_range(u64 start, u64 end) 85 { 86 if (!gru_start_paddr) 87 return false; 88 89 return start >= gru_start_paddr && end <= gru_end_paddr; 90 } 91 92 static bool uv_is_untracked_pat_range(u64 start, u64 end) 93 { 94 return is_ISA_range(start, end) || is_GRU_range(start, end); 95 } 96 97 static void __init early_get_pnodeid(void) 98 { 99 int pnode; 100 101 uv_cpuid.m_skt = 0; 102 if (UVH_RH10_GAM_ADDR_MAP_CONFIG) { 103 union uvh_rh10_gam_addr_map_config_u m_n_config; 104 105 m_n_config.v = uv_early_read_mmr(UVH_RH10_GAM_ADDR_MAP_CONFIG); 106 uv_cpuid.n_skt = m_n_config.s.n_skt; 107 uv_cpuid.nasid_shift = 0; 108 } else if (UVH_RH_GAM_ADDR_MAP_CONFIG) { 109 union uvh_rh_gam_addr_map_config_u m_n_config; 110 111 m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_ADDR_MAP_CONFIG); 112 uv_cpuid.n_skt = m_n_config.s.n_skt; 113 if (is_uv(UV3)) 114 uv_cpuid.m_skt = m_n_config.s3.m_skt; 115 if (is_uv(UV2)) 116 uv_cpuid.m_skt = m_n_config.s2.m_skt; 117 uv_cpuid.nasid_shift = 1; 118 } else { 119 unsigned long GAM_ADDR_MAP_CONFIG = 0; 120 121 WARN(GAM_ADDR_MAP_CONFIG == 0, 122 "UV: WARN: GAM_ADDR_MAP_CONFIG is not available\n"); 123 uv_cpuid.n_skt = 0; 124 uv_cpuid.nasid_shift = 0; 125 } 126 127 if (is_uv(UV4|UVY)) 128 uv_cpuid.gnode_shift = 2; /* min partition is 4 sockets */ 129 130 uv_cpuid.pnode_mask = (1 << uv_cpuid.n_skt) - 1; 131 pnode = (uv_node_id >> uv_cpuid.nasid_shift) & uv_cpuid.pnode_mask; 132 uv_cpuid.gpa_shift = 46; /* Default unless changed */ 133 134 pr_info("UV: n_skt:%d pnmsk:%x pn:%x\n", 135 uv_cpuid.n_skt, uv_cpuid.pnode_mask, pnode); 136 } 137 138 /* Running on a UV Hubbed system, determine which UV Hub Type it is */ 139 static int __init early_set_hub_type(void) 140 { 141 union uvh_node_id_u node_id; 142 143 /* 144 * The NODE_ID MMR is always at offset 0. 145 * Contains the chip part # + revision. 146 * Node_id field started with 15 bits, 147 * ... now 7 but upper 8 are masked to 0. 148 * All blades/nodes have the same part # and hub revision. 149 */ 150 node_id.v = uv_early_read_mmr(UVH_NODE_ID); 151 uv_node_id = node_id.sx.node_id; 152 153 switch (node_id.s.part_number) { 154 155 case UV5_HUB_PART_NUMBER: 156 uv_min_hub_revision_id = node_id.s.revision 157 + UV5_HUB_REVISION_BASE; 158 uv_hub_type_set(UV5); 159 break; 160 161 /* UV4/4A only have a revision difference */ 162 case UV4_HUB_PART_NUMBER: 163 uv_min_hub_revision_id = node_id.s.revision 164 + UV4_HUB_REVISION_BASE - 1; 165 uv_hub_type_set(UV4); 166 if (uv_min_hub_revision_id == UV4A_HUB_REVISION_BASE) 167 uv_hub_type_set(UV4|UV4A); 168 break; 169 170 case UV3_HUB_PART_NUMBER: 171 case UV3_HUB_PART_NUMBER_X: 172 uv_min_hub_revision_id = node_id.s.revision 173 + UV3_HUB_REVISION_BASE; 174 uv_hub_type_set(UV3); 175 break; 176 177 case UV2_HUB_PART_NUMBER: 178 case UV2_HUB_PART_NUMBER_X: 179 uv_min_hub_revision_id = node_id.s.revision 180 + UV2_HUB_REVISION_BASE - 1; 181 uv_hub_type_set(UV2); 182 break; 183 184 default: 185 return 0; 186 } 187 188 pr_info("UV: part#:%x rev:%d rev_id:%d UVtype:0x%x\n", 189 node_id.s.part_number, node_id.s.revision, 190 uv_min_hub_revision_id, is_uv(~0)); 191 192 return 1; 193 } 194 195 static void __init uv_tsc_check_sync(void) 196 { 197 u64 mmr; 198 int sync_state; 199 int mmr_shift; 200 char *state; 201 202 /* UV5 guarantees synced TSCs; do not zero TSC_ADJUST */ 203 if (!is_uv(UV2|UV3|UV4)) { 204 mark_tsc_async_resets("UV5+"); 205 return; 206 } 207 208 /* UV2,3,4, UV BIOS TSC sync state available */ 209 mmr = uv_early_read_mmr(UVH_TSC_SYNC_MMR); 210 mmr_shift = 211 is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT; 212 sync_state = (mmr >> mmr_shift) & UVH_TSC_SYNC_MASK; 213 214 /* Check if TSC is valid for all sockets */ 215 switch (sync_state) { 216 case UVH_TSC_SYNC_VALID: 217 state = "in sync"; 218 mark_tsc_async_resets("UV BIOS"); 219 break; 220 221 /* If BIOS state unknown, don't do anything */ 222 case UVH_TSC_SYNC_UNKNOWN: 223 state = "unknown"; 224 break; 225 226 /* Otherwise, BIOS indicates problem with TSC */ 227 default: 228 state = "unstable"; 229 mark_tsc_unstable("UV BIOS"); 230 break; 231 } 232 pr_info("UV: TSC sync state from BIOS:0%d(%s)\n", sync_state, state); 233 } 234 235 /* Selector for (4|4A|5) structs */ 236 #define uvxy_field(sname, field, undef) ( \ 237 is_uv(UV4A) ? sname.s4a.field : \ 238 is_uv(UV4) ? sname.s4.field : \ 239 is_uv(UV3) ? sname.s3.field : \ 240 undef) 241 242 /* [Copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */ 243 244 #define SMT_LEVEL 0 /* Leaf 0xb SMT level */ 245 #define INVALID_TYPE 0 /* Leaf 0xb sub-leaf types */ 246 #define SMT_TYPE 1 247 #define CORE_TYPE 2 248 #define LEAFB_SUBTYPE(ecx) (((ecx) >> 8) & 0xff) 249 #define BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f) 250 251 static void set_x2apic_bits(void) 252 { 253 unsigned int eax, ebx, ecx, edx, sub_index; 254 unsigned int sid_shift; 255 256 cpuid(0, &eax, &ebx, &ecx, &edx); 257 if (eax < 0xb) { 258 pr_info("UV: CPU does not have CPUID.11\n"); 259 return; 260 } 261 262 cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx); 263 if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) { 264 pr_info("UV: CPUID.11 not implemented\n"); 265 return; 266 } 267 268 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax); 269 sub_index = 1; 270 do { 271 cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx); 272 if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) { 273 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax); 274 break; 275 } 276 sub_index++; 277 } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE); 278 279 uv_cpuid.apicid_shift = 0; 280 uv_cpuid.apicid_mask = (~(-1 << sid_shift)); 281 uv_cpuid.socketid_shift = sid_shift; 282 } 283 284 static void __init early_get_apic_socketid_shift(void) 285 { 286 if (is_uv2_hub() || is_uv3_hub()) 287 uvh_apicid.v = uv_early_read_mmr(UVH_APICID); 288 289 set_x2apic_bits(); 290 291 pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n", uv_cpuid.apicid_shift, uv_cpuid.apicid_mask); 292 pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n", uv_cpuid.socketid_shift, uv_cpuid.pnode_mask); 293 } 294 295 static void __init uv_stringify(int len, char *to, char *from) 296 { 297 /* Relies on 'to' being NULL chars so result will be NULL terminated */ 298 strncpy(to, from, len-1); 299 300 /* Trim trailing spaces */ 301 (void)strim(to); 302 } 303 304 /* Find UV arch type entry in UVsystab */ 305 static unsigned long __init early_find_archtype(struct uv_systab *st) 306 { 307 int i; 308 309 for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) { 310 unsigned long ptr = st->entry[i].offset; 311 312 if (!ptr) 313 continue; 314 ptr += (unsigned long)st; 315 if (st->entry[i].type == UV_SYSTAB_TYPE_ARCH_TYPE) 316 return ptr; 317 } 318 return 0; 319 } 320 321 /* Validate UV arch type field in UVsystab */ 322 static int __init decode_arch_type(unsigned long ptr) 323 { 324 struct uv_arch_type_entry *uv_ate = (struct uv_arch_type_entry *)ptr; 325 int n = strlen(uv_ate->archtype); 326 327 if (n > 0 && n < sizeof(uv_ate->archtype)) { 328 pr_info("UV: UVarchtype received from BIOS\n"); 329 uv_stringify(sizeof(uv_archtype), uv_archtype, uv_ate->archtype); 330 return 1; 331 } 332 return 0; 333 } 334 335 /* Determine if UV arch type entry might exist in UVsystab */ 336 static int __init early_get_arch_type(void) 337 { 338 unsigned long uvst_physaddr, uvst_size, ptr; 339 struct uv_systab *st; 340 u32 rev; 341 int ret; 342 343 uvst_physaddr = get_uv_systab_phys(0); 344 if (!uvst_physaddr) 345 return 0; 346 347 st = early_memremap_ro(uvst_physaddr, sizeof(struct uv_systab)); 348 if (!st) { 349 pr_err("UV: Cannot access UVsystab, remap failed\n"); 350 return 0; 351 } 352 353 rev = st->revision; 354 if (rev < UV_SYSTAB_VERSION_UV5) { 355 early_memunmap(st, sizeof(struct uv_systab)); 356 return 0; 357 } 358 359 uvst_size = st->size; 360 early_memunmap(st, sizeof(struct uv_systab)); 361 st = early_memremap_ro(uvst_physaddr, uvst_size); 362 if (!st) { 363 pr_err("UV: Cannot access UVarchtype, remap failed\n"); 364 return 0; 365 } 366 367 ptr = early_find_archtype(st); 368 if (!ptr) { 369 early_memunmap(st, uvst_size); 370 return 0; 371 } 372 373 ret = decode_arch_type(ptr); 374 early_memunmap(st, uvst_size); 375 return ret; 376 } 377 378 /* UV system found, check which APIC MODE BIOS already selected */ 379 static void __init early_set_apic_mode(void) 380 { 381 if (x2apic_enabled()) 382 uv_system_type = UV_X2APIC; 383 else 384 uv_system_type = UV_LEGACY_APIC; 385 } 386 387 static int __init uv_set_system_type(char *_oem_id, char *_oem_table_id) 388 { 389 /* Save OEM_ID passed from ACPI MADT */ 390 uv_stringify(sizeof(oem_id), oem_id, _oem_id); 391 392 /* Check if BIOS sent us a UVarchtype */ 393 if (!early_get_arch_type()) 394 395 /* If not use OEM ID for UVarchtype */ 396 uv_stringify(sizeof(uv_archtype), uv_archtype, oem_id); 397 398 /* Check if not hubbed */ 399 if (strncmp(uv_archtype, "SGI", 3) != 0) { 400 401 /* (Not hubbed), check if not hubless */ 402 if (strncmp(uv_archtype, "NSGI", 4) != 0) 403 404 /* (Not hubless), not a UV */ 405 return 0; 406 407 /* Is UV hubless system */ 408 uv_hubless_system = 0x01; 409 410 /* UV5 Hubless */ 411 if (strncmp(uv_archtype, "NSGI5", 5) == 0) 412 uv_hubless_system |= 0x20; 413 414 /* UV4 Hubless: CH */ 415 else if (strncmp(uv_archtype, "NSGI4", 5) == 0) 416 uv_hubless_system |= 0x10; 417 418 /* UV3 Hubless: UV300/MC990X w/o hub */ 419 else 420 uv_hubless_system |= 0x8; 421 422 /* Copy OEM Table ID */ 423 uv_stringify(sizeof(oem_table_id), oem_table_id, _oem_table_id); 424 425 pr_info("UV: OEM IDs %s/%s, SystemType %d, HUBLESS ID %x\n", 426 oem_id, oem_table_id, uv_system_type, uv_hubless_system); 427 428 return 0; 429 } 430 431 if (numa_off) { 432 pr_err("UV: NUMA is off, disabling UV support\n"); 433 return 0; 434 } 435 436 /* Set hubbed type if true */ 437 uv_hub_info->hub_revision = 438 !strncmp(uv_archtype, "SGI5", 4) ? UV5_HUB_REVISION_BASE : 439 !strncmp(uv_archtype, "SGI4", 4) ? UV4_HUB_REVISION_BASE : 440 !strncmp(uv_archtype, "SGI3", 4) ? UV3_HUB_REVISION_BASE : 441 !strcmp(uv_archtype, "SGI2") ? UV2_HUB_REVISION_BASE : 0; 442 443 switch (uv_hub_info->hub_revision) { 444 case UV5_HUB_REVISION_BASE: 445 uv_hubbed_system = 0x21; 446 uv_hub_type_set(UV5); 447 break; 448 449 case UV4_HUB_REVISION_BASE: 450 uv_hubbed_system = 0x11; 451 uv_hub_type_set(UV4); 452 break; 453 454 case UV3_HUB_REVISION_BASE: 455 uv_hubbed_system = 0x9; 456 uv_hub_type_set(UV3); 457 break; 458 459 case UV2_HUB_REVISION_BASE: 460 uv_hubbed_system = 0x5; 461 uv_hub_type_set(UV2); 462 break; 463 464 default: 465 return 0; 466 } 467 468 /* Get UV hub chip part number & revision */ 469 early_set_hub_type(); 470 471 /* Other UV setup functions */ 472 early_set_apic_mode(); 473 early_get_pnodeid(); 474 early_get_apic_socketid_shift(); 475 x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range; 476 x86_platform.nmi_init = uv_nmi_init; 477 uv_tsc_check_sync(); 478 479 return 1; 480 } 481 482 /* Called early to probe for the correct APIC driver */ 483 static int __init uv_acpi_madt_oem_check(char *_oem_id, char *_oem_table_id) 484 { 485 /* Set up early hub info fields for Node 0 */ 486 uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0; 487 488 /* If not UV, return. */ 489 if (uv_set_system_type(_oem_id, _oem_table_id) == 0) 490 return 0; 491 492 /* Save for display of the OEM Table ID */ 493 uv_stringify(sizeof(oem_table_id), oem_table_id, _oem_table_id); 494 495 pr_info("UV: OEM IDs %s/%s, System/UVType %d/0x%x, HUB RevID %d\n", 496 oem_id, oem_table_id, uv_system_type, is_uv(UV_ANY), 497 uv_min_hub_revision_id); 498 499 return 0; 500 } 501 502 enum uv_system_type get_uv_system_type(void) 503 { 504 return uv_system_type; 505 } 506 507 int uv_get_hubless_system(void) 508 { 509 return uv_hubless_system; 510 } 511 EXPORT_SYMBOL_GPL(uv_get_hubless_system); 512 513 ssize_t uv_get_archtype(char *buf, int len) 514 { 515 return scnprintf(buf, len, "%s/%s", uv_archtype, oem_table_id); 516 } 517 EXPORT_SYMBOL_GPL(uv_get_archtype); 518 519 int is_uv_system(void) 520 { 521 return uv_system_type != UV_NONE; 522 } 523 EXPORT_SYMBOL_GPL(is_uv_system); 524 525 int is_uv_hubbed(int uvtype) 526 { 527 return (uv_hubbed_system & uvtype); 528 } 529 EXPORT_SYMBOL_GPL(is_uv_hubbed); 530 531 static int is_uv_hubless(int uvtype) 532 { 533 return (uv_hubless_system & uvtype); 534 } 535 536 void **__uv_hub_info_list; 537 EXPORT_SYMBOL_GPL(__uv_hub_info_list); 538 539 DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info); 540 EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info); 541 542 short uv_possible_blades; 543 EXPORT_SYMBOL_GPL(uv_possible_blades); 544 545 unsigned long sn_rtc_cycles_per_second; 546 EXPORT_SYMBOL(sn_rtc_cycles_per_second); 547 548 /* The following values are used for the per node hub info struct */ 549 static __initdata unsigned short *_node_to_pnode; 550 static __initdata unsigned short _min_socket, _max_socket; 551 static __initdata unsigned short _min_pnode, _max_pnode, _gr_table_len; 552 static __initdata struct uv_gam_range_entry *uv_gre_table; 553 static __initdata struct uv_gam_parameters *uv_gp_table; 554 static __initdata unsigned short *_socket_to_node; 555 static __initdata unsigned short *_socket_to_pnode; 556 static __initdata unsigned short *_pnode_to_socket; 557 558 static __initdata struct uv_gam_range_s *_gr_table; 559 560 #define SOCK_EMPTY ((unsigned short)~0) 561 562 /* Default UV memory block size is 2GB */ 563 static unsigned long mem_block_size __initdata = (2UL << 30); 564 565 /* Kernel parameter to specify UV mem block size */ 566 static int __init parse_mem_block_size(char *ptr) 567 { 568 unsigned long size = memparse(ptr, NULL); 569 570 /* Size will be rounded down by set_block_size() below */ 571 mem_block_size = size; 572 return 0; 573 } 574 early_param("uv_memblksize", parse_mem_block_size); 575 576 static __init int adj_blksize(u32 lgre) 577 { 578 unsigned long base = (unsigned long)lgre << UV_GAM_RANGE_SHFT; 579 unsigned long size; 580 581 for (size = mem_block_size; size > MIN_MEMORY_BLOCK_SIZE; size >>= 1) 582 if (IS_ALIGNED(base, size)) 583 break; 584 585 if (size >= mem_block_size) 586 return 0; 587 588 mem_block_size = size; 589 return 1; 590 } 591 592 static __init void set_block_size(void) 593 { 594 unsigned int order = ffs(mem_block_size); 595 596 if (order) { 597 /* adjust for ffs return of 1..64 */ 598 set_memory_block_size_order(order - 1); 599 pr_info("UV: mem_block_size set to 0x%lx\n", mem_block_size); 600 } else { 601 /* bad or zero value, default to 1UL << 31 (2GB) */ 602 pr_err("UV: mem_block_size error with 0x%lx\n", mem_block_size); 603 set_memory_block_size_order(31); 604 } 605 } 606 607 /* Build GAM range lookup table: */ 608 static __init void build_uv_gr_table(void) 609 { 610 struct uv_gam_range_entry *gre = uv_gre_table; 611 struct uv_gam_range_s *grt; 612 unsigned long last_limit = 0, ram_limit = 0; 613 int bytes, i, sid, lsid = -1, indx = 0, lindx = -1; 614 615 if (!gre) 616 return; 617 618 bytes = _gr_table_len * sizeof(struct uv_gam_range_s); 619 grt = kzalloc(bytes, GFP_KERNEL); 620 BUG_ON(!grt); 621 _gr_table = grt; 622 623 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) { 624 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) { 625 if (!ram_limit) { 626 /* Mark hole between RAM/non-RAM: */ 627 ram_limit = last_limit; 628 last_limit = gre->limit; 629 lsid++; 630 continue; 631 } 632 last_limit = gre->limit; 633 pr_info("UV: extra hole in GAM RE table @%d\n", (int)(gre - uv_gre_table)); 634 continue; 635 } 636 if (_max_socket < gre->sockid) { 637 pr_err("UV: GAM table sockid(%d) too large(>%d) @%d\n", gre->sockid, _max_socket, (int)(gre - uv_gre_table)); 638 continue; 639 } 640 sid = gre->sockid - _min_socket; 641 if (lsid < sid) { 642 /* New range: */ 643 grt = &_gr_table[indx]; 644 grt->base = lindx; 645 grt->nasid = gre->nasid; 646 grt->limit = last_limit = gre->limit; 647 lsid = sid; 648 lindx = indx++; 649 continue; 650 } 651 /* Update range: */ 652 if (lsid == sid && !ram_limit) { 653 /* .. if contiguous: */ 654 if (grt->limit == last_limit) { 655 grt->limit = last_limit = gre->limit; 656 continue; 657 } 658 } 659 /* Non-contiguous RAM range: */ 660 if (!ram_limit) { 661 grt++; 662 grt->base = lindx; 663 grt->nasid = gre->nasid; 664 grt->limit = last_limit = gre->limit; 665 continue; 666 } 667 /* Non-contiguous/non-RAM: */ 668 grt++; 669 /* base is this entry */ 670 grt->base = grt - _gr_table; 671 grt->nasid = gre->nasid; 672 grt->limit = last_limit = gre->limit; 673 lsid++; 674 } 675 676 /* Shorten table if possible */ 677 grt++; 678 i = grt - _gr_table; 679 if (i < _gr_table_len) { 680 void *ret; 681 682 bytes = i * sizeof(struct uv_gam_range_s); 683 ret = krealloc(_gr_table, bytes, GFP_KERNEL); 684 if (ret) { 685 _gr_table = ret; 686 _gr_table_len = i; 687 } 688 } 689 690 /* Display resultant GAM range table: */ 691 for (i = 0, grt = _gr_table; i < _gr_table_len; i++, grt++) { 692 unsigned long start, end; 693 int gb = grt->base; 694 695 start = gb < 0 ? 0 : (unsigned long)_gr_table[gb].limit << UV_GAM_RANGE_SHFT; 696 end = (unsigned long)grt->limit << UV_GAM_RANGE_SHFT; 697 698 pr_info("UV: GAM Range %2d %04x 0x%013lx-0x%013lx (%d)\n", i, grt->nasid, start, end, gb); 699 } 700 } 701 702 static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip) 703 { 704 unsigned long val; 705 int pnode; 706 707 pnode = uv_apicid_to_pnode(phys_apicid); 708 709 val = (1UL << UVH_IPI_INT_SEND_SHFT) | 710 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | 711 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | 712 APIC_DM_INIT; 713 714 uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 715 716 val = (1UL << UVH_IPI_INT_SEND_SHFT) | 717 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | 718 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | 719 APIC_DM_STARTUP; 720 721 uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 722 723 return 0; 724 } 725 726 static void uv_send_IPI_one(int cpu, int vector) 727 { 728 unsigned long apicid = per_cpu(x86_cpu_to_apicid, cpu); 729 int pnode = uv_apicid_to_pnode(apicid); 730 unsigned long dmode, val; 731 732 if (vector == NMI_VECTOR) 733 dmode = APIC_DELIVERY_MODE_NMI; 734 else 735 dmode = APIC_DELIVERY_MODE_FIXED; 736 737 val = (1UL << UVH_IPI_INT_SEND_SHFT) | 738 (apicid << UVH_IPI_INT_APIC_ID_SHFT) | 739 (dmode << UVH_IPI_INT_DELIVERY_MODE_SHFT) | 740 (vector << UVH_IPI_INT_VECTOR_SHFT); 741 742 uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 743 } 744 745 static void uv_send_IPI_mask(const struct cpumask *mask, int vector) 746 { 747 unsigned int cpu; 748 749 for_each_cpu(cpu, mask) 750 uv_send_IPI_one(cpu, vector); 751 } 752 753 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) 754 { 755 unsigned int this_cpu = smp_processor_id(); 756 unsigned int cpu; 757 758 for_each_cpu(cpu, mask) { 759 if (cpu != this_cpu) 760 uv_send_IPI_one(cpu, vector); 761 } 762 } 763 764 static void uv_send_IPI_allbutself(int vector) 765 { 766 unsigned int this_cpu = smp_processor_id(); 767 unsigned int cpu; 768 769 for_each_online_cpu(cpu) { 770 if (cpu != this_cpu) 771 uv_send_IPI_one(cpu, vector); 772 } 773 } 774 775 static void uv_send_IPI_all(int vector) 776 { 777 uv_send_IPI_mask(cpu_online_mask, vector); 778 } 779 780 static int uv_apic_id_valid(u32 apicid) 781 { 782 return 1; 783 } 784 785 static int uv_apic_id_registered(void) 786 { 787 return 1; 788 } 789 790 static void uv_init_apic_ldr(void) 791 { 792 } 793 794 static u32 apic_uv_calc_apicid(unsigned int cpu) 795 { 796 return apic_default_calc_apicid(cpu); 797 } 798 799 static unsigned int x2apic_get_apic_id(unsigned long id) 800 { 801 return id; 802 } 803 804 static u32 set_apic_id(unsigned int id) 805 { 806 return id; 807 } 808 809 static unsigned int uv_read_apic_id(void) 810 { 811 return x2apic_get_apic_id(apic_read(APIC_ID)); 812 } 813 814 static int uv_phys_pkg_id(int initial_apicid, int index_msb) 815 { 816 return uv_read_apic_id() >> index_msb; 817 } 818 819 static void uv_send_IPI_self(int vector) 820 { 821 apic_write(APIC_SELF_IPI, vector); 822 } 823 824 static int uv_probe(void) 825 { 826 return apic == &apic_x2apic_uv_x; 827 } 828 829 static struct apic apic_x2apic_uv_x __ro_after_init = { 830 831 .name = "UV large system", 832 .probe = uv_probe, 833 .acpi_madt_oem_check = uv_acpi_madt_oem_check, 834 .apic_id_valid = uv_apic_id_valid, 835 .apic_id_registered = uv_apic_id_registered, 836 837 .delivery_mode = APIC_DELIVERY_MODE_FIXED, 838 .dest_mode_logical = false, 839 840 .disable_esr = 0, 841 842 .check_apicid_used = NULL, 843 .init_apic_ldr = uv_init_apic_ldr, 844 .ioapic_phys_id_map = NULL, 845 .setup_apic_routing = NULL, 846 .cpu_present_to_apicid = default_cpu_present_to_apicid, 847 .apicid_to_cpu_present = NULL, 848 .check_phys_apicid_present = default_check_phys_apicid_present, 849 .phys_pkg_id = uv_phys_pkg_id, 850 851 .get_apic_id = x2apic_get_apic_id, 852 .set_apic_id = set_apic_id, 853 854 .calc_dest_apicid = apic_uv_calc_apicid, 855 856 .send_IPI = uv_send_IPI_one, 857 .send_IPI_mask = uv_send_IPI_mask, 858 .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself, 859 .send_IPI_allbutself = uv_send_IPI_allbutself, 860 .send_IPI_all = uv_send_IPI_all, 861 .send_IPI_self = uv_send_IPI_self, 862 863 .wakeup_secondary_cpu = uv_wakeup_secondary, 864 .inquire_remote_apic = NULL, 865 866 .read = native_apic_msr_read, 867 .write = native_apic_msr_write, 868 .eoi_write = native_apic_msr_eoi_write, 869 .icr_read = native_x2apic_icr_read, 870 .icr_write = native_x2apic_icr_write, 871 .wait_icr_idle = native_x2apic_wait_icr_idle, 872 .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle, 873 }; 874 875 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH 3 876 #define DEST_SHIFT UVXH_RH_GAM_ALIAS_0_REDIRECT_CONFIG_DEST_BASE_SHFT 877 878 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size) 879 { 880 union uvh_rh_gam_alias_2_overlay_config_u alias; 881 union uvh_rh_gam_alias_2_redirect_config_u redirect; 882 unsigned long m_redirect; 883 unsigned long m_overlay; 884 int i; 885 886 for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) { 887 switch (i) { 888 case 0: 889 m_redirect = UVH_RH_GAM_ALIAS_0_REDIRECT_CONFIG; 890 m_overlay = UVH_RH_GAM_ALIAS_0_OVERLAY_CONFIG; 891 break; 892 case 1: 893 m_redirect = UVH_RH_GAM_ALIAS_1_REDIRECT_CONFIG; 894 m_overlay = UVH_RH_GAM_ALIAS_1_OVERLAY_CONFIG; 895 break; 896 case 2: 897 m_redirect = UVH_RH_GAM_ALIAS_2_REDIRECT_CONFIG; 898 m_overlay = UVH_RH_GAM_ALIAS_2_OVERLAY_CONFIG; 899 break; 900 } 901 alias.v = uv_read_local_mmr(m_overlay); 902 if (alias.s.enable && alias.s.base == 0) { 903 *size = (1UL << alias.s.m_alias); 904 redirect.v = uv_read_local_mmr(m_redirect); 905 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT; 906 return; 907 } 908 } 909 *base = *size = 0; 910 } 911 912 enum map_type {map_wb, map_uc}; 913 static const char * const mt[] = { "WB", "UC" }; 914 915 static __init void map_high(char *id, unsigned long base, int pshift, int bshift, int max_pnode, enum map_type map_type) 916 { 917 unsigned long bytes, paddr; 918 919 paddr = base << pshift; 920 bytes = (1UL << bshift) * (max_pnode + 1); 921 if (!paddr) { 922 pr_info("UV: Map %s_HI base address NULL\n", id); 923 return; 924 } 925 if (map_type == map_uc) 926 init_extra_mapping_uc(paddr, bytes); 927 else 928 init_extra_mapping_wb(paddr, bytes); 929 930 pr_info("UV: Map %s_HI 0x%lx - 0x%lx %s (%d segments)\n", 931 id, paddr, paddr + bytes, mt[map_type], max_pnode + 1); 932 } 933 934 static __init void map_gru_high(int max_pnode) 935 { 936 union uvh_rh_gam_gru_overlay_config_u gru; 937 unsigned long mask, base; 938 int shift; 939 940 if (UVH_RH_GAM_GRU_OVERLAY_CONFIG) { 941 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG); 942 shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT; 943 mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_MASK; 944 } else if (UVH_RH10_GAM_GRU_OVERLAY_CONFIG) { 945 gru.v = uv_read_local_mmr(UVH_RH10_GAM_GRU_OVERLAY_CONFIG); 946 shift = UVH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT; 947 mask = UVH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_MASK; 948 } else { 949 pr_err("UV: GRU unavailable (no MMR)\n"); 950 return; 951 } 952 953 if (!gru.s.enable) { 954 pr_info("UV: GRU disabled (by BIOS)\n"); 955 return; 956 } 957 958 base = (gru.v & mask) >> shift; 959 map_high("GRU", base, shift, shift, max_pnode, map_wb); 960 gru_start_paddr = ((u64)base << shift); 961 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1); 962 } 963 964 static __init void map_mmr_high(int max_pnode) 965 { 966 unsigned long base; 967 int shift; 968 bool enable; 969 970 if (UVH_RH10_GAM_MMR_OVERLAY_CONFIG) { 971 union uvh_rh10_gam_mmr_overlay_config_u mmr; 972 973 mmr.v = uv_read_local_mmr(UVH_RH10_GAM_MMR_OVERLAY_CONFIG); 974 enable = mmr.s.enable; 975 base = mmr.s.base; 976 shift = UVH_RH10_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT; 977 } else if (UVH_RH_GAM_MMR_OVERLAY_CONFIG) { 978 union uvh_rh_gam_mmr_overlay_config_u mmr; 979 980 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG); 981 enable = mmr.s.enable; 982 base = mmr.s.base; 983 shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT; 984 } else { 985 pr_err("UV:%s:RH_GAM_MMR_OVERLAY_CONFIG MMR undefined?\n", 986 __func__); 987 return; 988 } 989 990 if (enable) 991 map_high("MMR", base, shift, shift, max_pnode, map_uc); 992 else 993 pr_info("UV: MMR disabled\n"); 994 } 995 996 /* Arch specific ENUM cases */ 997 enum mmioh_arch { 998 UV2_MMIOH = -1, 999 UVY_MMIOH0, UVY_MMIOH1, 1000 UVX_MMIOH0, UVX_MMIOH1, 1001 }; 1002 1003 /* Calculate and Map MMIOH Regions */ 1004 static void __init calc_mmioh_map(enum mmioh_arch index, 1005 int min_pnode, int max_pnode, 1006 int shift, unsigned long base, int m_io, int n_io) 1007 { 1008 unsigned long mmr, nasid_mask; 1009 int nasid, min_nasid, max_nasid, lnasid, mapped; 1010 int i, fi, li, n, max_io; 1011 char id[8]; 1012 1013 /* One (UV2) mapping */ 1014 if (index == UV2_MMIOH) { 1015 strncpy(id, "MMIOH", sizeof(id)); 1016 max_io = max_pnode; 1017 mapped = 0; 1018 goto map_exit; 1019 } 1020 1021 /* small and large MMIOH mappings */ 1022 switch (index) { 1023 case UVY_MMIOH0: 1024 mmr = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG0; 1025 nasid_mask = UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK; 1026 n = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG0_DEPTH; 1027 min_nasid = min_pnode; 1028 max_nasid = max_pnode; 1029 mapped = 1; 1030 break; 1031 case UVY_MMIOH1: 1032 mmr = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG1; 1033 nasid_mask = UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK; 1034 n = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG1_DEPTH; 1035 min_nasid = min_pnode; 1036 max_nasid = max_pnode; 1037 mapped = 1; 1038 break; 1039 case UVX_MMIOH0: 1040 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0; 1041 nasid_mask = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_MASK; 1042 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_DEPTH; 1043 min_nasid = min_pnode * 2; 1044 max_nasid = max_pnode * 2; 1045 mapped = 1; 1046 break; 1047 case UVX_MMIOH1: 1048 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1; 1049 nasid_mask = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_MASK; 1050 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_DEPTH; 1051 min_nasid = min_pnode * 2; 1052 max_nasid = max_pnode * 2; 1053 mapped = 1; 1054 break; 1055 default: 1056 pr_err("UV:%s:Invalid mapping type:%d\n", __func__, index); 1057 return; 1058 } 1059 1060 /* enum values chosen so (index mod 2) is MMIOH 0/1 (low/high) */ 1061 snprintf(id, sizeof(id), "MMIOH%d", index%2); 1062 1063 max_io = lnasid = fi = li = -1; 1064 for (i = 0; i < n; i++) { 1065 unsigned long m_redirect = mmr + i * 8; 1066 unsigned long redirect = uv_read_local_mmr(m_redirect); 1067 1068 nasid = redirect & nasid_mask; 1069 if (i == 0) 1070 pr_info("UV: %s redirect base 0x%lx(@0x%lx) 0x%04x\n", 1071 id, redirect, m_redirect, nasid); 1072 1073 /* Invalid NASID check */ 1074 if (nasid < min_nasid || max_nasid < nasid) { 1075 pr_err("UV:%s:Invalid NASID:%x (range:%x..%x)\n", 1076 __func__, index, min_nasid, max_nasid); 1077 nasid = -1; 1078 } 1079 1080 if (nasid == lnasid) { 1081 li = i; 1082 /* Last entry check: */ 1083 if (i != n-1) 1084 continue; 1085 } 1086 1087 /* Check if we have a cached (or last) redirect to print: */ 1088 if (lnasid != -1 || (i == n-1 && nasid != -1)) { 1089 unsigned long addr1, addr2; 1090 int f, l; 1091 1092 if (lnasid == -1) { 1093 f = l = i; 1094 lnasid = nasid; 1095 } else { 1096 f = fi; 1097 l = li; 1098 } 1099 addr1 = (base << shift) + f * (1ULL << m_io); 1100 addr2 = (base << shift) + (l + 1) * (1ULL << m_io); 1101 pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n", 1102 id, fi, li, lnasid, addr1, addr2); 1103 if (max_io < l) 1104 max_io = l; 1105 } 1106 fi = li = i; 1107 lnasid = nasid; 1108 } 1109 1110 map_exit: 1111 pr_info("UV: %s base:0x%lx shift:%d m_io:%d max_io:%d max_pnode:0x%x\n", 1112 id, base, shift, m_io, max_io, max_pnode); 1113 1114 if (max_io >= 0 && !mapped) 1115 map_high(id, base, shift, m_io, max_io, map_uc); 1116 } 1117 1118 static __init void map_mmioh_high(int min_pnode, int max_pnode) 1119 { 1120 /* UVY flavor */ 1121 if (UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0) { 1122 union uvh_rh10_gam_mmioh_overlay_config0_u mmioh0; 1123 union uvh_rh10_gam_mmioh_overlay_config1_u mmioh1; 1124 1125 mmioh0.v = uv_read_local_mmr(UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0); 1126 if (unlikely(mmioh0.s.enable == 0)) 1127 pr_info("UV: MMIOH0 disabled\n"); 1128 else 1129 calc_mmioh_map(UVY_MMIOH0, min_pnode, max_pnode, 1130 UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT, 1131 mmioh0.s.base, mmioh0.s.m_io, mmioh0.s.n_io); 1132 1133 mmioh1.v = uv_read_local_mmr(UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1); 1134 if (unlikely(mmioh1.s.enable == 0)) 1135 pr_info("UV: MMIOH1 disabled\n"); 1136 else 1137 calc_mmioh_map(UVY_MMIOH1, min_pnode, max_pnode, 1138 UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT, 1139 mmioh1.s.base, mmioh1.s.m_io, mmioh1.s.n_io); 1140 return; 1141 } 1142 /* UVX flavor */ 1143 if (UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0) { 1144 union uvh_rh_gam_mmioh_overlay_config0_u mmioh0; 1145 union uvh_rh_gam_mmioh_overlay_config1_u mmioh1; 1146 1147 mmioh0.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0); 1148 if (unlikely(mmioh0.s.enable == 0)) 1149 pr_info("UV: MMIOH0 disabled\n"); 1150 else { 1151 unsigned long base = uvxy_field(mmioh0, base, 0); 1152 int m_io = uvxy_field(mmioh0, m_io, 0); 1153 int n_io = uvxy_field(mmioh0, n_io, 0); 1154 1155 calc_mmioh_map(UVX_MMIOH0, min_pnode, max_pnode, 1156 UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT, 1157 base, m_io, n_io); 1158 } 1159 1160 mmioh1.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1); 1161 if (unlikely(mmioh1.s.enable == 0)) 1162 pr_info("UV: MMIOH1 disabled\n"); 1163 else { 1164 unsigned long base = uvxy_field(mmioh1, base, 0); 1165 int m_io = uvxy_field(mmioh1, m_io, 0); 1166 int n_io = uvxy_field(mmioh1, n_io, 0); 1167 1168 calc_mmioh_map(UVX_MMIOH1, min_pnode, max_pnode, 1169 UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT, 1170 base, m_io, n_io); 1171 } 1172 return; 1173 } 1174 1175 /* UV2 flavor */ 1176 if (UVH_RH_GAM_MMIOH_OVERLAY_CONFIG) { 1177 union uvh_rh_gam_mmioh_overlay_config_u mmioh; 1178 1179 mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG); 1180 if (unlikely(mmioh.s2.enable == 0)) 1181 pr_info("UV: MMIOH disabled\n"); 1182 else 1183 calc_mmioh_map(UV2_MMIOH, min_pnode, max_pnode, 1184 UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_BASE_SHFT, 1185 mmioh.s2.base, mmioh.s2.m_io, mmioh.s2.n_io); 1186 return; 1187 } 1188 } 1189 1190 static __init void map_low_mmrs(void) 1191 { 1192 if (UV_GLOBAL_MMR32_BASE) 1193 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE); 1194 1195 if (UV_LOCAL_MMR_BASE) 1196 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE); 1197 } 1198 1199 static __init void uv_rtc_init(void) 1200 { 1201 long status; 1202 u64 ticks_per_sec; 1203 1204 status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec); 1205 1206 if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) { 1207 pr_warn("UV: unable to determine platform RTC clock frequency, guessing.\n"); 1208 1209 /* BIOS gives wrong value for clock frequency, so guess: */ 1210 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL; 1211 } else { 1212 sn_rtc_cycles_per_second = ticks_per_sec; 1213 } 1214 } 1215 1216 /* Direct Legacy VGA I/O traffic to designated IOH */ 1217 static int uv_set_vga_state(struct pci_dev *pdev, bool decode, unsigned int command_bits, u32 flags) 1218 { 1219 int domain, bus, rc; 1220 1221 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) 1222 return 0; 1223 1224 if ((command_bits & PCI_COMMAND_IO) == 0) 1225 return 0; 1226 1227 domain = pci_domain_nr(pdev->bus); 1228 bus = pdev->bus->number; 1229 1230 rc = uv_bios_set_legacy_vga_target(decode, domain, bus); 1231 1232 return rc; 1233 } 1234 1235 /* 1236 * Called on each CPU to initialize the per_cpu UV data area. 1237 * FIXME: hotplug not supported yet 1238 */ 1239 void uv_cpu_init(void) 1240 { 1241 /* CPU 0 initialization will be done via uv_system_init. */ 1242 if (smp_processor_id() == 0) 1243 return; 1244 1245 uv_hub_info->nr_online_cpus++; 1246 } 1247 1248 struct mn { 1249 unsigned char m_val; 1250 unsigned char n_val; 1251 unsigned char m_shift; 1252 unsigned char n_lshift; 1253 }; 1254 1255 /* Initialize caller's MN struct and fill in values */ 1256 static void get_mn(struct mn *mnp) 1257 { 1258 memset(mnp, 0, sizeof(*mnp)); 1259 mnp->n_val = uv_cpuid.n_skt; 1260 if (is_uv(UV4|UVY)) { 1261 mnp->m_val = 0; 1262 mnp->n_lshift = 0; 1263 } else if (is_uv3_hub()) { 1264 union uvyh_gr0_gam_gr_config_u m_gr_config; 1265 1266 mnp->m_val = uv_cpuid.m_skt; 1267 m_gr_config.v = uv_read_local_mmr(UVH_GR0_GAM_GR_CONFIG); 1268 mnp->n_lshift = m_gr_config.s3.m_skt; 1269 } else if (is_uv2_hub()) { 1270 mnp->m_val = uv_cpuid.m_skt; 1271 mnp->n_lshift = mnp->m_val == 40 ? 40 : 39; 1272 } 1273 mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0; 1274 } 1275 1276 static void __init uv_init_hub_info(struct uv_hub_info_s *hi) 1277 { 1278 struct mn mn; 1279 1280 get_mn(&mn); 1281 hi->gpa_mask = mn.m_val ? 1282 (1UL << (mn.m_val + mn.n_val)) - 1 : 1283 (1UL << uv_cpuid.gpa_shift) - 1; 1284 1285 hi->m_val = mn.m_val; 1286 hi->n_val = mn.n_val; 1287 hi->m_shift = mn.m_shift; 1288 hi->n_lshift = mn.n_lshift ? mn.n_lshift : 0; 1289 hi->hub_revision = uv_hub_info->hub_revision; 1290 hi->hub_type = uv_hub_info->hub_type; 1291 hi->pnode_mask = uv_cpuid.pnode_mask; 1292 hi->nasid_shift = uv_cpuid.nasid_shift; 1293 hi->min_pnode = _min_pnode; 1294 hi->min_socket = _min_socket; 1295 hi->pnode_to_socket = _pnode_to_socket; 1296 hi->socket_to_node = _socket_to_node; 1297 hi->socket_to_pnode = _socket_to_pnode; 1298 hi->gr_table_len = _gr_table_len; 1299 hi->gr_table = _gr_table; 1300 1301 uv_cpuid.gnode_shift = max_t(unsigned int, uv_cpuid.gnode_shift, mn.n_val); 1302 hi->gnode_extra = (uv_node_id & ~((1 << uv_cpuid.gnode_shift) - 1)) >> 1; 1303 if (mn.m_val) 1304 hi->gnode_upper = (u64)hi->gnode_extra << mn.m_val; 1305 1306 if (uv_gp_table) { 1307 hi->global_mmr_base = uv_gp_table->mmr_base; 1308 hi->global_mmr_shift = uv_gp_table->mmr_shift; 1309 hi->global_gru_base = uv_gp_table->gru_base; 1310 hi->global_gru_shift = uv_gp_table->gru_shift; 1311 hi->gpa_shift = uv_gp_table->gpa_shift; 1312 hi->gpa_mask = (1UL << hi->gpa_shift) - 1; 1313 } else { 1314 hi->global_mmr_base = 1315 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG) & 1316 ~UV_MMR_ENABLE; 1317 hi->global_mmr_shift = _UV_GLOBAL_MMR64_PNODE_SHIFT; 1318 } 1319 1320 get_lowmem_redirect(&hi->lowmem_remap_base, &hi->lowmem_remap_top); 1321 1322 hi->apic_pnode_shift = uv_cpuid.socketid_shift; 1323 1324 /* Show system specific info: */ 1325 pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n", hi->n_val, hi->m_val, hi->m_shift, hi->n_lshift); 1326 pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n", hi->gpa_mask, hi->gpa_shift, hi->pnode_mask, hi->apic_pnode_shift); 1327 pr_info("UV: mmr_base/shift:0x%lx/%ld\n", hi->global_mmr_base, hi->global_mmr_shift); 1328 if (hi->global_gru_base) 1329 pr_info("UV: gru_base/shift:0x%lx/%ld\n", 1330 hi->global_gru_base, hi->global_gru_shift); 1331 1332 pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n", hi->gnode_upper, hi->gnode_extra); 1333 } 1334 1335 static void __init decode_gam_params(unsigned long ptr) 1336 { 1337 uv_gp_table = (struct uv_gam_parameters *)ptr; 1338 1339 pr_info("UV: GAM Params...\n"); 1340 pr_info("UV: mmr_base/shift:0x%llx/%d gru_base/shift:0x%llx/%d gpa_shift:%d\n", 1341 uv_gp_table->mmr_base, uv_gp_table->mmr_shift, 1342 uv_gp_table->gru_base, uv_gp_table->gru_shift, 1343 uv_gp_table->gpa_shift); 1344 } 1345 1346 static void __init decode_gam_rng_tbl(unsigned long ptr) 1347 { 1348 struct uv_gam_range_entry *gre = (struct uv_gam_range_entry *)ptr; 1349 unsigned long lgre = 0, gend = 0; 1350 int index = 0; 1351 int sock_min = 999999, pnode_min = 99999; 1352 int sock_max = -1, pnode_max = -1; 1353 1354 uv_gre_table = gre; 1355 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) { 1356 unsigned long size = ((unsigned long)(gre->limit - lgre) 1357 << UV_GAM_RANGE_SHFT); 1358 int order = 0; 1359 char suffix[] = " KMGTPE"; 1360 int flag = ' '; 1361 1362 while (size > 9999 && order < sizeof(suffix)) { 1363 size /= 1024; 1364 order++; 1365 } 1366 1367 /* adjust max block size to current range start */ 1368 if (gre->type == 1 || gre->type == 2) 1369 if (adj_blksize(lgre)) 1370 flag = '*'; 1371 1372 if (!index) { 1373 pr_info("UV: GAM Range Table...\n"); 1374 pr_info("UV: # %20s %14s %6s %4s %5s %3s %2s\n", "Range", "", "Size", "Type", "NASID", "SID", "PN"); 1375 } 1376 pr_info("UV: %2d: 0x%014lx-0x%014lx%c %5lu%c %3d %04x %02x %02x\n", 1377 index++, 1378 (unsigned long)lgre << UV_GAM_RANGE_SHFT, 1379 (unsigned long)gre->limit << UV_GAM_RANGE_SHFT, 1380 flag, size, suffix[order], 1381 gre->type, gre->nasid, gre->sockid, gre->pnode); 1382 1383 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) 1384 gend = (unsigned long)gre->limit << UV_GAM_RANGE_SHFT; 1385 1386 /* update to next range start */ 1387 lgre = gre->limit; 1388 if (sock_min > gre->sockid) 1389 sock_min = gre->sockid; 1390 if (sock_max < gre->sockid) 1391 sock_max = gre->sockid; 1392 if (pnode_min > gre->pnode) 1393 pnode_min = gre->pnode; 1394 if (pnode_max < gre->pnode) 1395 pnode_max = gre->pnode; 1396 } 1397 _min_socket = sock_min; 1398 _max_socket = sock_max; 1399 _min_pnode = pnode_min; 1400 _max_pnode = pnode_max; 1401 _gr_table_len = index; 1402 1403 pr_info("UV: GRT: %d entries, sockets(min:%x,max:%x), pnodes(min:%x,max:%x), gap_end(%d)\n", 1404 index, _min_socket, _max_socket, _min_pnode, _max_pnode, fls64(gend)); 1405 } 1406 1407 /* Walk through UVsystab decoding the fields */ 1408 static int __init decode_uv_systab(void) 1409 { 1410 struct uv_systab *st; 1411 int i; 1412 1413 /* Get mapped UVsystab pointer */ 1414 st = uv_systab; 1415 1416 /* If UVsystab is version 1, there is no extended UVsystab */ 1417 if (st && st->revision == UV_SYSTAB_VERSION_1) 1418 return 0; 1419 1420 if ((!st) || (st->revision < UV_SYSTAB_VERSION_UV4_LATEST)) { 1421 int rev = st ? st->revision : 0; 1422 1423 pr_err("UV: BIOS UVsystab mismatch, (%x < %x)\n", 1424 rev, UV_SYSTAB_VERSION_UV4_LATEST); 1425 pr_err("UV: Does not support UV, switch to non-UV x86_64\n"); 1426 uv_system_type = UV_NONE; 1427 1428 return -EINVAL; 1429 } 1430 1431 for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) { 1432 unsigned long ptr = st->entry[i].offset; 1433 1434 if (!ptr) 1435 continue; 1436 1437 /* point to payload */ 1438 ptr += (unsigned long)st; 1439 1440 switch (st->entry[i].type) { 1441 case UV_SYSTAB_TYPE_GAM_PARAMS: 1442 decode_gam_params(ptr); 1443 break; 1444 1445 case UV_SYSTAB_TYPE_GAM_RNG_TBL: 1446 decode_gam_rng_tbl(ptr); 1447 break; 1448 1449 case UV_SYSTAB_TYPE_ARCH_TYPE: 1450 /* already processed in early startup */ 1451 break; 1452 1453 default: 1454 pr_err("UV:%s:Unrecognized UV_SYSTAB_TYPE:%d, skipped\n", 1455 __func__, st->entry[i].type); 1456 break; 1457 } 1458 } 1459 return 0; 1460 } 1461 1462 /* Set up physical blade translations from UVH_NODE_PRESENT_TABLE */ 1463 static __init void boot_init_possible_blades(struct uv_hub_info_s *hub_info) 1464 { 1465 unsigned long np; 1466 int i, uv_pb = 0; 1467 1468 if (UVH_NODE_PRESENT_TABLE) { 1469 pr_info("UV: NODE_PRESENT_DEPTH = %d\n", 1470 UVH_NODE_PRESENT_TABLE_DEPTH); 1471 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) { 1472 np = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8); 1473 pr_info("UV: NODE_PRESENT(%d) = 0x%016lx\n", i, np); 1474 uv_pb += hweight64(np); 1475 } 1476 } 1477 if (UVH_NODE_PRESENT_0) { 1478 np = uv_read_local_mmr(UVH_NODE_PRESENT_0); 1479 pr_info("UV: NODE_PRESENT_0 = 0x%016lx\n", np); 1480 uv_pb += hweight64(np); 1481 } 1482 if (UVH_NODE_PRESENT_1) { 1483 np = uv_read_local_mmr(UVH_NODE_PRESENT_1); 1484 pr_info("UV: NODE_PRESENT_1 = 0x%016lx\n", np); 1485 uv_pb += hweight64(np); 1486 } 1487 if (uv_possible_blades != uv_pb) 1488 uv_possible_blades = uv_pb; 1489 1490 pr_info("UV: number nodes/possible blades %d\n", uv_pb); 1491 } 1492 1493 static void __init build_socket_tables(void) 1494 { 1495 struct uv_gam_range_entry *gre = uv_gre_table; 1496 int num, nump; 1497 int cpu, i, lnid; 1498 int minsock = _min_socket; 1499 int maxsock = _max_socket; 1500 int minpnode = _min_pnode; 1501 int maxpnode = _max_pnode; 1502 size_t bytes; 1503 1504 if (!gre) { 1505 if (is_uv2_hub() || is_uv3_hub()) { 1506 pr_info("UV: No UVsystab socket table, ignoring\n"); 1507 return; 1508 } 1509 pr_err("UV: Error: UVsystab address translations not available!\n"); 1510 BUG(); 1511 } 1512 1513 /* Build socket id -> node id, pnode */ 1514 num = maxsock - minsock + 1; 1515 bytes = num * sizeof(_socket_to_node[0]); 1516 _socket_to_node = kmalloc(bytes, GFP_KERNEL); 1517 _socket_to_pnode = kmalloc(bytes, GFP_KERNEL); 1518 1519 nump = maxpnode - minpnode + 1; 1520 bytes = nump * sizeof(_pnode_to_socket[0]); 1521 _pnode_to_socket = kmalloc(bytes, GFP_KERNEL); 1522 BUG_ON(!_socket_to_node || !_socket_to_pnode || !_pnode_to_socket); 1523 1524 for (i = 0; i < num; i++) 1525 _socket_to_node[i] = _socket_to_pnode[i] = SOCK_EMPTY; 1526 1527 for (i = 0; i < nump; i++) 1528 _pnode_to_socket[i] = SOCK_EMPTY; 1529 1530 /* Fill in pnode/node/addr conversion list values: */ 1531 pr_info("UV: GAM Building socket/pnode conversion tables\n"); 1532 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) { 1533 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) 1534 continue; 1535 i = gre->sockid - minsock; 1536 /* Duplicate: */ 1537 if (_socket_to_pnode[i] != SOCK_EMPTY) 1538 continue; 1539 _socket_to_pnode[i] = gre->pnode; 1540 1541 i = gre->pnode - minpnode; 1542 _pnode_to_socket[i] = gre->sockid; 1543 1544 pr_info("UV: sid:%02x type:%d nasid:%04x pn:%02x pn2s:%2x\n", 1545 gre->sockid, gre->type, gre->nasid, 1546 _socket_to_pnode[gre->sockid - minsock], 1547 _pnode_to_socket[gre->pnode - minpnode]); 1548 } 1549 1550 /* Set socket -> node values: */ 1551 lnid = NUMA_NO_NODE; 1552 for_each_present_cpu(cpu) { 1553 int nid = cpu_to_node(cpu); 1554 int apicid, sockid; 1555 1556 if (lnid == nid) 1557 continue; 1558 lnid = nid; 1559 apicid = per_cpu(x86_cpu_to_apicid, cpu); 1560 sockid = apicid >> uv_cpuid.socketid_shift; 1561 _socket_to_node[sockid - minsock] = nid; 1562 pr_info("UV: sid:%02x: apicid:%04x node:%2d\n", 1563 sockid, apicid, nid); 1564 } 1565 1566 /* Set up physical blade to pnode translation from GAM Range Table: */ 1567 bytes = num_possible_nodes() * sizeof(_node_to_pnode[0]); 1568 _node_to_pnode = kmalloc(bytes, GFP_KERNEL); 1569 BUG_ON(!_node_to_pnode); 1570 1571 for (lnid = 0; lnid < num_possible_nodes(); lnid++) { 1572 unsigned short sockid; 1573 1574 for (sockid = minsock; sockid <= maxsock; sockid++) { 1575 if (lnid == _socket_to_node[sockid - minsock]) { 1576 _node_to_pnode[lnid] = _socket_to_pnode[sockid - minsock]; 1577 break; 1578 } 1579 } 1580 if (sockid > maxsock) { 1581 pr_err("UV: socket for node %d not found!\n", lnid); 1582 BUG(); 1583 } 1584 } 1585 1586 /* 1587 * If socket id == pnode or socket id == node for all nodes, 1588 * system runs faster by removing corresponding conversion table. 1589 */ 1590 pr_info("UV: Checking socket->node/pnode for identity maps\n"); 1591 if (minsock == 0) { 1592 for (i = 0; i < num; i++) 1593 if (_socket_to_node[i] == SOCK_EMPTY || i != _socket_to_node[i]) 1594 break; 1595 if (i >= num) { 1596 kfree(_socket_to_node); 1597 _socket_to_node = NULL; 1598 pr_info("UV: 1:1 socket_to_node table removed\n"); 1599 } 1600 } 1601 if (minsock == minpnode) { 1602 for (i = 0; i < num; i++) 1603 if (_socket_to_pnode[i] != SOCK_EMPTY && 1604 _socket_to_pnode[i] != i + minpnode) 1605 break; 1606 if (i >= num) { 1607 kfree(_socket_to_pnode); 1608 _socket_to_pnode = NULL; 1609 pr_info("UV: 1:1 socket_to_pnode table removed\n"); 1610 } 1611 } 1612 } 1613 1614 /* Check which reboot to use */ 1615 static void check_efi_reboot(void) 1616 { 1617 /* If EFI reboot not available, use ACPI reboot */ 1618 if (!efi_enabled(EFI_BOOT)) 1619 reboot_type = BOOT_ACPI; 1620 } 1621 1622 /* 1623 * User proc fs file handling now deprecated. 1624 * Recommend using /sys/firmware/sgi_uv/... instead. 1625 */ 1626 static int __maybe_unused proc_hubbed_show(struct seq_file *file, void *data) 1627 { 1628 pr_notice_once("%s: using deprecated /proc/sgi_uv/hubbed, use /sys/firmware/sgi_uv/hub_type\n", 1629 current->comm); 1630 seq_printf(file, "0x%x\n", uv_hubbed_system); 1631 return 0; 1632 } 1633 1634 static int __maybe_unused proc_hubless_show(struct seq_file *file, void *data) 1635 { 1636 pr_notice_once("%s: using deprecated /proc/sgi_uv/hubless, use /sys/firmware/sgi_uv/hubless\n", 1637 current->comm); 1638 seq_printf(file, "0x%x\n", uv_hubless_system); 1639 return 0; 1640 } 1641 1642 static int __maybe_unused proc_archtype_show(struct seq_file *file, void *data) 1643 { 1644 pr_notice_once("%s: using deprecated /proc/sgi_uv/archtype, use /sys/firmware/sgi_uv/archtype\n", 1645 current->comm); 1646 seq_printf(file, "%s/%s\n", uv_archtype, oem_table_id); 1647 return 0; 1648 } 1649 1650 static __init void uv_setup_proc_files(int hubless) 1651 { 1652 struct proc_dir_entry *pde; 1653 1654 pde = proc_mkdir(UV_PROC_NODE, NULL); 1655 proc_create_single("archtype", 0, pde, proc_archtype_show); 1656 if (hubless) 1657 proc_create_single("hubless", 0, pde, proc_hubless_show); 1658 else 1659 proc_create_single("hubbed", 0, pde, proc_hubbed_show); 1660 } 1661 1662 /* Initialize UV hubless systems */ 1663 static __init int uv_system_init_hubless(void) 1664 { 1665 int rc; 1666 1667 /* Setup PCH NMI handler */ 1668 uv_nmi_setup_hubless(); 1669 1670 /* Init kernel/BIOS interface */ 1671 rc = uv_bios_init(); 1672 if (rc < 0) 1673 return rc; 1674 1675 /* Process UVsystab */ 1676 rc = decode_uv_systab(); 1677 if (rc < 0) 1678 return rc; 1679 1680 /* Set section block size for current node memory */ 1681 set_block_size(); 1682 1683 /* Create user access node */ 1684 if (rc >= 0) 1685 uv_setup_proc_files(1); 1686 1687 check_efi_reboot(); 1688 1689 return rc; 1690 } 1691 1692 static void __init uv_system_init_hub(void) 1693 { 1694 struct uv_hub_info_s hub_info = {0}; 1695 int bytes, cpu, nodeid; 1696 unsigned short min_pnode = 9999, max_pnode = 0; 1697 char *hub = is_uv5_hub() ? "UV500" : 1698 is_uv4_hub() ? "UV400" : 1699 is_uv3_hub() ? "UV300" : 1700 is_uv2_hub() ? "UV2000/3000" : NULL; 1701 1702 if (!hub) { 1703 pr_err("UV: Unknown/unsupported UV hub\n"); 1704 return; 1705 } 1706 pr_info("UV: Found %s hub\n", hub); 1707 1708 map_low_mmrs(); 1709 1710 /* Get uv_systab for decoding, setup UV BIOS calls */ 1711 uv_bios_init(); 1712 1713 /* If there's an UVsystab problem then abort UV init: */ 1714 if (decode_uv_systab() < 0) { 1715 pr_err("UV: Mangled UVsystab format\n"); 1716 return; 1717 } 1718 1719 build_socket_tables(); 1720 build_uv_gr_table(); 1721 set_block_size(); 1722 uv_init_hub_info(&hub_info); 1723 uv_possible_blades = num_possible_nodes(); 1724 if (!_node_to_pnode) 1725 boot_init_possible_blades(&hub_info); 1726 1727 /* uv_num_possible_blades() is really the hub count: */ 1728 pr_info("UV: Found %d hubs, %d nodes, %d CPUs\n", uv_num_possible_blades(), num_possible_nodes(), num_possible_cpus()); 1729 1730 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, &sn_region_size, &system_serial_number); 1731 hub_info.coherency_domain_number = sn_coherency_id; 1732 uv_rtc_init(); 1733 1734 bytes = sizeof(void *) * uv_num_possible_blades(); 1735 __uv_hub_info_list = kzalloc(bytes, GFP_KERNEL); 1736 BUG_ON(!__uv_hub_info_list); 1737 1738 bytes = sizeof(struct uv_hub_info_s); 1739 for_each_node(nodeid) { 1740 struct uv_hub_info_s *new_hub; 1741 1742 if (__uv_hub_info_list[nodeid]) { 1743 pr_err("UV: Node %d UV HUB already initialized!?\n", nodeid); 1744 BUG(); 1745 } 1746 1747 /* Allocate new per hub info list */ 1748 new_hub = (nodeid == 0) ? &uv_hub_info_node0 : kzalloc_node(bytes, GFP_KERNEL, nodeid); 1749 BUG_ON(!new_hub); 1750 __uv_hub_info_list[nodeid] = new_hub; 1751 new_hub = uv_hub_info_list(nodeid); 1752 BUG_ON(!new_hub); 1753 *new_hub = hub_info; 1754 1755 /* Use information from GAM table if available: */ 1756 if (_node_to_pnode) 1757 new_hub->pnode = _node_to_pnode[nodeid]; 1758 else /* Or fill in during CPU loop: */ 1759 new_hub->pnode = 0xffff; 1760 1761 new_hub->numa_blade_id = uv_node_to_blade_id(nodeid); 1762 new_hub->memory_nid = NUMA_NO_NODE; 1763 new_hub->nr_possible_cpus = 0; 1764 new_hub->nr_online_cpus = 0; 1765 } 1766 1767 /* Initialize per CPU info: */ 1768 for_each_possible_cpu(cpu) { 1769 int apicid = per_cpu(x86_cpu_to_apicid, cpu); 1770 int numa_node_id; 1771 unsigned short pnode; 1772 1773 nodeid = cpu_to_node(cpu); 1774 numa_node_id = numa_cpu_node(cpu); 1775 pnode = uv_apicid_to_pnode(apicid); 1776 1777 uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list(nodeid); 1778 uv_cpu_info_per(cpu)->blade_cpu_id = uv_cpu_hub_info(cpu)->nr_possible_cpus++; 1779 if (uv_cpu_hub_info(cpu)->memory_nid == NUMA_NO_NODE) 1780 uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu); 1781 1782 /* Init memoryless node: */ 1783 if (nodeid != numa_node_id && 1784 uv_hub_info_list(numa_node_id)->pnode == 0xffff) 1785 uv_hub_info_list(numa_node_id)->pnode = pnode; 1786 else if (uv_cpu_hub_info(cpu)->pnode == 0xffff) 1787 uv_cpu_hub_info(cpu)->pnode = pnode; 1788 } 1789 1790 for_each_node(nodeid) { 1791 unsigned short pnode = uv_hub_info_list(nodeid)->pnode; 1792 1793 /* Add pnode info for pre-GAM list nodes without CPUs: */ 1794 if (pnode == 0xffff) { 1795 unsigned long paddr; 1796 1797 paddr = node_start_pfn(nodeid) << PAGE_SHIFT; 1798 pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr)); 1799 uv_hub_info_list(nodeid)->pnode = pnode; 1800 } 1801 min_pnode = min(pnode, min_pnode); 1802 max_pnode = max(pnode, max_pnode); 1803 pr_info("UV: UVHUB node:%2d pn:%02x nrcpus:%d\n", 1804 nodeid, 1805 uv_hub_info_list(nodeid)->pnode, 1806 uv_hub_info_list(nodeid)->nr_possible_cpus); 1807 } 1808 1809 pr_info("UV: min_pnode:%02x max_pnode:%02x\n", min_pnode, max_pnode); 1810 map_gru_high(max_pnode); 1811 map_mmr_high(max_pnode); 1812 map_mmioh_high(min_pnode, max_pnode); 1813 1814 uv_nmi_setup(); 1815 uv_cpu_init(); 1816 uv_setup_proc_files(0); 1817 1818 /* Register Legacy VGA I/O redirection handler: */ 1819 pci_register_set_vga_state(uv_set_vga_state); 1820 1821 check_efi_reboot(); 1822 } 1823 1824 /* 1825 * There is a different code path needed to initialize a UV system that does 1826 * not have a "UV HUB" (referred to as "hubless"). 1827 */ 1828 void __init uv_system_init(void) 1829 { 1830 if (likely(!is_uv_system() && !is_uv_hubless(1))) 1831 return; 1832 1833 if (is_uv_system()) 1834 uv_system_init_hub(); 1835 else 1836 uv_system_init_hubless(); 1837 } 1838 1839 apic_driver(apic_x2apic_uv_x); 1840