1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * SGI UV APIC functions (note: not an Intel compatible APIC) 7 * 8 * (C) Copyright 2020 Hewlett Packard Enterprise Development LP 9 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved. 10 */ 11 #include <linux/crash_dump.h> 12 #include <linux/cpuhotplug.h> 13 #include <linux/cpumask.h> 14 #include <linux/proc_fs.h> 15 #include <linux/memory.h> 16 #include <linux/export.h> 17 #include <linux/pci.h> 18 #include <linux/acpi.h> 19 #include <linux/efi.h> 20 21 #include <asm/e820/api.h> 22 #include <asm/uv/uv_mmrs.h> 23 #include <asm/uv/uv_hub.h> 24 #include <asm/uv/bios.h> 25 #include <asm/uv/uv.h> 26 #include <asm/apic.h> 27 28 #include "local.h" 29 30 static enum uv_system_type uv_system_type; 31 static int uv_hubbed_system; 32 static int uv_hubless_system; 33 static u64 gru_start_paddr, gru_end_paddr; 34 static union uvh_apicid uvh_apicid; 35 static int uv_node_id; 36 37 /* Unpack AT/OEM/TABLE ID's to be NULL terminated strings */ 38 static u8 uv_archtype[UV_AT_SIZE + 1]; 39 static u8 oem_id[ACPI_OEM_ID_SIZE + 1]; 40 static u8 oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1]; 41 42 /* Information derived from CPUID and some UV MMRs */ 43 static struct { 44 unsigned int apicid_shift; 45 unsigned int apicid_mask; 46 unsigned int socketid_shift; /* aka pnode_shift for UV2/3 */ 47 unsigned int pnode_mask; 48 unsigned int nasid_shift; 49 unsigned int gpa_shift; 50 unsigned int gnode_shift; 51 unsigned int m_skt; 52 unsigned int n_skt; 53 } uv_cpuid; 54 55 static int uv_min_hub_revision_id; 56 57 static struct apic apic_x2apic_uv_x; 58 static struct uv_hub_info_s uv_hub_info_node0; 59 60 /* Set this to use hardware error handler instead of kernel panic: */ 61 static int disable_uv_undefined_panic = 1; 62 63 unsigned long uv_undefined(char *str) 64 { 65 if (likely(!disable_uv_undefined_panic)) 66 panic("UV: error: undefined MMR: %s\n", str); 67 else 68 pr_crit("UV: error: undefined MMR: %s\n", str); 69 70 /* Cause a machine fault: */ 71 return ~0ul; 72 } 73 EXPORT_SYMBOL(uv_undefined); 74 75 static unsigned long __init uv_early_read_mmr(unsigned long addr) 76 { 77 unsigned long val, *mmr; 78 79 mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr)); 80 val = *mmr; 81 early_iounmap(mmr, sizeof(*mmr)); 82 83 return val; 84 } 85 86 static inline bool is_GRU_range(u64 start, u64 end) 87 { 88 if (!gru_start_paddr) 89 return false; 90 91 return start >= gru_start_paddr && end <= gru_end_paddr; 92 } 93 94 static bool uv_is_untracked_pat_range(u64 start, u64 end) 95 { 96 return is_ISA_range(start, end) || is_GRU_range(start, end); 97 } 98 99 static void __init early_get_pnodeid(void) 100 { 101 int pnode; 102 103 uv_cpuid.m_skt = 0; 104 if (UVH_RH10_GAM_ADDR_MAP_CONFIG) { 105 union uvh_rh10_gam_addr_map_config_u m_n_config; 106 107 m_n_config.v = uv_early_read_mmr(UVH_RH10_GAM_ADDR_MAP_CONFIG); 108 uv_cpuid.n_skt = m_n_config.s.n_skt; 109 uv_cpuid.nasid_shift = 0; 110 } else if (UVH_RH_GAM_ADDR_MAP_CONFIG) { 111 union uvh_rh_gam_addr_map_config_u m_n_config; 112 113 m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_ADDR_MAP_CONFIG); 114 uv_cpuid.n_skt = m_n_config.s.n_skt; 115 if (is_uv(UV3)) 116 uv_cpuid.m_skt = m_n_config.s3.m_skt; 117 if (is_uv(UV2)) 118 uv_cpuid.m_skt = m_n_config.s2.m_skt; 119 uv_cpuid.nasid_shift = 1; 120 } else { 121 unsigned long GAM_ADDR_MAP_CONFIG = 0; 122 123 WARN(GAM_ADDR_MAP_CONFIG == 0, 124 "UV: WARN: GAM_ADDR_MAP_CONFIG is not available\n"); 125 uv_cpuid.n_skt = 0; 126 uv_cpuid.nasid_shift = 0; 127 } 128 129 if (is_uv(UV4|UVY)) 130 uv_cpuid.gnode_shift = 2; /* min partition is 4 sockets */ 131 132 uv_cpuid.pnode_mask = (1 << uv_cpuid.n_skt) - 1; 133 pnode = (uv_node_id >> uv_cpuid.nasid_shift) & uv_cpuid.pnode_mask; 134 uv_cpuid.gpa_shift = 46; /* Default unless changed */ 135 136 pr_info("UV: n_skt:%d pnmsk:%x pn:%x\n", 137 uv_cpuid.n_skt, uv_cpuid.pnode_mask, pnode); 138 } 139 140 /* Running on a UV Hubbed system, determine which UV Hub Type it is */ 141 static int __init early_set_hub_type(void) 142 { 143 union uvh_node_id_u node_id; 144 145 /* 146 * The NODE_ID MMR is always at offset 0. 147 * Contains the chip part # + revision. 148 * Node_id field started with 15 bits, 149 * ... now 7 but upper 8 are masked to 0. 150 * All blades/nodes have the same part # and hub revision. 151 */ 152 node_id.v = uv_early_read_mmr(UVH_NODE_ID); 153 uv_node_id = node_id.sx.node_id; 154 155 switch (node_id.s.part_number) { 156 157 case UV5_HUB_PART_NUMBER: 158 uv_min_hub_revision_id = node_id.s.revision 159 + UV5_HUB_REVISION_BASE; 160 uv_hub_type_set(UV5); 161 break; 162 163 /* UV4/4A only have a revision difference */ 164 case UV4_HUB_PART_NUMBER: 165 uv_min_hub_revision_id = node_id.s.revision 166 + UV4_HUB_REVISION_BASE - 1; 167 uv_hub_type_set(UV4); 168 if (uv_min_hub_revision_id == UV4A_HUB_REVISION_BASE) 169 uv_hub_type_set(UV4|UV4A); 170 break; 171 172 case UV3_HUB_PART_NUMBER: 173 case UV3_HUB_PART_NUMBER_X: 174 uv_min_hub_revision_id = node_id.s.revision 175 + UV3_HUB_REVISION_BASE; 176 uv_hub_type_set(UV3); 177 break; 178 179 case UV2_HUB_PART_NUMBER: 180 case UV2_HUB_PART_NUMBER_X: 181 uv_min_hub_revision_id = node_id.s.revision 182 + UV2_HUB_REVISION_BASE - 1; 183 uv_hub_type_set(UV2); 184 break; 185 186 default: 187 return 0; 188 } 189 190 pr_info("UV: part#:%x rev:%d rev_id:%d UVtype:0x%x\n", 191 node_id.s.part_number, node_id.s.revision, 192 uv_min_hub_revision_id, is_uv(~0)); 193 194 return 1; 195 } 196 197 static void __init uv_tsc_check_sync(void) 198 { 199 u64 mmr; 200 int sync_state; 201 int mmr_shift; 202 char *state; 203 204 /* UV5 guarantees synced TSCs; do not zero TSC_ADJUST */ 205 if (!is_uv(UV2|UV3|UV4)) { 206 mark_tsc_async_resets("UV5+"); 207 return; 208 } 209 210 /* UV2,3,4, UV BIOS TSC sync state available */ 211 mmr = uv_early_read_mmr(UVH_TSC_SYNC_MMR); 212 mmr_shift = 213 is_uv2_hub() ? UVH_TSC_SYNC_SHIFT_UV2K : UVH_TSC_SYNC_SHIFT; 214 sync_state = (mmr >> mmr_shift) & UVH_TSC_SYNC_MASK; 215 216 /* Check if TSC is valid for all sockets */ 217 switch (sync_state) { 218 case UVH_TSC_SYNC_VALID: 219 state = "in sync"; 220 mark_tsc_async_resets("UV BIOS"); 221 break; 222 223 /* If BIOS state unknown, don't do anything */ 224 case UVH_TSC_SYNC_UNKNOWN: 225 state = "unknown"; 226 break; 227 228 /* Otherwise, BIOS indicates problem with TSC */ 229 default: 230 state = "unstable"; 231 mark_tsc_unstable("UV BIOS"); 232 break; 233 } 234 pr_info("UV: TSC sync state from BIOS:0%d(%s)\n", sync_state, state); 235 } 236 237 /* Selector for (4|4A|5) structs */ 238 #define uvxy_field(sname, field, undef) ( \ 239 is_uv(UV4A) ? sname.s4a.field : \ 240 is_uv(UV4) ? sname.s4.field : \ 241 is_uv(UV3) ? sname.s3.field : \ 242 undef) 243 244 /* [Copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */ 245 246 #define SMT_LEVEL 0 /* Leaf 0xb SMT level */ 247 #define INVALID_TYPE 0 /* Leaf 0xb sub-leaf types */ 248 #define SMT_TYPE 1 249 #define CORE_TYPE 2 250 #define LEAFB_SUBTYPE(ecx) (((ecx) >> 8) & 0xff) 251 #define BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f) 252 253 static void set_x2apic_bits(void) 254 { 255 unsigned int eax, ebx, ecx, edx, sub_index; 256 unsigned int sid_shift; 257 258 cpuid(0, &eax, &ebx, &ecx, &edx); 259 if (eax < 0xb) { 260 pr_info("UV: CPU does not have CPUID.11\n"); 261 return; 262 } 263 264 cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx); 265 if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) { 266 pr_info("UV: CPUID.11 not implemented\n"); 267 return; 268 } 269 270 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax); 271 sub_index = 1; 272 do { 273 cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx); 274 if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) { 275 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax); 276 break; 277 } 278 sub_index++; 279 } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE); 280 281 uv_cpuid.apicid_shift = 0; 282 uv_cpuid.apicid_mask = (~(-1 << sid_shift)); 283 uv_cpuid.socketid_shift = sid_shift; 284 } 285 286 static void __init early_get_apic_socketid_shift(void) 287 { 288 if (is_uv2_hub() || is_uv3_hub()) 289 uvh_apicid.v = uv_early_read_mmr(UVH_APICID); 290 291 set_x2apic_bits(); 292 293 pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n", uv_cpuid.apicid_shift, uv_cpuid.apicid_mask); 294 pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n", uv_cpuid.socketid_shift, uv_cpuid.pnode_mask); 295 } 296 297 static void __init uv_stringify(int len, char *to, char *from) 298 { 299 /* Relies on 'to' being NULL chars so result will be NULL terminated */ 300 strncpy(to, from, len-1); 301 302 /* Trim trailing spaces */ 303 (void)strim(to); 304 } 305 306 /* Find UV arch type entry in UVsystab */ 307 static unsigned long __init early_find_archtype(struct uv_systab *st) 308 { 309 int i; 310 311 for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) { 312 unsigned long ptr = st->entry[i].offset; 313 314 if (!ptr) 315 continue; 316 ptr += (unsigned long)st; 317 if (st->entry[i].type == UV_SYSTAB_TYPE_ARCH_TYPE) 318 return ptr; 319 } 320 return 0; 321 } 322 323 /* Validate UV arch type field in UVsystab */ 324 static int __init decode_arch_type(unsigned long ptr) 325 { 326 struct uv_arch_type_entry *uv_ate = (struct uv_arch_type_entry *)ptr; 327 int n = strlen(uv_ate->archtype); 328 329 if (n > 0 && n < sizeof(uv_ate->archtype)) { 330 pr_info("UV: UVarchtype received from BIOS\n"); 331 uv_stringify(sizeof(uv_archtype), uv_archtype, uv_ate->archtype); 332 return 1; 333 } 334 return 0; 335 } 336 337 /* Determine if UV arch type entry might exist in UVsystab */ 338 static int __init early_get_arch_type(void) 339 { 340 unsigned long uvst_physaddr, uvst_size, ptr; 341 struct uv_systab *st; 342 u32 rev; 343 int ret; 344 345 uvst_physaddr = get_uv_systab_phys(0); 346 if (!uvst_physaddr) 347 return 0; 348 349 st = early_memremap_ro(uvst_physaddr, sizeof(struct uv_systab)); 350 if (!st) { 351 pr_err("UV: Cannot access UVsystab, remap failed\n"); 352 return 0; 353 } 354 355 rev = st->revision; 356 if (rev < UV_SYSTAB_VERSION_UV5) { 357 early_memunmap(st, sizeof(struct uv_systab)); 358 return 0; 359 } 360 361 uvst_size = st->size; 362 early_memunmap(st, sizeof(struct uv_systab)); 363 st = early_memremap_ro(uvst_physaddr, uvst_size); 364 if (!st) { 365 pr_err("UV: Cannot access UVarchtype, remap failed\n"); 366 return 0; 367 } 368 369 ptr = early_find_archtype(st); 370 if (!ptr) { 371 early_memunmap(st, uvst_size); 372 return 0; 373 } 374 375 ret = decode_arch_type(ptr); 376 early_memunmap(st, uvst_size); 377 return ret; 378 } 379 380 /* UV system found, check which APIC MODE BIOS already selected */ 381 static void __init early_set_apic_mode(void) 382 { 383 if (x2apic_enabled()) 384 uv_system_type = UV_X2APIC; 385 else 386 uv_system_type = UV_LEGACY_APIC; 387 } 388 389 static int __init uv_set_system_type(char *_oem_id, char *_oem_table_id) 390 { 391 /* Save OEM_ID passed from ACPI MADT */ 392 uv_stringify(sizeof(oem_id), oem_id, _oem_id); 393 394 /* Check if BIOS sent us a UVarchtype */ 395 if (!early_get_arch_type()) 396 397 /* If not use OEM ID for UVarchtype */ 398 uv_stringify(sizeof(uv_archtype), uv_archtype, oem_id); 399 400 /* Check if not hubbed */ 401 if (strncmp(uv_archtype, "SGI", 3) != 0) { 402 403 /* (Not hubbed), check if not hubless */ 404 if (strncmp(uv_archtype, "NSGI", 4) != 0) 405 406 /* (Not hubless), not a UV */ 407 return 0; 408 409 /* Is UV hubless system */ 410 uv_hubless_system = 0x01; 411 412 /* UV5 Hubless */ 413 if (strncmp(uv_archtype, "NSGI5", 5) == 0) 414 uv_hubless_system |= 0x20; 415 416 /* UV4 Hubless: CH */ 417 else if (strncmp(uv_archtype, "NSGI4", 5) == 0) 418 uv_hubless_system |= 0x10; 419 420 /* UV3 Hubless: UV300/MC990X w/o hub */ 421 else 422 uv_hubless_system |= 0x8; 423 424 /* Copy OEM Table ID */ 425 uv_stringify(sizeof(oem_table_id), oem_table_id, _oem_table_id); 426 427 pr_info("UV: OEM IDs %s/%s, SystemType %d, HUBLESS ID %x\n", 428 oem_id, oem_table_id, uv_system_type, uv_hubless_system); 429 430 return 0; 431 } 432 433 if (numa_off) { 434 pr_err("UV: NUMA is off, disabling UV support\n"); 435 return 0; 436 } 437 438 /* Set hubbed type if true */ 439 uv_hub_info->hub_revision = 440 !strncmp(uv_archtype, "SGI5", 4) ? UV5_HUB_REVISION_BASE : 441 !strncmp(uv_archtype, "SGI4", 4) ? UV4_HUB_REVISION_BASE : 442 !strncmp(uv_archtype, "SGI3", 4) ? UV3_HUB_REVISION_BASE : 443 !strcmp(uv_archtype, "SGI2") ? UV2_HUB_REVISION_BASE : 0; 444 445 switch (uv_hub_info->hub_revision) { 446 case UV5_HUB_REVISION_BASE: 447 uv_hubbed_system = 0x21; 448 uv_hub_type_set(UV5); 449 break; 450 451 case UV4_HUB_REVISION_BASE: 452 uv_hubbed_system = 0x11; 453 uv_hub_type_set(UV4); 454 break; 455 456 case UV3_HUB_REVISION_BASE: 457 uv_hubbed_system = 0x9; 458 uv_hub_type_set(UV3); 459 break; 460 461 case UV2_HUB_REVISION_BASE: 462 uv_hubbed_system = 0x5; 463 uv_hub_type_set(UV2); 464 break; 465 466 default: 467 return 0; 468 } 469 470 /* Get UV hub chip part number & revision */ 471 early_set_hub_type(); 472 473 /* Other UV setup functions */ 474 early_set_apic_mode(); 475 early_get_pnodeid(); 476 early_get_apic_socketid_shift(); 477 x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range; 478 x86_platform.nmi_init = uv_nmi_init; 479 uv_tsc_check_sync(); 480 481 return 1; 482 } 483 484 /* Called early to probe for the correct APIC driver */ 485 static int __init uv_acpi_madt_oem_check(char *_oem_id, char *_oem_table_id) 486 { 487 /* Set up early hub info fields for Node 0 */ 488 uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0; 489 490 /* If not UV, return. */ 491 if (uv_set_system_type(_oem_id, _oem_table_id) == 0) 492 return 0; 493 494 /* Save for display of the OEM Table ID */ 495 uv_stringify(sizeof(oem_table_id), oem_table_id, _oem_table_id); 496 497 pr_info("UV: OEM IDs %s/%s, System/UVType %d/0x%x, HUB RevID %d\n", 498 oem_id, oem_table_id, uv_system_type, is_uv(UV_ANY), 499 uv_min_hub_revision_id); 500 501 return 0; 502 } 503 504 enum uv_system_type get_uv_system_type(void) 505 { 506 return uv_system_type; 507 } 508 509 int uv_get_hubless_system(void) 510 { 511 return uv_hubless_system; 512 } 513 EXPORT_SYMBOL_GPL(uv_get_hubless_system); 514 515 ssize_t uv_get_archtype(char *buf, int len) 516 { 517 return scnprintf(buf, len, "%s/%s", uv_archtype, oem_table_id); 518 } 519 EXPORT_SYMBOL_GPL(uv_get_archtype); 520 521 int is_uv_system(void) 522 { 523 return uv_system_type != UV_NONE; 524 } 525 EXPORT_SYMBOL_GPL(is_uv_system); 526 527 int is_uv_hubbed(int uvtype) 528 { 529 return (uv_hubbed_system & uvtype); 530 } 531 EXPORT_SYMBOL_GPL(is_uv_hubbed); 532 533 static int is_uv_hubless(int uvtype) 534 { 535 return (uv_hubless_system & uvtype); 536 } 537 538 void **__uv_hub_info_list; 539 EXPORT_SYMBOL_GPL(__uv_hub_info_list); 540 541 DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info); 542 EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info); 543 544 short uv_possible_blades; 545 EXPORT_SYMBOL_GPL(uv_possible_blades); 546 547 unsigned long sn_rtc_cycles_per_second; 548 EXPORT_SYMBOL(sn_rtc_cycles_per_second); 549 550 /* The following values are used for the per node hub info struct */ 551 static __initdata unsigned short _min_socket, _max_socket; 552 static __initdata unsigned short _min_pnode, _max_pnode, _gr_table_len; 553 static __initdata struct uv_gam_range_entry *uv_gre_table; 554 static __initdata struct uv_gam_parameters *uv_gp_table; 555 static __initdata unsigned short *_socket_to_node; 556 static __initdata unsigned short *_socket_to_pnode; 557 static __initdata unsigned short *_pnode_to_socket; 558 static __initdata unsigned short *_node_to_socket; 559 560 static __initdata struct uv_gam_range_s *_gr_table; 561 562 #define SOCK_EMPTY ((unsigned short)~0) 563 564 /* Default UV memory block size is 2GB */ 565 static unsigned long mem_block_size __initdata = (2UL << 30); 566 567 /* Kernel parameter to specify UV mem block size */ 568 static int __init parse_mem_block_size(char *ptr) 569 { 570 unsigned long size = memparse(ptr, NULL); 571 572 /* Size will be rounded down by set_block_size() below */ 573 mem_block_size = size; 574 return 0; 575 } 576 early_param("uv_memblksize", parse_mem_block_size); 577 578 static __init int adj_blksize(u32 lgre) 579 { 580 unsigned long base = (unsigned long)lgre << UV_GAM_RANGE_SHFT; 581 unsigned long size; 582 583 for (size = mem_block_size; size > MIN_MEMORY_BLOCK_SIZE; size >>= 1) 584 if (IS_ALIGNED(base, size)) 585 break; 586 587 if (size >= mem_block_size) 588 return 0; 589 590 mem_block_size = size; 591 return 1; 592 } 593 594 static __init void set_block_size(void) 595 { 596 unsigned int order = ffs(mem_block_size); 597 598 if (order) { 599 /* adjust for ffs return of 1..64 */ 600 set_memory_block_size_order(order - 1); 601 pr_info("UV: mem_block_size set to 0x%lx\n", mem_block_size); 602 } else { 603 /* bad or zero value, default to 1UL << 31 (2GB) */ 604 pr_err("UV: mem_block_size error with 0x%lx\n", mem_block_size); 605 set_memory_block_size_order(31); 606 } 607 } 608 609 /* Build GAM range lookup table: */ 610 static __init void build_uv_gr_table(void) 611 { 612 struct uv_gam_range_entry *gre = uv_gre_table; 613 struct uv_gam_range_s *grt; 614 unsigned long last_limit = 0, ram_limit = 0; 615 int bytes, i, sid, lsid = -1, indx = 0, lindx = -1; 616 617 if (!gre) 618 return; 619 620 bytes = _gr_table_len * sizeof(struct uv_gam_range_s); 621 grt = kzalloc(bytes, GFP_KERNEL); 622 if (WARN_ON_ONCE(!grt)) 623 return; 624 _gr_table = grt; 625 626 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) { 627 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) { 628 if (!ram_limit) { 629 /* Mark hole between RAM/non-RAM: */ 630 ram_limit = last_limit; 631 last_limit = gre->limit; 632 lsid++; 633 continue; 634 } 635 last_limit = gre->limit; 636 pr_info("UV: extra hole in GAM RE table @%d\n", (int)(gre - uv_gre_table)); 637 continue; 638 } 639 if (_max_socket < gre->sockid) { 640 pr_err("UV: GAM table sockid(%d) too large(>%d) @%d\n", gre->sockid, _max_socket, (int)(gre - uv_gre_table)); 641 continue; 642 } 643 sid = gre->sockid - _min_socket; 644 if (lsid < sid) { 645 /* New range: */ 646 grt = &_gr_table[indx]; 647 grt->base = lindx; 648 grt->nasid = gre->nasid; 649 grt->limit = last_limit = gre->limit; 650 lsid = sid; 651 lindx = indx++; 652 continue; 653 } 654 /* Update range: */ 655 if (lsid == sid && !ram_limit) { 656 /* .. if contiguous: */ 657 if (grt->limit == last_limit) { 658 grt->limit = last_limit = gre->limit; 659 continue; 660 } 661 } 662 /* Non-contiguous RAM range: */ 663 if (!ram_limit) { 664 grt++; 665 grt->base = lindx; 666 grt->nasid = gre->nasid; 667 grt->limit = last_limit = gre->limit; 668 continue; 669 } 670 /* Non-contiguous/non-RAM: */ 671 grt++; 672 /* base is this entry */ 673 grt->base = grt - _gr_table; 674 grt->nasid = gre->nasid; 675 grt->limit = last_limit = gre->limit; 676 lsid++; 677 } 678 679 /* Shorten table if possible */ 680 grt++; 681 i = grt - _gr_table; 682 if (i < _gr_table_len) { 683 void *ret; 684 685 bytes = i * sizeof(struct uv_gam_range_s); 686 ret = krealloc(_gr_table, bytes, GFP_KERNEL); 687 if (ret) { 688 _gr_table = ret; 689 _gr_table_len = i; 690 } 691 } 692 693 /* Display resultant GAM range table: */ 694 for (i = 0, grt = _gr_table; i < _gr_table_len; i++, grt++) { 695 unsigned long start, end; 696 int gb = grt->base; 697 698 start = gb < 0 ? 0 : (unsigned long)_gr_table[gb].limit << UV_GAM_RANGE_SHFT; 699 end = (unsigned long)grt->limit << UV_GAM_RANGE_SHFT; 700 701 pr_info("UV: GAM Range %2d %04x 0x%013lx-0x%013lx (%d)\n", i, grt->nasid, start, end, gb); 702 } 703 } 704 705 static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip) 706 { 707 unsigned long val; 708 int pnode; 709 710 pnode = uv_apicid_to_pnode(phys_apicid); 711 712 val = (1UL << UVH_IPI_INT_SEND_SHFT) | 713 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | 714 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | 715 APIC_DM_INIT; 716 717 uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 718 719 val = (1UL << UVH_IPI_INT_SEND_SHFT) | 720 (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) | 721 ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) | 722 APIC_DM_STARTUP; 723 724 uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 725 726 return 0; 727 } 728 729 static void uv_send_IPI_one(int cpu, int vector) 730 { 731 unsigned long apicid = per_cpu(x86_cpu_to_apicid, cpu); 732 int pnode = uv_apicid_to_pnode(apicid); 733 unsigned long dmode, val; 734 735 if (vector == NMI_VECTOR) 736 dmode = APIC_DELIVERY_MODE_NMI; 737 else 738 dmode = APIC_DELIVERY_MODE_FIXED; 739 740 val = (1UL << UVH_IPI_INT_SEND_SHFT) | 741 (apicid << UVH_IPI_INT_APIC_ID_SHFT) | 742 (dmode << UVH_IPI_INT_DELIVERY_MODE_SHFT) | 743 (vector << UVH_IPI_INT_VECTOR_SHFT); 744 745 uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 746 } 747 748 static void uv_send_IPI_mask(const struct cpumask *mask, int vector) 749 { 750 unsigned int cpu; 751 752 for_each_cpu(cpu, mask) 753 uv_send_IPI_one(cpu, vector); 754 } 755 756 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) 757 { 758 unsigned int this_cpu = smp_processor_id(); 759 unsigned int cpu; 760 761 for_each_cpu(cpu, mask) { 762 if (cpu != this_cpu) 763 uv_send_IPI_one(cpu, vector); 764 } 765 } 766 767 static void uv_send_IPI_allbutself(int vector) 768 { 769 unsigned int this_cpu = smp_processor_id(); 770 unsigned int cpu; 771 772 for_each_online_cpu(cpu) { 773 if (cpu != this_cpu) 774 uv_send_IPI_one(cpu, vector); 775 } 776 } 777 778 static void uv_send_IPI_all(int vector) 779 { 780 uv_send_IPI_mask(cpu_online_mask, vector); 781 } 782 783 static u32 set_apic_id(unsigned int id) 784 { 785 return id; 786 } 787 788 static unsigned int uv_read_apic_id(void) 789 { 790 return x2apic_get_apic_id(apic_read(APIC_ID)); 791 } 792 793 static int uv_phys_pkg_id(int initial_apicid, int index_msb) 794 { 795 return uv_read_apic_id() >> index_msb; 796 } 797 798 static int uv_probe(void) 799 { 800 return apic == &apic_x2apic_uv_x; 801 } 802 803 static struct apic apic_x2apic_uv_x __ro_after_init = { 804 805 .name = "UV large system", 806 .probe = uv_probe, 807 .acpi_madt_oem_check = uv_acpi_madt_oem_check, 808 809 .delivery_mode = APIC_DELIVERY_MODE_FIXED, 810 .dest_mode_logical = false, 811 812 .disable_esr = 0, 813 814 .cpu_present_to_apicid = default_cpu_present_to_apicid, 815 .phys_pkg_id = uv_phys_pkg_id, 816 817 .max_apic_id = UINT_MAX, 818 .get_apic_id = x2apic_get_apic_id, 819 .set_apic_id = set_apic_id, 820 821 .calc_dest_apicid = apic_default_calc_apicid, 822 823 .send_IPI = uv_send_IPI_one, 824 .send_IPI_mask = uv_send_IPI_mask, 825 .send_IPI_mask_allbutself = uv_send_IPI_mask_allbutself, 826 .send_IPI_allbutself = uv_send_IPI_allbutself, 827 .send_IPI_all = uv_send_IPI_all, 828 .send_IPI_self = x2apic_send_IPI_self, 829 830 .wakeup_secondary_cpu = uv_wakeup_secondary, 831 832 .read = native_apic_msr_read, 833 .write = native_apic_msr_write, 834 .eoi = native_apic_msr_eoi, 835 .icr_read = native_x2apic_icr_read, 836 .icr_write = native_x2apic_icr_write, 837 }; 838 839 #define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH 3 840 #define DEST_SHIFT UVXH_RH_GAM_ALIAS_0_REDIRECT_CONFIG_DEST_BASE_SHFT 841 842 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size) 843 { 844 union uvh_rh_gam_alias_2_overlay_config_u alias; 845 union uvh_rh_gam_alias_2_redirect_config_u redirect; 846 unsigned long m_redirect; 847 unsigned long m_overlay; 848 int i; 849 850 for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) { 851 switch (i) { 852 case 0: 853 m_redirect = UVH_RH_GAM_ALIAS_0_REDIRECT_CONFIG; 854 m_overlay = UVH_RH_GAM_ALIAS_0_OVERLAY_CONFIG; 855 break; 856 case 1: 857 m_redirect = UVH_RH_GAM_ALIAS_1_REDIRECT_CONFIG; 858 m_overlay = UVH_RH_GAM_ALIAS_1_OVERLAY_CONFIG; 859 break; 860 case 2: 861 m_redirect = UVH_RH_GAM_ALIAS_2_REDIRECT_CONFIG; 862 m_overlay = UVH_RH_GAM_ALIAS_2_OVERLAY_CONFIG; 863 break; 864 } 865 alias.v = uv_read_local_mmr(m_overlay); 866 if (alias.s.enable && alias.s.base == 0) { 867 *size = (1UL << alias.s.m_alias); 868 redirect.v = uv_read_local_mmr(m_redirect); 869 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT; 870 return; 871 } 872 } 873 *base = *size = 0; 874 } 875 876 enum map_type {map_wb, map_uc}; 877 static const char * const mt[] = { "WB", "UC" }; 878 879 static __init void map_high(char *id, unsigned long base, int pshift, int bshift, int max_pnode, enum map_type map_type) 880 { 881 unsigned long bytes, paddr; 882 883 paddr = base << pshift; 884 bytes = (1UL << bshift) * (max_pnode + 1); 885 if (!paddr) { 886 pr_info("UV: Map %s_HI base address NULL\n", id); 887 return; 888 } 889 if (map_type == map_uc) 890 init_extra_mapping_uc(paddr, bytes); 891 else 892 init_extra_mapping_wb(paddr, bytes); 893 894 pr_info("UV: Map %s_HI 0x%lx - 0x%lx %s (%d segments)\n", 895 id, paddr, paddr + bytes, mt[map_type], max_pnode + 1); 896 } 897 898 static __init void map_gru_high(int max_pnode) 899 { 900 union uvh_rh_gam_gru_overlay_config_u gru; 901 unsigned long mask, base; 902 int shift; 903 904 if (UVH_RH_GAM_GRU_OVERLAY_CONFIG) { 905 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG); 906 shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT; 907 mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_BASE_MASK; 908 } else if (UVH_RH10_GAM_GRU_OVERLAY_CONFIG) { 909 gru.v = uv_read_local_mmr(UVH_RH10_GAM_GRU_OVERLAY_CONFIG); 910 shift = UVH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_SHFT; 911 mask = UVH_RH10_GAM_GRU_OVERLAY_CONFIG_BASE_MASK; 912 } else { 913 pr_err("UV: GRU unavailable (no MMR)\n"); 914 return; 915 } 916 917 if (!gru.s.enable) { 918 pr_info("UV: GRU disabled (by BIOS)\n"); 919 return; 920 } 921 922 base = (gru.v & mask) >> shift; 923 map_high("GRU", base, shift, shift, max_pnode, map_wb); 924 gru_start_paddr = ((u64)base << shift); 925 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1); 926 } 927 928 static __init void map_mmr_high(int max_pnode) 929 { 930 unsigned long base; 931 int shift; 932 bool enable; 933 934 if (UVH_RH10_GAM_MMR_OVERLAY_CONFIG) { 935 union uvh_rh10_gam_mmr_overlay_config_u mmr; 936 937 mmr.v = uv_read_local_mmr(UVH_RH10_GAM_MMR_OVERLAY_CONFIG); 938 enable = mmr.s.enable; 939 base = mmr.s.base; 940 shift = UVH_RH10_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT; 941 } else if (UVH_RH_GAM_MMR_OVERLAY_CONFIG) { 942 union uvh_rh_gam_mmr_overlay_config_u mmr; 943 944 mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG); 945 enable = mmr.s.enable; 946 base = mmr.s.base; 947 shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_BASE_SHFT; 948 } else { 949 pr_err("UV:%s:RH_GAM_MMR_OVERLAY_CONFIG MMR undefined?\n", 950 __func__); 951 return; 952 } 953 954 if (enable) 955 map_high("MMR", base, shift, shift, max_pnode, map_uc); 956 else 957 pr_info("UV: MMR disabled\n"); 958 } 959 960 /* Arch specific ENUM cases */ 961 enum mmioh_arch { 962 UV2_MMIOH = -1, 963 UVY_MMIOH0, UVY_MMIOH1, 964 UVX_MMIOH0, UVX_MMIOH1, 965 }; 966 967 /* Calculate and Map MMIOH Regions */ 968 static void __init calc_mmioh_map(enum mmioh_arch index, 969 int min_pnode, int max_pnode, 970 int shift, unsigned long base, int m_io, int n_io) 971 { 972 unsigned long mmr, nasid_mask; 973 int nasid, min_nasid, max_nasid, lnasid, mapped; 974 int i, fi, li, n, max_io; 975 char id[8]; 976 977 /* One (UV2) mapping */ 978 if (index == UV2_MMIOH) { 979 strncpy(id, "MMIOH", sizeof(id)); 980 max_io = max_pnode; 981 mapped = 0; 982 goto map_exit; 983 } 984 985 /* small and large MMIOH mappings */ 986 switch (index) { 987 case UVY_MMIOH0: 988 mmr = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG0; 989 nasid_mask = UVYH_RH10_GAM_MMIOH_REDIRECT_CONFIG0_NASID_MASK; 990 n = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG0_DEPTH; 991 min_nasid = min_pnode; 992 max_nasid = max_pnode; 993 mapped = 1; 994 break; 995 case UVY_MMIOH1: 996 mmr = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG1; 997 nasid_mask = UVYH_RH10_GAM_MMIOH_REDIRECT_CONFIG1_NASID_MASK; 998 n = UVH_RH10_GAM_MMIOH_REDIRECT_CONFIG1_DEPTH; 999 min_nasid = min_pnode; 1000 max_nasid = max_pnode; 1001 mapped = 1; 1002 break; 1003 case UVX_MMIOH0: 1004 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0; 1005 nasid_mask = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_NASID_MASK; 1006 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG0_DEPTH; 1007 min_nasid = min_pnode * 2; 1008 max_nasid = max_pnode * 2; 1009 mapped = 1; 1010 break; 1011 case UVX_MMIOH1: 1012 mmr = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1; 1013 nasid_mask = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_NASID_MASK; 1014 n = UVH_RH_GAM_MMIOH_REDIRECT_CONFIG1_DEPTH; 1015 min_nasid = min_pnode * 2; 1016 max_nasid = max_pnode * 2; 1017 mapped = 1; 1018 break; 1019 default: 1020 pr_err("UV:%s:Invalid mapping type:%d\n", __func__, index); 1021 return; 1022 } 1023 1024 /* enum values chosen so (index mod 2) is MMIOH 0/1 (low/high) */ 1025 snprintf(id, sizeof(id), "MMIOH%d", index%2); 1026 1027 max_io = lnasid = fi = li = -1; 1028 for (i = 0; i < n; i++) { 1029 unsigned long m_redirect = mmr + i * 8; 1030 unsigned long redirect = uv_read_local_mmr(m_redirect); 1031 1032 nasid = redirect & nasid_mask; 1033 if (i == 0) 1034 pr_info("UV: %s redirect base 0x%lx(@0x%lx) 0x%04x\n", 1035 id, redirect, m_redirect, nasid); 1036 1037 /* Invalid NASID check */ 1038 if (nasid < min_nasid || max_nasid < nasid) { 1039 /* Not an error: unused table entries get "poison" values */ 1040 pr_debug("UV:%s:Invalid NASID(%x):%x (range:%x..%x)\n", 1041 __func__, index, nasid, min_nasid, max_nasid); 1042 nasid = -1; 1043 } 1044 1045 if (nasid == lnasid) { 1046 li = i; 1047 /* Last entry check: */ 1048 if (i != n-1) 1049 continue; 1050 } 1051 1052 /* Check if we have a cached (or last) redirect to print: */ 1053 if (lnasid != -1 || (i == n-1 && nasid != -1)) { 1054 unsigned long addr1, addr2; 1055 int f, l; 1056 1057 if (lnasid == -1) { 1058 f = l = i; 1059 lnasid = nasid; 1060 } else { 1061 f = fi; 1062 l = li; 1063 } 1064 addr1 = (base << shift) + f * (1ULL << m_io); 1065 addr2 = (base << shift) + (l + 1) * (1ULL << m_io); 1066 pr_info("UV: %s[%03d..%03d] NASID 0x%04x ADDR 0x%016lx - 0x%016lx\n", 1067 id, fi, li, lnasid, addr1, addr2); 1068 if (max_io < l) 1069 max_io = l; 1070 } 1071 fi = li = i; 1072 lnasid = nasid; 1073 } 1074 1075 map_exit: 1076 pr_info("UV: %s base:0x%lx shift:%d m_io:%d max_io:%d max_pnode:0x%x\n", 1077 id, base, shift, m_io, max_io, max_pnode); 1078 1079 if (max_io >= 0 && !mapped) 1080 map_high(id, base, shift, m_io, max_io, map_uc); 1081 } 1082 1083 static __init void map_mmioh_high(int min_pnode, int max_pnode) 1084 { 1085 /* UVY flavor */ 1086 if (UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0) { 1087 union uvh_rh10_gam_mmioh_overlay_config0_u mmioh0; 1088 union uvh_rh10_gam_mmioh_overlay_config1_u mmioh1; 1089 1090 mmioh0.v = uv_read_local_mmr(UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0); 1091 if (unlikely(mmioh0.s.enable == 0)) 1092 pr_info("UV: MMIOH0 disabled\n"); 1093 else 1094 calc_mmioh_map(UVY_MMIOH0, min_pnode, max_pnode, 1095 UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT, 1096 mmioh0.s.base, mmioh0.s.m_io, mmioh0.s.n_io); 1097 1098 mmioh1.v = uv_read_local_mmr(UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1); 1099 if (unlikely(mmioh1.s.enable == 0)) 1100 pr_info("UV: MMIOH1 disabled\n"); 1101 else 1102 calc_mmioh_map(UVY_MMIOH1, min_pnode, max_pnode, 1103 UVH_RH10_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT, 1104 mmioh1.s.base, mmioh1.s.m_io, mmioh1.s.n_io); 1105 return; 1106 } 1107 /* UVX flavor */ 1108 if (UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0) { 1109 union uvh_rh_gam_mmioh_overlay_config0_u mmioh0; 1110 union uvh_rh_gam_mmioh_overlay_config1_u mmioh1; 1111 1112 mmioh0.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0); 1113 if (unlikely(mmioh0.s.enable == 0)) 1114 pr_info("UV: MMIOH0 disabled\n"); 1115 else { 1116 unsigned long base = uvxy_field(mmioh0, base, 0); 1117 int m_io = uvxy_field(mmioh0, m_io, 0); 1118 int n_io = uvxy_field(mmioh0, n_io, 0); 1119 1120 calc_mmioh_map(UVX_MMIOH0, min_pnode, max_pnode, 1121 UVH_RH_GAM_MMIOH_OVERLAY_CONFIG0_BASE_SHFT, 1122 base, m_io, n_io); 1123 } 1124 1125 mmioh1.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1); 1126 if (unlikely(mmioh1.s.enable == 0)) 1127 pr_info("UV: MMIOH1 disabled\n"); 1128 else { 1129 unsigned long base = uvxy_field(mmioh1, base, 0); 1130 int m_io = uvxy_field(mmioh1, m_io, 0); 1131 int n_io = uvxy_field(mmioh1, n_io, 0); 1132 1133 calc_mmioh_map(UVX_MMIOH1, min_pnode, max_pnode, 1134 UVH_RH_GAM_MMIOH_OVERLAY_CONFIG1_BASE_SHFT, 1135 base, m_io, n_io); 1136 } 1137 return; 1138 } 1139 1140 /* UV2 flavor */ 1141 if (UVH_RH_GAM_MMIOH_OVERLAY_CONFIG) { 1142 union uvh_rh_gam_mmioh_overlay_config_u mmioh; 1143 1144 mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG); 1145 if (unlikely(mmioh.s2.enable == 0)) 1146 pr_info("UV: MMIOH disabled\n"); 1147 else 1148 calc_mmioh_map(UV2_MMIOH, min_pnode, max_pnode, 1149 UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_BASE_SHFT, 1150 mmioh.s2.base, mmioh.s2.m_io, mmioh.s2.n_io); 1151 return; 1152 } 1153 } 1154 1155 static __init void map_low_mmrs(void) 1156 { 1157 if (UV_GLOBAL_MMR32_BASE) 1158 init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE); 1159 1160 if (UV_LOCAL_MMR_BASE) 1161 init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE); 1162 } 1163 1164 static __init void uv_rtc_init(void) 1165 { 1166 long status; 1167 u64 ticks_per_sec; 1168 1169 status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK, &ticks_per_sec); 1170 1171 if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) { 1172 pr_warn("UV: unable to determine platform RTC clock frequency, guessing.\n"); 1173 1174 /* BIOS gives wrong value for clock frequency, so guess: */ 1175 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL; 1176 } else { 1177 sn_rtc_cycles_per_second = ticks_per_sec; 1178 } 1179 } 1180 1181 /* Direct Legacy VGA I/O traffic to designated IOH */ 1182 static int uv_set_vga_state(struct pci_dev *pdev, bool decode, unsigned int command_bits, u32 flags) 1183 { 1184 int domain, bus, rc; 1185 1186 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE)) 1187 return 0; 1188 1189 if ((command_bits & PCI_COMMAND_IO) == 0) 1190 return 0; 1191 1192 domain = pci_domain_nr(pdev->bus); 1193 bus = pdev->bus->number; 1194 1195 rc = uv_bios_set_legacy_vga_target(decode, domain, bus); 1196 1197 return rc; 1198 } 1199 1200 /* 1201 * Called on each CPU to initialize the per_cpu UV data area. 1202 * FIXME: hotplug not supported yet 1203 */ 1204 void uv_cpu_init(void) 1205 { 1206 /* CPU 0 initialization will be done via uv_system_init. */ 1207 if (smp_processor_id() == 0) 1208 return; 1209 1210 uv_hub_info->nr_online_cpus++; 1211 } 1212 1213 struct mn { 1214 unsigned char m_val; 1215 unsigned char n_val; 1216 unsigned char m_shift; 1217 unsigned char n_lshift; 1218 }; 1219 1220 /* Initialize caller's MN struct and fill in values */ 1221 static void get_mn(struct mn *mnp) 1222 { 1223 memset(mnp, 0, sizeof(*mnp)); 1224 mnp->n_val = uv_cpuid.n_skt; 1225 if (is_uv(UV4|UVY)) { 1226 mnp->m_val = 0; 1227 mnp->n_lshift = 0; 1228 } else if (is_uv3_hub()) { 1229 union uvyh_gr0_gam_gr_config_u m_gr_config; 1230 1231 mnp->m_val = uv_cpuid.m_skt; 1232 m_gr_config.v = uv_read_local_mmr(UVH_GR0_GAM_GR_CONFIG); 1233 mnp->n_lshift = m_gr_config.s3.m_skt; 1234 } else if (is_uv2_hub()) { 1235 mnp->m_val = uv_cpuid.m_skt; 1236 mnp->n_lshift = mnp->m_val == 40 ? 40 : 39; 1237 } 1238 mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0; 1239 } 1240 1241 static void __init uv_init_hub_info(struct uv_hub_info_s *hi) 1242 { 1243 struct mn mn; 1244 1245 get_mn(&mn); 1246 hi->gpa_mask = mn.m_val ? 1247 (1UL << (mn.m_val + mn.n_val)) - 1 : 1248 (1UL << uv_cpuid.gpa_shift) - 1; 1249 1250 hi->m_val = mn.m_val; 1251 hi->n_val = mn.n_val; 1252 hi->m_shift = mn.m_shift; 1253 hi->n_lshift = mn.n_lshift ? mn.n_lshift : 0; 1254 hi->hub_revision = uv_hub_info->hub_revision; 1255 hi->hub_type = uv_hub_info->hub_type; 1256 hi->pnode_mask = uv_cpuid.pnode_mask; 1257 hi->nasid_shift = uv_cpuid.nasid_shift; 1258 hi->min_pnode = _min_pnode; 1259 hi->min_socket = _min_socket; 1260 hi->node_to_socket = _node_to_socket; 1261 hi->pnode_to_socket = _pnode_to_socket; 1262 hi->socket_to_node = _socket_to_node; 1263 hi->socket_to_pnode = _socket_to_pnode; 1264 hi->gr_table_len = _gr_table_len; 1265 hi->gr_table = _gr_table; 1266 1267 uv_cpuid.gnode_shift = max_t(unsigned int, uv_cpuid.gnode_shift, mn.n_val); 1268 hi->gnode_extra = (uv_node_id & ~((1 << uv_cpuid.gnode_shift) - 1)) >> 1; 1269 if (mn.m_val) 1270 hi->gnode_upper = (u64)hi->gnode_extra << mn.m_val; 1271 1272 if (uv_gp_table) { 1273 hi->global_mmr_base = uv_gp_table->mmr_base; 1274 hi->global_mmr_shift = uv_gp_table->mmr_shift; 1275 hi->global_gru_base = uv_gp_table->gru_base; 1276 hi->global_gru_shift = uv_gp_table->gru_shift; 1277 hi->gpa_shift = uv_gp_table->gpa_shift; 1278 hi->gpa_mask = (1UL << hi->gpa_shift) - 1; 1279 } else { 1280 hi->global_mmr_base = 1281 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG) & 1282 ~UV_MMR_ENABLE; 1283 hi->global_mmr_shift = _UV_GLOBAL_MMR64_PNODE_SHIFT; 1284 } 1285 1286 get_lowmem_redirect(&hi->lowmem_remap_base, &hi->lowmem_remap_top); 1287 1288 hi->apic_pnode_shift = uv_cpuid.socketid_shift; 1289 1290 /* Show system specific info: */ 1291 pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n", hi->n_val, hi->m_val, hi->m_shift, hi->n_lshift); 1292 pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n", hi->gpa_mask, hi->gpa_shift, hi->pnode_mask, hi->apic_pnode_shift); 1293 pr_info("UV: mmr_base/shift:0x%lx/%ld\n", hi->global_mmr_base, hi->global_mmr_shift); 1294 if (hi->global_gru_base) 1295 pr_info("UV: gru_base/shift:0x%lx/%ld\n", 1296 hi->global_gru_base, hi->global_gru_shift); 1297 1298 pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n", hi->gnode_upper, hi->gnode_extra); 1299 } 1300 1301 static void __init decode_gam_params(unsigned long ptr) 1302 { 1303 uv_gp_table = (struct uv_gam_parameters *)ptr; 1304 1305 pr_info("UV: GAM Params...\n"); 1306 pr_info("UV: mmr_base/shift:0x%llx/%d gru_base/shift:0x%llx/%d gpa_shift:%d\n", 1307 uv_gp_table->mmr_base, uv_gp_table->mmr_shift, 1308 uv_gp_table->gru_base, uv_gp_table->gru_shift, 1309 uv_gp_table->gpa_shift); 1310 } 1311 1312 static void __init decode_gam_rng_tbl(unsigned long ptr) 1313 { 1314 struct uv_gam_range_entry *gre = (struct uv_gam_range_entry *)ptr; 1315 unsigned long lgre = 0, gend = 0; 1316 int index = 0; 1317 int sock_min = INT_MAX, pnode_min = INT_MAX; 1318 int sock_max = -1, pnode_max = -1; 1319 1320 uv_gre_table = gre; 1321 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) { 1322 unsigned long size = ((unsigned long)(gre->limit - lgre) 1323 << UV_GAM_RANGE_SHFT); 1324 int order = 0; 1325 char suffix[] = " KMGTPE"; 1326 int flag = ' '; 1327 1328 while (size > 9999 && order < sizeof(suffix)) { 1329 size /= 1024; 1330 order++; 1331 } 1332 1333 /* adjust max block size to current range start */ 1334 if (gre->type == 1 || gre->type == 2) 1335 if (adj_blksize(lgre)) 1336 flag = '*'; 1337 1338 if (!index) { 1339 pr_info("UV: GAM Range Table...\n"); 1340 pr_info("UV: # %20s %14s %6s %4s %5s %3s %2s\n", "Range", "", "Size", "Type", "NASID", "SID", "PN"); 1341 } 1342 pr_info("UV: %2d: 0x%014lx-0x%014lx%c %5lu%c %3d %04x %02x %02x\n", 1343 index++, 1344 (unsigned long)lgre << UV_GAM_RANGE_SHFT, 1345 (unsigned long)gre->limit << UV_GAM_RANGE_SHFT, 1346 flag, size, suffix[order], 1347 gre->type, gre->nasid, gre->sockid, gre->pnode); 1348 1349 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) 1350 gend = (unsigned long)gre->limit << UV_GAM_RANGE_SHFT; 1351 1352 /* update to next range start */ 1353 lgre = gre->limit; 1354 if (sock_min > gre->sockid) 1355 sock_min = gre->sockid; 1356 if (sock_max < gre->sockid) 1357 sock_max = gre->sockid; 1358 if (pnode_min > gre->pnode) 1359 pnode_min = gre->pnode; 1360 if (pnode_max < gre->pnode) 1361 pnode_max = gre->pnode; 1362 } 1363 _min_socket = sock_min; 1364 _max_socket = sock_max; 1365 _min_pnode = pnode_min; 1366 _max_pnode = pnode_max; 1367 _gr_table_len = index; 1368 1369 pr_info("UV: GRT: %d entries, sockets(min:%x,max:%x), pnodes(min:%x,max:%x), gap_end(%d)\n", 1370 index, _min_socket, _max_socket, _min_pnode, _max_pnode, fls64(gend)); 1371 } 1372 1373 /* Walk through UVsystab decoding the fields */ 1374 static int __init decode_uv_systab(void) 1375 { 1376 struct uv_systab *st; 1377 int i; 1378 1379 /* Get mapped UVsystab pointer */ 1380 st = uv_systab; 1381 1382 /* If UVsystab is version 1, there is no extended UVsystab */ 1383 if (st && st->revision == UV_SYSTAB_VERSION_1) 1384 return 0; 1385 1386 if ((!st) || (st->revision < UV_SYSTAB_VERSION_UV4_LATEST)) { 1387 int rev = st ? st->revision : 0; 1388 1389 pr_err("UV: BIOS UVsystab mismatch, (%x < %x)\n", 1390 rev, UV_SYSTAB_VERSION_UV4_LATEST); 1391 pr_err("UV: Does not support UV, switch to non-UV x86_64\n"); 1392 uv_system_type = UV_NONE; 1393 1394 return -EINVAL; 1395 } 1396 1397 for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) { 1398 unsigned long ptr = st->entry[i].offset; 1399 1400 if (!ptr) 1401 continue; 1402 1403 /* point to payload */ 1404 ptr += (unsigned long)st; 1405 1406 switch (st->entry[i].type) { 1407 case UV_SYSTAB_TYPE_GAM_PARAMS: 1408 decode_gam_params(ptr); 1409 break; 1410 1411 case UV_SYSTAB_TYPE_GAM_RNG_TBL: 1412 decode_gam_rng_tbl(ptr); 1413 break; 1414 1415 case UV_SYSTAB_TYPE_ARCH_TYPE: 1416 /* already processed in early startup */ 1417 break; 1418 1419 default: 1420 pr_err("UV:%s:Unrecognized UV_SYSTAB_TYPE:%d, skipped\n", 1421 __func__, st->entry[i].type); 1422 break; 1423 } 1424 } 1425 return 0; 1426 } 1427 1428 /* 1429 * Given a bitmask 'bits' representing presnt blades, numbered 1430 * starting at 'base', masking off unused high bits of blade number 1431 * with 'mask', update the minimum and maximum blade numbers that we 1432 * have found. (Masking with 'mask' necessary because of BIOS 1433 * treatment of system partitioning when creating this table we are 1434 * interpreting.) 1435 */ 1436 static inline void blade_update_min_max(unsigned long bits, int base, int mask, int *min, int *max) 1437 { 1438 int first, last; 1439 1440 if (!bits) 1441 return; 1442 first = (base + __ffs(bits)) & mask; 1443 last = (base + __fls(bits)) & mask; 1444 1445 if (*min > first) 1446 *min = first; 1447 if (*max < last) 1448 *max = last; 1449 } 1450 1451 /* Set up physical blade translations from UVH_NODE_PRESENT_TABLE */ 1452 static __init void boot_init_possible_blades(struct uv_hub_info_s *hub_info) 1453 { 1454 unsigned long np; 1455 int i, uv_pb = 0; 1456 int sock_min = INT_MAX, sock_max = -1, s_mask; 1457 1458 s_mask = (1 << uv_cpuid.n_skt) - 1; 1459 1460 if (UVH_NODE_PRESENT_TABLE) { 1461 pr_info("UV: NODE_PRESENT_DEPTH = %d\n", 1462 UVH_NODE_PRESENT_TABLE_DEPTH); 1463 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) { 1464 np = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8); 1465 pr_info("UV: NODE_PRESENT(%d) = 0x%016lx\n", i, np); 1466 blade_update_min_max(np, i * 64, s_mask, &sock_min, &sock_max); 1467 } 1468 } 1469 if (UVH_NODE_PRESENT_0) { 1470 np = uv_read_local_mmr(UVH_NODE_PRESENT_0); 1471 pr_info("UV: NODE_PRESENT_0 = 0x%016lx\n", np); 1472 blade_update_min_max(np, 0, s_mask, &sock_min, &sock_max); 1473 } 1474 if (UVH_NODE_PRESENT_1) { 1475 np = uv_read_local_mmr(UVH_NODE_PRESENT_1); 1476 pr_info("UV: NODE_PRESENT_1 = 0x%016lx\n", np); 1477 blade_update_min_max(np, 64, s_mask, &sock_min, &sock_max); 1478 } 1479 1480 /* Only update if we actually found some bits indicating blades present */ 1481 if (sock_max >= sock_min) { 1482 _min_socket = sock_min; 1483 _max_socket = sock_max; 1484 uv_pb = sock_max - sock_min + 1; 1485 } 1486 if (uv_possible_blades != uv_pb) 1487 uv_possible_blades = uv_pb; 1488 1489 pr_info("UV: number nodes/possible blades %d (%d - %d)\n", 1490 uv_pb, sock_min, sock_max); 1491 } 1492 1493 static int __init alloc_conv_table(int num_elem, unsigned short **table) 1494 { 1495 int i; 1496 size_t bytes; 1497 1498 bytes = num_elem * sizeof(*table[0]); 1499 *table = kmalloc(bytes, GFP_KERNEL); 1500 if (WARN_ON_ONCE(!*table)) 1501 return -ENOMEM; 1502 for (i = 0; i < num_elem; i++) 1503 ((unsigned short *)*table)[i] = SOCK_EMPTY; 1504 return 0; 1505 } 1506 1507 /* Remove conversion table if it's 1:1 */ 1508 #define FREE_1_TO_1_TABLE(tbl, min, max, max2) free_1_to_1_table(&tbl, #tbl, min, max, max2) 1509 1510 static void __init free_1_to_1_table(unsigned short **tp, char *tname, int min, int max, int max2) 1511 { 1512 int i; 1513 unsigned short *table = *tp; 1514 1515 if (table == NULL) 1516 return; 1517 if (max != max2) 1518 return; 1519 for (i = 0; i < max; i++) { 1520 if (i != table[i]) 1521 return; 1522 } 1523 kfree(table); 1524 *tp = NULL; 1525 pr_info("UV: %s is 1:1, conversion table removed\n", tname); 1526 } 1527 1528 /* 1529 * Build Socket Tables 1530 * If the number of nodes is >1 per socket, socket to node table will 1531 * contain lowest node number on that socket. 1532 */ 1533 static void __init build_socket_tables(void) 1534 { 1535 struct uv_gam_range_entry *gre = uv_gre_table; 1536 int nums, numn, nump; 1537 int cpu, i, lnid; 1538 int minsock = _min_socket; 1539 int maxsock = _max_socket; 1540 int minpnode = _min_pnode; 1541 int maxpnode = _max_pnode; 1542 1543 if (!gre) { 1544 if (is_uv2_hub() || is_uv3_hub()) { 1545 pr_info("UV: No UVsystab socket table, ignoring\n"); 1546 return; 1547 } 1548 pr_err("UV: Error: UVsystab address translations not available!\n"); 1549 WARN_ON_ONCE(!gre); 1550 return; 1551 } 1552 1553 numn = num_possible_nodes(); 1554 nump = maxpnode - minpnode + 1; 1555 nums = maxsock - minsock + 1; 1556 1557 /* Allocate and clear tables */ 1558 if ((alloc_conv_table(nump, &_pnode_to_socket) < 0) 1559 || (alloc_conv_table(nums, &_socket_to_pnode) < 0) 1560 || (alloc_conv_table(numn, &_node_to_socket) < 0) 1561 || (alloc_conv_table(nums, &_socket_to_node) < 0)) { 1562 kfree(_pnode_to_socket); 1563 kfree(_socket_to_pnode); 1564 kfree(_node_to_socket); 1565 return; 1566 } 1567 1568 /* Fill in pnode/node/addr conversion list values: */ 1569 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) { 1570 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) 1571 continue; 1572 i = gre->sockid - minsock; 1573 if (_socket_to_pnode[i] == SOCK_EMPTY) 1574 _socket_to_pnode[i] = gre->pnode; 1575 1576 i = gre->pnode - minpnode; 1577 if (_pnode_to_socket[i] == SOCK_EMPTY) 1578 _pnode_to_socket[i] = gre->sockid; 1579 1580 pr_info("UV: sid:%02x type:%d nasid:%04x pn:%02x pn2s:%2x\n", 1581 gre->sockid, gre->type, gre->nasid, 1582 _socket_to_pnode[gre->sockid - minsock], 1583 _pnode_to_socket[gre->pnode - minpnode]); 1584 } 1585 1586 /* Set socket -> node values: */ 1587 lnid = NUMA_NO_NODE; 1588 for_each_possible_cpu(cpu) { 1589 int nid = cpu_to_node(cpu); 1590 int apicid, sockid; 1591 1592 if (lnid == nid) 1593 continue; 1594 lnid = nid; 1595 1596 apicid = per_cpu(x86_cpu_to_apicid, cpu); 1597 sockid = apicid >> uv_cpuid.socketid_shift; 1598 1599 if (_socket_to_node[sockid - minsock] == SOCK_EMPTY) 1600 _socket_to_node[sockid - minsock] = nid; 1601 1602 if (_node_to_socket[nid] == SOCK_EMPTY) 1603 _node_to_socket[nid] = sockid; 1604 1605 pr_info("UV: sid:%02x: apicid:%04x socket:%02d node:%03x s2n:%03x\n", 1606 sockid, 1607 apicid, 1608 _node_to_socket[nid], 1609 nid, 1610 _socket_to_node[sockid - minsock]); 1611 } 1612 1613 /* 1614 * If e.g. socket id == pnode for all pnodes, 1615 * system runs faster by removing corresponding conversion table. 1616 */ 1617 FREE_1_TO_1_TABLE(_socket_to_node, _min_socket, nums, numn); 1618 FREE_1_TO_1_TABLE(_node_to_socket, _min_socket, nums, numn); 1619 FREE_1_TO_1_TABLE(_socket_to_pnode, _min_pnode, nums, nump); 1620 FREE_1_TO_1_TABLE(_pnode_to_socket, _min_pnode, nums, nump); 1621 } 1622 1623 /* Check which reboot to use */ 1624 static void check_efi_reboot(void) 1625 { 1626 /* If EFI reboot not available, use ACPI reboot */ 1627 if (!efi_enabled(EFI_BOOT)) 1628 reboot_type = BOOT_ACPI; 1629 } 1630 1631 /* 1632 * User proc fs file handling now deprecated. 1633 * Recommend using /sys/firmware/sgi_uv/... instead. 1634 */ 1635 static int __maybe_unused proc_hubbed_show(struct seq_file *file, void *data) 1636 { 1637 pr_notice_once("%s: using deprecated /proc/sgi_uv/hubbed, use /sys/firmware/sgi_uv/hub_type\n", 1638 current->comm); 1639 seq_printf(file, "0x%x\n", uv_hubbed_system); 1640 return 0; 1641 } 1642 1643 static int __maybe_unused proc_hubless_show(struct seq_file *file, void *data) 1644 { 1645 pr_notice_once("%s: using deprecated /proc/sgi_uv/hubless, use /sys/firmware/sgi_uv/hubless\n", 1646 current->comm); 1647 seq_printf(file, "0x%x\n", uv_hubless_system); 1648 return 0; 1649 } 1650 1651 static int __maybe_unused proc_archtype_show(struct seq_file *file, void *data) 1652 { 1653 pr_notice_once("%s: using deprecated /proc/sgi_uv/archtype, use /sys/firmware/sgi_uv/archtype\n", 1654 current->comm); 1655 seq_printf(file, "%s/%s\n", uv_archtype, oem_table_id); 1656 return 0; 1657 } 1658 1659 static __init void uv_setup_proc_files(int hubless) 1660 { 1661 struct proc_dir_entry *pde; 1662 1663 pde = proc_mkdir(UV_PROC_NODE, NULL); 1664 proc_create_single("archtype", 0, pde, proc_archtype_show); 1665 if (hubless) 1666 proc_create_single("hubless", 0, pde, proc_hubless_show); 1667 else 1668 proc_create_single("hubbed", 0, pde, proc_hubbed_show); 1669 } 1670 1671 /* Initialize UV hubless systems */ 1672 static __init int uv_system_init_hubless(void) 1673 { 1674 int rc; 1675 1676 /* Setup PCH NMI handler */ 1677 uv_nmi_setup_hubless(); 1678 1679 /* Init kernel/BIOS interface */ 1680 rc = uv_bios_init(); 1681 if (rc < 0) 1682 return rc; 1683 1684 /* Process UVsystab */ 1685 rc = decode_uv_systab(); 1686 if (rc < 0) 1687 return rc; 1688 1689 /* Set section block size for current node memory */ 1690 set_block_size(); 1691 1692 /* Create user access node */ 1693 if (rc >= 0) 1694 uv_setup_proc_files(1); 1695 1696 check_efi_reboot(); 1697 1698 return rc; 1699 } 1700 1701 static void __init uv_system_init_hub(void) 1702 { 1703 struct uv_hub_info_s hub_info = {0}; 1704 int bytes, cpu, nodeid, bid; 1705 unsigned short min_pnode = USHRT_MAX, max_pnode = 0; 1706 char *hub = is_uv5_hub() ? "UV500" : 1707 is_uv4_hub() ? "UV400" : 1708 is_uv3_hub() ? "UV300" : 1709 is_uv2_hub() ? "UV2000/3000" : NULL; 1710 struct uv_hub_info_s **uv_hub_info_list_blade; 1711 1712 if (!hub) { 1713 pr_err("UV: Unknown/unsupported UV hub\n"); 1714 return; 1715 } 1716 pr_info("UV: Found %s hub\n", hub); 1717 1718 map_low_mmrs(); 1719 1720 /* Get uv_systab for decoding, setup UV BIOS calls */ 1721 uv_bios_init(); 1722 1723 /* If there's an UVsystab problem then abort UV init: */ 1724 if (decode_uv_systab() < 0) { 1725 pr_err("UV: Mangled UVsystab format\n"); 1726 return; 1727 } 1728 1729 build_socket_tables(); 1730 build_uv_gr_table(); 1731 set_block_size(); 1732 uv_init_hub_info(&hub_info); 1733 /* If UV2 or UV3 may need to get # blades from HW */ 1734 if (is_uv(UV2|UV3) && !uv_gre_table) 1735 boot_init_possible_blades(&hub_info); 1736 else 1737 /* min/max sockets set in decode_gam_rng_tbl */ 1738 uv_possible_blades = (_max_socket - _min_socket) + 1; 1739 1740 /* uv_num_possible_blades() is really the hub count: */ 1741 pr_info("UV: Found %d hubs, %d nodes, %d CPUs\n", uv_num_possible_blades(), num_possible_nodes(), num_possible_cpus()); 1742 1743 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, &sn_region_size, &system_serial_number); 1744 hub_info.coherency_domain_number = sn_coherency_id; 1745 uv_rtc_init(); 1746 1747 /* 1748 * __uv_hub_info_list[] is indexed by node, but there is only 1749 * one hub_info structure per blade. First, allocate one 1750 * structure per blade. Further down we create a per-node 1751 * table (__uv_hub_info_list[]) pointing to hub_info 1752 * structures for the correct blade. 1753 */ 1754 1755 bytes = sizeof(void *) * uv_num_possible_blades(); 1756 uv_hub_info_list_blade = kzalloc(bytes, GFP_KERNEL); 1757 if (WARN_ON_ONCE(!uv_hub_info_list_blade)) 1758 return; 1759 1760 bytes = sizeof(struct uv_hub_info_s); 1761 for_each_possible_blade(bid) { 1762 struct uv_hub_info_s *new_hub; 1763 1764 /* Allocate & fill new per hub info list */ 1765 new_hub = (bid == 0) ? &uv_hub_info_node0 1766 : kzalloc_node(bytes, GFP_KERNEL, uv_blade_to_node(bid)); 1767 if (WARN_ON_ONCE(!new_hub)) { 1768 /* do not kfree() bid 0, which is statically allocated */ 1769 while (--bid > 0) 1770 kfree(uv_hub_info_list_blade[bid]); 1771 kfree(uv_hub_info_list_blade); 1772 return; 1773 } 1774 1775 uv_hub_info_list_blade[bid] = new_hub; 1776 *new_hub = hub_info; 1777 1778 /* Use information from GAM table if available: */ 1779 if (uv_gre_table) 1780 new_hub->pnode = uv_blade_to_pnode(bid); 1781 else /* Or fill in during CPU loop: */ 1782 new_hub->pnode = 0xffff; 1783 1784 new_hub->numa_blade_id = bid; 1785 new_hub->memory_nid = NUMA_NO_NODE; 1786 new_hub->nr_possible_cpus = 0; 1787 new_hub->nr_online_cpus = 0; 1788 } 1789 1790 /* 1791 * Now populate __uv_hub_info_list[] for each node with the 1792 * pointer to the struct for the blade it resides on. 1793 */ 1794 1795 bytes = sizeof(void *) * num_possible_nodes(); 1796 __uv_hub_info_list = kzalloc(bytes, GFP_KERNEL); 1797 if (WARN_ON_ONCE(!__uv_hub_info_list)) { 1798 for_each_possible_blade(bid) 1799 /* bid 0 is statically allocated */ 1800 if (bid != 0) 1801 kfree(uv_hub_info_list_blade[bid]); 1802 kfree(uv_hub_info_list_blade); 1803 return; 1804 } 1805 1806 for_each_node(nodeid) 1807 __uv_hub_info_list[nodeid] = uv_hub_info_list_blade[uv_node_to_blade_id(nodeid)]; 1808 1809 /* Initialize per CPU info: */ 1810 for_each_possible_cpu(cpu) { 1811 int apicid = per_cpu(x86_cpu_to_apicid, cpu); 1812 unsigned short bid; 1813 unsigned short pnode; 1814 1815 pnode = uv_apicid_to_pnode(apicid); 1816 bid = uv_pnode_to_socket(pnode) - _min_socket; 1817 1818 uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list_blade[bid]; 1819 uv_cpu_info_per(cpu)->blade_cpu_id = uv_cpu_hub_info(cpu)->nr_possible_cpus++; 1820 if (uv_cpu_hub_info(cpu)->memory_nid == NUMA_NO_NODE) 1821 uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu); 1822 1823 if (uv_cpu_hub_info(cpu)->pnode == 0xffff) 1824 uv_cpu_hub_info(cpu)->pnode = pnode; 1825 } 1826 1827 for_each_possible_blade(bid) { 1828 unsigned short pnode = uv_hub_info_list_blade[bid]->pnode; 1829 1830 if (pnode == 0xffff) 1831 continue; 1832 1833 min_pnode = min(pnode, min_pnode); 1834 max_pnode = max(pnode, max_pnode); 1835 pr_info("UV: HUB:%2d pn:%02x nrcpus:%d\n", 1836 bid, 1837 uv_hub_info_list_blade[bid]->pnode, 1838 uv_hub_info_list_blade[bid]->nr_possible_cpus); 1839 } 1840 1841 pr_info("UV: min_pnode:%02x max_pnode:%02x\n", min_pnode, max_pnode); 1842 map_gru_high(max_pnode); 1843 map_mmr_high(max_pnode); 1844 map_mmioh_high(min_pnode, max_pnode); 1845 1846 kfree(uv_hub_info_list_blade); 1847 uv_hub_info_list_blade = NULL; 1848 1849 uv_nmi_setup(); 1850 uv_cpu_init(); 1851 uv_setup_proc_files(0); 1852 1853 /* Register Legacy VGA I/O redirection handler: */ 1854 pci_register_set_vga_state(uv_set_vga_state); 1855 1856 check_efi_reboot(); 1857 } 1858 1859 /* 1860 * There is a different code path needed to initialize a UV system that does 1861 * not have a "UV HUB" (referred to as "hubless"). 1862 */ 1863 void __init uv_system_init(void) 1864 { 1865 if (likely(!is_uv_system() && !is_uv_hubless(1))) 1866 return; 1867 1868 if (is_uv_system()) 1869 uv_system_init_hub(); 1870 else 1871 uv_system_init_hubless(); 1872 } 1873 1874 apic_driver(apic_x2apic_uv_x); 1875