1 #include <linux/threads.h> 2 #include <linux/cpumask.h> 3 #include <linux/string.h> 4 #include <linux/kernel.h> 5 #include <linux/ctype.h> 6 #include <linux/dmar.h> 7 #include <linux/irq.h> 8 #include <linux/cpu.h> 9 10 #include <asm/smp.h> 11 #include <asm/x2apic.h> 12 13 static DEFINE_PER_CPU(u32, x86_cpu_to_logical_apicid); 14 static DEFINE_PER_CPU(cpumask_var_t, cpus_in_cluster); 15 static DEFINE_PER_CPU(cpumask_var_t, ipi_mask); 16 17 static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id) 18 { 19 return x2apic_enabled(); 20 } 21 22 static inline u32 x2apic_cluster(int cpu) 23 { 24 return per_cpu(x86_cpu_to_logical_apicid, cpu) >> 16; 25 } 26 27 static void x2apic_send_IPI(int cpu, int vector) 28 { 29 u32 dest = per_cpu(x86_cpu_to_logical_apicid, cpu); 30 31 x2apic_wrmsr_fence(); 32 __x2apic_send_IPI_dest(dest, vector, APIC_DEST_LOGICAL); 33 } 34 35 static void 36 __x2apic_send_IPI_mask(const struct cpumask *mask, int vector, int apic_dest) 37 { 38 struct cpumask *cpus_in_cluster_ptr; 39 struct cpumask *ipi_mask_ptr; 40 unsigned int cpu, this_cpu; 41 unsigned long flags; 42 u32 dest; 43 44 x2apic_wrmsr_fence(); 45 46 local_irq_save(flags); 47 48 this_cpu = smp_processor_id(); 49 50 /* 51 * We are to modify mask, so we need an own copy 52 * and be sure it's manipulated with irq off. 53 */ 54 ipi_mask_ptr = this_cpu_cpumask_var_ptr(ipi_mask); 55 cpumask_copy(ipi_mask_ptr, mask); 56 57 /* 58 * The idea is to send one IPI per cluster. 59 */ 60 for_each_cpu(cpu, ipi_mask_ptr) { 61 unsigned long i; 62 63 cpus_in_cluster_ptr = per_cpu(cpus_in_cluster, cpu); 64 dest = 0; 65 66 /* Collect cpus in cluster. */ 67 for_each_cpu_and(i, ipi_mask_ptr, cpus_in_cluster_ptr) { 68 if (apic_dest == APIC_DEST_ALLINC || i != this_cpu) 69 dest |= per_cpu(x86_cpu_to_logical_apicid, i); 70 } 71 72 if (!dest) 73 continue; 74 75 __x2apic_send_IPI_dest(dest, vector, apic->dest_logical); 76 /* 77 * Cluster sibling cpus should be discared now so 78 * we would not send IPI them second time. 79 */ 80 cpumask_andnot(ipi_mask_ptr, ipi_mask_ptr, cpus_in_cluster_ptr); 81 } 82 83 local_irq_restore(flags); 84 } 85 86 static void x2apic_send_IPI_mask(const struct cpumask *mask, int vector) 87 { 88 __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLINC); 89 } 90 91 static void 92 x2apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) 93 { 94 __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLBUT); 95 } 96 97 static void x2apic_send_IPI_allbutself(int vector) 98 { 99 __x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLBUT); 100 } 101 102 static void x2apic_send_IPI_all(int vector) 103 { 104 __x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLINC); 105 } 106 107 static int 108 x2apic_cpu_mask_to_apicid(const struct cpumask *mask, struct irq_data *irqdata, 109 unsigned int *apicid) 110 { 111 struct cpumask *effmsk = irq_data_get_effective_affinity_mask(irqdata); 112 unsigned int cpu; 113 u32 dest = 0; 114 u16 cluster; 115 116 cpu = cpumask_first(mask); 117 if (cpu >= nr_cpu_ids) 118 return -EINVAL; 119 120 dest = per_cpu(x86_cpu_to_logical_apicid, cpu); 121 cluster = x2apic_cluster(cpu); 122 123 cpumask_clear(effmsk); 124 for_each_cpu(cpu, mask) { 125 if (cluster != x2apic_cluster(cpu)) 126 continue; 127 dest |= per_cpu(x86_cpu_to_logical_apicid, cpu); 128 cpumask_set_cpu(cpu, effmsk); 129 } 130 131 *apicid = dest; 132 return 0; 133 } 134 135 static void init_x2apic_ldr(void) 136 { 137 unsigned int this_cpu = smp_processor_id(); 138 unsigned int cpu; 139 140 per_cpu(x86_cpu_to_logical_apicid, this_cpu) = apic_read(APIC_LDR); 141 142 cpumask_set_cpu(this_cpu, per_cpu(cpus_in_cluster, this_cpu)); 143 for_each_online_cpu(cpu) { 144 if (x2apic_cluster(this_cpu) != x2apic_cluster(cpu)) 145 continue; 146 cpumask_set_cpu(this_cpu, per_cpu(cpus_in_cluster, cpu)); 147 cpumask_set_cpu(cpu, per_cpu(cpus_in_cluster, this_cpu)); 148 } 149 } 150 151 /* 152 * At CPU state changes, update the x2apic cluster sibling info. 153 */ 154 static int x2apic_prepare_cpu(unsigned int cpu) 155 { 156 if (!zalloc_cpumask_var(&per_cpu(cpus_in_cluster, cpu), GFP_KERNEL)) 157 return -ENOMEM; 158 159 if (!zalloc_cpumask_var(&per_cpu(ipi_mask, cpu), GFP_KERNEL)) { 160 free_cpumask_var(per_cpu(cpus_in_cluster, cpu)); 161 return -ENOMEM; 162 } 163 164 return 0; 165 } 166 167 static int x2apic_dead_cpu(unsigned int this_cpu) 168 { 169 int cpu; 170 171 for_each_online_cpu(cpu) { 172 if (x2apic_cluster(this_cpu) != x2apic_cluster(cpu)) 173 continue; 174 cpumask_clear_cpu(this_cpu, per_cpu(cpus_in_cluster, cpu)); 175 cpumask_clear_cpu(cpu, per_cpu(cpus_in_cluster, this_cpu)); 176 } 177 free_cpumask_var(per_cpu(cpus_in_cluster, this_cpu)); 178 free_cpumask_var(per_cpu(ipi_mask, this_cpu)); 179 return 0; 180 } 181 182 static int x2apic_cluster_probe(void) 183 { 184 int cpu = smp_processor_id(); 185 int ret; 186 187 if (!x2apic_mode) 188 return 0; 189 190 ret = cpuhp_setup_state(CPUHP_X2APIC_PREPARE, "x86/x2apic:prepare", 191 x2apic_prepare_cpu, x2apic_dead_cpu); 192 if (ret < 0) { 193 pr_err("Failed to register X2APIC_PREPARE\n"); 194 return 0; 195 } 196 cpumask_set_cpu(cpu, per_cpu(cpus_in_cluster, cpu)); 197 return 1; 198 } 199 200 static const struct cpumask *x2apic_cluster_target_cpus(void) 201 { 202 return cpu_all_mask; 203 } 204 205 /* 206 * Each x2apic cluster is an allocation domain. 207 */ 208 static void cluster_vector_allocation_domain(int cpu, struct cpumask *retmask, 209 const struct cpumask *mask) 210 { 211 /* 212 * To minimize vector pressure, default case of boot, device bringup 213 * etc will use a single cpu for the interrupt destination. 214 * 215 * On explicit migration requests coming from irqbalance etc, 216 * interrupts will be routed to the x2apic cluster (cluster-id 217 * derived from the first cpu in the mask) members specified 218 * in the mask. 219 */ 220 if (mask == x2apic_cluster_target_cpus()) 221 cpumask_copy(retmask, cpumask_of(cpu)); 222 else 223 cpumask_and(retmask, mask, per_cpu(cpus_in_cluster, cpu)); 224 } 225 226 static struct apic apic_x2apic_cluster __ro_after_init = { 227 228 .name = "cluster x2apic", 229 .probe = x2apic_cluster_probe, 230 .acpi_madt_oem_check = x2apic_acpi_madt_oem_check, 231 .apic_id_valid = x2apic_apic_id_valid, 232 .apic_id_registered = x2apic_apic_id_registered, 233 234 .irq_delivery_mode = dest_LowestPrio, 235 .irq_dest_mode = 1, /* logical */ 236 237 .target_cpus = x2apic_cluster_target_cpus, 238 .disable_esr = 0, 239 .dest_logical = APIC_DEST_LOGICAL, 240 .check_apicid_used = NULL, 241 242 .vector_allocation_domain = cluster_vector_allocation_domain, 243 .init_apic_ldr = init_x2apic_ldr, 244 245 .ioapic_phys_id_map = NULL, 246 .setup_apic_routing = NULL, 247 .cpu_present_to_apicid = default_cpu_present_to_apicid, 248 .apicid_to_cpu_present = NULL, 249 .check_phys_apicid_present = default_check_phys_apicid_present, 250 .phys_pkg_id = x2apic_phys_pkg_id, 251 252 .get_apic_id = x2apic_get_apic_id, 253 .set_apic_id = x2apic_set_apic_id, 254 255 .cpu_mask_to_apicid = x2apic_cpu_mask_to_apicid, 256 257 .send_IPI = x2apic_send_IPI, 258 .send_IPI_mask = x2apic_send_IPI_mask, 259 .send_IPI_mask_allbutself = x2apic_send_IPI_mask_allbutself, 260 .send_IPI_allbutself = x2apic_send_IPI_allbutself, 261 .send_IPI_all = x2apic_send_IPI_all, 262 .send_IPI_self = x2apic_send_IPI_self, 263 264 .inquire_remote_apic = NULL, 265 266 .read = native_apic_msr_read, 267 .write = native_apic_msr_write, 268 .eoi_write = native_apic_msr_eoi_write, 269 .icr_read = native_x2apic_icr_read, 270 .icr_write = native_x2apic_icr_write, 271 .wait_icr_idle = native_x2apic_wait_icr_idle, 272 .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle, 273 }; 274 275 apic_driver(apic_x2apic_cluster); 276