1 #include <linux/threads.h> 2 #include <linux/cpumask.h> 3 #include <linux/string.h> 4 #include <linux/kernel.h> 5 #include <linux/ctype.h> 6 #include <linux/init.h> 7 #include <linux/dmar.h> 8 #include <linux/cpu.h> 9 10 #include <asm/smp.h> 11 #include <asm/apic.h> 12 #include <asm/ipi.h> 13 14 static DEFINE_PER_CPU(u32, x86_cpu_to_logical_apicid); 15 static DEFINE_PER_CPU(cpumask_var_t, cpus_in_cluster); 16 static DEFINE_PER_CPU(cpumask_var_t, ipi_mask); 17 18 static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id) 19 { 20 return x2apic_enabled(); 21 } 22 23 /* 24 * need to use more than cpu 0, because we need more vectors when 25 * MSI-X are used. 26 */ 27 static const struct cpumask *x2apic_target_cpus(void) 28 { 29 return cpu_online_mask; 30 } 31 32 /* 33 * for now each logical cpu is in its own vector allocation domain. 34 */ 35 static void x2apic_vector_allocation_domain(int cpu, struct cpumask *retmask) 36 { 37 cpumask_clear(retmask); 38 cpumask_set_cpu(cpu, retmask); 39 } 40 41 static void 42 __x2apic_send_IPI_dest(unsigned int apicid, int vector, unsigned int dest) 43 { 44 unsigned long cfg; 45 46 cfg = __prepare_ICR(0, vector, dest); 47 48 /* 49 * send the IPI. 50 */ 51 native_x2apic_icr_write(cfg, apicid); 52 } 53 54 static inline u32 x2apic_cluster(int cpu) 55 { 56 return per_cpu(x86_cpu_to_logical_apicid, cpu) >> 16; 57 } 58 59 static void 60 __x2apic_send_IPI_mask(const struct cpumask *mask, int vector, int apic_dest) 61 { 62 struct cpumask *cpus_in_cluster_ptr; 63 struct cpumask *ipi_mask_ptr; 64 unsigned int cpu, this_cpu; 65 unsigned long flags; 66 u32 dest; 67 68 x2apic_wrmsr_fence(); 69 70 local_irq_save(flags); 71 72 this_cpu = smp_processor_id(); 73 74 /* 75 * We are to modify mask, so we need an own copy 76 * and be sure it's manipulated with irq off. 77 */ 78 ipi_mask_ptr = __raw_get_cpu_var(ipi_mask); 79 cpumask_copy(ipi_mask_ptr, mask); 80 81 /* 82 * The idea is to send one IPI per cluster. 83 */ 84 for_each_cpu(cpu, ipi_mask_ptr) { 85 unsigned long i; 86 87 cpus_in_cluster_ptr = per_cpu(cpus_in_cluster, cpu); 88 dest = 0; 89 90 /* Collect cpus in cluster. */ 91 for_each_cpu_and(i, ipi_mask_ptr, cpus_in_cluster_ptr) { 92 if (apic_dest == APIC_DEST_ALLINC || i != this_cpu) 93 dest |= per_cpu(x86_cpu_to_logical_apicid, i); 94 } 95 96 if (!dest) 97 continue; 98 99 __x2apic_send_IPI_dest(dest, vector, apic->dest_logical); 100 /* 101 * Cluster sibling cpus should be discared now so 102 * we would not send IPI them second time. 103 */ 104 cpumask_andnot(ipi_mask_ptr, ipi_mask_ptr, cpus_in_cluster_ptr); 105 } 106 107 local_irq_restore(flags); 108 } 109 110 static void x2apic_send_IPI_mask(const struct cpumask *mask, int vector) 111 { 112 __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLINC); 113 } 114 115 static void 116 x2apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector) 117 { 118 __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLBUT); 119 } 120 121 static void x2apic_send_IPI_allbutself(int vector) 122 { 123 __x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLBUT); 124 } 125 126 static void x2apic_send_IPI_all(int vector) 127 { 128 __x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLINC); 129 } 130 131 static int x2apic_apic_id_registered(void) 132 { 133 return 1; 134 } 135 136 static unsigned int x2apic_cpu_mask_to_apicid(const struct cpumask *cpumask) 137 { 138 /* 139 * We're using fixed IRQ delivery, can only return one logical APIC ID. 140 * May as well be the first. 141 */ 142 int cpu = cpumask_first(cpumask); 143 144 if ((unsigned)cpu < nr_cpu_ids) 145 return per_cpu(x86_cpu_to_logical_apicid, cpu); 146 else 147 return BAD_APICID; 148 } 149 150 static unsigned int 151 x2apic_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 152 const struct cpumask *andmask) 153 { 154 int cpu; 155 156 /* 157 * We're using fixed IRQ delivery, can only return one logical APIC ID. 158 * May as well be the first. 159 */ 160 for_each_cpu_and(cpu, cpumask, andmask) { 161 if (cpumask_test_cpu(cpu, cpu_online_mask)) 162 break; 163 } 164 165 return per_cpu(x86_cpu_to_logical_apicid, cpu); 166 } 167 168 static unsigned int x2apic_cluster_phys_get_apic_id(unsigned long x) 169 { 170 unsigned int id; 171 172 id = x; 173 return id; 174 } 175 176 static unsigned long set_apic_id(unsigned int id) 177 { 178 unsigned long x; 179 180 x = id; 181 return x; 182 } 183 184 static int x2apic_cluster_phys_pkg_id(int initial_apicid, int index_msb) 185 { 186 return initial_apicid >> index_msb; 187 } 188 189 static void x2apic_send_IPI_self(int vector) 190 { 191 apic_write(APIC_SELF_IPI, vector); 192 } 193 194 static void init_x2apic_ldr(void) 195 { 196 unsigned int this_cpu = smp_processor_id(); 197 unsigned int cpu; 198 199 per_cpu(x86_cpu_to_logical_apicid, this_cpu) = apic_read(APIC_LDR); 200 201 __cpu_set(this_cpu, per_cpu(cpus_in_cluster, this_cpu)); 202 for_each_online_cpu(cpu) { 203 if (x2apic_cluster(this_cpu) != x2apic_cluster(cpu)) 204 continue; 205 __cpu_set(this_cpu, per_cpu(cpus_in_cluster, cpu)); 206 __cpu_set(cpu, per_cpu(cpus_in_cluster, this_cpu)); 207 } 208 } 209 210 /* 211 * At CPU state changes, update the x2apic cluster sibling info. 212 */ 213 static int __cpuinit 214 update_clusterinfo(struct notifier_block *nfb, unsigned long action, void *hcpu) 215 { 216 unsigned int this_cpu = (unsigned long)hcpu; 217 unsigned int cpu; 218 int err = 0; 219 220 switch (action) { 221 case CPU_UP_PREPARE: 222 if (!zalloc_cpumask_var(&per_cpu(cpus_in_cluster, this_cpu), 223 GFP_KERNEL)) { 224 err = -ENOMEM; 225 } else if (!zalloc_cpumask_var(&per_cpu(ipi_mask, this_cpu), 226 GFP_KERNEL)) { 227 free_cpumask_var(per_cpu(cpus_in_cluster, this_cpu)); 228 err = -ENOMEM; 229 } 230 break; 231 case CPU_UP_CANCELED: 232 case CPU_UP_CANCELED_FROZEN: 233 case CPU_DEAD: 234 for_each_online_cpu(cpu) { 235 if (x2apic_cluster(this_cpu) != x2apic_cluster(cpu)) 236 continue; 237 __cpu_clear(this_cpu, per_cpu(cpus_in_cluster, cpu)); 238 __cpu_clear(cpu, per_cpu(cpus_in_cluster, this_cpu)); 239 } 240 free_cpumask_var(per_cpu(cpus_in_cluster, this_cpu)); 241 free_cpumask_var(per_cpu(ipi_mask, this_cpu)); 242 break; 243 } 244 245 return notifier_from_errno(err); 246 } 247 248 static struct notifier_block __refdata x2apic_cpu_notifier = { 249 .notifier_call = update_clusterinfo, 250 }; 251 252 static int x2apic_init_cpu_notifier(void) 253 { 254 int cpu = smp_processor_id(); 255 256 zalloc_cpumask_var(&per_cpu(cpus_in_cluster, cpu), GFP_KERNEL); 257 zalloc_cpumask_var(&per_cpu(ipi_mask, cpu), GFP_KERNEL); 258 259 BUG_ON(!per_cpu(cpus_in_cluster, cpu) || !per_cpu(ipi_mask, cpu)); 260 261 __cpu_set(cpu, per_cpu(cpus_in_cluster, cpu)); 262 register_hotcpu_notifier(&x2apic_cpu_notifier); 263 return 1; 264 } 265 266 static int x2apic_cluster_probe(void) 267 { 268 if (x2apic_mode) 269 return x2apic_init_cpu_notifier(); 270 else 271 return 0; 272 } 273 274 struct apic apic_x2apic_cluster = { 275 276 .name = "cluster x2apic", 277 .probe = x2apic_cluster_probe, 278 .acpi_madt_oem_check = x2apic_acpi_madt_oem_check, 279 .apic_id_registered = x2apic_apic_id_registered, 280 281 .irq_delivery_mode = dest_LowestPrio, 282 .irq_dest_mode = 1, /* logical */ 283 284 .target_cpus = x2apic_target_cpus, 285 .disable_esr = 0, 286 .dest_logical = APIC_DEST_LOGICAL, 287 .check_apicid_used = NULL, 288 .check_apicid_present = NULL, 289 290 .vector_allocation_domain = x2apic_vector_allocation_domain, 291 .init_apic_ldr = init_x2apic_ldr, 292 293 .ioapic_phys_id_map = NULL, 294 .setup_apic_routing = NULL, 295 .multi_timer_check = NULL, 296 .cpu_present_to_apicid = default_cpu_present_to_apicid, 297 .apicid_to_cpu_present = NULL, 298 .setup_portio_remap = NULL, 299 .check_phys_apicid_present = default_check_phys_apicid_present, 300 .enable_apic_mode = NULL, 301 .phys_pkg_id = x2apic_cluster_phys_pkg_id, 302 .mps_oem_check = NULL, 303 304 .get_apic_id = x2apic_cluster_phys_get_apic_id, 305 .set_apic_id = set_apic_id, 306 .apic_id_mask = 0xFFFFFFFFu, 307 308 .cpu_mask_to_apicid = x2apic_cpu_mask_to_apicid, 309 .cpu_mask_to_apicid_and = x2apic_cpu_mask_to_apicid_and, 310 311 .send_IPI_mask = x2apic_send_IPI_mask, 312 .send_IPI_mask_allbutself = x2apic_send_IPI_mask_allbutself, 313 .send_IPI_allbutself = x2apic_send_IPI_allbutself, 314 .send_IPI_all = x2apic_send_IPI_all, 315 .send_IPI_self = x2apic_send_IPI_self, 316 317 .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW, 318 .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH, 319 .wait_for_init_deassert = NULL, 320 .smp_callin_clear_local_apic = NULL, 321 .inquire_remote_apic = NULL, 322 323 .read = native_apic_msr_read, 324 .write = native_apic_msr_write, 325 .icr_read = native_x2apic_icr_read, 326 .icr_write = native_x2apic_icr_write, 327 .wait_icr_idle = native_x2apic_wait_icr_idle, 328 .safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle, 329 }; 330