1 /* 2 * Local APIC related interfaces to support IOAPIC, MSI, HT_IRQ etc. 3 * 4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo 5 * Moved from arch/x86/kernel/apic/io_apic.c. 6 * Jiang Liu <jiang.liu@linux.intel.com> 7 * Enable support of hierarchical irqdomains 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 #include <linux/interrupt.h> 14 #include <linux/init.h> 15 #include <linux/compiler.h> 16 #include <linux/slab.h> 17 #include <asm/irqdomain.h> 18 #include <asm/hw_irq.h> 19 #include <asm/apic.h> 20 #include <asm/i8259.h> 21 #include <asm/desc.h> 22 #include <asm/irq_remapping.h> 23 24 struct apic_chip_data { 25 struct irq_cfg cfg; 26 cpumask_var_t domain; 27 cpumask_var_t old_domain; 28 u8 move_in_progress : 1; 29 }; 30 31 struct irq_domain *x86_vector_domain; 32 static DEFINE_RAW_SPINLOCK(vector_lock); 33 static cpumask_var_t vector_cpumask; 34 static struct irq_chip lapic_controller; 35 #ifdef CONFIG_X86_IO_APIC 36 static struct apic_chip_data *legacy_irq_data[NR_IRQS_LEGACY]; 37 #endif 38 39 void lock_vector_lock(void) 40 { 41 /* Used to the online set of cpus does not change 42 * during assign_irq_vector. 43 */ 44 raw_spin_lock(&vector_lock); 45 } 46 47 void unlock_vector_lock(void) 48 { 49 raw_spin_unlock(&vector_lock); 50 } 51 52 static struct apic_chip_data *apic_chip_data(struct irq_data *irq_data) 53 { 54 if (!irq_data) 55 return NULL; 56 57 while (irq_data->parent_data) 58 irq_data = irq_data->parent_data; 59 60 return irq_data->chip_data; 61 } 62 63 struct irq_cfg *irqd_cfg(struct irq_data *irq_data) 64 { 65 struct apic_chip_data *data = apic_chip_data(irq_data); 66 67 return data ? &data->cfg : NULL; 68 } 69 70 struct irq_cfg *irq_cfg(unsigned int irq) 71 { 72 return irqd_cfg(irq_get_irq_data(irq)); 73 } 74 75 static struct apic_chip_data *alloc_apic_chip_data(int node) 76 { 77 struct apic_chip_data *data; 78 79 data = kzalloc_node(sizeof(*data), GFP_KERNEL, node); 80 if (!data) 81 return NULL; 82 if (!zalloc_cpumask_var_node(&data->domain, GFP_KERNEL, node)) 83 goto out_data; 84 if (!zalloc_cpumask_var_node(&data->old_domain, GFP_KERNEL, node)) 85 goto out_domain; 86 return data; 87 out_domain: 88 free_cpumask_var(data->domain); 89 out_data: 90 kfree(data); 91 return NULL; 92 } 93 94 static void free_apic_chip_data(struct apic_chip_data *data) 95 { 96 if (data) { 97 free_cpumask_var(data->domain); 98 free_cpumask_var(data->old_domain); 99 kfree(data); 100 } 101 } 102 103 static int __assign_irq_vector(int irq, struct apic_chip_data *d, 104 const struct cpumask *mask) 105 { 106 /* 107 * NOTE! The local APIC isn't very good at handling 108 * multiple interrupts at the same interrupt level. 109 * As the interrupt level is determined by taking the 110 * vector number and shifting that right by 4, we 111 * want to spread these out a bit so that they don't 112 * all fall in the same interrupt level. 113 * 114 * Also, we've got to be careful not to trash gate 115 * 0x80, because int 0x80 is hm, kind of importantish. ;) 116 */ 117 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; 118 static int current_offset = VECTOR_OFFSET_START % 16; 119 int cpu, err; 120 121 if (d->move_in_progress) 122 return -EBUSY; 123 124 /* Only try and allocate irqs on cpus that are present */ 125 err = -ENOSPC; 126 cpumask_clear(d->old_domain); 127 cpu = cpumask_first_and(mask, cpu_online_mask); 128 while (cpu < nr_cpu_ids) { 129 int new_cpu, vector, offset; 130 131 apic->vector_allocation_domain(cpu, vector_cpumask, mask); 132 133 if (cpumask_subset(vector_cpumask, d->domain)) { 134 err = 0; 135 if (cpumask_equal(vector_cpumask, d->domain)) 136 break; 137 /* 138 * New cpumask using the vector is a proper subset of 139 * the current in use mask. So cleanup the vector 140 * allocation for the members that are not used anymore. 141 */ 142 cpumask_andnot(d->old_domain, d->domain, 143 vector_cpumask); 144 d->move_in_progress = 145 cpumask_intersects(d->old_domain, cpu_online_mask); 146 cpumask_and(d->domain, d->domain, vector_cpumask); 147 break; 148 } 149 150 vector = current_vector; 151 offset = current_offset; 152 next: 153 vector += 16; 154 if (vector >= first_system_vector) { 155 offset = (offset + 1) % 16; 156 vector = FIRST_EXTERNAL_VECTOR + offset; 157 } 158 159 if (unlikely(current_vector == vector)) { 160 cpumask_or(d->old_domain, d->old_domain, 161 vector_cpumask); 162 cpumask_andnot(vector_cpumask, mask, d->old_domain); 163 cpu = cpumask_first_and(vector_cpumask, 164 cpu_online_mask); 165 continue; 166 } 167 168 if (test_bit(vector, used_vectors)) 169 goto next; 170 171 for_each_cpu_and(new_cpu, vector_cpumask, cpu_online_mask) { 172 if (!IS_ERR_OR_NULL(per_cpu(vector_irq, new_cpu)[vector])) 173 goto next; 174 } 175 /* Found one! */ 176 current_vector = vector; 177 current_offset = offset; 178 if (d->cfg.vector) { 179 cpumask_copy(d->old_domain, d->domain); 180 d->move_in_progress = 181 cpumask_intersects(d->old_domain, cpu_online_mask); 182 } 183 for_each_cpu_and(new_cpu, vector_cpumask, cpu_online_mask) 184 per_cpu(vector_irq, new_cpu)[vector] = irq_to_desc(irq); 185 d->cfg.vector = vector; 186 cpumask_copy(d->domain, vector_cpumask); 187 err = 0; 188 break; 189 } 190 191 if (!err) { 192 /* cache destination APIC IDs into cfg->dest_apicid */ 193 err = apic->cpu_mask_to_apicid_and(mask, d->domain, 194 &d->cfg.dest_apicid); 195 } 196 197 return err; 198 } 199 200 static int assign_irq_vector(int irq, struct apic_chip_data *data, 201 const struct cpumask *mask) 202 { 203 int err; 204 unsigned long flags; 205 206 raw_spin_lock_irqsave(&vector_lock, flags); 207 err = __assign_irq_vector(irq, data, mask); 208 raw_spin_unlock_irqrestore(&vector_lock, flags); 209 return err; 210 } 211 212 static int assign_irq_vector_policy(int irq, int node, 213 struct apic_chip_data *data, 214 struct irq_alloc_info *info) 215 { 216 if (info && info->mask) 217 return assign_irq_vector(irq, data, info->mask); 218 if (node != NUMA_NO_NODE && 219 assign_irq_vector(irq, data, cpumask_of_node(node)) == 0) 220 return 0; 221 return assign_irq_vector(irq, data, apic->target_cpus()); 222 } 223 224 static void clear_irq_vector(int irq, struct apic_chip_data *data) 225 { 226 struct irq_desc *desc; 227 unsigned long flags; 228 int cpu, vector; 229 230 raw_spin_lock_irqsave(&vector_lock, flags); 231 BUG_ON(!data->cfg.vector); 232 233 vector = data->cfg.vector; 234 for_each_cpu_and(cpu, data->domain, cpu_online_mask) 235 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED; 236 237 data->cfg.vector = 0; 238 cpumask_clear(data->domain); 239 240 if (likely(!data->move_in_progress)) { 241 raw_spin_unlock_irqrestore(&vector_lock, flags); 242 return; 243 } 244 245 desc = irq_to_desc(irq); 246 for_each_cpu_and(cpu, data->old_domain, cpu_online_mask) { 247 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; 248 vector++) { 249 if (per_cpu(vector_irq, cpu)[vector] != desc) 250 continue; 251 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED; 252 break; 253 } 254 } 255 data->move_in_progress = 0; 256 raw_spin_unlock_irqrestore(&vector_lock, flags); 257 } 258 259 void init_irq_alloc_info(struct irq_alloc_info *info, 260 const struct cpumask *mask) 261 { 262 memset(info, 0, sizeof(*info)); 263 info->mask = mask; 264 } 265 266 void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src) 267 { 268 if (src) 269 *dst = *src; 270 else 271 memset(dst, 0, sizeof(*dst)); 272 } 273 274 static void x86_vector_free_irqs(struct irq_domain *domain, 275 unsigned int virq, unsigned int nr_irqs) 276 { 277 struct irq_data *irq_data; 278 int i; 279 280 for (i = 0; i < nr_irqs; i++) { 281 irq_data = irq_domain_get_irq_data(x86_vector_domain, virq + i); 282 if (irq_data && irq_data->chip_data) { 283 clear_irq_vector(virq + i, irq_data->chip_data); 284 free_apic_chip_data(irq_data->chip_data); 285 #ifdef CONFIG_X86_IO_APIC 286 if (virq + i < nr_legacy_irqs()) 287 legacy_irq_data[virq + i] = NULL; 288 #endif 289 irq_domain_reset_irq_data(irq_data); 290 } 291 } 292 } 293 294 static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq, 295 unsigned int nr_irqs, void *arg) 296 { 297 struct irq_alloc_info *info = arg; 298 struct apic_chip_data *data; 299 struct irq_data *irq_data; 300 int i, err, node; 301 302 if (disable_apic) 303 return -ENXIO; 304 305 /* Currently vector allocator can't guarantee contiguous allocations */ 306 if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1) 307 return -ENOSYS; 308 309 for (i = 0; i < nr_irqs; i++) { 310 irq_data = irq_domain_get_irq_data(domain, virq + i); 311 BUG_ON(!irq_data); 312 node = irq_data_get_node(irq_data); 313 #ifdef CONFIG_X86_IO_APIC 314 if (virq + i < nr_legacy_irqs() && legacy_irq_data[virq + i]) 315 data = legacy_irq_data[virq + i]; 316 else 317 #endif 318 data = alloc_apic_chip_data(node); 319 if (!data) { 320 err = -ENOMEM; 321 goto error; 322 } 323 324 irq_data->chip = &lapic_controller; 325 irq_data->chip_data = data; 326 irq_data->hwirq = virq + i; 327 err = assign_irq_vector_policy(virq + i, node, data, info); 328 if (err) 329 goto error; 330 } 331 332 return 0; 333 334 error: 335 x86_vector_free_irqs(domain, virq, i + 1); 336 return err; 337 } 338 339 static const struct irq_domain_ops x86_vector_domain_ops = { 340 .alloc = x86_vector_alloc_irqs, 341 .free = x86_vector_free_irqs, 342 }; 343 344 int __init arch_probe_nr_irqs(void) 345 { 346 int nr; 347 348 if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) 349 nr_irqs = NR_VECTORS * nr_cpu_ids; 350 351 nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids; 352 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) 353 /* 354 * for MSI and HT dyn irq 355 */ 356 if (gsi_top <= NR_IRQS_LEGACY) 357 nr += 8 * nr_cpu_ids; 358 else 359 nr += gsi_top * 16; 360 #endif 361 if (nr < nr_irqs) 362 nr_irqs = nr; 363 364 /* 365 * We don't know if PIC is present at this point so we need to do 366 * probe() to get the right number of legacy IRQs. 367 */ 368 return legacy_pic->probe(); 369 } 370 371 #ifdef CONFIG_X86_IO_APIC 372 static void init_legacy_irqs(void) 373 { 374 int i, node = cpu_to_node(0); 375 struct apic_chip_data *data; 376 377 /* 378 * For legacy IRQ's, start with assigning irq0 to irq15 to 379 * ISA_IRQ_VECTOR(i) for all cpu's. 380 */ 381 for (i = 0; i < nr_legacy_irqs(); i++) { 382 data = legacy_irq_data[i] = alloc_apic_chip_data(node); 383 BUG_ON(!data); 384 385 data->cfg.vector = ISA_IRQ_VECTOR(i); 386 cpumask_setall(data->domain); 387 irq_set_chip_data(i, data); 388 } 389 } 390 #else 391 static void init_legacy_irqs(void) { } 392 #endif 393 394 int __init arch_early_irq_init(void) 395 { 396 init_legacy_irqs(); 397 398 x86_vector_domain = irq_domain_add_tree(NULL, &x86_vector_domain_ops, 399 NULL); 400 BUG_ON(x86_vector_domain == NULL); 401 irq_set_default_host(x86_vector_domain); 402 403 arch_init_msi_domain(x86_vector_domain); 404 arch_init_htirq_domain(x86_vector_domain); 405 406 BUG_ON(!alloc_cpumask_var(&vector_cpumask, GFP_KERNEL)); 407 408 return arch_early_ioapic_init(); 409 } 410 411 /* Initialize vector_irq on a new cpu */ 412 static void __setup_vector_irq(int cpu) 413 { 414 struct apic_chip_data *data; 415 struct irq_desc *desc; 416 int irq, vector; 417 418 /* Mark the inuse vectors */ 419 for_each_irq_desc(irq, desc) { 420 struct irq_data *idata = irq_desc_get_irq_data(desc); 421 422 data = apic_chip_data(idata); 423 if (!data || !cpumask_test_cpu(cpu, data->domain)) 424 continue; 425 vector = data->cfg.vector; 426 per_cpu(vector_irq, cpu)[vector] = desc; 427 } 428 /* Mark the free vectors */ 429 for (vector = 0; vector < NR_VECTORS; ++vector) { 430 desc = per_cpu(vector_irq, cpu)[vector]; 431 if (IS_ERR_OR_NULL(desc)) 432 continue; 433 434 data = apic_chip_data(irq_desc_get_irq_data(desc)); 435 if (!cpumask_test_cpu(cpu, data->domain)) 436 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED; 437 } 438 } 439 440 /* 441 * Setup the vector to irq mappings. Must be called with vector_lock held. 442 */ 443 void setup_vector_irq(int cpu) 444 { 445 int irq; 446 447 lockdep_assert_held(&vector_lock); 448 /* 449 * On most of the platforms, legacy PIC delivers the interrupts on the 450 * boot cpu. But there are certain platforms where PIC interrupts are 451 * delivered to multiple cpu's. If the legacy IRQ is handled by the 452 * legacy PIC, for the new cpu that is coming online, setup the static 453 * legacy vector to irq mapping: 454 */ 455 for (irq = 0; irq < nr_legacy_irqs(); irq++) 456 per_cpu(vector_irq, cpu)[ISA_IRQ_VECTOR(irq)] = irq_to_desc(irq); 457 458 __setup_vector_irq(cpu); 459 } 460 461 static int apic_retrigger_irq(struct irq_data *irq_data) 462 { 463 struct apic_chip_data *data = apic_chip_data(irq_data); 464 unsigned long flags; 465 int cpu; 466 467 raw_spin_lock_irqsave(&vector_lock, flags); 468 cpu = cpumask_first_and(data->domain, cpu_online_mask); 469 apic->send_IPI_mask(cpumask_of(cpu), data->cfg.vector); 470 raw_spin_unlock_irqrestore(&vector_lock, flags); 471 472 return 1; 473 } 474 475 void apic_ack_edge(struct irq_data *data) 476 { 477 irq_complete_move(irqd_cfg(data)); 478 irq_move_irq(data); 479 ack_APIC_irq(); 480 } 481 482 static int apic_set_affinity(struct irq_data *irq_data, 483 const struct cpumask *dest, bool force) 484 { 485 struct apic_chip_data *data = irq_data->chip_data; 486 int err, irq = irq_data->irq; 487 488 if (!config_enabled(CONFIG_SMP)) 489 return -EPERM; 490 491 if (!cpumask_intersects(dest, cpu_online_mask)) 492 return -EINVAL; 493 494 err = assign_irq_vector(irq, data, dest); 495 if (err) { 496 if (assign_irq_vector(irq, data, 497 irq_data_get_affinity_mask(irq_data))) 498 pr_err("Failed to recover vector for irq %d\n", irq); 499 return err; 500 } 501 502 return IRQ_SET_MASK_OK; 503 } 504 505 static struct irq_chip lapic_controller = { 506 .irq_ack = apic_ack_edge, 507 .irq_set_affinity = apic_set_affinity, 508 .irq_retrigger = apic_retrigger_irq, 509 }; 510 511 #ifdef CONFIG_SMP 512 static void __send_cleanup_vector(struct apic_chip_data *data) 513 { 514 cpumask_var_t cleanup_mask; 515 516 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { 517 unsigned int i; 518 519 for_each_cpu_and(i, data->old_domain, cpu_online_mask) 520 apic->send_IPI_mask(cpumask_of(i), 521 IRQ_MOVE_CLEANUP_VECTOR); 522 } else { 523 cpumask_and(cleanup_mask, data->old_domain, cpu_online_mask); 524 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); 525 free_cpumask_var(cleanup_mask); 526 } 527 data->move_in_progress = 0; 528 } 529 530 void send_cleanup_vector(struct irq_cfg *cfg) 531 { 532 struct apic_chip_data *data; 533 534 data = container_of(cfg, struct apic_chip_data, cfg); 535 if (data->move_in_progress) 536 __send_cleanup_vector(data); 537 } 538 539 asmlinkage __visible void smp_irq_move_cleanup_interrupt(void) 540 { 541 unsigned vector, me; 542 543 entering_ack_irq(); 544 545 /* Prevent vectors vanishing under us */ 546 raw_spin_lock(&vector_lock); 547 548 me = smp_processor_id(); 549 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { 550 struct apic_chip_data *data; 551 struct irq_desc *desc; 552 unsigned int irr; 553 554 retry: 555 desc = __this_cpu_read(vector_irq[vector]); 556 if (IS_ERR_OR_NULL(desc)) 557 continue; 558 559 if (!raw_spin_trylock(&desc->lock)) { 560 raw_spin_unlock(&vector_lock); 561 cpu_relax(); 562 raw_spin_lock(&vector_lock); 563 goto retry; 564 } 565 566 data = apic_chip_data(irq_desc_get_irq_data(desc)); 567 if (!data) 568 goto unlock; 569 570 /* 571 * Check if the irq migration is in progress. If so, we 572 * haven't received the cleanup request yet for this irq. 573 */ 574 if (data->move_in_progress) 575 goto unlock; 576 577 if (vector == data->cfg.vector && 578 cpumask_test_cpu(me, data->domain)) 579 goto unlock; 580 581 irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); 582 /* 583 * Check if the vector that needs to be cleanedup is 584 * registered at the cpu's IRR. If so, then this is not 585 * the best time to clean it up. Lets clean it up in the 586 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR 587 * to myself. 588 */ 589 if (irr & (1 << (vector % 32))) { 590 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); 591 goto unlock; 592 } 593 __this_cpu_write(vector_irq[vector], VECTOR_UNUSED); 594 unlock: 595 raw_spin_unlock(&desc->lock); 596 } 597 598 raw_spin_unlock(&vector_lock); 599 600 exiting_irq(); 601 } 602 603 static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) 604 { 605 unsigned me; 606 struct apic_chip_data *data; 607 608 data = container_of(cfg, struct apic_chip_data, cfg); 609 if (likely(!data->move_in_progress)) 610 return; 611 612 me = smp_processor_id(); 613 if (vector == data->cfg.vector && cpumask_test_cpu(me, data->domain)) 614 __send_cleanup_vector(data); 615 } 616 617 void irq_complete_move(struct irq_cfg *cfg) 618 { 619 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); 620 } 621 622 void irq_force_complete_move(int irq) 623 { 624 struct irq_cfg *cfg = irq_cfg(irq); 625 626 if (cfg) 627 __irq_complete_move(cfg, cfg->vector); 628 } 629 #endif 630 631 static void __init print_APIC_field(int base) 632 { 633 int i; 634 635 printk(KERN_DEBUG); 636 637 for (i = 0; i < 8; i++) 638 pr_cont("%08x", apic_read(base + i*0x10)); 639 640 pr_cont("\n"); 641 } 642 643 static void __init print_local_APIC(void *dummy) 644 { 645 unsigned int i, v, ver, maxlvt; 646 u64 icr; 647 648 pr_debug("printing local APIC contents on CPU#%d/%d:\n", 649 smp_processor_id(), hard_smp_processor_id()); 650 v = apic_read(APIC_ID); 651 pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id()); 652 v = apic_read(APIC_LVR); 653 pr_info("... APIC VERSION: %08x\n", v); 654 ver = GET_APIC_VERSION(v); 655 maxlvt = lapic_get_maxlvt(); 656 657 v = apic_read(APIC_TASKPRI); 658 pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); 659 660 /* !82489DX */ 661 if (APIC_INTEGRATED(ver)) { 662 if (!APIC_XAPIC(ver)) { 663 v = apic_read(APIC_ARBPRI); 664 pr_debug("... APIC ARBPRI: %08x (%02x)\n", 665 v, v & APIC_ARBPRI_MASK); 666 } 667 v = apic_read(APIC_PROCPRI); 668 pr_debug("... APIC PROCPRI: %08x\n", v); 669 } 670 671 /* 672 * Remote read supported only in the 82489DX and local APIC for 673 * Pentium processors. 674 */ 675 if (!APIC_INTEGRATED(ver) || maxlvt == 3) { 676 v = apic_read(APIC_RRR); 677 pr_debug("... APIC RRR: %08x\n", v); 678 } 679 680 v = apic_read(APIC_LDR); 681 pr_debug("... APIC LDR: %08x\n", v); 682 if (!x2apic_enabled()) { 683 v = apic_read(APIC_DFR); 684 pr_debug("... APIC DFR: %08x\n", v); 685 } 686 v = apic_read(APIC_SPIV); 687 pr_debug("... APIC SPIV: %08x\n", v); 688 689 pr_debug("... APIC ISR field:\n"); 690 print_APIC_field(APIC_ISR); 691 pr_debug("... APIC TMR field:\n"); 692 print_APIC_field(APIC_TMR); 693 pr_debug("... APIC IRR field:\n"); 694 print_APIC_field(APIC_IRR); 695 696 /* !82489DX */ 697 if (APIC_INTEGRATED(ver)) { 698 /* Due to the Pentium erratum 3AP. */ 699 if (maxlvt > 3) 700 apic_write(APIC_ESR, 0); 701 702 v = apic_read(APIC_ESR); 703 pr_debug("... APIC ESR: %08x\n", v); 704 } 705 706 icr = apic_icr_read(); 707 pr_debug("... APIC ICR: %08x\n", (u32)icr); 708 pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32)); 709 710 v = apic_read(APIC_LVTT); 711 pr_debug("... APIC LVTT: %08x\n", v); 712 713 if (maxlvt > 3) { 714 /* PC is LVT#4. */ 715 v = apic_read(APIC_LVTPC); 716 pr_debug("... APIC LVTPC: %08x\n", v); 717 } 718 v = apic_read(APIC_LVT0); 719 pr_debug("... APIC LVT0: %08x\n", v); 720 v = apic_read(APIC_LVT1); 721 pr_debug("... APIC LVT1: %08x\n", v); 722 723 if (maxlvt > 2) { 724 /* ERR is LVT#3. */ 725 v = apic_read(APIC_LVTERR); 726 pr_debug("... APIC LVTERR: %08x\n", v); 727 } 728 729 v = apic_read(APIC_TMICT); 730 pr_debug("... APIC TMICT: %08x\n", v); 731 v = apic_read(APIC_TMCCT); 732 pr_debug("... APIC TMCCT: %08x\n", v); 733 v = apic_read(APIC_TDCR); 734 pr_debug("... APIC TDCR: %08x\n", v); 735 736 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { 737 v = apic_read(APIC_EFEAT); 738 maxlvt = (v >> 16) & 0xff; 739 pr_debug("... APIC EFEAT: %08x\n", v); 740 v = apic_read(APIC_ECTRL); 741 pr_debug("... APIC ECTRL: %08x\n", v); 742 for (i = 0; i < maxlvt; i++) { 743 v = apic_read(APIC_EILVTn(i)); 744 pr_debug("... APIC EILVT%d: %08x\n", i, v); 745 } 746 } 747 pr_cont("\n"); 748 } 749 750 static void __init print_local_APICs(int maxcpu) 751 { 752 int cpu; 753 754 if (!maxcpu) 755 return; 756 757 preempt_disable(); 758 for_each_online_cpu(cpu) { 759 if (cpu >= maxcpu) 760 break; 761 smp_call_function_single(cpu, print_local_APIC, NULL, 1); 762 } 763 preempt_enable(); 764 } 765 766 static void __init print_PIC(void) 767 { 768 unsigned int v; 769 unsigned long flags; 770 771 if (!nr_legacy_irqs()) 772 return; 773 774 pr_debug("\nprinting PIC contents\n"); 775 776 raw_spin_lock_irqsave(&i8259A_lock, flags); 777 778 v = inb(0xa1) << 8 | inb(0x21); 779 pr_debug("... PIC IMR: %04x\n", v); 780 781 v = inb(0xa0) << 8 | inb(0x20); 782 pr_debug("... PIC IRR: %04x\n", v); 783 784 outb(0x0b, 0xa0); 785 outb(0x0b, 0x20); 786 v = inb(0xa0) << 8 | inb(0x20); 787 outb(0x0a, 0xa0); 788 outb(0x0a, 0x20); 789 790 raw_spin_unlock_irqrestore(&i8259A_lock, flags); 791 792 pr_debug("... PIC ISR: %04x\n", v); 793 794 v = inb(0x4d1) << 8 | inb(0x4d0); 795 pr_debug("... PIC ELCR: %04x\n", v); 796 } 797 798 static int show_lapic __initdata = 1; 799 static __init int setup_show_lapic(char *arg) 800 { 801 int num = -1; 802 803 if (strcmp(arg, "all") == 0) { 804 show_lapic = CONFIG_NR_CPUS; 805 } else { 806 get_option(&arg, &num); 807 if (num >= 0) 808 show_lapic = num; 809 } 810 811 return 1; 812 } 813 __setup("show_lapic=", setup_show_lapic); 814 815 static int __init print_ICs(void) 816 { 817 if (apic_verbosity == APIC_QUIET) 818 return 0; 819 820 print_PIC(); 821 822 /* don't print out if apic is not there */ 823 if (!cpu_has_apic && !apic_from_smp_config()) 824 return 0; 825 826 print_local_APICs(show_lapic); 827 print_IO_APICs(); 828 829 return 0; 830 } 831 832 late_initcall(print_ICs); 833