1 /* 2 * Local APIC related interfaces to support IOAPIC, MSI, HT_IRQ etc. 3 * 4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo 5 * Moved from arch/x86/kernel/apic/io_apic.c. 6 * Jiang Liu <jiang.liu@linux.intel.com> 7 * Enable support of hierarchical irqdomains 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 #include <linux/interrupt.h> 14 #include <linux/init.h> 15 #include <linux/compiler.h> 16 #include <linux/slab.h> 17 #include <asm/irqdomain.h> 18 #include <asm/hw_irq.h> 19 #include <asm/apic.h> 20 #include <asm/i8259.h> 21 #include <asm/desc.h> 22 #include <asm/irq_remapping.h> 23 24 struct apic_chip_data { 25 struct irq_cfg cfg; 26 cpumask_var_t domain; 27 cpumask_var_t old_domain; 28 u8 move_in_progress : 1; 29 }; 30 31 struct irq_domain *x86_vector_domain; 32 EXPORT_SYMBOL_GPL(x86_vector_domain); 33 static DEFINE_RAW_SPINLOCK(vector_lock); 34 static cpumask_var_t vector_cpumask; 35 static struct irq_chip lapic_controller; 36 #ifdef CONFIG_X86_IO_APIC 37 static struct apic_chip_data *legacy_irq_data[NR_IRQS_LEGACY]; 38 #endif 39 40 void lock_vector_lock(void) 41 { 42 /* Used to the online set of cpus does not change 43 * during assign_irq_vector. 44 */ 45 raw_spin_lock(&vector_lock); 46 } 47 48 void unlock_vector_lock(void) 49 { 50 raw_spin_unlock(&vector_lock); 51 } 52 53 static struct apic_chip_data *apic_chip_data(struct irq_data *irq_data) 54 { 55 if (!irq_data) 56 return NULL; 57 58 while (irq_data->parent_data) 59 irq_data = irq_data->parent_data; 60 61 return irq_data->chip_data; 62 } 63 64 struct irq_cfg *irqd_cfg(struct irq_data *irq_data) 65 { 66 struct apic_chip_data *data = apic_chip_data(irq_data); 67 68 return data ? &data->cfg : NULL; 69 } 70 EXPORT_SYMBOL_GPL(irqd_cfg); 71 72 struct irq_cfg *irq_cfg(unsigned int irq) 73 { 74 return irqd_cfg(irq_get_irq_data(irq)); 75 } 76 77 static struct apic_chip_data *alloc_apic_chip_data(int node) 78 { 79 struct apic_chip_data *data; 80 81 data = kzalloc_node(sizeof(*data), GFP_KERNEL, node); 82 if (!data) 83 return NULL; 84 if (!zalloc_cpumask_var_node(&data->domain, GFP_KERNEL, node)) 85 goto out_data; 86 if (!zalloc_cpumask_var_node(&data->old_domain, GFP_KERNEL, node)) 87 goto out_domain; 88 return data; 89 out_domain: 90 free_cpumask_var(data->domain); 91 out_data: 92 kfree(data); 93 return NULL; 94 } 95 96 static void free_apic_chip_data(struct apic_chip_data *data) 97 { 98 if (data) { 99 free_cpumask_var(data->domain); 100 free_cpumask_var(data->old_domain); 101 kfree(data); 102 } 103 } 104 105 static int __assign_irq_vector(int irq, struct apic_chip_data *d, 106 const struct cpumask *mask) 107 { 108 /* 109 * NOTE! The local APIC isn't very good at handling 110 * multiple interrupts at the same interrupt level. 111 * As the interrupt level is determined by taking the 112 * vector number and shifting that right by 4, we 113 * want to spread these out a bit so that they don't 114 * all fall in the same interrupt level. 115 * 116 * Also, we've got to be careful not to trash gate 117 * 0x80, because int 0x80 is hm, kind of importantish. ;) 118 */ 119 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; 120 static int current_offset = VECTOR_OFFSET_START % 16; 121 int cpu, err; 122 123 if (d->move_in_progress) 124 return -EBUSY; 125 126 /* Only try and allocate irqs on cpus that are present */ 127 err = -ENOSPC; 128 cpumask_clear(d->old_domain); 129 cpu = cpumask_first_and(mask, cpu_online_mask); 130 while (cpu < nr_cpu_ids) { 131 int new_cpu, vector, offset; 132 133 apic->vector_allocation_domain(cpu, vector_cpumask, mask); 134 135 if (cpumask_subset(vector_cpumask, d->domain)) { 136 err = 0; 137 if (cpumask_equal(vector_cpumask, d->domain)) 138 break; 139 /* 140 * New cpumask using the vector is a proper subset of 141 * the current in use mask. So cleanup the vector 142 * allocation for the members that are not used anymore. 143 */ 144 cpumask_andnot(d->old_domain, d->domain, 145 vector_cpumask); 146 d->move_in_progress = 147 cpumask_intersects(d->old_domain, cpu_online_mask); 148 cpumask_and(d->domain, d->domain, vector_cpumask); 149 break; 150 } 151 152 vector = current_vector; 153 offset = current_offset; 154 next: 155 vector += 16; 156 if (vector >= first_system_vector) { 157 offset = (offset + 1) % 16; 158 vector = FIRST_EXTERNAL_VECTOR + offset; 159 } 160 161 if (unlikely(current_vector == vector)) { 162 cpumask_or(d->old_domain, d->old_domain, 163 vector_cpumask); 164 cpumask_andnot(vector_cpumask, mask, d->old_domain); 165 cpu = cpumask_first_and(vector_cpumask, 166 cpu_online_mask); 167 continue; 168 } 169 170 if (test_bit(vector, used_vectors)) 171 goto next; 172 173 for_each_cpu_and(new_cpu, vector_cpumask, cpu_online_mask) { 174 if (!IS_ERR_OR_NULL(per_cpu(vector_irq, new_cpu)[vector])) 175 goto next; 176 } 177 /* Found one! */ 178 current_vector = vector; 179 current_offset = offset; 180 if (d->cfg.vector) { 181 cpumask_copy(d->old_domain, d->domain); 182 d->move_in_progress = 183 cpumask_intersects(d->old_domain, cpu_online_mask); 184 } 185 for_each_cpu_and(new_cpu, vector_cpumask, cpu_online_mask) 186 per_cpu(vector_irq, new_cpu)[vector] = irq_to_desc(irq); 187 d->cfg.vector = vector; 188 cpumask_copy(d->domain, vector_cpumask); 189 err = 0; 190 break; 191 } 192 193 if (!err) { 194 /* cache destination APIC IDs into cfg->dest_apicid */ 195 err = apic->cpu_mask_to_apicid_and(mask, d->domain, 196 &d->cfg.dest_apicid); 197 } 198 199 return err; 200 } 201 202 static int assign_irq_vector(int irq, struct apic_chip_data *data, 203 const struct cpumask *mask) 204 { 205 int err; 206 unsigned long flags; 207 208 raw_spin_lock_irqsave(&vector_lock, flags); 209 err = __assign_irq_vector(irq, data, mask); 210 raw_spin_unlock_irqrestore(&vector_lock, flags); 211 return err; 212 } 213 214 static int assign_irq_vector_policy(int irq, int node, 215 struct apic_chip_data *data, 216 struct irq_alloc_info *info) 217 { 218 if (info && info->mask) 219 return assign_irq_vector(irq, data, info->mask); 220 if (node != NUMA_NO_NODE && 221 assign_irq_vector(irq, data, cpumask_of_node(node)) == 0) 222 return 0; 223 return assign_irq_vector(irq, data, apic->target_cpus()); 224 } 225 226 static void clear_irq_vector(int irq, struct apic_chip_data *data) 227 { 228 struct irq_desc *desc; 229 unsigned long flags; 230 int cpu, vector; 231 232 raw_spin_lock_irqsave(&vector_lock, flags); 233 BUG_ON(!data->cfg.vector); 234 235 vector = data->cfg.vector; 236 for_each_cpu_and(cpu, data->domain, cpu_online_mask) 237 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED; 238 239 data->cfg.vector = 0; 240 cpumask_clear(data->domain); 241 242 if (likely(!data->move_in_progress)) { 243 raw_spin_unlock_irqrestore(&vector_lock, flags); 244 return; 245 } 246 247 desc = irq_to_desc(irq); 248 for_each_cpu_and(cpu, data->old_domain, cpu_online_mask) { 249 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; 250 vector++) { 251 if (per_cpu(vector_irq, cpu)[vector] != desc) 252 continue; 253 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED; 254 break; 255 } 256 } 257 data->move_in_progress = 0; 258 raw_spin_unlock_irqrestore(&vector_lock, flags); 259 } 260 261 void init_irq_alloc_info(struct irq_alloc_info *info, 262 const struct cpumask *mask) 263 { 264 memset(info, 0, sizeof(*info)); 265 info->mask = mask; 266 } 267 268 void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src) 269 { 270 if (src) 271 *dst = *src; 272 else 273 memset(dst, 0, sizeof(*dst)); 274 } 275 276 static void x86_vector_free_irqs(struct irq_domain *domain, 277 unsigned int virq, unsigned int nr_irqs) 278 { 279 struct irq_data *irq_data; 280 int i; 281 282 for (i = 0; i < nr_irqs; i++) { 283 irq_data = irq_domain_get_irq_data(x86_vector_domain, virq + i); 284 if (irq_data && irq_data->chip_data) { 285 clear_irq_vector(virq + i, irq_data->chip_data); 286 free_apic_chip_data(irq_data->chip_data); 287 #ifdef CONFIG_X86_IO_APIC 288 if (virq + i < nr_legacy_irqs()) 289 legacy_irq_data[virq + i] = NULL; 290 #endif 291 irq_domain_reset_irq_data(irq_data); 292 } 293 } 294 } 295 296 static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq, 297 unsigned int nr_irqs, void *arg) 298 { 299 struct irq_alloc_info *info = arg; 300 struct apic_chip_data *data; 301 struct irq_data *irq_data; 302 int i, err, node; 303 304 if (disable_apic) 305 return -ENXIO; 306 307 /* Currently vector allocator can't guarantee contiguous allocations */ 308 if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1) 309 return -ENOSYS; 310 311 for (i = 0; i < nr_irqs; i++) { 312 irq_data = irq_domain_get_irq_data(domain, virq + i); 313 BUG_ON(!irq_data); 314 node = irq_data_get_node(irq_data); 315 #ifdef CONFIG_X86_IO_APIC 316 if (virq + i < nr_legacy_irqs() && legacy_irq_data[virq + i]) 317 data = legacy_irq_data[virq + i]; 318 else 319 #endif 320 data = alloc_apic_chip_data(node); 321 if (!data) { 322 err = -ENOMEM; 323 goto error; 324 } 325 326 irq_data->chip = &lapic_controller; 327 irq_data->chip_data = data; 328 irq_data->hwirq = virq + i; 329 err = assign_irq_vector_policy(virq + i, node, data, info); 330 if (err) 331 goto error; 332 } 333 334 return 0; 335 336 error: 337 x86_vector_free_irqs(domain, virq, i + 1); 338 return err; 339 } 340 341 static const struct irq_domain_ops x86_vector_domain_ops = { 342 .alloc = x86_vector_alloc_irqs, 343 .free = x86_vector_free_irqs, 344 }; 345 346 int __init arch_probe_nr_irqs(void) 347 { 348 int nr; 349 350 if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) 351 nr_irqs = NR_VECTORS * nr_cpu_ids; 352 353 nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids; 354 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) 355 /* 356 * for MSI and HT dyn irq 357 */ 358 if (gsi_top <= NR_IRQS_LEGACY) 359 nr += 8 * nr_cpu_ids; 360 else 361 nr += gsi_top * 16; 362 #endif 363 if (nr < nr_irqs) 364 nr_irqs = nr; 365 366 /* 367 * We don't know if PIC is present at this point so we need to do 368 * probe() to get the right number of legacy IRQs. 369 */ 370 return legacy_pic->probe(); 371 } 372 373 #ifdef CONFIG_X86_IO_APIC 374 static void init_legacy_irqs(void) 375 { 376 int i, node = cpu_to_node(0); 377 struct apic_chip_data *data; 378 379 /* 380 * For legacy IRQ's, start with assigning irq0 to irq15 to 381 * ISA_IRQ_VECTOR(i) for all cpu's. 382 */ 383 for (i = 0; i < nr_legacy_irqs(); i++) { 384 data = legacy_irq_data[i] = alloc_apic_chip_data(node); 385 BUG_ON(!data); 386 387 data->cfg.vector = ISA_IRQ_VECTOR(i); 388 cpumask_setall(data->domain); 389 irq_set_chip_data(i, data); 390 } 391 } 392 #else 393 static void init_legacy_irqs(void) { } 394 #endif 395 396 int __init arch_early_irq_init(void) 397 { 398 init_legacy_irqs(); 399 400 x86_vector_domain = irq_domain_add_tree(NULL, &x86_vector_domain_ops, 401 NULL); 402 BUG_ON(x86_vector_domain == NULL); 403 irq_set_default_host(x86_vector_domain); 404 405 arch_init_msi_domain(x86_vector_domain); 406 arch_init_htirq_domain(x86_vector_domain); 407 408 BUG_ON(!alloc_cpumask_var(&vector_cpumask, GFP_KERNEL)); 409 410 return arch_early_ioapic_init(); 411 } 412 413 /* Initialize vector_irq on a new cpu */ 414 static void __setup_vector_irq(int cpu) 415 { 416 struct apic_chip_data *data; 417 struct irq_desc *desc; 418 int irq, vector; 419 420 /* Mark the inuse vectors */ 421 for_each_irq_desc(irq, desc) { 422 struct irq_data *idata = irq_desc_get_irq_data(desc); 423 424 data = apic_chip_data(idata); 425 if (!data || !cpumask_test_cpu(cpu, data->domain)) 426 continue; 427 vector = data->cfg.vector; 428 per_cpu(vector_irq, cpu)[vector] = desc; 429 } 430 /* Mark the free vectors */ 431 for (vector = 0; vector < NR_VECTORS; ++vector) { 432 desc = per_cpu(vector_irq, cpu)[vector]; 433 if (IS_ERR_OR_NULL(desc)) 434 continue; 435 436 data = apic_chip_data(irq_desc_get_irq_data(desc)); 437 if (!cpumask_test_cpu(cpu, data->domain)) 438 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED; 439 } 440 } 441 442 /* 443 * Setup the vector to irq mappings. Must be called with vector_lock held. 444 */ 445 void setup_vector_irq(int cpu) 446 { 447 int irq; 448 449 lockdep_assert_held(&vector_lock); 450 /* 451 * On most of the platforms, legacy PIC delivers the interrupts on the 452 * boot cpu. But there are certain platforms where PIC interrupts are 453 * delivered to multiple cpu's. If the legacy IRQ is handled by the 454 * legacy PIC, for the new cpu that is coming online, setup the static 455 * legacy vector to irq mapping: 456 */ 457 for (irq = 0; irq < nr_legacy_irqs(); irq++) 458 per_cpu(vector_irq, cpu)[ISA_IRQ_VECTOR(irq)] = irq_to_desc(irq); 459 460 __setup_vector_irq(cpu); 461 } 462 463 static int apic_retrigger_irq(struct irq_data *irq_data) 464 { 465 struct apic_chip_data *data = apic_chip_data(irq_data); 466 unsigned long flags; 467 int cpu; 468 469 raw_spin_lock_irqsave(&vector_lock, flags); 470 cpu = cpumask_first_and(data->domain, cpu_online_mask); 471 apic->send_IPI_mask(cpumask_of(cpu), data->cfg.vector); 472 raw_spin_unlock_irqrestore(&vector_lock, flags); 473 474 return 1; 475 } 476 477 void apic_ack_edge(struct irq_data *data) 478 { 479 irq_complete_move(irqd_cfg(data)); 480 irq_move_irq(data); 481 ack_APIC_irq(); 482 } 483 484 static int apic_set_affinity(struct irq_data *irq_data, 485 const struct cpumask *dest, bool force) 486 { 487 struct apic_chip_data *data = irq_data->chip_data; 488 int err, irq = irq_data->irq; 489 490 if (!config_enabled(CONFIG_SMP)) 491 return -EPERM; 492 493 if (!cpumask_intersects(dest, cpu_online_mask)) 494 return -EINVAL; 495 496 err = assign_irq_vector(irq, data, dest); 497 if (err) { 498 if (assign_irq_vector(irq, data, 499 irq_data_get_affinity_mask(irq_data))) 500 pr_err("Failed to recover vector for irq %d\n", irq); 501 return err; 502 } 503 504 return IRQ_SET_MASK_OK; 505 } 506 507 static struct irq_chip lapic_controller = { 508 .irq_ack = apic_ack_edge, 509 .irq_set_affinity = apic_set_affinity, 510 .irq_retrigger = apic_retrigger_irq, 511 }; 512 513 #ifdef CONFIG_SMP 514 static void __send_cleanup_vector(struct apic_chip_data *data) 515 { 516 cpumask_var_t cleanup_mask; 517 518 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { 519 unsigned int i; 520 521 for_each_cpu_and(i, data->old_domain, cpu_online_mask) 522 apic->send_IPI_mask(cpumask_of(i), 523 IRQ_MOVE_CLEANUP_VECTOR); 524 } else { 525 cpumask_and(cleanup_mask, data->old_domain, cpu_online_mask); 526 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); 527 free_cpumask_var(cleanup_mask); 528 } 529 data->move_in_progress = 0; 530 } 531 532 void send_cleanup_vector(struct irq_cfg *cfg) 533 { 534 struct apic_chip_data *data; 535 536 data = container_of(cfg, struct apic_chip_data, cfg); 537 if (data->move_in_progress) 538 __send_cleanup_vector(data); 539 } 540 541 asmlinkage __visible void smp_irq_move_cleanup_interrupt(void) 542 { 543 unsigned vector, me; 544 545 entering_ack_irq(); 546 547 /* Prevent vectors vanishing under us */ 548 raw_spin_lock(&vector_lock); 549 550 me = smp_processor_id(); 551 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { 552 struct apic_chip_data *data; 553 struct irq_desc *desc; 554 unsigned int irr; 555 556 retry: 557 desc = __this_cpu_read(vector_irq[vector]); 558 if (IS_ERR_OR_NULL(desc)) 559 continue; 560 561 if (!raw_spin_trylock(&desc->lock)) { 562 raw_spin_unlock(&vector_lock); 563 cpu_relax(); 564 raw_spin_lock(&vector_lock); 565 goto retry; 566 } 567 568 data = apic_chip_data(irq_desc_get_irq_data(desc)); 569 if (!data) 570 goto unlock; 571 572 /* 573 * Check if the irq migration is in progress. If so, we 574 * haven't received the cleanup request yet for this irq. 575 */ 576 if (data->move_in_progress) 577 goto unlock; 578 579 if (vector == data->cfg.vector && 580 cpumask_test_cpu(me, data->domain)) 581 goto unlock; 582 583 irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); 584 /* 585 * Check if the vector that needs to be cleanedup is 586 * registered at the cpu's IRR. If so, then this is not 587 * the best time to clean it up. Lets clean it up in the 588 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR 589 * to myself. 590 */ 591 if (irr & (1 << (vector % 32))) { 592 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); 593 goto unlock; 594 } 595 __this_cpu_write(vector_irq[vector], VECTOR_UNUSED); 596 unlock: 597 raw_spin_unlock(&desc->lock); 598 } 599 600 raw_spin_unlock(&vector_lock); 601 602 exiting_irq(); 603 } 604 605 static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) 606 { 607 unsigned me; 608 struct apic_chip_data *data; 609 610 data = container_of(cfg, struct apic_chip_data, cfg); 611 if (likely(!data->move_in_progress)) 612 return; 613 614 me = smp_processor_id(); 615 if (vector == data->cfg.vector && cpumask_test_cpu(me, data->domain)) 616 __send_cleanup_vector(data); 617 } 618 619 void irq_complete_move(struct irq_cfg *cfg) 620 { 621 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); 622 } 623 624 void irq_force_complete_move(int irq) 625 { 626 struct irq_cfg *cfg = irq_cfg(irq); 627 628 if (cfg) 629 __irq_complete_move(cfg, cfg->vector); 630 } 631 #endif 632 633 static void __init print_APIC_field(int base) 634 { 635 int i; 636 637 printk(KERN_DEBUG); 638 639 for (i = 0; i < 8; i++) 640 pr_cont("%08x", apic_read(base + i*0x10)); 641 642 pr_cont("\n"); 643 } 644 645 static void __init print_local_APIC(void *dummy) 646 { 647 unsigned int i, v, ver, maxlvt; 648 u64 icr; 649 650 pr_debug("printing local APIC contents on CPU#%d/%d:\n", 651 smp_processor_id(), hard_smp_processor_id()); 652 v = apic_read(APIC_ID); 653 pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id()); 654 v = apic_read(APIC_LVR); 655 pr_info("... APIC VERSION: %08x\n", v); 656 ver = GET_APIC_VERSION(v); 657 maxlvt = lapic_get_maxlvt(); 658 659 v = apic_read(APIC_TASKPRI); 660 pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); 661 662 /* !82489DX */ 663 if (APIC_INTEGRATED(ver)) { 664 if (!APIC_XAPIC(ver)) { 665 v = apic_read(APIC_ARBPRI); 666 pr_debug("... APIC ARBPRI: %08x (%02x)\n", 667 v, v & APIC_ARBPRI_MASK); 668 } 669 v = apic_read(APIC_PROCPRI); 670 pr_debug("... APIC PROCPRI: %08x\n", v); 671 } 672 673 /* 674 * Remote read supported only in the 82489DX and local APIC for 675 * Pentium processors. 676 */ 677 if (!APIC_INTEGRATED(ver) || maxlvt == 3) { 678 v = apic_read(APIC_RRR); 679 pr_debug("... APIC RRR: %08x\n", v); 680 } 681 682 v = apic_read(APIC_LDR); 683 pr_debug("... APIC LDR: %08x\n", v); 684 if (!x2apic_enabled()) { 685 v = apic_read(APIC_DFR); 686 pr_debug("... APIC DFR: %08x\n", v); 687 } 688 v = apic_read(APIC_SPIV); 689 pr_debug("... APIC SPIV: %08x\n", v); 690 691 pr_debug("... APIC ISR field:\n"); 692 print_APIC_field(APIC_ISR); 693 pr_debug("... APIC TMR field:\n"); 694 print_APIC_field(APIC_TMR); 695 pr_debug("... APIC IRR field:\n"); 696 print_APIC_field(APIC_IRR); 697 698 /* !82489DX */ 699 if (APIC_INTEGRATED(ver)) { 700 /* Due to the Pentium erratum 3AP. */ 701 if (maxlvt > 3) 702 apic_write(APIC_ESR, 0); 703 704 v = apic_read(APIC_ESR); 705 pr_debug("... APIC ESR: %08x\n", v); 706 } 707 708 icr = apic_icr_read(); 709 pr_debug("... APIC ICR: %08x\n", (u32)icr); 710 pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32)); 711 712 v = apic_read(APIC_LVTT); 713 pr_debug("... APIC LVTT: %08x\n", v); 714 715 if (maxlvt > 3) { 716 /* PC is LVT#4. */ 717 v = apic_read(APIC_LVTPC); 718 pr_debug("... APIC LVTPC: %08x\n", v); 719 } 720 v = apic_read(APIC_LVT0); 721 pr_debug("... APIC LVT0: %08x\n", v); 722 v = apic_read(APIC_LVT1); 723 pr_debug("... APIC LVT1: %08x\n", v); 724 725 if (maxlvt > 2) { 726 /* ERR is LVT#3. */ 727 v = apic_read(APIC_LVTERR); 728 pr_debug("... APIC LVTERR: %08x\n", v); 729 } 730 731 v = apic_read(APIC_TMICT); 732 pr_debug("... APIC TMICT: %08x\n", v); 733 v = apic_read(APIC_TMCCT); 734 pr_debug("... APIC TMCCT: %08x\n", v); 735 v = apic_read(APIC_TDCR); 736 pr_debug("... APIC TDCR: %08x\n", v); 737 738 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { 739 v = apic_read(APIC_EFEAT); 740 maxlvt = (v >> 16) & 0xff; 741 pr_debug("... APIC EFEAT: %08x\n", v); 742 v = apic_read(APIC_ECTRL); 743 pr_debug("... APIC ECTRL: %08x\n", v); 744 for (i = 0; i < maxlvt; i++) { 745 v = apic_read(APIC_EILVTn(i)); 746 pr_debug("... APIC EILVT%d: %08x\n", i, v); 747 } 748 } 749 pr_cont("\n"); 750 } 751 752 static void __init print_local_APICs(int maxcpu) 753 { 754 int cpu; 755 756 if (!maxcpu) 757 return; 758 759 preempt_disable(); 760 for_each_online_cpu(cpu) { 761 if (cpu >= maxcpu) 762 break; 763 smp_call_function_single(cpu, print_local_APIC, NULL, 1); 764 } 765 preempt_enable(); 766 } 767 768 static void __init print_PIC(void) 769 { 770 unsigned int v; 771 unsigned long flags; 772 773 if (!nr_legacy_irqs()) 774 return; 775 776 pr_debug("\nprinting PIC contents\n"); 777 778 raw_spin_lock_irqsave(&i8259A_lock, flags); 779 780 v = inb(0xa1) << 8 | inb(0x21); 781 pr_debug("... PIC IMR: %04x\n", v); 782 783 v = inb(0xa0) << 8 | inb(0x20); 784 pr_debug("... PIC IRR: %04x\n", v); 785 786 outb(0x0b, 0xa0); 787 outb(0x0b, 0x20); 788 v = inb(0xa0) << 8 | inb(0x20); 789 outb(0x0a, 0xa0); 790 outb(0x0a, 0x20); 791 792 raw_spin_unlock_irqrestore(&i8259A_lock, flags); 793 794 pr_debug("... PIC ISR: %04x\n", v); 795 796 v = inb(0x4d1) << 8 | inb(0x4d0); 797 pr_debug("... PIC ELCR: %04x\n", v); 798 } 799 800 static int show_lapic __initdata = 1; 801 static __init int setup_show_lapic(char *arg) 802 { 803 int num = -1; 804 805 if (strcmp(arg, "all") == 0) { 806 show_lapic = CONFIG_NR_CPUS; 807 } else { 808 get_option(&arg, &num); 809 if (num >= 0) 810 show_lapic = num; 811 } 812 813 return 1; 814 } 815 __setup("show_lapic=", setup_show_lapic); 816 817 static int __init print_ICs(void) 818 { 819 if (apic_verbosity == APIC_QUIET) 820 return 0; 821 822 print_PIC(); 823 824 /* don't print out if apic is not there */ 825 if (!cpu_has_apic && !apic_from_smp_config()) 826 return 0; 827 828 print_local_APICs(show_lapic); 829 print_IO_APICs(); 830 831 return 0; 832 } 833 834 late_initcall(print_ICs); 835