1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Local APIC related interfaces to support IOAPIC, MSI, etc. 4 * 5 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo 6 * Moved from arch/x86/kernel/apic/io_apic.c. 7 * Jiang Liu <jiang.liu@linux.intel.com> 8 * Enable support of hierarchical irqdomains 9 */ 10 #include <linux/interrupt.h> 11 #include <linux/irq.h> 12 #include <linux/seq_file.h> 13 #include <linux/init.h> 14 #include <linux/compiler.h> 15 #include <linux/slab.h> 16 #include <asm/irqdomain.h> 17 #include <asm/hw_irq.h> 18 #include <asm/traps.h> 19 #include <asm/apic.h> 20 #include <asm/i8259.h> 21 #include <asm/desc.h> 22 #include <asm/irq_remapping.h> 23 24 #include <asm/trace/irq_vectors.h> 25 26 struct apic_chip_data { 27 struct irq_cfg hw_irq_cfg; 28 unsigned int vector; 29 unsigned int prev_vector; 30 unsigned int cpu; 31 unsigned int prev_cpu; 32 unsigned int irq; 33 struct hlist_node clist; 34 unsigned int move_in_progress : 1, 35 is_managed : 1, 36 can_reserve : 1, 37 has_reserved : 1; 38 }; 39 40 struct irq_domain *x86_vector_domain; 41 EXPORT_SYMBOL_GPL(x86_vector_domain); 42 static DEFINE_RAW_SPINLOCK(vector_lock); 43 static cpumask_var_t vector_searchmask; 44 static struct irq_chip lapic_controller; 45 static struct irq_matrix *vector_matrix; 46 #ifdef CONFIG_SMP 47 static DEFINE_PER_CPU(struct hlist_head, cleanup_list); 48 #endif 49 50 void lock_vector_lock(void) 51 { 52 /* Used to the online set of cpus does not change 53 * during assign_irq_vector. 54 */ 55 raw_spin_lock(&vector_lock); 56 } 57 58 void unlock_vector_lock(void) 59 { 60 raw_spin_unlock(&vector_lock); 61 } 62 63 void init_irq_alloc_info(struct irq_alloc_info *info, 64 const struct cpumask *mask) 65 { 66 memset(info, 0, sizeof(*info)); 67 info->mask = mask; 68 } 69 70 void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src) 71 { 72 if (src) 73 *dst = *src; 74 else 75 memset(dst, 0, sizeof(*dst)); 76 } 77 78 static struct apic_chip_data *apic_chip_data(struct irq_data *irqd) 79 { 80 if (!irqd) 81 return NULL; 82 83 while (irqd->parent_data) 84 irqd = irqd->parent_data; 85 86 return irqd->chip_data; 87 } 88 89 struct irq_cfg *irqd_cfg(struct irq_data *irqd) 90 { 91 struct apic_chip_data *apicd = apic_chip_data(irqd); 92 93 return apicd ? &apicd->hw_irq_cfg : NULL; 94 } 95 EXPORT_SYMBOL_GPL(irqd_cfg); 96 97 struct irq_cfg *irq_cfg(unsigned int irq) 98 { 99 return irqd_cfg(irq_get_irq_data(irq)); 100 } 101 102 static struct apic_chip_data *alloc_apic_chip_data(int node) 103 { 104 struct apic_chip_data *apicd; 105 106 apicd = kzalloc_node(sizeof(*apicd), GFP_KERNEL, node); 107 if (apicd) 108 INIT_HLIST_NODE(&apicd->clist); 109 return apicd; 110 } 111 112 static void free_apic_chip_data(struct apic_chip_data *apicd) 113 { 114 kfree(apicd); 115 } 116 117 static void apic_update_irq_cfg(struct irq_data *irqd, unsigned int vector, 118 unsigned int cpu) 119 { 120 struct apic_chip_data *apicd = apic_chip_data(irqd); 121 122 lockdep_assert_held(&vector_lock); 123 124 apicd->hw_irq_cfg.vector = vector; 125 apicd->hw_irq_cfg.dest_apicid = apic->calc_dest_apicid(cpu); 126 irq_data_update_effective_affinity(irqd, cpumask_of(cpu)); 127 trace_vector_config(irqd->irq, vector, cpu, 128 apicd->hw_irq_cfg.dest_apicid); 129 } 130 131 static void apic_update_vector(struct irq_data *irqd, unsigned int newvec, 132 unsigned int newcpu) 133 { 134 struct apic_chip_data *apicd = apic_chip_data(irqd); 135 struct irq_desc *desc = irq_data_to_desc(irqd); 136 bool managed = irqd_affinity_is_managed(irqd); 137 138 lockdep_assert_held(&vector_lock); 139 140 trace_vector_update(irqd->irq, newvec, newcpu, apicd->vector, 141 apicd->cpu); 142 143 /* 144 * If there is no vector associated or if the associated vector is 145 * the shutdown vector, which is associated to make PCI/MSI 146 * shutdown mode work, then there is nothing to release. Clear out 147 * prev_vector for this and the offlined target case. 148 */ 149 apicd->prev_vector = 0; 150 if (!apicd->vector || apicd->vector == MANAGED_IRQ_SHUTDOWN_VECTOR) 151 goto setnew; 152 /* 153 * If the target CPU of the previous vector is online, then mark 154 * the vector as move in progress and store it for cleanup when the 155 * first interrupt on the new vector arrives. If the target CPU is 156 * offline then the regular release mechanism via the cleanup 157 * vector is not possible and the vector can be immediately freed 158 * in the underlying matrix allocator. 159 */ 160 if (cpu_online(apicd->cpu)) { 161 apicd->move_in_progress = true; 162 apicd->prev_vector = apicd->vector; 163 apicd->prev_cpu = apicd->cpu; 164 WARN_ON_ONCE(apicd->cpu == newcpu); 165 } else { 166 irq_matrix_free(vector_matrix, apicd->cpu, apicd->vector, 167 managed); 168 } 169 170 setnew: 171 apicd->vector = newvec; 172 apicd->cpu = newcpu; 173 BUG_ON(!IS_ERR_OR_NULL(per_cpu(vector_irq, newcpu)[newvec])); 174 per_cpu(vector_irq, newcpu)[newvec] = desc; 175 } 176 177 static void vector_assign_managed_shutdown(struct irq_data *irqd) 178 { 179 unsigned int cpu = cpumask_first(cpu_online_mask); 180 181 apic_update_irq_cfg(irqd, MANAGED_IRQ_SHUTDOWN_VECTOR, cpu); 182 } 183 184 static int reserve_managed_vector(struct irq_data *irqd) 185 { 186 const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd); 187 struct apic_chip_data *apicd = apic_chip_data(irqd); 188 unsigned long flags; 189 int ret; 190 191 raw_spin_lock_irqsave(&vector_lock, flags); 192 apicd->is_managed = true; 193 ret = irq_matrix_reserve_managed(vector_matrix, affmsk); 194 raw_spin_unlock_irqrestore(&vector_lock, flags); 195 trace_vector_reserve_managed(irqd->irq, ret); 196 return ret; 197 } 198 199 static void reserve_irq_vector_locked(struct irq_data *irqd) 200 { 201 struct apic_chip_data *apicd = apic_chip_data(irqd); 202 203 irq_matrix_reserve(vector_matrix); 204 apicd->can_reserve = true; 205 apicd->has_reserved = true; 206 irqd_set_can_reserve(irqd); 207 trace_vector_reserve(irqd->irq, 0); 208 vector_assign_managed_shutdown(irqd); 209 } 210 211 static int reserve_irq_vector(struct irq_data *irqd) 212 { 213 unsigned long flags; 214 215 raw_spin_lock_irqsave(&vector_lock, flags); 216 reserve_irq_vector_locked(irqd); 217 raw_spin_unlock_irqrestore(&vector_lock, flags); 218 return 0; 219 } 220 221 static int 222 assign_vector_locked(struct irq_data *irqd, const struct cpumask *dest) 223 { 224 struct apic_chip_data *apicd = apic_chip_data(irqd); 225 bool resvd = apicd->has_reserved; 226 unsigned int cpu = apicd->cpu; 227 int vector = apicd->vector; 228 229 lockdep_assert_held(&vector_lock); 230 231 /* 232 * If the current target CPU is online and in the new requested 233 * affinity mask, there is no point in moving the interrupt from 234 * one CPU to another. 235 */ 236 if (vector && cpu_online(cpu) && cpumask_test_cpu(cpu, dest)) 237 return 0; 238 239 /* 240 * Careful here. @apicd might either have move_in_progress set or 241 * be enqueued for cleanup. Assigning a new vector would either 242 * leave a stale vector on some CPU around or in case of a pending 243 * cleanup corrupt the hlist. 244 */ 245 if (apicd->move_in_progress || !hlist_unhashed(&apicd->clist)) 246 return -EBUSY; 247 248 vector = irq_matrix_alloc(vector_matrix, dest, resvd, &cpu); 249 trace_vector_alloc(irqd->irq, vector, resvd, vector); 250 if (vector < 0) 251 return vector; 252 apic_update_vector(irqd, vector, cpu); 253 apic_update_irq_cfg(irqd, vector, cpu); 254 255 return 0; 256 } 257 258 static int assign_irq_vector(struct irq_data *irqd, const struct cpumask *dest) 259 { 260 unsigned long flags; 261 int ret; 262 263 raw_spin_lock_irqsave(&vector_lock, flags); 264 cpumask_and(vector_searchmask, dest, cpu_online_mask); 265 ret = assign_vector_locked(irqd, vector_searchmask); 266 raw_spin_unlock_irqrestore(&vector_lock, flags); 267 return ret; 268 } 269 270 static int assign_irq_vector_any_locked(struct irq_data *irqd) 271 { 272 /* Get the affinity mask - either irq_default_affinity or (user) set */ 273 const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd); 274 int node = irq_data_get_node(irqd); 275 276 if (node == NUMA_NO_NODE) 277 goto all; 278 /* Try the intersection of @affmsk and node mask */ 279 cpumask_and(vector_searchmask, cpumask_of_node(node), affmsk); 280 if (!assign_vector_locked(irqd, vector_searchmask)) 281 return 0; 282 /* Try the node mask */ 283 if (!assign_vector_locked(irqd, cpumask_of_node(node))) 284 return 0; 285 all: 286 /* Try the full affinity mask */ 287 cpumask_and(vector_searchmask, affmsk, cpu_online_mask); 288 if (!assign_vector_locked(irqd, vector_searchmask)) 289 return 0; 290 /* Try the full online mask */ 291 return assign_vector_locked(irqd, cpu_online_mask); 292 } 293 294 static int 295 assign_irq_vector_policy(struct irq_data *irqd, struct irq_alloc_info *info) 296 { 297 if (irqd_affinity_is_managed(irqd)) 298 return reserve_managed_vector(irqd); 299 if (info->mask) 300 return assign_irq_vector(irqd, info->mask); 301 /* 302 * Make only a global reservation with no guarantee. A real vector 303 * is associated at activation time. 304 */ 305 return reserve_irq_vector(irqd); 306 } 307 308 static int 309 assign_managed_vector(struct irq_data *irqd, const struct cpumask *dest) 310 { 311 const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd); 312 struct apic_chip_data *apicd = apic_chip_data(irqd); 313 int vector, cpu; 314 315 cpumask_and(vector_searchmask, dest, affmsk); 316 317 /* set_affinity might call here for nothing */ 318 if (apicd->vector && cpumask_test_cpu(apicd->cpu, vector_searchmask)) 319 return 0; 320 vector = irq_matrix_alloc_managed(vector_matrix, vector_searchmask, 321 &cpu); 322 trace_vector_alloc_managed(irqd->irq, vector, vector); 323 if (vector < 0) 324 return vector; 325 apic_update_vector(irqd, vector, cpu); 326 apic_update_irq_cfg(irqd, vector, cpu); 327 return 0; 328 } 329 330 static void clear_irq_vector(struct irq_data *irqd) 331 { 332 struct apic_chip_data *apicd = apic_chip_data(irqd); 333 bool managed = irqd_affinity_is_managed(irqd); 334 unsigned int vector = apicd->vector; 335 336 lockdep_assert_held(&vector_lock); 337 338 if (!vector) 339 return; 340 341 trace_vector_clear(irqd->irq, vector, apicd->cpu, apicd->prev_vector, 342 apicd->prev_cpu); 343 344 per_cpu(vector_irq, apicd->cpu)[vector] = VECTOR_SHUTDOWN; 345 irq_matrix_free(vector_matrix, apicd->cpu, vector, managed); 346 apicd->vector = 0; 347 348 /* Clean up move in progress */ 349 vector = apicd->prev_vector; 350 if (!vector) 351 return; 352 353 per_cpu(vector_irq, apicd->prev_cpu)[vector] = VECTOR_SHUTDOWN; 354 irq_matrix_free(vector_matrix, apicd->prev_cpu, vector, managed); 355 apicd->prev_vector = 0; 356 apicd->move_in_progress = 0; 357 hlist_del_init(&apicd->clist); 358 } 359 360 static void x86_vector_deactivate(struct irq_domain *dom, struct irq_data *irqd) 361 { 362 struct apic_chip_data *apicd = apic_chip_data(irqd); 363 unsigned long flags; 364 365 trace_vector_deactivate(irqd->irq, apicd->is_managed, 366 apicd->can_reserve, false); 367 368 /* Regular fixed assigned interrupt */ 369 if (!apicd->is_managed && !apicd->can_reserve) 370 return; 371 /* If the interrupt has a global reservation, nothing to do */ 372 if (apicd->has_reserved) 373 return; 374 375 raw_spin_lock_irqsave(&vector_lock, flags); 376 clear_irq_vector(irqd); 377 if (apicd->can_reserve) 378 reserve_irq_vector_locked(irqd); 379 else 380 vector_assign_managed_shutdown(irqd); 381 raw_spin_unlock_irqrestore(&vector_lock, flags); 382 } 383 384 static int activate_reserved(struct irq_data *irqd) 385 { 386 struct apic_chip_data *apicd = apic_chip_data(irqd); 387 int ret; 388 389 ret = assign_irq_vector_any_locked(irqd); 390 if (!ret) { 391 apicd->has_reserved = false; 392 /* 393 * Core might have disabled reservation mode after 394 * allocating the irq descriptor. Ideally this should 395 * happen before allocation time, but that would require 396 * completely convoluted ways of transporting that 397 * information. 398 */ 399 if (!irqd_can_reserve(irqd)) 400 apicd->can_reserve = false; 401 } 402 403 /* 404 * Check to ensure that the effective affinity mask is a subset 405 * the user supplied affinity mask, and warn the user if it is not 406 */ 407 if (!cpumask_subset(irq_data_get_effective_affinity_mask(irqd), 408 irq_data_get_affinity_mask(irqd))) { 409 pr_warn("irq %u: Affinity broken due to vector space exhaustion.\n", 410 irqd->irq); 411 } 412 413 return ret; 414 } 415 416 static int activate_managed(struct irq_data *irqd) 417 { 418 const struct cpumask *dest = irq_data_get_affinity_mask(irqd); 419 int ret; 420 421 cpumask_and(vector_searchmask, dest, cpu_online_mask); 422 if (WARN_ON_ONCE(cpumask_empty(vector_searchmask))) { 423 /* Something in the core code broke! Survive gracefully */ 424 pr_err("Managed startup for irq %u, but no CPU\n", irqd->irq); 425 return -EINVAL; 426 } 427 428 ret = assign_managed_vector(irqd, vector_searchmask); 429 /* 430 * This should not happen. The vector reservation got buggered. Handle 431 * it gracefully. 432 */ 433 if (WARN_ON_ONCE(ret < 0)) { 434 pr_err("Managed startup irq %u, no vector available\n", 435 irqd->irq); 436 } 437 return ret; 438 } 439 440 static int x86_vector_activate(struct irq_domain *dom, struct irq_data *irqd, 441 bool reserve) 442 { 443 struct apic_chip_data *apicd = apic_chip_data(irqd); 444 unsigned long flags; 445 int ret = 0; 446 447 trace_vector_activate(irqd->irq, apicd->is_managed, 448 apicd->can_reserve, reserve); 449 450 raw_spin_lock_irqsave(&vector_lock, flags); 451 if (!apicd->can_reserve && !apicd->is_managed) 452 assign_irq_vector_any_locked(irqd); 453 else if (reserve || irqd_is_managed_and_shutdown(irqd)) 454 vector_assign_managed_shutdown(irqd); 455 else if (apicd->is_managed) 456 ret = activate_managed(irqd); 457 else if (apicd->has_reserved) 458 ret = activate_reserved(irqd); 459 raw_spin_unlock_irqrestore(&vector_lock, flags); 460 return ret; 461 } 462 463 static void vector_free_reserved_and_managed(struct irq_data *irqd) 464 { 465 const struct cpumask *dest = irq_data_get_affinity_mask(irqd); 466 struct apic_chip_data *apicd = apic_chip_data(irqd); 467 468 trace_vector_teardown(irqd->irq, apicd->is_managed, 469 apicd->has_reserved); 470 471 if (apicd->has_reserved) 472 irq_matrix_remove_reserved(vector_matrix); 473 if (apicd->is_managed) 474 irq_matrix_remove_managed(vector_matrix, dest); 475 } 476 477 static void x86_vector_free_irqs(struct irq_domain *domain, 478 unsigned int virq, unsigned int nr_irqs) 479 { 480 struct apic_chip_data *apicd; 481 struct irq_data *irqd; 482 unsigned long flags; 483 int i; 484 485 for (i = 0; i < nr_irqs; i++) { 486 irqd = irq_domain_get_irq_data(x86_vector_domain, virq + i); 487 if (irqd && irqd->chip_data) { 488 raw_spin_lock_irqsave(&vector_lock, flags); 489 clear_irq_vector(irqd); 490 vector_free_reserved_and_managed(irqd); 491 apicd = irqd->chip_data; 492 irq_domain_reset_irq_data(irqd); 493 raw_spin_unlock_irqrestore(&vector_lock, flags); 494 free_apic_chip_data(apicd); 495 } 496 } 497 } 498 499 static bool vector_configure_legacy(unsigned int virq, struct irq_data *irqd, 500 struct apic_chip_data *apicd) 501 { 502 unsigned long flags; 503 bool realloc = false; 504 505 apicd->vector = ISA_IRQ_VECTOR(virq); 506 apicd->cpu = 0; 507 508 raw_spin_lock_irqsave(&vector_lock, flags); 509 /* 510 * If the interrupt is activated, then it must stay at this vector 511 * position. That's usually the timer interrupt (0). 512 */ 513 if (irqd_is_activated(irqd)) { 514 trace_vector_setup(virq, true, 0); 515 apic_update_irq_cfg(irqd, apicd->vector, apicd->cpu); 516 } else { 517 /* Release the vector */ 518 apicd->can_reserve = true; 519 irqd_set_can_reserve(irqd); 520 clear_irq_vector(irqd); 521 realloc = true; 522 } 523 raw_spin_unlock_irqrestore(&vector_lock, flags); 524 return realloc; 525 } 526 527 static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq, 528 unsigned int nr_irqs, void *arg) 529 { 530 struct irq_alloc_info *info = arg; 531 struct apic_chip_data *apicd; 532 struct irq_data *irqd; 533 int i, err, node; 534 535 if (disable_apic) 536 return -ENXIO; 537 538 /* Currently vector allocator can't guarantee contiguous allocations */ 539 if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1) 540 return -ENOSYS; 541 542 for (i = 0; i < nr_irqs; i++) { 543 irqd = irq_domain_get_irq_data(domain, virq + i); 544 BUG_ON(!irqd); 545 node = irq_data_get_node(irqd); 546 WARN_ON_ONCE(irqd->chip_data); 547 apicd = alloc_apic_chip_data(node); 548 if (!apicd) { 549 err = -ENOMEM; 550 goto error; 551 } 552 553 apicd->irq = virq + i; 554 irqd->chip = &lapic_controller; 555 irqd->chip_data = apicd; 556 irqd->hwirq = virq + i; 557 irqd_set_single_target(irqd); 558 /* 559 * Prevent that any of these interrupts is invoked in 560 * non interrupt context via e.g. generic_handle_irq() 561 * as that can corrupt the affinity move state. 562 */ 563 irqd_set_handle_enforce_irqctx(irqd); 564 565 /* Don't invoke affinity setter on deactivated interrupts */ 566 irqd_set_affinity_on_activate(irqd); 567 568 /* 569 * Legacy vectors are already assigned when the IOAPIC 570 * takes them over. They stay on the same vector. This is 571 * required for check_timer() to work correctly as it might 572 * switch back to legacy mode. Only update the hardware 573 * config. 574 */ 575 if (info->flags & X86_IRQ_ALLOC_LEGACY) { 576 if (!vector_configure_legacy(virq + i, irqd, apicd)) 577 continue; 578 } 579 580 err = assign_irq_vector_policy(irqd, info); 581 trace_vector_setup(virq + i, false, err); 582 if (err) { 583 irqd->chip_data = NULL; 584 free_apic_chip_data(apicd); 585 goto error; 586 } 587 } 588 589 return 0; 590 591 error: 592 x86_vector_free_irqs(domain, virq, i); 593 return err; 594 } 595 596 #ifdef CONFIG_GENERIC_IRQ_DEBUGFS 597 static void x86_vector_debug_show(struct seq_file *m, struct irq_domain *d, 598 struct irq_data *irqd, int ind) 599 { 600 struct apic_chip_data apicd; 601 unsigned long flags; 602 int irq; 603 604 if (!irqd) { 605 irq_matrix_debug_show(m, vector_matrix, ind); 606 return; 607 } 608 609 irq = irqd->irq; 610 if (irq < nr_legacy_irqs() && !test_bit(irq, &io_apic_irqs)) { 611 seq_printf(m, "%*sVector: %5d\n", ind, "", ISA_IRQ_VECTOR(irq)); 612 seq_printf(m, "%*sTarget: Legacy PIC all CPUs\n", ind, ""); 613 return; 614 } 615 616 if (!irqd->chip_data) { 617 seq_printf(m, "%*sVector: Not assigned\n", ind, ""); 618 return; 619 } 620 621 raw_spin_lock_irqsave(&vector_lock, flags); 622 memcpy(&apicd, irqd->chip_data, sizeof(apicd)); 623 raw_spin_unlock_irqrestore(&vector_lock, flags); 624 625 seq_printf(m, "%*sVector: %5u\n", ind, "", apicd.vector); 626 seq_printf(m, "%*sTarget: %5u\n", ind, "", apicd.cpu); 627 if (apicd.prev_vector) { 628 seq_printf(m, "%*sPrevious vector: %5u\n", ind, "", apicd.prev_vector); 629 seq_printf(m, "%*sPrevious target: %5u\n", ind, "", apicd.prev_cpu); 630 } 631 seq_printf(m, "%*smove_in_progress: %u\n", ind, "", apicd.move_in_progress ? 1 : 0); 632 seq_printf(m, "%*sis_managed: %u\n", ind, "", apicd.is_managed ? 1 : 0); 633 seq_printf(m, "%*scan_reserve: %u\n", ind, "", apicd.can_reserve ? 1 : 0); 634 seq_printf(m, "%*shas_reserved: %u\n", ind, "", apicd.has_reserved ? 1 : 0); 635 seq_printf(m, "%*scleanup_pending: %u\n", ind, "", !hlist_unhashed(&apicd.clist)); 636 } 637 #endif 638 639 static const struct irq_domain_ops x86_vector_domain_ops = { 640 .alloc = x86_vector_alloc_irqs, 641 .free = x86_vector_free_irqs, 642 .activate = x86_vector_activate, 643 .deactivate = x86_vector_deactivate, 644 #ifdef CONFIG_GENERIC_IRQ_DEBUGFS 645 .debug_show = x86_vector_debug_show, 646 #endif 647 }; 648 649 int __init arch_probe_nr_irqs(void) 650 { 651 int nr; 652 653 if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) 654 nr_irqs = NR_VECTORS * nr_cpu_ids; 655 656 nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids; 657 #if defined(CONFIG_PCI_MSI) 658 /* 659 * for MSI and HT dyn irq 660 */ 661 if (gsi_top <= NR_IRQS_LEGACY) 662 nr += 8 * nr_cpu_ids; 663 else 664 nr += gsi_top * 16; 665 #endif 666 if (nr < nr_irqs) 667 nr_irqs = nr; 668 669 /* 670 * We don't know if PIC is present at this point so we need to do 671 * probe() to get the right number of legacy IRQs. 672 */ 673 return legacy_pic->probe(); 674 } 675 676 void lapic_assign_legacy_vector(unsigned int irq, bool replace) 677 { 678 /* 679 * Use assign system here so it wont get accounted as allocated 680 * and moveable in the cpu hotplug check and it prevents managed 681 * irq reservation from touching it. 682 */ 683 irq_matrix_assign_system(vector_matrix, ISA_IRQ_VECTOR(irq), replace); 684 } 685 686 void __init lapic_assign_system_vectors(void) 687 { 688 unsigned int i, vector = 0; 689 690 for_each_set_bit_from(vector, system_vectors, NR_VECTORS) 691 irq_matrix_assign_system(vector_matrix, vector, false); 692 693 if (nr_legacy_irqs() > 1) 694 lapic_assign_legacy_vector(PIC_CASCADE_IR, false); 695 696 /* System vectors are reserved, online it */ 697 irq_matrix_online(vector_matrix); 698 699 /* Mark the preallocated legacy interrupts */ 700 for (i = 0; i < nr_legacy_irqs(); i++) { 701 if (i != PIC_CASCADE_IR) 702 irq_matrix_assign(vector_matrix, ISA_IRQ_VECTOR(i)); 703 } 704 } 705 706 int __init arch_early_irq_init(void) 707 { 708 struct fwnode_handle *fn; 709 710 fn = irq_domain_alloc_named_fwnode("VECTOR"); 711 BUG_ON(!fn); 712 x86_vector_domain = irq_domain_create_tree(fn, &x86_vector_domain_ops, 713 NULL); 714 BUG_ON(x86_vector_domain == NULL); 715 irq_set_default_host(x86_vector_domain); 716 717 arch_init_msi_domain(x86_vector_domain); 718 719 BUG_ON(!alloc_cpumask_var(&vector_searchmask, GFP_KERNEL)); 720 721 /* 722 * Allocate the vector matrix allocator data structure and limit the 723 * search area. 724 */ 725 vector_matrix = irq_alloc_matrix(NR_VECTORS, FIRST_EXTERNAL_VECTOR, 726 FIRST_SYSTEM_VECTOR); 727 BUG_ON(!vector_matrix); 728 729 return arch_early_ioapic_init(); 730 } 731 732 #ifdef CONFIG_SMP 733 734 static struct irq_desc *__setup_vector_irq(int vector) 735 { 736 int isairq = vector - ISA_IRQ_VECTOR(0); 737 738 /* Check whether the irq is in the legacy space */ 739 if (isairq < 0 || isairq >= nr_legacy_irqs()) 740 return VECTOR_UNUSED; 741 /* Check whether the irq is handled by the IOAPIC */ 742 if (test_bit(isairq, &io_apic_irqs)) 743 return VECTOR_UNUSED; 744 return irq_to_desc(isairq); 745 } 746 747 /* Online the local APIC infrastructure and initialize the vectors */ 748 void lapic_online(void) 749 { 750 unsigned int vector; 751 752 lockdep_assert_held(&vector_lock); 753 754 /* Online the vector matrix array for this CPU */ 755 irq_matrix_online(vector_matrix); 756 757 /* 758 * The interrupt affinity logic never targets interrupts to offline 759 * CPUs. The exception are the legacy PIC interrupts. In general 760 * they are only targeted to CPU0, but depending on the platform 761 * they can be distributed to any online CPU in hardware. The 762 * kernel has no influence on that. So all active legacy vectors 763 * must be installed on all CPUs. All non legacy interrupts can be 764 * cleared. 765 */ 766 for (vector = 0; vector < NR_VECTORS; vector++) 767 this_cpu_write(vector_irq[vector], __setup_vector_irq(vector)); 768 } 769 770 void lapic_offline(void) 771 { 772 lock_vector_lock(); 773 irq_matrix_offline(vector_matrix); 774 unlock_vector_lock(); 775 } 776 777 static int apic_set_affinity(struct irq_data *irqd, 778 const struct cpumask *dest, bool force) 779 { 780 int err; 781 782 if (WARN_ON_ONCE(!irqd_is_activated(irqd))) 783 return -EIO; 784 785 raw_spin_lock(&vector_lock); 786 cpumask_and(vector_searchmask, dest, cpu_online_mask); 787 if (irqd_affinity_is_managed(irqd)) 788 err = assign_managed_vector(irqd, vector_searchmask); 789 else 790 err = assign_vector_locked(irqd, vector_searchmask); 791 raw_spin_unlock(&vector_lock); 792 return err ? err : IRQ_SET_MASK_OK; 793 } 794 795 #else 796 # define apic_set_affinity NULL 797 #endif 798 799 static int apic_retrigger_irq(struct irq_data *irqd) 800 { 801 struct apic_chip_data *apicd = apic_chip_data(irqd); 802 unsigned long flags; 803 804 raw_spin_lock_irqsave(&vector_lock, flags); 805 apic->send_IPI(apicd->cpu, apicd->vector); 806 raw_spin_unlock_irqrestore(&vector_lock, flags); 807 808 return 1; 809 } 810 811 void apic_ack_irq(struct irq_data *irqd) 812 { 813 irq_move_irq(irqd); 814 ack_APIC_irq(); 815 } 816 817 void apic_ack_edge(struct irq_data *irqd) 818 { 819 irq_complete_move(irqd_cfg(irqd)); 820 apic_ack_irq(irqd); 821 } 822 823 static struct irq_chip lapic_controller = { 824 .name = "APIC", 825 .irq_ack = apic_ack_edge, 826 .irq_set_affinity = apic_set_affinity, 827 .irq_retrigger = apic_retrigger_irq, 828 }; 829 830 #ifdef CONFIG_SMP 831 832 static void free_moved_vector(struct apic_chip_data *apicd) 833 { 834 unsigned int vector = apicd->prev_vector; 835 unsigned int cpu = apicd->prev_cpu; 836 bool managed = apicd->is_managed; 837 838 /* 839 * Managed interrupts are usually not migrated away 840 * from an online CPU, but CPU isolation 'managed_irq' 841 * can make that happen. 842 * 1) Activation does not take the isolation into account 843 * to keep the code simple 844 * 2) Migration away from an isolated CPU can happen when 845 * a non-isolated CPU which is in the calculated 846 * affinity mask comes online. 847 */ 848 trace_vector_free_moved(apicd->irq, cpu, vector, managed); 849 irq_matrix_free(vector_matrix, cpu, vector, managed); 850 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED; 851 hlist_del_init(&apicd->clist); 852 apicd->prev_vector = 0; 853 apicd->move_in_progress = 0; 854 } 855 856 DEFINE_IDTENTRY_SYSVEC(sysvec_irq_move_cleanup) 857 { 858 struct hlist_head *clhead = this_cpu_ptr(&cleanup_list); 859 struct apic_chip_data *apicd; 860 struct hlist_node *tmp; 861 862 ack_APIC_irq(); 863 /* Prevent vectors vanishing under us */ 864 raw_spin_lock(&vector_lock); 865 866 hlist_for_each_entry_safe(apicd, tmp, clhead, clist) { 867 unsigned int irr, vector = apicd->prev_vector; 868 869 /* 870 * Paranoia: Check if the vector that needs to be cleaned 871 * up is registered at the APICs IRR. If so, then this is 872 * not the best time to clean it up. Clean it up in the 873 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR 874 * to this CPU. IRQ_MOVE_CLEANUP_VECTOR is the lowest 875 * priority external vector, so on return from this 876 * interrupt the device interrupt will happen first. 877 */ 878 irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); 879 if (irr & (1U << (vector % 32))) { 880 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); 881 continue; 882 } 883 free_moved_vector(apicd); 884 } 885 886 raw_spin_unlock(&vector_lock); 887 } 888 889 static void __send_cleanup_vector(struct apic_chip_data *apicd) 890 { 891 unsigned int cpu; 892 893 raw_spin_lock(&vector_lock); 894 apicd->move_in_progress = 0; 895 cpu = apicd->prev_cpu; 896 if (cpu_online(cpu)) { 897 hlist_add_head(&apicd->clist, per_cpu_ptr(&cleanup_list, cpu)); 898 apic->send_IPI(cpu, IRQ_MOVE_CLEANUP_VECTOR); 899 } else { 900 apicd->prev_vector = 0; 901 } 902 raw_spin_unlock(&vector_lock); 903 } 904 905 void send_cleanup_vector(struct irq_cfg *cfg) 906 { 907 struct apic_chip_data *apicd; 908 909 apicd = container_of(cfg, struct apic_chip_data, hw_irq_cfg); 910 if (apicd->move_in_progress) 911 __send_cleanup_vector(apicd); 912 } 913 914 void irq_complete_move(struct irq_cfg *cfg) 915 { 916 struct apic_chip_data *apicd; 917 918 apicd = container_of(cfg, struct apic_chip_data, hw_irq_cfg); 919 if (likely(!apicd->move_in_progress)) 920 return; 921 922 /* 923 * If the interrupt arrived on the new target CPU, cleanup the 924 * vector on the old target CPU. A vector check is not required 925 * because an interrupt can never move from one vector to another 926 * on the same CPU. 927 */ 928 if (apicd->cpu == smp_processor_id()) 929 __send_cleanup_vector(apicd); 930 } 931 932 /* 933 * Called from fixup_irqs() with @desc->lock held and interrupts disabled. 934 */ 935 void irq_force_complete_move(struct irq_desc *desc) 936 { 937 struct apic_chip_data *apicd; 938 struct irq_data *irqd; 939 unsigned int vector; 940 941 /* 942 * The function is called for all descriptors regardless of which 943 * irqdomain they belong to. For example if an IRQ is provided by 944 * an irq_chip as part of a GPIO driver, the chip data for that 945 * descriptor is specific to the irq_chip in question. 946 * 947 * Check first that the chip_data is what we expect 948 * (apic_chip_data) before touching it any further. 949 */ 950 irqd = irq_domain_get_irq_data(x86_vector_domain, 951 irq_desc_get_irq(desc)); 952 if (!irqd) 953 return; 954 955 raw_spin_lock(&vector_lock); 956 apicd = apic_chip_data(irqd); 957 if (!apicd) 958 goto unlock; 959 960 /* 961 * If prev_vector is empty, no action required. 962 */ 963 vector = apicd->prev_vector; 964 if (!vector) 965 goto unlock; 966 967 /* 968 * This is tricky. If the cleanup of the old vector has not been 969 * done yet, then the following setaffinity call will fail with 970 * -EBUSY. This can leave the interrupt in a stale state. 971 * 972 * All CPUs are stuck in stop machine with interrupts disabled so 973 * calling __irq_complete_move() would be completely pointless. 974 * 975 * 1) The interrupt is in move_in_progress state. That means that we 976 * have not seen an interrupt since the io_apic was reprogrammed to 977 * the new vector. 978 * 979 * 2) The interrupt has fired on the new vector, but the cleanup IPIs 980 * have not been processed yet. 981 */ 982 if (apicd->move_in_progress) { 983 /* 984 * In theory there is a race: 985 * 986 * set_ioapic(new_vector) <-- Interrupt is raised before update 987 * is effective, i.e. it's raised on 988 * the old vector. 989 * 990 * So if the target cpu cannot handle that interrupt before 991 * the old vector is cleaned up, we get a spurious interrupt 992 * and in the worst case the ioapic irq line becomes stale. 993 * 994 * But in case of cpu hotplug this should be a non issue 995 * because if the affinity update happens right before all 996 * cpus rendevouz in stop machine, there is no way that the 997 * interrupt can be blocked on the target cpu because all cpus 998 * loops first with interrupts enabled in stop machine, so the 999 * old vector is not yet cleaned up when the interrupt fires. 1000 * 1001 * So the only way to run into this issue is if the delivery 1002 * of the interrupt on the apic/system bus would be delayed 1003 * beyond the point where the target cpu disables interrupts 1004 * in stop machine. I doubt that it can happen, but at least 1005 * there is a theroretical chance. Virtualization might be 1006 * able to expose this, but AFAICT the IOAPIC emulation is not 1007 * as stupid as the real hardware. 1008 * 1009 * Anyway, there is nothing we can do about that at this point 1010 * w/o refactoring the whole fixup_irq() business completely. 1011 * We print at least the irq number and the old vector number, 1012 * so we have the necessary information when a problem in that 1013 * area arises. 1014 */ 1015 pr_warn("IRQ fixup: irq %d move in progress, old vector %d\n", 1016 irqd->irq, vector); 1017 } 1018 free_moved_vector(apicd); 1019 unlock: 1020 raw_spin_unlock(&vector_lock); 1021 } 1022 1023 #ifdef CONFIG_HOTPLUG_CPU 1024 /* 1025 * Note, this is not accurate accounting, but at least good enough to 1026 * prevent that the actual interrupt move will run out of vectors. 1027 */ 1028 int lapic_can_unplug_cpu(void) 1029 { 1030 unsigned int rsvd, avl, tomove, cpu = smp_processor_id(); 1031 int ret = 0; 1032 1033 raw_spin_lock(&vector_lock); 1034 tomove = irq_matrix_allocated(vector_matrix); 1035 avl = irq_matrix_available(vector_matrix, true); 1036 if (avl < tomove) { 1037 pr_warn("CPU %u has %u vectors, %u available. Cannot disable CPU\n", 1038 cpu, tomove, avl); 1039 ret = -ENOSPC; 1040 goto out; 1041 } 1042 rsvd = irq_matrix_reserved(vector_matrix); 1043 if (avl < rsvd) { 1044 pr_warn("Reserved vectors %u > available %u. IRQ request may fail\n", 1045 rsvd, avl); 1046 } 1047 out: 1048 raw_spin_unlock(&vector_lock); 1049 return ret; 1050 } 1051 #endif /* HOTPLUG_CPU */ 1052 #endif /* SMP */ 1053 1054 static void __init print_APIC_field(int base) 1055 { 1056 int i; 1057 1058 printk(KERN_DEBUG); 1059 1060 for (i = 0; i < 8; i++) 1061 pr_cont("%08x", apic_read(base + i*0x10)); 1062 1063 pr_cont("\n"); 1064 } 1065 1066 static void __init print_local_APIC(void *dummy) 1067 { 1068 unsigned int i, v, ver, maxlvt; 1069 u64 icr; 1070 1071 pr_debug("printing local APIC contents on CPU#%d/%d:\n", 1072 smp_processor_id(), hard_smp_processor_id()); 1073 v = apic_read(APIC_ID); 1074 pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id()); 1075 v = apic_read(APIC_LVR); 1076 pr_info("... APIC VERSION: %08x\n", v); 1077 ver = GET_APIC_VERSION(v); 1078 maxlvt = lapic_get_maxlvt(); 1079 1080 v = apic_read(APIC_TASKPRI); 1081 pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); 1082 1083 /* !82489DX */ 1084 if (APIC_INTEGRATED(ver)) { 1085 if (!APIC_XAPIC(ver)) { 1086 v = apic_read(APIC_ARBPRI); 1087 pr_debug("... APIC ARBPRI: %08x (%02x)\n", 1088 v, v & APIC_ARBPRI_MASK); 1089 } 1090 v = apic_read(APIC_PROCPRI); 1091 pr_debug("... APIC PROCPRI: %08x\n", v); 1092 } 1093 1094 /* 1095 * Remote read supported only in the 82489DX and local APIC for 1096 * Pentium processors. 1097 */ 1098 if (!APIC_INTEGRATED(ver) || maxlvt == 3) { 1099 v = apic_read(APIC_RRR); 1100 pr_debug("... APIC RRR: %08x\n", v); 1101 } 1102 1103 v = apic_read(APIC_LDR); 1104 pr_debug("... APIC LDR: %08x\n", v); 1105 if (!x2apic_enabled()) { 1106 v = apic_read(APIC_DFR); 1107 pr_debug("... APIC DFR: %08x\n", v); 1108 } 1109 v = apic_read(APIC_SPIV); 1110 pr_debug("... APIC SPIV: %08x\n", v); 1111 1112 pr_debug("... APIC ISR field:\n"); 1113 print_APIC_field(APIC_ISR); 1114 pr_debug("... APIC TMR field:\n"); 1115 print_APIC_field(APIC_TMR); 1116 pr_debug("... APIC IRR field:\n"); 1117 print_APIC_field(APIC_IRR); 1118 1119 /* !82489DX */ 1120 if (APIC_INTEGRATED(ver)) { 1121 /* Due to the Pentium erratum 3AP. */ 1122 if (maxlvt > 3) 1123 apic_write(APIC_ESR, 0); 1124 1125 v = apic_read(APIC_ESR); 1126 pr_debug("... APIC ESR: %08x\n", v); 1127 } 1128 1129 icr = apic_icr_read(); 1130 pr_debug("... APIC ICR: %08x\n", (u32)icr); 1131 pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32)); 1132 1133 v = apic_read(APIC_LVTT); 1134 pr_debug("... APIC LVTT: %08x\n", v); 1135 1136 if (maxlvt > 3) { 1137 /* PC is LVT#4. */ 1138 v = apic_read(APIC_LVTPC); 1139 pr_debug("... APIC LVTPC: %08x\n", v); 1140 } 1141 v = apic_read(APIC_LVT0); 1142 pr_debug("... APIC LVT0: %08x\n", v); 1143 v = apic_read(APIC_LVT1); 1144 pr_debug("... APIC LVT1: %08x\n", v); 1145 1146 if (maxlvt > 2) { 1147 /* ERR is LVT#3. */ 1148 v = apic_read(APIC_LVTERR); 1149 pr_debug("... APIC LVTERR: %08x\n", v); 1150 } 1151 1152 v = apic_read(APIC_TMICT); 1153 pr_debug("... APIC TMICT: %08x\n", v); 1154 v = apic_read(APIC_TMCCT); 1155 pr_debug("... APIC TMCCT: %08x\n", v); 1156 v = apic_read(APIC_TDCR); 1157 pr_debug("... APIC TDCR: %08x\n", v); 1158 1159 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { 1160 v = apic_read(APIC_EFEAT); 1161 maxlvt = (v >> 16) & 0xff; 1162 pr_debug("... APIC EFEAT: %08x\n", v); 1163 v = apic_read(APIC_ECTRL); 1164 pr_debug("... APIC ECTRL: %08x\n", v); 1165 for (i = 0; i < maxlvt; i++) { 1166 v = apic_read(APIC_EILVTn(i)); 1167 pr_debug("... APIC EILVT%d: %08x\n", i, v); 1168 } 1169 } 1170 pr_cont("\n"); 1171 } 1172 1173 static void __init print_local_APICs(int maxcpu) 1174 { 1175 int cpu; 1176 1177 if (!maxcpu) 1178 return; 1179 1180 preempt_disable(); 1181 for_each_online_cpu(cpu) { 1182 if (cpu >= maxcpu) 1183 break; 1184 smp_call_function_single(cpu, print_local_APIC, NULL, 1); 1185 } 1186 preempt_enable(); 1187 } 1188 1189 static void __init print_PIC(void) 1190 { 1191 unsigned int v; 1192 unsigned long flags; 1193 1194 if (!nr_legacy_irqs()) 1195 return; 1196 1197 pr_debug("\nprinting PIC contents\n"); 1198 1199 raw_spin_lock_irqsave(&i8259A_lock, flags); 1200 1201 v = inb(0xa1) << 8 | inb(0x21); 1202 pr_debug("... PIC IMR: %04x\n", v); 1203 1204 v = inb(0xa0) << 8 | inb(0x20); 1205 pr_debug("... PIC IRR: %04x\n", v); 1206 1207 outb(0x0b, 0xa0); 1208 outb(0x0b, 0x20); 1209 v = inb(0xa0) << 8 | inb(0x20); 1210 outb(0x0a, 0xa0); 1211 outb(0x0a, 0x20); 1212 1213 raw_spin_unlock_irqrestore(&i8259A_lock, flags); 1214 1215 pr_debug("... PIC ISR: %04x\n", v); 1216 1217 v = inb(0x4d1) << 8 | inb(0x4d0); 1218 pr_debug("... PIC ELCR: %04x\n", v); 1219 } 1220 1221 static int show_lapic __initdata = 1; 1222 static __init int setup_show_lapic(char *arg) 1223 { 1224 int num = -1; 1225 1226 if (strcmp(arg, "all") == 0) { 1227 show_lapic = CONFIG_NR_CPUS; 1228 } else { 1229 get_option(&arg, &num); 1230 if (num >= 0) 1231 show_lapic = num; 1232 } 1233 1234 return 1; 1235 } 1236 __setup("show_lapic=", setup_show_lapic); 1237 1238 static int __init print_ICs(void) 1239 { 1240 if (apic_verbosity == APIC_QUIET) 1241 return 0; 1242 1243 print_PIC(); 1244 1245 /* don't print out if apic is not there */ 1246 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) 1247 return 0; 1248 1249 print_local_APICs(show_lapic); 1250 print_IO_APICs(); 1251 1252 return 0; 1253 } 1254 1255 late_initcall(print_ICs); 1256