xref: /openbmc/linux/arch/x86/kernel/apic/msi.c (revision dea54fba) 
1 /*
2  * Support of MSI, HPET and DMAR interrupts.
3  *
4  * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
5  *	Moved from arch/x86/kernel/apic/io_apic.c.
6  * Jiang Liu <jiang.liu@linux.intel.com>
7  *	Convert to hierarchical irqdomain
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of the GNU General Public License version 2 as
11  * published by the Free Software Foundation.
12  */
13 #include <linux/mm.h>
14 #include <linux/interrupt.h>
15 #include <linux/pci.h>
16 #include <linux/dmar.h>
17 #include <linux/hpet.h>
18 #include <linux/msi.h>
19 #include <asm/irqdomain.h>
20 #include <asm/msidef.h>
21 #include <asm/hpet.h>
22 #include <asm/hw_irq.h>
23 #include <asm/apic.h>
24 #include <asm/irq_remapping.h>
25 
26 static struct irq_domain *msi_default_domain;
27 
28 static void irq_msi_compose_msg(struct irq_data *data, struct msi_msg *msg)
29 {
30 	struct irq_cfg *cfg = irqd_cfg(data);
31 
32 	msg->address_hi = MSI_ADDR_BASE_HI;
33 
34 	if (x2apic_enabled())
35 		msg->address_hi |= MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid);
36 
37 	msg->address_lo =
38 		MSI_ADDR_BASE_LO |
39 		((apic->irq_dest_mode == 0) ?
40 			MSI_ADDR_DEST_MODE_PHYSICAL :
41 			MSI_ADDR_DEST_MODE_LOGICAL) |
42 		((apic->irq_delivery_mode != dest_LowestPrio) ?
43 			MSI_ADDR_REDIRECTION_CPU :
44 			MSI_ADDR_REDIRECTION_LOWPRI) |
45 		MSI_ADDR_DEST_ID(cfg->dest_apicid);
46 
47 	msg->data =
48 		MSI_DATA_TRIGGER_EDGE |
49 		MSI_DATA_LEVEL_ASSERT |
50 		((apic->irq_delivery_mode != dest_LowestPrio) ?
51 			MSI_DATA_DELIVERY_FIXED :
52 			MSI_DATA_DELIVERY_LOWPRI) |
53 		MSI_DATA_VECTOR(cfg->vector);
54 }
55 
56 /*
57  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
58  * which implement the MSI or MSI-X Capability Structure.
59  */
60 static struct irq_chip pci_msi_controller = {
61 	.name			= "PCI-MSI",
62 	.irq_unmask		= pci_msi_unmask_irq,
63 	.irq_mask		= pci_msi_mask_irq,
64 	.irq_ack		= irq_chip_ack_parent,
65 	.irq_retrigger		= irq_chip_retrigger_hierarchy,
66 	.irq_compose_msi_msg	= irq_msi_compose_msg,
67 	.flags			= IRQCHIP_SKIP_SET_WAKE,
68 };
69 
70 int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
71 {
72 	struct irq_domain *domain;
73 	struct irq_alloc_info info;
74 
75 	init_irq_alloc_info(&info, NULL);
76 	info.type = X86_IRQ_ALLOC_TYPE_MSI;
77 	info.msi_dev = dev;
78 
79 	domain = irq_remapping_get_irq_domain(&info);
80 	if (domain == NULL)
81 		domain = msi_default_domain;
82 	if (domain == NULL)
83 		return -ENOSYS;
84 
85 	return msi_domain_alloc_irqs(domain, &dev->dev, nvec);
86 }
87 
88 void native_teardown_msi_irq(unsigned int irq)
89 {
90 	irq_domain_free_irqs(irq, 1);
91 }
92 
93 static irq_hw_number_t pci_msi_get_hwirq(struct msi_domain_info *info,
94 					 msi_alloc_info_t *arg)
95 {
96 	return arg->msi_hwirq;
97 }
98 
99 int pci_msi_prepare(struct irq_domain *domain, struct device *dev, int nvec,
100 		    msi_alloc_info_t *arg)
101 {
102 	struct pci_dev *pdev = to_pci_dev(dev);
103 	struct msi_desc *desc = first_pci_msi_entry(pdev);
104 
105 	init_irq_alloc_info(arg, NULL);
106 	arg->msi_dev = pdev;
107 	if (desc->msi_attrib.is_msix) {
108 		arg->type = X86_IRQ_ALLOC_TYPE_MSIX;
109 	} else {
110 		arg->type = X86_IRQ_ALLOC_TYPE_MSI;
111 		arg->flags |= X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
112 	}
113 
114 	return 0;
115 }
116 EXPORT_SYMBOL_GPL(pci_msi_prepare);
117 
118 void pci_msi_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc)
119 {
120 	arg->msi_hwirq = pci_msi_domain_calc_hwirq(arg->msi_dev, desc);
121 }
122 EXPORT_SYMBOL_GPL(pci_msi_set_desc);
123 
124 static struct msi_domain_ops pci_msi_domain_ops = {
125 	.get_hwirq	= pci_msi_get_hwirq,
126 	.msi_prepare	= pci_msi_prepare,
127 	.set_desc	= pci_msi_set_desc,
128 };
129 
130 static struct msi_domain_info pci_msi_domain_info = {
131 	.flags		= MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
132 			  MSI_FLAG_PCI_MSIX,
133 	.ops		= &pci_msi_domain_ops,
134 	.chip		= &pci_msi_controller,
135 	.handler	= handle_edge_irq,
136 	.handler_name	= "edge",
137 };
138 
139 void __init arch_init_msi_domain(struct irq_domain *parent)
140 {
141 	struct fwnode_handle *fn;
142 
143 	if (disable_apic)
144 		return;
145 
146 	fn = irq_domain_alloc_named_fwnode("PCI-MSI");
147 	if (fn) {
148 		msi_default_domain =
149 			pci_msi_create_irq_domain(fn, &pci_msi_domain_info,
150 						  parent);
151 		irq_domain_free_fwnode(fn);
152 	}
153 	if (!msi_default_domain)
154 		pr_warn("failed to initialize irqdomain for MSI/MSI-x.\n");
155 }
156 
157 #ifdef CONFIG_IRQ_REMAP
158 static struct irq_chip pci_msi_ir_controller = {
159 	.name			= "IR-PCI-MSI",
160 	.irq_unmask		= pci_msi_unmask_irq,
161 	.irq_mask		= pci_msi_mask_irq,
162 	.irq_ack		= irq_chip_ack_parent,
163 	.irq_retrigger		= irq_chip_retrigger_hierarchy,
164 	.irq_set_vcpu_affinity	= irq_chip_set_vcpu_affinity_parent,
165 	.flags			= IRQCHIP_SKIP_SET_WAKE,
166 };
167 
168 static struct msi_domain_info pci_msi_ir_domain_info = {
169 	.flags		= MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
170 			  MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX,
171 	.ops		= &pci_msi_domain_ops,
172 	.chip		= &pci_msi_ir_controller,
173 	.handler	= handle_edge_irq,
174 	.handler_name	= "edge",
175 };
176 
177 struct irq_domain *arch_create_remap_msi_irq_domain(struct irq_domain *parent,
178 						    const char *name, int id)
179 {
180 	struct fwnode_handle *fn;
181 	struct irq_domain *d;
182 
183 	fn = irq_domain_alloc_named_id_fwnode(name, id);
184 	if (!fn)
185 		return NULL;
186 	d = pci_msi_create_irq_domain(fn, &pci_msi_ir_domain_info, parent);
187 	irq_domain_free_fwnode(fn);
188 	return d;
189 }
190 #endif
191 
192 #ifdef CONFIG_DMAR_TABLE
193 static void dmar_msi_write_msg(struct irq_data *data, struct msi_msg *msg)
194 {
195 	dmar_msi_write(data->irq, msg);
196 }
197 
198 static struct irq_chip dmar_msi_controller = {
199 	.name			= "DMAR-MSI",
200 	.irq_unmask		= dmar_msi_unmask,
201 	.irq_mask		= dmar_msi_mask,
202 	.irq_ack		= irq_chip_ack_parent,
203 	.irq_set_affinity	= msi_domain_set_affinity,
204 	.irq_retrigger		= irq_chip_retrigger_hierarchy,
205 	.irq_compose_msi_msg	= irq_msi_compose_msg,
206 	.irq_write_msi_msg	= dmar_msi_write_msg,
207 	.flags			= IRQCHIP_SKIP_SET_WAKE,
208 };
209 
210 static irq_hw_number_t dmar_msi_get_hwirq(struct msi_domain_info *info,
211 					  msi_alloc_info_t *arg)
212 {
213 	return arg->dmar_id;
214 }
215 
216 static int dmar_msi_init(struct irq_domain *domain,
217 			 struct msi_domain_info *info, unsigned int virq,
218 			 irq_hw_number_t hwirq, msi_alloc_info_t *arg)
219 {
220 	irq_domain_set_info(domain, virq, arg->dmar_id, info->chip, NULL,
221 			    handle_edge_irq, arg->dmar_data, "edge");
222 
223 	return 0;
224 }
225 
226 static struct msi_domain_ops dmar_msi_domain_ops = {
227 	.get_hwirq	= dmar_msi_get_hwirq,
228 	.msi_init	= dmar_msi_init,
229 };
230 
231 static struct msi_domain_info dmar_msi_domain_info = {
232 	.ops		= &dmar_msi_domain_ops,
233 	.chip		= &dmar_msi_controller,
234 };
235 
236 static struct irq_domain *dmar_get_irq_domain(void)
237 {
238 	static struct irq_domain *dmar_domain;
239 	static DEFINE_MUTEX(dmar_lock);
240 	struct fwnode_handle *fn;
241 
242 	mutex_lock(&dmar_lock);
243 	if (dmar_domain)
244 		goto out;
245 
246 	fn = irq_domain_alloc_named_fwnode("DMAR-MSI");
247 	if (fn) {
248 		dmar_domain = msi_create_irq_domain(fn, &dmar_msi_domain_info,
249 						    x86_vector_domain);
250 		irq_domain_free_fwnode(fn);
251 	}
252 out:
253 	mutex_unlock(&dmar_lock);
254 	return dmar_domain;
255 }
256 
257 int dmar_alloc_hwirq(int id, int node, void *arg)
258 {
259 	struct irq_domain *domain = dmar_get_irq_domain();
260 	struct irq_alloc_info info;
261 
262 	if (!domain)
263 		return -1;
264 
265 	init_irq_alloc_info(&info, NULL);
266 	info.type = X86_IRQ_ALLOC_TYPE_DMAR;
267 	info.dmar_id = id;
268 	info.dmar_data = arg;
269 
270 	return irq_domain_alloc_irqs(domain, 1, node, &info);
271 }
272 
273 void dmar_free_hwirq(int irq)
274 {
275 	irq_domain_free_irqs(irq, 1);
276 }
277 #endif
278 
279 /*
280  * MSI message composition
281  */
282 #ifdef CONFIG_HPET_TIMER
283 static inline int hpet_dev_id(struct irq_domain *domain)
284 {
285 	struct msi_domain_info *info = msi_get_domain_info(domain);
286 
287 	return (int)(long)info->data;
288 }
289 
290 static void hpet_msi_write_msg(struct irq_data *data, struct msi_msg *msg)
291 {
292 	hpet_msi_write(irq_data_get_irq_handler_data(data), msg);
293 }
294 
295 static struct irq_chip hpet_msi_controller __ro_after_init = {
296 	.name = "HPET-MSI",
297 	.irq_unmask = hpet_msi_unmask,
298 	.irq_mask = hpet_msi_mask,
299 	.irq_ack = irq_chip_ack_parent,
300 	.irq_set_affinity = msi_domain_set_affinity,
301 	.irq_retrigger = irq_chip_retrigger_hierarchy,
302 	.irq_compose_msi_msg = irq_msi_compose_msg,
303 	.irq_write_msi_msg = hpet_msi_write_msg,
304 	.flags = IRQCHIP_SKIP_SET_WAKE,
305 };
306 
307 static irq_hw_number_t hpet_msi_get_hwirq(struct msi_domain_info *info,
308 					  msi_alloc_info_t *arg)
309 {
310 	return arg->hpet_index;
311 }
312 
313 static int hpet_msi_init(struct irq_domain *domain,
314 			 struct msi_domain_info *info, unsigned int virq,
315 			 irq_hw_number_t hwirq, msi_alloc_info_t *arg)
316 {
317 	irq_set_status_flags(virq, IRQ_MOVE_PCNTXT);
318 	irq_domain_set_info(domain, virq, arg->hpet_index, info->chip, NULL,
319 			    handle_edge_irq, arg->hpet_data, "edge");
320 
321 	return 0;
322 }
323 
324 static void hpet_msi_free(struct irq_domain *domain,
325 			  struct msi_domain_info *info, unsigned int virq)
326 {
327 	irq_clear_status_flags(virq, IRQ_MOVE_PCNTXT);
328 }
329 
330 static struct msi_domain_ops hpet_msi_domain_ops = {
331 	.get_hwirq	= hpet_msi_get_hwirq,
332 	.msi_init	= hpet_msi_init,
333 	.msi_free	= hpet_msi_free,
334 };
335 
336 static struct msi_domain_info hpet_msi_domain_info = {
337 	.ops		= &hpet_msi_domain_ops,
338 	.chip		= &hpet_msi_controller,
339 };
340 
341 struct irq_domain *hpet_create_irq_domain(int hpet_id)
342 {
343 	struct msi_domain_info *domain_info;
344 	struct irq_domain *parent, *d;
345 	struct irq_alloc_info info;
346 	struct fwnode_handle *fn;
347 
348 	if (x86_vector_domain == NULL)
349 		return NULL;
350 
351 	domain_info = kzalloc(sizeof(*domain_info), GFP_KERNEL);
352 	if (!domain_info)
353 		return NULL;
354 
355 	*domain_info = hpet_msi_domain_info;
356 	domain_info->data = (void *)(long)hpet_id;
357 
358 	init_irq_alloc_info(&info, NULL);
359 	info.type = X86_IRQ_ALLOC_TYPE_HPET;
360 	info.hpet_id = hpet_id;
361 	parent = irq_remapping_get_ir_irq_domain(&info);
362 	if (parent == NULL)
363 		parent = x86_vector_domain;
364 	else
365 		hpet_msi_controller.name = "IR-HPET-MSI";
366 
367 	fn = irq_domain_alloc_named_id_fwnode(hpet_msi_controller.name,
368 					      hpet_id);
369 	if (!fn) {
370 		kfree(domain_info);
371 		return NULL;
372 	}
373 
374 	d = msi_create_irq_domain(fn, domain_info, parent);
375 	irq_domain_free_fwnode(fn);
376 	return d;
377 }
378 
379 int hpet_assign_irq(struct irq_domain *domain, struct hpet_dev *dev,
380 		    int dev_num)
381 {
382 	struct irq_alloc_info info;
383 
384 	init_irq_alloc_info(&info, NULL);
385 	info.type = X86_IRQ_ALLOC_TYPE_HPET;
386 	info.hpet_data = dev;
387 	info.hpet_id = hpet_dev_id(domain);
388 	info.hpet_index = dev_num;
389 
390 	return irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, &info);
391 }
392 #endif
393