1 /* 2 * Support of MSI, HPET and DMAR interrupts. 3 * 4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo 5 * Moved from arch/x86/kernel/apic/io_apic.c. 6 * Jiang Liu <jiang.liu@linux.intel.com> 7 * Convert to hierarchical irqdomain 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 #include <linux/mm.h> 14 #include <linux/interrupt.h> 15 #include <linux/irq.h> 16 #include <linux/pci.h> 17 #include <linux/dmar.h> 18 #include <linux/hpet.h> 19 #include <linux/msi.h> 20 #include <asm/irqdomain.h> 21 #include <asm/msidef.h> 22 #include <asm/hpet.h> 23 #include <asm/hw_irq.h> 24 #include <asm/apic.h> 25 #include <asm/irq_remapping.h> 26 27 static struct irq_domain *msi_default_domain; 28 29 static void irq_msi_compose_msg(struct irq_data *data, struct msi_msg *msg) 30 { 31 struct irq_cfg *cfg = irqd_cfg(data); 32 33 msg->address_hi = MSI_ADDR_BASE_HI; 34 35 if (x2apic_enabled()) 36 msg->address_hi |= MSI_ADDR_EXT_DEST_ID(cfg->dest_apicid); 37 38 msg->address_lo = 39 MSI_ADDR_BASE_LO | 40 ((apic->irq_dest_mode == 0) ? 41 MSI_ADDR_DEST_MODE_PHYSICAL : 42 MSI_ADDR_DEST_MODE_LOGICAL) | 43 MSI_ADDR_REDIRECTION_CPU | 44 MSI_ADDR_DEST_ID(cfg->dest_apicid); 45 46 msg->data = 47 MSI_DATA_TRIGGER_EDGE | 48 MSI_DATA_LEVEL_ASSERT | 49 MSI_DATA_DELIVERY_FIXED | 50 MSI_DATA_VECTOR(cfg->vector); 51 } 52 53 /* 54 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, 55 * which implement the MSI or MSI-X Capability Structure. 56 */ 57 static struct irq_chip pci_msi_controller = { 58 .name = "PCI-MSI", 59 .irq_unmask = pci_msi_unmask_irq, 60 .irq_mask = pci_msi_mask_irq, 61 .irq_ack = irq_chip_ack_parent, 62 .irq_retrigger = irq_chip_retrigger_hierarchy, 63 .irq_compose_msi_msg = irq_msi_compose_msg, 64 .flags = IRQCHIP_SKIP_SET_WAKE, 65 }; 66 67 int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) 68 { 69 struct irq_domain *domain; 70 struct irq_alloc_info info; 71 72 init_irq_alloc_info(&info, NULL); 73 info.type = X86_IRQ_ALLOC_TYPE_MSI; 74 info.msi_dev = dev; 75 76 domain = irq_remapping_get_irq_domain(&info); 77 if (domain == NULL) 78 domain = msi_default_domain; 79 if (domain == NULL) 80 return -ENOSYS; 81 82 return msi_domain_alloc_irqs(domain, &dev->dev, nvec); 83 } 84 85 void native_teardown_msi_irq(unsigned int irq) 86 { 87 irq_domain_free_irqs(irq, 1); 88 } 89 90 static irq_hw_number_t pci_msi_get_hwirq(struct msi_domain_info *info, 91 msi_alloc_info_t *arg) 92 { 93 return arg->msi_hwirq; 94 } 95 96 int pci_msi_prepare(struct irq_domain *domain, struct device *dev, int nvec, 97 msi_alloc_info_t *arg) 98 { 99 struct pci_dev *pdev = to_pci_dev(dev); 100 struct msi_desc *desc = first_pci_msi_entry(pdev); 101 102 init_irq_alloc_info(arg, NULL); 103 arg->msi_dev = pdev; 104 if (desc->msi_attrib.is_msix) { 105 arg->type = X86_IRQ_ALLOC_TYPE_MSIX; 106 } else { 107 arg->type = X86_IRQ_ALLOC_TYPE_MSI; 108 arg->flags |= X86_IRQ_ALLOC_CONTIGUOUS_VECTORS; 109 } 110 111 return 0; 112 } 113 EXPORT_SYMBOL_GPL(pci_msi_prepare); 114 115 void pci_msi_set_desc(msi_alloc_info_t *arg, struct msi_desc *desc) 116 { 117 arg->msi_hwirq = pci_msi_domain_calc_hwirq(arg->msi_dev, desc); 118 } 119 EXPORT_SYMBOL_GPL(pci_msi_set_desc); 120 121 static struct msi_domain_ops pci_msi_domain_ops = { 122 .get_hwirq = pci_msi_get_hwirq, 123 .msi_prepare = pci_msi_prepare, 124 .set_desc = pci_msi_set_desc, 125 }; 126 127 static struct msi_domain_info pci_msi_domain_info = { 128 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 129 MSI_FLAG_PCI_MSIX, 130 .ops = &pci_msi_domain_ops, 131 .chip = &pci_msi_controller, 132 .handler = handle_edge_irq, 133 .handler_name = "edge", 134 }; 135 136 void __init arch_init_msi_domain(struct irq_domain *parent) 137 { 138 struct fwnode_handle *fn; 139 140 if (disable_apic) 141 return; 142 143 fn = irq_domain_alloc_named_fwnode("PCI-MSI"); 144 if (fn) { 145 msi_default_domain = 146 pci_msi_create_irq_domain(fn, &pci_msi_domain_info, 147 parent); 148 irq_domain_free_fwnode(fn); 149 } 150 if (!msi_default_domain) 151 pr_warn("failed to initialize irqdomain for MSI/MSI-x.\n"); 152 } 153 154 #ifdef CONFIG_IRQ_REMAP 155 static struct irq_chip pci_msi_ir_controller = { 156 .name = "IR-PCI-MSI", 157 .irq_unmask = pci_msi_unmask_irq, 158 .irq_mask = pci_msi_mask_irq, 159 .irq_ack = irq_chip_ack_parent, 160 .irq_retrigger = irq_chip_retrigger_hierarchy, 161 .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent, 162 .flags = IRQCHIP_SKIP_SET_WAKE, 163 }; 164 165 static struct msi_domain_info pci_msi_ir_domain_info = { 166 .flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | 167 MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX, 168 .ops = &pci_msi_domain_ops, 169 .chip = &pci_msi_ir_controller, 170 .handler = handle_edge_irq, 171 .handler_name = "edge", 172 }; 173 174 struct irq_domain *arch_create_remap_msi_irq_domain(struct irq_domain *parent, 175 const char *name, int id) 176 { 177 struct fwnode_handle *fn; 178 struct irq_domain *d; 179 180 fn = irq_domain_alloc_named_id_fwnode(name, id); 181 if (!fn) 182 return NULL; 183 d = pci_msi_create_irq_domain(fn, &pci_msi_ir_domain_info, parent); 184 irq_domain_free_fwnode(fn); 185 return d; 186 } 187 #endif 188 189 #ifdef CONFIG_DMAR_TABLE 190 static void dmar_msi_write_msg(struct irq_data *data, struct msi_msg *msg) 191 { 192 dmar_msi_write(data->irq, msg); 193 } 194 195 static struct irq_chip dmar_msi_controller = { 196 .name = "DMAR-MSI", 197 .irq_unmask = dmar_msi_unmask, 198 .irq_mask = dmar_msi_mask, 199 .irq_ack = irq_chip_ack_parent, 200 .irq_set_affinity = msi_domain_set_affinity, 201 .irq_retrigger = irq_chip_retrigger_hierarchy, 202 .irq_compose_msi_msg = irq_msi_compose_msg, 203 .irq_write_msi_msg = dmar_msi_write_msg, 204 .flags = IRQCHIP_SKIP_SET_WAKE, 205 }; 206 207 static irq_hw_number_t dmar_msi_get_hwirq(struct msi_domain_info *info, 208 msi_alloc_info_t *arg) 209 { 210 return arg->dmar_id; 211 } 212 213 static int dmar_msi_init(struct irq_domain *domain, 214 struct msi_domain_info *info, unsigned int virq, 215 irq_hw_number_t hwirq, msi_alloc_info_t *arg) 216 { 217 irq_domain_set_info(domain, virq, arg->dmar_id, info->chip, NULL, 218 handle_edge_irq, arg->dmar_data, "edge"); 219 220 return 0; 221 } 222 223 static struct msi_domain_ops dmar_msi_domain_ops = { 224 .get_hwirq = dmar_msi_get_hwirq, 225 .msi_init = dmar_msi_init, 226 }; 227 228 static struct msi_domain_info dmar_msi_domain_info = { 229 .ops = &dmar_msi_domain_ops, 230 .chip = &dmar_msi_controller, 231 }; 232 233 static struct irq_domain *dmar_get_irq_domain(void) 234 { 235 static struct irq_domain *dmar_domain; 236 static DEFINE_MUTEX(dmar_lock); 237 struct fwnode_handle *fn; 238 239 mutex_lock(&dmar_lock); 240 if (dmar_domain) 241 goto out; 242 243 fn = irq_domain_alloc_named_fwnode("DMAR-MSI"); 244 if (fn) { 245 dmar_domain = msi_create_irq_domain(fn, &dmar_msi_domain_info, 246 x86_vector_domain); 247 irq_domain_free_fwnode(fn); 248 } 249 out: 250 mutex_unlock(&dmar_lock); 251 return dmar_domain; 252 } 253 254 int dmar_alloc_hwirq(int id, int node, void *arg) 255 { 256 struct irq_domain *domain = dmar_get_irq_domain(); 257 struct irq_alloc_info info; 258 259 if (!domain) 260 return -1; 261 262 init_irq_alloc_info(&info, NULL); 263 info.type = X86_IRQ_ALLOC_TYPE_DMAR; 264 info.dmar_id = id; 265 info.dmar_data = arg; 266 267 return irq_domain_alloc_irqs(domain, 1, node, &info); 268 } 269 270 void dmar_free_hwirq(int irq) 271 { 272 irq_domain_free_irqs(irq, 1); 273 } 274 #endif 275 276 /* 277 * MSI message composition 278 */ 279 #ifdef CONFIG_HPET_TIMER 280 static inline int hpet_dev_id(struct irq_domain *domain) 281 { 282 struct msi_domain_info *info = msi_get_domain_info(domain); 283 284 return (int)(long)info->data; 285 } 286 287 static void hpet_msi_write_msg(struct irq_data *data, struct msi_msg *msg) 288 { 289 hpet_msi_write(irq_data_get_irq_handler_data(data), msg); 290 } 291 292 static struct irq_chip hpet_msi_controller __ro_after_init = { 293 .name = "HPET-MSI", 294 .irq_unmask = hpet_msi_unmask, 295 .irq_mask = hpet_msi_mask, 296 .irq_ack = irq_chip_ack_parent, 297 .irq_set_affinity = msi_domain_set_affinity, 298 .irq_retrigger = irq_chip_retrigger_hierarchy, 299 .irq_compose_msi_msg = irq_msi_compose_msg, 300 .irq_write_msi_msg = hpet_msi_write_msg, 301 .flags = IRQCHIP_SKIP_SET_WAKE, 302 }; 303 304 static irq_hw_number_t hpet_msi_get_hwirq(struct msi_domain_info *info, 305 msi_alloc_info_t *arg) 306 { 307 return arg->hpet_index; 308 } 309 310 static int hpet_msi_init(struct irq_domain *domain, 311 struct msi_domain_info *info, unsigned int virq, 312 irq_hw_number_t hwirq, msi_alloc_info_t *arg) 313 { 314 irq_set_status_flags(virq, IRQ_MOVE_PCNTXT); 315 irq_domain_set_info(domain, virq, arg->hpet_index, info->chip, NULL, 316 handle_edge_irq, arg->hpet_data, "edge"); 317 318 return 0; 319 } 320 321 static void hpet_msi_free(struct irq_domain *domain, 322 struct msi_domain_info *info, unsigned int virq) 323 { 324 irq_clear_status_flags(virq, IRQ_MOVE_PCNTXT); 325 } 326 327 static struct msi_domain_ops hpet_msi_domain_ops = { 328 .get_hwirq = hpet_msi_get_hwirq, 329 .msi_init = hpet_msi_init, 330 .msi_free = hpet_msi_free, 331 }; 332 333 static struct msi_domain_info hpet_msi_domain_info = { 334 .ops = &hpet_msi_domain_ops, 335 .chip = &hpet_msi_controller, 336 }; 337 338 struct irq_domain *hpet_create_irq_domain(int hpet_id) 339 { 340 struct msi_domain_info *domain_info; 341 struct irq_domain *parent, *d; 342 struct irq_alloc_info info; 343 struct fwnode_handle *fn; 344 345 if (x86_vector_domain == NULL) 346 return NULL; 347 348 domain_info = kzalloc(sizeof(*domain_info), GFP_KERNEL); 349 if (!domain_info) 350 return NULL; 351 352 *domain_info = hpet_msi_domain_info; 353 domain_info->data = (void *)(long)hpet_id; 354 355 init_irq_alloc_info(&info, NULL); 356 info.type = X86_IRQ_ALLOC_TYPE_HPET; 357 info.hpet_id = hpet_id; 358 parent = irq_remapping_get_ir_irq_domain(&info); 359 if (parent == NULL) 360 parent = x86_vector_domain; 361 else 362 hpet_msi_controller.name = "IR-HPET-MSI"; 363 364 fn = irq_domain_alloc_named_id_fwnode(hpet_msi_controller.name, 365 hpet_id); 366 if (!fn) { 367 kfree(domain_info); 368 return NULL; 369 } 370 371 d = msi_create_irq_domain(fn, domain_info, parent); 372 irq_domain_free_fwnode(fn); 373 return d; 374 } 375 376 int hpet_assign_irq(struct irq_domain *domain, struct hpet_dev *dev, 377 int dev_num) 378 { 379 struct irq_alloc_info info; 380 381 init_irq_alloc_info(&info, NULL); 382 info.type = X86_IRQ_ALLOC_TYPE_HPET; 383 info.hpet_data = dev; 384 info.hpet_id = hpet_dev_id(domain); 385 info.hpet_index = dev_num; 386 387 return irq_domain_alloc_irqs(domain, 1, NUMA_NO_NODE, &info); 388 } 389 #endif 390