1 /* 2 * Intel IO-APIC support for multi-Pentium hosts. 3 * 4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo 5 * 6 * Many thanks to Stig Venaas for trying out countless experimental 7 * patches and reporting/debugging problems patiently! 8 * 9 * (c) 1999, Multiple IO-APIC support, developed by 10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and 11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, 12 * further tested and cleaned up by Zach Brown <zab@redhat.com> 13 * and Ingo Molnar <mingo@redhat.com> 14 * 15 * Fixes 16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 17 * thanks to Eric Gilmore 18 * and Rolf G. Tews 19 * for testing these extensively 20 * Paul Diefenbaugh : Added full ACPI support 21 */ 22 23 #include <linux/mm.h> 24 #include <linux/interrupt.h> 25 #include <linux/init.h> 26 #include <linux/delay.h> 27 #include <linux/sched.h> 28 #include <linux/pci.h> 29 #include <linux/mc146818rtc.h> 30 #include <linux/compiler.h> 31 #include <linux/acpi.h> 32 #include <linux/module.h> 33 #include <linux/syscore_ops.h> 34 #include <linux/msi.h> 35 #include <linux/htirq.h> 36 #include <linux/freezer.h> 37 #include <linux/kthread.h> 38 #include <linux/jiffies.h> /* time_after() */ 39 #include <linux/slab.h> 40 #ifdef CONFIG_ACPI 41 #include <acpi/acpi_bus.h> 42 #endif 43 #include <linux/bootmem.h> 44 #include <linux/dmar.h> 45 #include <linux/hpet.h> 46 47 #include <asm/idle.h> 48 #include <asm/io.h> 49 #include <asm/smp.h> 50 #include <asm/cpu.h> 51 #include <asm/desc.h> 52 #include <asm/proto.h> 53 #include <asm/acpi.h> 54 #include <asm/dma.h> 55 #include <asm/timer.h> 56 #include <asm/i8259.h> 57 #include <asm/msidef.h> 58 #include <asm/hypertransport.h> 59 #include <asm/setup.h> 60 #include <asm/irq_remapping.h> 61 #include <asm/hpet.h> 62 #include <asm/hw_irq.h> 63 64 #include <asm/apic.h> 65 66 #define __apicdebuginit(type) static type __init 67 #define for_each_irq_pin(entry, head) \ 68 for (entry = head; entry; entry = entry->next) 69 70 /* 71 * Is the SiS APIC rmw bug present ? 72 * -1 = don't know, 0 = no, 1 = yes 73 */ 74 int sis_apic_bug = -1; 75 76 static DEFINE_RAW_SPINLOCK(ioapic_lock); 77 static DEFINE_RAW_SPINLOCK(vector_lock); 78 79 static struct ioapic { 80 /* 81 * # of IRQ routing registers 82 */ 83 int nr_registers; 84 /* 85 * Saved state during suspend/resume, or while enabling intr-remap. 86 */ 87 struct IO_APIC_route_entry *saved_registers; 88 /* I/O APIC config */ 89 struct mpc_ioapic mp_config; 90 /* IO APIC gsi routing info */ 91 struct mp_ioapic_gsi gsi_config; 92 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1); 93 } ioapics[MAX_IO_APICS]; 94 95 #define mpc_ioapic_ver(id) ioapics[id].mp_config.apicver 96 97 int mpc_ioapic_id(int id) 98 { 99 return ioapics[id].mp_config.apicid; 100 } 101 102 unsigned int mpc_ioapic_addr(int id) 103 { 104 return ioapics[id].mp_config.apicaddr; 105 } 106 107 struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int id) 108 { 109 return &ioapics[id].gsi_config; 110 } 111 112 int nr_ioapics; 113 114 /* The one past the highest gsi number used */ 115 u32 gsi_top; 116 117 /* MP IRQ source entries */ 118 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; 119 120 /* # of MP IRQ source entries */ 121 int mp_irq_entries; 122 123 /* GSI interrupts */ 124 static int nr_irqs_gsi = NR_IRQS_LEGACY; 125 126 #if defined (CONFIG_MCA) || defined (CONFIG_EISA) 127 int mp_bus_id_to_type[MAX_MP_BUSSES]; 128 #endif 129 130 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); 131 132 int skip_ioapic_setup; 133 134 /** 135 * disable_ioapic_support() - disables ioapic support at runtime 136 */ 137 void disable_ioapic_support(void) 138 { 139 #ifdef CONFIG_PCI 140 noioapicquirk = 1; 141 noioapicreroute = -1; 142 #endif 143 skip_ioapic_setup = 1; 144 } 145 146 static int __init parse_noapic(char *str) 147 { 148 /* disable IO-APIC */ 149 disable_ioapic_support(); 150 return 0; 151 } 152 early_param("noapic", parse_noapic); 153 154 static int io_apic_setup_irq_pin(unsigned int irq, int node, 155 struct io_apic_irq_attr *attr); 156 157 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */ 158 void mp_save_irq(struct mpc_intsrc *m) 159 { 160 int i; 161 162 apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x," 163 " IRQ %02x, APIC ID %x, APIC INT %02x\n", 164 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus, 165 m->srcbusirq, m->dstapic, m->dstirq); 166 167 for (i = 0; i < mp_irq_entries; i++) { 168 if (!memcmp(&mp_irqs[i], m, sizeof(*m))) 169 return; 170 } 171 172 memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m)); 173 if (++mp_irq_entries == MAX_IRQ_SOURCES) 174 panic("Max # of irq sources exceeded!!\n"); 175 } 176 177 struct irq_pin_list { 178 int apic, pin; 179 struct irq_pin_list *next; 180 }; 181 182 static struct irq_pin_list *alloc_irq_pin_list(int node) 183 { 184 return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node); 185 } 186 187 188 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ 189 #ifdef CONFIG_SPARSE_IRQ 190 static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY]; 191 #else 192 static struct irq_cfg irq_cfgx[NR_IRQS]; 193 #endif 194 195 int __init arch_early_irq_init(void) 196 { 197 struct irq_cfg *cfg; 198 int count, node, i; 199 200 if (!legacy_pic->nr_legacy_irqs) { 201 nr_irqs_gsi = 0; 202 io_apic_irqs = ~0UL; 203 } 204 205 for (i = 0; i < nr_ioapics; i++) { 206 ioapics[i].saved_registers = 207 kzalloc(sizeof(struct IO_APIC_route_entry) * 208 ioapics[i].nr_registers, GFP_KERNEL); 209 if (!ioapics[i].saved_registers) 210 pr_err("IOAPIC %d: suspend/resume impossible!\n", i); 211 } 212 213 cfg = irq_cfgx; 214 count = ARRAY_SIZE(irq_cfgx); 215 node = cpu_to_node(0); 216 217 /* Make sure the legacy interrupts are marked in the bitmap */ 218 irq_reserve_irqs(0, legacy_pic->nr_legacy_irqs); 219 220 for (i = 0; i < count; i++) { 221 irq_set_chip_data(i, &cfg[i]); 222 zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node); 223 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node); 224 /* 225 * For legacy IRQ's, start with assigning irq0 to irq15 to 226 * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0. 227 */ 228 if (i < legacy_pic->nr_legacy_irqs) { 229 cfg[i].vector = IRQ0_VECTOR + i; 230 cpumask_set_cpu(0, cfg[i].domain); 231 } 232 } 233 234 return 0; 235 } 236 237 #ifdef CONFIG_SPARSE_IRQ 238 static struct irq_cfg *irq_cfg(unsigned int irq) 239 { 240 return irq_get_chip_data(irq); 241 } 242 243 static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node) 244 { 245 struct irq_cfg *cfg; 246 247 cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node); 248 if (!cfg) 249 return NULL; 250 if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node)) 251 goto out_cfg; 252 if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node)) 253 goto out_domain; 254 return cfg; 255 out_domain: 256 free_cpumask_var(cfg->domain); 257 out_cfg: 258 kfree(cfg); 259 return NULL; 260 } 261 262 static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg) 263 { 264 if (!cfg) 265 return; 266 irq_set_chip_data(at, NULL); 267 free_cpumask_var(cfg->domain); 268 free_cpumask_var(cfg->old_domain); 269 kfree(cfg); 270 } 271 272 #else 273 274 struct irq_cfg *irq_cfg(unsigned int irq) 275 { 276 return irq < nr_irqs ? irq_cfgx + irq : NULL; 277 } 278 279 static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node) 280 { 281 return irq_cfgx + irq; 282 } 283 284 static inline void free_irq_cfg(unsigned int at, struct irq_cfg *cfg) { } 285 286 #endif 287 288 static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node) 289 { 290 int res = irq_alloc_desc_at(at, node); 291 struct irq_cfg *cfg; 292 293 if (res < 0) { 294 if (res != -EEXIST) 295 return NULL; 296 cfg = irq_get_chip_data(at); 297 if (cfg) 298 return cfg; 299 } 300 301 cfg = alloc_irq_cfg(at, node); 302 if (cfg) 303 irq_set_chip_data(at, cfg); 304 else 305 irq_free_desc(at); 306 return cfg; 307 } 308 309 static int alloc_irq_from(unsigned int from, int node) 310 { 311 return irq_alloc_desc_from(from, node); 312 } 313 314 static void free_irq_at(unsigned int at, struct irq_cfg *cfg) 315 { 316 free_irq_cfg(at, cfg); 317 irq_free_desc(at); 318 } 319 320 struct io_apic { 321 unsigned int index; 322 unsigned int unused[3]; 323 unsigned int data; 324 unsigned int unused2[11]; 325 unsigned int eoi; 326 }; 327 328 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) 329 { 330 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) 331 + (mpc_ioapic_addr(idx) & ~PAGE_MASK); 332 } 333 334 static inline void io_apic_eoi(unsigned int apic, unsigned int vector) 335 { 336 struct io_apic __iomem *io_apic = io_apic_base(apic); 337 writel(vector, &io_apic->eoi); 338 } 339 340 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg) 341 { 342 struct io_apic __iomem *io_apic = io_apic_base(apic); 343 writel(reg, &io_apic->index); 344 return readl(&io_apic->data); 345 } 346 347 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) 348 { 349 struct io_apic __iomem *io_apic = io_apic_base(apic); 350 writel(reg, &io_apic->index); 351 writel(value, &io_apic->data); 352 } 353 354 /* 355 * Re-write a value: to be used for read-modify-write 356 * cycles where the read already set up the index register. 357 * 358 * Older SiS APIC requires we rewrite the index register 359 */ 360 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) 361 { 362 struct io_apic __iomem *io_apic = io_apic_base(apic); 363 364 if (sis_apic_bug) 365 writel(reg, &io_apic->index); 366 writel(value, &io_apic->data); 367 } 368 369 static bool io_apic_level_ack_pending(struct irq_cfg *cfg) 370 { 371 struct irq_pin_list *entry; 372 unsigned long flags; 373 374 raw_spin_lock_irqsave(&ioapic_lock, flags); 375 for_each_irq_pin(entry, cfg->irq_2_pin) { 376 unsigned int reg; 377 int pin; 378 379 pin = entry->pin; 380 reg = io_apic_read(entry->apic, 0x10 + pin*2); 381 /* Is the remote IRR bit set? */ 382 if (reg & IO_APIC_REDIR_REMOTE_IRR) { 383 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 384 return true; 385 } 386 } 387 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 388 389 return false; 390 } 391 392 union entry_union { 393 struct { u32 w1, w2; }; 394 struct IO_APIC_route_entry entry; 395 }; 396 397 static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin) 398 { 399 union entry_union eu; 400 401 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); 402 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); 403 return eu.entry; 404 } 405 406 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) 407 { 408 union entry_union eu; 409 unsigned long flags; 410 raw_spin_lock_irqsave(&ioapic_lock, flags); 411 eu.entry = __ioapic_read_entry(apic, pin); 412 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 413 return eu.entry; 414 } 415 416 /* 417 * When we write a new IO APIC routing entry, we need to write the high 418 * word first! If the mask bit in the low word is clear, we will enable 419 * the interrupt, and we need to make sure the entry is fully populated 420 * before that happens. 421 */ 422 static void 423 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) 424 { 425 union entry_union eu = {{0, 0}}; 426 427 eu.entry = e; 428 io_apic_write(apic, 0x11 + 2*pin, eu.w2); 429 io_apic_write(apic, 0x10 + 2*pin, eu.w1); 430 } 431 432 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) 433 { 434 unsigned long flags; 435 raw_spin_lock_irqsave(&ioapic_lock, flags); 436 __ioapic_write_entry(apic, pin, e); 437 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 438 } 439 440 /* 441 * When we mask an IO APIC routing entry, we need to write the low 442 * word first, in order to set the mask bit before we change the 443 * high bits! 444 */ 445 static void ioapic_mask_entry(int apic, int pin) 446 { 447 unsigned long flags; 448 union entry_union eu = { .entry.mask = 1 }; 449 450 raw_spin_lock_irqsave(&ioapic_lock, flags); 451 io_apic_write(apic, 0x10 + 2*pin, eu.w1); 452 io_apic_write(apic, 0x11 + 2*pin, eu.w2); 453 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 454 } 455 456 /* 457 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are 458 * shared ISA-space IRQs, so we have to support them. We are super 459 * fast in the common case, and fast for shared ISA-space IRQs. 460 */ 461 static int 462 __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) 463 { 464 struct irq_pin_list **last, *entry; 465 466 /* don't allow duplicates */ 467 last = &cfg->irq_2_pin; 468 for_each_irq_pin(entry, cfg->irq_2_pin) { 469 if (entry->apic == apic && entry->pin == pin) 470 return 0; 471 last = &entry->next; 472 } 473 474 entry = alloc_irq_pin_list(node); 475 if (!entry) { 476 printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n", 477 node, apic, pin); 478 return -ENOMEM; 479 } 480 entry->apic = apic; 481 entry->pin = pin; 482 483 *last = entry; 484 return 0; 485 } 486 487 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) 488 { 489 if (__add_pin_to_irq_node(cfg, node, apic, pin)) 490 panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); 491 } 492 493 /* 494 * Reroute an IRQ to a different pin. 495 */ 496 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node, 497 int oldapic, int oldpin, 498 int newapic, int newpin) 499 { 500 struct irq_pin_list *entry; 501 502 for_each_irq_pin(entry, cfg->irq_2_pin) { 503 if (entry->apic == oldapic && entry->pin == oldpin) { 504 entry->apic = newapic; 505 entry->pin = newpin; 506 /* every one is different, right? */ 507 return; 508 } 509 } 510 511 /* old apic/pin didn't exist, so just add new ones */ 512 add_pin_to_irq_node(cfg, node, newapic, newpin); 513 } 514 515 static void __io_apic_modify_irq(struct irq_pin_list *entry, 516 int mask_and, int mask_or, 517 void (*final)(struct irq_pin_list *entry)) 518 { 519 unsigned int reg, pin; 520 521 pin = entry->pin; 522 reg = io_apic_read(entry->apic, 0x10 + pin * 2); 523 reg &= mask_and; 524 reg |= mask_or; 525 io_apic_modify(entry->apic, 0x10 + pin * 2, reg); 526 if (final) 527 final(entry); 528 } 529 530 static void io_apic_modify_irq(struct irq_cfg *cfg, 531 int mask_and, int mask_or, 532 void (*final)(struct irq_pin_list *entry)) 533 { 534 struct irq_pin_list *entry; 535 536 for_each_irq_pin(entry, cfg->irq_2_pin) 537 __io_apic_modify_irq(entry, mask_and, mask_or, final); 538 } 539 540 static void io_apic_sync(struct irq_pin_list *entry) 541 { 542 /* 543 * Synchronize the IO-APIC and the CPU by doing 544 * a dummy read from the IO-APIC 545 */ 546 struct io_apic __iomem *io_apic; 547 io_apic = io_apic_base(entry->apic); 548 readl(&io_apic->data); 549 } 550 551 static void mask_ioapic(struct irq_cfg *cfg) 552 { 553 unsigned long flags; 554 555 raw_spin_lock_irqsave(&ioapic_lock, flags); 556 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); 557 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 558 } 559 560 static void mask_ioapic_irq(struct irq_data *data) 561 { 562 mask_ioapic(data->chip_data); 563 } 564 565 static void __unmask_ioapic(struct irq_cfg *cfg) 566 { 567 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); 568 } 569 570 static void unmask_ioapic(struct irq_cfg *cfg) 571 { 572 unsigned long flags; 573 574 raw_spin_lock_irqsave(&ioapic_lock, flags); 575 __unmask_ioapic(cfg); 576 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 577 } 578 579 static void unmask_ioapic_irq(struct irq_data *data) 580 { 581 unmask_ioapic(data->chip_data); 582 } 583 584 /* 585 * IO-APIC versions below 0x20 don't support EOI register. 586 * For the record, here is the information about various versions: 587 * 0Xh 82489DX 588 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant 589 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant 590 * 30h-FFh Reserved 591 * 592 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic 593 * version as 0x2. This is an error with documentation and these ICH chips 594 * use io-apic's of version 0x20. 595 * 596 * For IO-APIC's with EOI register, we use that to do an explicit EOI. 597 * Otherwise, we simulate the EOI message manually by changing the trigger 598 * mode to edge and then back to level, with RTE being masked during this. 599 */ 600 static void __eoi_ioapic_pin(int apic, int pin, int vector, struct irq_cfg *cfg) 601 { 602 if (mpc_ioapic_ver(apic) >= 0x20) { 603 /* 604 * Intr-remapping uses pin number as the virtual vector 605 * in the RTE. Actual vector is programmed in 606 * intr-remapping table entry. Hence for the io-apic 607 * EOI we use the pin number. 608 */ 609 if (cfg && irq_remapped(cfg)) 610 io_apic_eoi(apic, pin); 611 else 612 io_apic_eoi(apic, vector); 613 } else { 614 struct IO_APIC_route_entry entry, entry1; 615 616 entry = entry1 = __ioapic_read_entry(apic, pin); 617 618 /* 619 * Mask the entry and change the trigger mode to edge. 620 */ 621 entry1.mask = 1; 622 entry1.trigger = IOAPIC_EDGE; 623 624 __ioapic_write_entry(apic, pin, entry1); 625 626 /* 627 * Restore the previous level triggered entry. 628 */ 629 __ioapic_write_entry(apic, pin, entry); 630 } 631 } 632 633 static void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg) 634 { 635 struct irq_pin_list *entry; 636 unsigned long flags; 637 638 raw_spin_lock_irqsave(&ioapic_lock, flags); 639 for_each_irq_pin(entry, cfg->irq_2_pin) 640 __eoi_ioapic_pin(entry->apic, entry->pin, cfg->vector, cfg); 641 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 642 } 643 644 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) 645 { 646 struct IO_APIC_route_entry entry; 647 648 /* Check delivery_mode to be sure we're not clearing an SMI pin */ 649 entry = ioapic_read_entry(apic, pin); 650 if (entry.delivery_mode == dest_SMI) 651 return; 652 653 /* 654 * Make sure the entry is masked and re-read the contents to check 655 * if it is a level triggered pin and if the remote-IRR is set. 656 */ 657 if (!entry.mask) { 658 entry.mask = 1; 659 ioapic_write_entry(apic, pin, entry); 660 entry = ioapic_read_entry(apic, pin); 661 } 662 663 if (entry.irr) { 664 unsigned long flags; 665 666 /* 667 * Make sure the trigger mode is set to level. Explicit EOI 668 * doesn't clear the remote-IRR if the trigger mode is not 669 * set to level. 670 */ 671 if (!entry.trigger) { 672 entry.trigger = IOAPIC_LEVEL; 673 ioapic_write_entry(apic, pin, entry); 674 } 675 676 raw_spin_lock_irqsave(&ioapic_lock, flags); 677 __eoi_ioapic_pin(apic, pin, entry.vector, NULL); 678 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 679 } 680 681 /* 682 * Clear the rest of the bits in the IO-APIC RTE except for the mask 683 * bit. 684 */ 685 ioapic_mask_entry(apic, pin); 686 entry = ioapic_read_entry(apic, pin); 687 if (entry.irr) 688 printk(KERN_ERR "Unable to reset IRR for apic: %d, pin :%d\n", 689 mpc_ioapic_id(apic), pin); 690 } 691 692 static void clear_IO_APIC (void) 693 { 694 int apic, pin; 695 696 for (apic = 0; apic < nr_ioapics; apic++) 697 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) 698 clear_IO_APIC_pin(apic, pin); 699 } 700 701 #ifdef CONFIG_X86_32 702 /* 703 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to 704 * specific CPU-side IRQs. 705 */ 706 707 #define MAX_PIRQS 8 708 static int pirq_entries[MAX_PIRQS] = { 709 [0 ... MAX_PIRQS - 1] = -1 710 }; 711 712 static int __init ioapic_pirq_setup(char *str) 713 { 714 int i, max; 715 int ints[MAX_PIRQS+1]; 716 717 get_options(str, ARRAY_SIZE(ints), ints); 718 719 apic_printk(APIC_VERBOSE, KERN_INFO 720 "PIRQ redirection, working around broken MP-BIOS.\n"); 721 max = MAX_PIRQS; 722 if (ints[0] < MAX_PIRQS) 723 max = ints[0]; 724 725 for (i = 0; i < max; i++) { 726 apic_printk(APIC_VERBOSE, KERN_DEBUG 727 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); 728 /* 729 * PIRQs are mapped upside down, usually. 730 */ 731 pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; 732 } 733 return 1; 734 } 735 736 __setup("pirq=", ioapic_pirq_setup); 737 #endif /* CONFIG_X86_32 */ 738 739 /* 740 * Saves all the IO-APIC RTE's 741 */ 742 int save_ioapic_entries(void) 743 { 744 int apic, pin; 745 int err = 0; 746 747 for (apic = 0; apic < nr_ioapics; apic++) { 748 if (!ioapics[apic].saved_registers) { 749 err = -ENOMEM; 750 continue; 751 } 752 753 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) 754 ioapics[apic].saved_registers[pin] = 755 ioapic_read_entry(apic, pin); 756 } 757 758 return err; 759 } 760 761 /* 762 * Mask all IO APIC entries. 763 */ 764 void mask_ioapic_entries(void) 765 { 766 int apic, pin; 767 768 for (apic = 0; apic < nr_ioapics; apic++) { 769 if (!ioapics[apic].saved_registers) 770 continue; 771 772 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) { 773 struct IO_APIC_route_entry entry; 774 775 entry = ioapics[apic].saved_registers[pin]; 776 if (!entry.mask) { 777 entry.mask = 1; 778 ioapic_write_entry(apic, pin, entry); 779 } 780 } 781 } 782 } 783 784 /* 785 * Restore IO APIC entries which was saved in the ioapic structure. 786 */ 787 int restore_ioapic_entries(void) 788 { 789 int apic, pin; 790 791 for (apic = 0; apic < nr_ioapics; apic++) { 792 if (!ioapics[apic].saved_registers) 793 continue; 794 795 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) 796 ioapic_write_entry(apic, pin, 797 ioapics[apic].saved_registers[pin]); 798 } 799 return 0; 800 } 801 802 /* 803 * Find the IRQ entry number of a certain pin. 804 */ 805 static int find_irq_entry(int apic, int pin, int type) 806 { 807 int i; 808 809 for (i = 0; i < mp_irq_entries; i++) 810 if (mp_irqs[i].irqtype == type && 811 (mp_irqs[i].dstapic == mpc_ioapic_id(apic) || 812 mp_irqs[i].dstapic == MP_APIC_ALL) && 813 mp_irqs[i].dstirq == pin) 814 return i; 815 816 return -1; 817 } 818 819 /* 820 * Find the pin to which IRQ[irq] (ISA) is connected 821 */ 822 static int __init find_isa_irq_pin(int irq, int type) 823 { 824 int i; 825 826 for (i = 0; i < mp_irq_entries; i++) { 827 int lbus = mp_irqs[i].srcbus; 828 829 if (test_bit(lbus, mp_bus_not_pci) && 830 (mp_irqs[i].irqtype == type) && 831 (mp_irqs[i].srcbusirq == irq)) 832 833 return mp_irqs[i].dstirq; 834 } 835 return -1; 836 } 837 838 static int __init find_isa_irq_apic(int irq, int type) 839 { 840 int i; 841 842 for (i = 0; i < mp_irq_entries; i++) { 843 int lbus = mp_irqs[i].srcbus; 844 845 if (test_bit(lbus, mp_bus_not_pci) && 846 (mp_irqs[i].irqtype == type) && 847 (mp_irqs[i].srcbusirq == irq)) 848 break; 849 } 850 if (i < mp_irq_entries) { 851 int apic; 852 for(apic = 0; apic < nr_ioapics; apic++) { 853 if (mpc_ioapic_id(apic) == mp_irqs[i].dstapic) 854 return apic; 855 } 856 } 857 858 return -1; 859 } 860 861 #if defined(CONFIG_EISA) || defined(CONFIG_MCA) 862 /* 863 * EISA Edge/Level control register, ELCR 864 */ 865 static int EISA_ELCR(unsigned int irq) 866 { 867 if (irq < legacy_pic->nr_legacy_irqs) { 868 unsigned int port = 0x4d0 + (irq >> 3); 869 return (inb(port) >> (irq & 7)) & 1; 870 } 871 apic_printk(APIC_VERBOSE, KERN_INFO 872 "Broken MPtable reports ISA irq %d\n", irq); 873 return 0; 874 } 875 876 #endif 877 878 /* ISA interrupts are always polarity zero edge triggered, 879 * when listed as conforming in the MP table. */ 880 881 #define default_ISA_trigger(idx) (0) 882 #define default_ISA_polarity(idx) (0) 883 884 /* EISA interrupts are always polarity zero and can be edge or level 885 * trigger depending on the ELCR value. If an interrupt is listed as 886 * EISA conforming in the MP table, that means its trigger type must 887 * be read in from the ELCR */ 888 889 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) 890 #define default_EISA_polarity(idx) default_ISA_polarity(idx) 891 892 /* PCI interrupts are always polarity one level triggered, 893 * when listed as conforming in the MP table. */ 894 895 #define default_PCI_trigger(idx) (1) 896 #define default_PCI_polarity(idx) (1) 897 898 /* MCA interrupts are always polarity zero level triggered, 899 * when listed as conforming in the MP table. */ 900 901 #define default_MCA_trigger(idx) (1) 902 #define default_MCA_polarity(idx) default_ISA_polarity(idx) 903 904 static int irq_polarity(int idx) 905 { 906 int bus = mp_irqs[idx].srcbus; 907 int polarity; 908 909 /* 910 * Determine IRQ line polarity (high active or low active): 911 */ 912 switch (mp_irqs[idx].irqflag & 3) 913 { 914 case 0: /* conforms, ie. bus-type dependent polarity */ 915 if (test_bit(bus, mp_bus_not_pci)) 916 polarity = default_ISA_polarity(idx); 917 else 918 polarity = default_PCI_polarity(idx); 919 break; 920 case 1: /* high active */ 921 { 922 polarity = 0; 923 break; 924 } 925 case 2: /* reserved */ 926 { 927 printk(KERN_WARNING "broken BIOS!!\n"); 928 polarity = 1; 929 break; 930 } 931 case 3: /* low active */ 932 { 933 polarity = 1; 934 break; 935 } 936 default: /* invalid */ 937 { 938 printk(KERN_WARNING "broken BIOS!!\n"); 939 polarity = 1; 940 break; 941 } 942 } 943 return polarity; 944 } 945 946 static int irq_trigger(int idx) 947 { 948 int bus = mp_irqs[idx].srcbus; 949 int trigger; 950 951 /* 952 * Determine IRQ trigger mode (edge or level sensitive): 953 */ 954 switch ((mp_irqs[idx].irqflag>>2) & 3) 955 { 956 case 0: /* conforms, ie. bus-type dependent */ 957 if (test_bit(bus, mp_bus_not_pci)) 958 trigger = default_ISA_trigger(idx); 959 else 960 trigger = default_PCI_trigger(idx); 961 #if defined(CONFIG_EISA) || defined(CONFIG_MCA) 962 switch (mp_bus_id_to_type[bus]) { 963 case MP_BUS_ISA: /* ISA pin */ 964 { 965 /* set before the switch */ 966 break; 967 } 968 case MP_BUS_EISA: /* EISA pin */ 969 { 970 trigger = default_EISA_trigger(idx); 971 break; 972 } 973 case MP_BUS_PCI: /* PCI pin */ 974 { 975 /* set before the switch */ 976 break; 977 } 978 case MP_BUS_MCA: /* MCA pin */ 979 { 980 trigger = default_MCA_trigger(idx); 981 break; 982 } 983 default: 984 { 985 printk(KERN_WARNING "broken BIOS!!\n"); 986 trigger = 1; 987 break; 988 } 989 } 990 #endif 991 break; 992 case 1: /* edge */ 993 { 994 trigger = 0; 995 break; 996 } 997 case 2: /* reserved */ 998 { 999 printk(KERN_WARNING "broken BIOS!!\n"); 1000 trigger = 1; 1001 break; 1002 } 1003 case 3: /* level */ 1004 { 1005 trigger = 1; 1006 break; 1007 } 1008 default: /* invalid */ 1009 { 1010 printk(KERN_WARNING "broken BIOS!!\n"); 1011 trigger = 0; 1012 break; 1013 } 1014 } 1015 return trigger; 1016 } 1017 1018 static int pin_2_irq(int idx, int apic, int pin) 1019 { 1020 int irq; 1021 int bus = mp_irqs[idx].srcbus; 1022 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(apic); 1023 1024 /* 1025 * Debugging check, we are in big trouble if this message pops up! 1026 */ 1027 if (mp_irqs[idx].dstirq != pin) 1028 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); 1029 1030 if (test_bit(bus, mp_bus_not_pci)) { 1031 irq = mp_irqs[idx].srcbusirq; 1032 } else { 1033 u32 gsi = gsi_cfg->gsi_base + pin; 1034 1035 if (gsi >= NR_IRQS_LEGACY) 1036 irq = gsi; 1037 else 1038 irq = gsi_top + gsi; 1039 } 1040 1041 #ifdef CONFIG_X86_32 1042 /* 1043 * PCI IRQ command line redirection. Yes, limits are hardcoded. 1044 */ 1045 if ((pin >= 16) && (pin <= 23)) { 1046 if (pirq_entries[pin-16] != -1) { 1047 if (!pirq_entries[pin-16]) { 1048 apic_printk(APIC_VERBOSE, KERN_DEBUG 1049 "disabling PIRQ%d\n", pin-16); 1050 } else { 1051 irq = pirq_entries[pin-16]; 1052 apic_printk(APIC_VERBOSE, KERN_DEBUG 1053 "using PIRQ%d -> IRQ %d\n", 1054 pin-16, irq); 1055 } 1056 } 1057 } 1058 #endif 1059 1060 return irq; 1061 } 1062 1063 /* 1064 * Find a specific PCI IRQ entry. 1065 * Not an __init, possibly needed by modules 1066 */ 1067 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin, 1068 struct io_apic_irq_attr *irq_attr) 1069 { 1070 int apic, i, best_guess = -1; 1071 1072 apic_printk(APIC_DEBUG, 1073 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", 1074 bus, slot, pin); 1075 if (test_bit(bus, mp_bus_not_pci)) { 1076 apic_printk(APIC_VERBOSE, 1077 "PCI BIOS passed nonexistent PCI bus %d!\n", bus); 1078 return -1; 1079 } 1080 for (i = 0; i < mp_irq_entries; i++) { 1081 int lbus = mp_irqs[i].srcbus; 1082 1083 for (apic = 0; apic < nr_ioapics; apic++) 1084 if (mpc_ioapic_id(apic) == mp_irqs[i].dstapic || 1085 mp_irqs[i].dstapic == MP_APIC_ALL) 1086 break; 1087 1088 if (!test_bit(lbus, mp_bus_not_pci) && 1089 !mp_irqs[i].irqtype && 1090 (bus == lbus) && 1091 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) { 1092 int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq); 1093 1094 if (!(apic || IO_APIC_IRQ(irq))) 1095 continue; 1096 1097 if (pin == (mp_irqs[i].srcbusirq & 3)) { 1098 set_io_apic_irq_attr(irq_attr, apic, 1099 mp_irqs[i].dstirq, 1100 irq_trigger(i), 1101 irq_polarity(i)); 1102 return irq; 1103 } 1104 /* 1105 * Use the first all-but-pin matching entry as a 1106 * best-guess fuzzy result for broken mptables. 1107 */ 1108 if (best_guess < 0) { 1109 set_io_apic_irq_attr(irq_attr, apic, 1110 mp_irqs[i].dstirq, 1111 irq_trigger(i), 1112 irq_polarity(i)); 1113 best_guess = irq; 1114 } 1115 } 1116 } 1117 return best_guess; 1118 } 1119 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); 1120 1121 void lock_vector_lock(void) 1122 { 1123 /* Used to the online set of cpus does not change 1124 * during assign_irq_vector. 1125 */ 1126 raw_spin_lock(&vector_lock); 1127 } 1128 1129 void unlock_vector_lock(void) 1130 { 1131 raw_spin_unlock(&vector_lock); 1132 } 1133 1134 static int 1135 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) 1136 { 1137 /* 1138 * NOTE! The local APIC isn't very good at handling 1139 * multiple interrupts at the same interrupt level. 1140 * As the interrupt level is determined by taking the 1141 * vector number and shifting that right by 4, we 1142 * want to spread these out a bit so that they don't 1143 * all fall in the same interrupt level. 1144 * 1145 * Also, we've got to be careful not to trash gate 1146 * 0x80, because int 0x80 is hm, kind of importantish. ;) 1147 */ 1148 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; 1149 static int current_offset = VECTOR_OFFSET_START % 8; 1150 unsigned int old_vector; 1151 int cpu, err; 1152 cpumask_var_t tmp_mask; 1153 1154 if (cfg->move_in_progress) 1155 return -EBUSY; 1156 1157 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) 1158 return -ENOMEM; 1159 1160 old_vector = cfg->vector; 1161 if (old_vector) { 1162 cpumask_and(tmp_mask, mask, cpu_online_mask); 1163 cpumask_and(tmp_mask, cfg->domain, tmp_mask); 1164 if (!cpumask_empty(tmp_mask)) { 1165 free_cpumask_var(tmp_mask); 1166 return 0; 1167 } 1168 } 1169 1170 /* Only try and allocate irqs on cpus that are present */ 1171 err = -ENOSPC; 1172 for_each_cpu_and(cpu, mask, cpu_online_mask) { 1173 int new_cpu; 1174 int vector, offset; 1175 1176 apic->vector_allocation_domain(cpu, tmp_mask); 1177 1178 vector = current_vector; 1179 offset = current_offset; 1180 next: 1181 vector += 8; 1182 if (vector >= first_system_vector) { 1183 /* If out of vectors on large boxen, must share them. */ 1184 offset = (offset + 1) % 8; 1185 vector = FIRST_EXTERNAL_VECTOR + offset; 1186 } 1187 if (unlikely(current_vector == vector)) 1188 continue; 1189 1190 if (test_bit(vector, used_vectors)) 1191 goto next; 1192 1193 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) 1194 if (per_cpu(vector_irq, new_cpu)[vector] != -1) 1195 goto next; 1196 /* Found one! */ 1197 current_vector = vector; 1198 current_offset = offset; 1199 if (old_vector) { 1200 cfg->move_in_progress = 1; 1201 cpumask_copy(cfg->old_domain, cfg->domain); 1202 } 1203 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) 1204 per_cpu(vector_irq, new_cpu)[vector] = irq; 1205 cfg->vector = vector; 1206 cpumask_copy(cfg->domain, tmp_mask); 1207 err = 0; 1208 break; 1209 } 1210 free_cpumask_var(tmp_mask); 1211 return err; 1212 } 1213 1214 int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) 1215 { 1216 int err; 1217 unsigned long flags; 1218 1219 raw_spin_lock_irqsave(&vector_lock, flags); 1220 err = __assign_irq_vector(irq, cfg, mask); 1221 raw_spin_unlock_irqrestore(&vector_lock, flags); 1222 return err; 1223 } 1224 1225 static void __clear_irq_vector(int irq, struct irq_cfg *cfg) 1226 { 1227 int cpu, vector; 1228 1229 BUG_ON(!cfg->vector); 1230 1231 vector = cfg->vector; 1232 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) 1233 per_cpu(vector_irq, cpu)[vector] = -1; 1234 1235 cfg->vector = 0; 1236 cpumask_clear(cfg->domain); 1237 1238 if (likely(!cfg->move_in_progress)) 1239 return; 1240 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { 1241 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; 1242 vector++) { 1243 if (per_cpu(vector_irq, cpu)[vector] != irq) 1244 continue; 1245 per_cpu(vector_irq, cpu)[vector] = -1; 1246 break; 1247 } 1248 } 1249 cfg->move_in_progress = 0; 1250 } 1251 1252 void __setup_vector_irq(int cpu) 1253 { 1254 /* Initialize vector_irq on a new cpu */ 1255 int irq, vector; 1256 struct irq_cfg *cfg; 1257 1258 /* 1259 * vector_lock will make sure that we don't run into irq vector 1260 * assignments that might be happening on another cpu in parallel, 1261 * while we setup our initial vector to irq mappings. 1262 */ 1263 raw_spin_lock(&vector_lock); 1264 /* Mark the inuse vectors */ 1265 for_each_active_irq(irq) { 1266 cfg = irq_get_chip_data(irq); 1267 if (!cfg) 1268 continue; 1269 /* 1270 * If it is a legacy IRQ handled by the legacy PIC, this cpu 1271 * will be part of the irq_cfg's domain. 1272 */ 1273 if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq)) 1274 cpumask_set_cpu(cpu, cfg->domain); 1275 1276 if (!cpumask_test_cpu(cpu, cfg->domain)) 1277 continue; 1278 vector = cfg->vector; 1279 per_cpu(vector_irq, cpu)[vector] = irq; 1280 } 1281 /* Mark the free vectors */ 1282 for (vector = 0; vector < NR_VECTORS; ++vector) { 1283 irq = per_cpu(vector_irq, cpu)[vector]; 1284 if (irq < 0) 1285 continue; 1286 1287 cfg = irq_cfg(irq); 1288 if (!cpumask_test_cpu(cpu, cfg->domain)) 1289 per_cpu(vector_irq, cpu)[vector] = -1; 1290 } 1291 raw_spin_unlock(&vector_lock); 1292 } 1293 1294 static struct irq_chip ioapic_chip; 1295 1296 #ifdef CONFIG_X86_32 1297 static inline int IO_APIC_irq_trigger(int irq) 1298 { 1299 int apic, idx, pin; 1300 1301 for (apic = 0; apic < nr_ioapics; apic++) { 1302 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) { 1303 idx = find_irq_entry(apic, pin, mp_INT); 1304 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) 1305 return irq_trigger(idx); 1306 } 1307 } 1308 /* 1309 * nonexistent IRQs are edge default 1310 */ 1311 return 0; 1312 } 1313 #else 1314 static inline int IO_APIC_irq_trigger(int irq) 1315 { 1316 return 1; 1317 } 1318 #endif 1319 1320 static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg, 1321 unsigned long trigger) 1322 { 1323 struct irq_chip *chip = &ioapic_chip; 1324 irq_flow_handler_t hdl; 1325 bool fasteoi; 1326 1327 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || 1328 trigger == IOAPIC_LEVEL) { 1329 irq_set_status_flags(irq, IRQ_LEVEL); 1330 fasteoi = true; 1331 } else { 1332 irq_clear_status_flags(irq, IRQ_LEVEL); 1333 fasteoi = false; 1334 } 1335 1336 if (irq_remapped(cfg)) { 1337 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); 1338 irq_remap_modify_chip_defaults(chip); 1339 fasteoi = trigger != 0; 1340 } 1341 1342 hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq; 1343 irq_set_chip_and_handler_name(irq, chip, hdl, 1344 fasteoi ? "fasteoi" : "edge"); 1345 } 1346 1347 static int setup_ioapic_entry(int apic_id, int irq, 1348 struct IO_APIC_route_entry *entry, 1349 unsigned int destination, int trigger, 1350 int polarity, int vector, int pin) 1351 { 1352 /* 1353 * add it to the IO-APIC irq-routing table: 1354 */ 1355 memset(entry,0,sizeof(*entry)); 1356 1357 if (intr_remapping_enabled) { 1358 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id); 1359 struct irte irte; 1360 struct IR_IO_APIC_route_entry *ir_entry = 1361 (struct IR_IO_APIC_route_entry *) entry; 1362 int index; 1363 1364 if (!iommu) 1365 panic("No mapping iommu for ioapic %d\n", apic_id); 1366 1367 index = alloc_irte(iommu, irq, 1); 1368 if (index < 0) 1369 panic("Failed to allocate IRTE for ioapic %d\n", apic_id); 1370 1371 prepare_irte(&irte, vector, destination); 1372 1373 /* Set source-id of interrupt request */ 1374 set_ioapic_sid(&irte, apic_id); 1375 1376 modify_irte(irq, &irte); 1377 1378 ir_entry->index2 = (index >> 15) & 0x1; 1379 ir_entry->zero = 0; 1380 ir_entry->format = 1; 1381 ir_entry->index = (index & 0x7fff); 1382 /* 1383 * IO-APIC RTE will be configured with virtual vector. 1384 * irq handler will do the explicit EOI to the io-apic. 1385 */ 1386 ir_entry->vector = pin; 1387 1388 apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: " 1389 "Set IRTE entry (P:%d FPD:%d Dst_Mode:%d " 1390 "Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X " 1391 "Avail:%X Vector:%02X Dest:%08X " 1392 "SID:%04X SQ:%X SVT:%X)\n", 1393 apic_id, irte.present, irte.fpd, irte.dst_mode, 1394 irte.redir_hint, irte.trigger_mode, irte.dlvry_mode, 1395 irte.avail, irte.vector, irte.dest_id, 1396 irte.sid, irte.sq, irte.svt); 1397 } else { 1398 entry->delivery_mode = apic->irq_delivery_mode; 1399 entry->dest_mode = apic->irq_dest_mode; 1400 entry->dest = destination; 1401 entry->vector = vector; 1402 } 1403 1404 entry->mask = 0; /* enable IRQ */ 1405 entry->trigger = trigger; 1406 entry->polarity = polarity; 1407 1408 /* Mask level triggered irqs. 1409 * Use IRQ_DELAYED_DISABLE for edge triggered irqs. 1410 */ 1411 if (trigger) 1412 entry->mask = 1; 1413 return 0; 1414 } 1415 1416 static void setup_ioapic_irq(int apic_id, int pin, unsigned int irq, 1417 struct irq_cfg *cfg, int trigger, int polarity) 1418 { 1419 struct IO_APIC_route_entry entry; 1420 unsigned int dest; 1421 1422 if (!IO_APIC_IRQ(irq)) 1423 return; 1424 /* 1425 * For legacy irqs, cfg->domain starts with cpu 0 for legacy 1426 * controllers like 8259. Now that IO-APIC can handle this irq, update 1427 * the cfg->domain. 1428 */ 1429 if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain)) 1430 apic->vector_allocation_domain(0, cfg->domain); 1431 1432 if (assign_irq_vector(irq, cfg, apic->target_cpus())) 1433 return; 1434 1435 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); 1436 1437 apic_printk(APIC_VERBOSE,KERN_DEBUG 1438 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " 1439 "IRQ %d Mode:%i Active:%i Dest:%d)\n", 1440 apic_id, mpc_ioapic_id(apic_id), pin, cfg->vector, 1441 irq, trigger, polarity, dest); 1442 1443 1444 if (setup_ioapic_entry(mpc_ioapic_id(apic_id), irq, &entry, 1445 dest, trigger, polarity, cfg->vector, pin)) { 1446 printk("Failed to setup ioapic entry for ioapic %d, pin %d\n", 1447 mpc_ioapic_id(apic_id), pin); 1448 __clear_irq_vector(irq, cfg); 1449 return; 1450 } 1451 1452 ioapic_register_intr(irq, cfg, trigger); 1453 if (irq < legacy_pic->nr_legacy_irqs) 1454 legacy_pic->mask(irq); 1455 1456 ioapic_write_entry(apic_id, pin, entry); 1457 } 1458 1459 static bool __init io_apic_pin_not_connected(int idx, int apic_id, int pin) 1460 { 1461 if (idx != -1) 1462 return false; 1463 1464 apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n", 1465 mpc_ioapic_id(apic_id), pin); 1466 return true; 1467 } 1468 1469 static void __init __io_apic_setup_irqs(unsigned int apic_id) 1470 { 1471 int idx, node = cpu_to_node(0); 1472 struct io_apic_irq_attr attr; 1473 unsigned int pin, irq; 1474 1475 for (pin = 0; pin < ioapics[apic_id].nr_registers; pin++) { 1476 idx = find_irq_entry(apic_id, pin, mp_INT); 1477 if (io_apic_pin_not_connected(idx, apic_id, pin)) 1478 continue; 1479 1480 irq = pin_2_irq(idx, apic_id, pin); 1481 1482 if ((apic_id > 0) && (irq > 16)) 1483 continue; 1484 1485 /* 1486 * Skip the timer IRQ if there's a quirk handler 1487 * installed and if it returns 1: 1488 */ 1489 if (apic->multi_timer_check && 1490 apic->multi_timer_check(apic_id, irq)) 1491 continue; 1492 1493 set_io_apic_irq_attr(&attr, apic_id, pin, irq_trigger(idx), 1494 irq_polarity(idx)); 1495 1496 io_apic_setup_irq_pin(irq, node, &attr); 1497 } 1498 } 1499 1500 static void __init setup_IO_APIC_irqs(void) 1501 { 1502 unsigned int apic_id; 1503 1504 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); 1505 1506 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) 1507 __io_apic_setup_irqs(apic_id); 1508 } 1509 1510 /* 1511 * for the gsit that is not in first ioapic 1512 * but could not use acpi_register_gsi() 1513 * like some special sci in IBM x3330 1514 */ 1515 void setup_IO_APIC_irq_extra(u32 gsi) 1516 { 1517 int apic_id = 0, pin, idx, irq, node = cpu_to_node(0); 1518 struct io_apic_irq_attr attr; 1519 1520 /* 1521 * Convert 'gsi' to 'ioapic.pin'. 1522 */ 1523 apic_id = mp_find_ioapic(gsi); 1524 if (apic_id < 0) 1525 return; 1526 1527 pin = mp_find_ioapic_pin(apic_id, gsi); 1528 idx = find_irq_entry(apic_id, pin, mp_INT); 1529 if (idx == -1) 1530 return; 1531 1532 irq = pin_2_irq(idx, apic_id, pin); 1533 1534 /* Only handle the non legacy irqs on secondary ioapics */ 1535 if (apic_id == 0 || irq < NR_IRQS_LEGACY) 1536 return; 1537 1538 set_io_apic_irq_attr(&attr, apic_id, pin, irq_trigger(idx), 1539 irq_polarity(idx)); 1540 1541 io_apic_setup_irq_pin_once(irq, node, &attr); 1542 } 1543 1544 /* 1545 * Set up the timer pin, possibly with the 8259A-master behind. 1546 */ 1547 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin, 1548 int vector) 1549 { 1550 struct IO_APIC_route_entry entry; 1551 1552 if (intr_remapping_enabled) 1553 return; 1554 1555 memset(&entry, 0, sizeof(entry)); 1556 1557 /* 1558 * We use logical delivery to get the timer IRQ 1559 * to the first CPU. 1560 */ 1561 entry.dest_mode = apic->irq_dest_mode; 1562 entry.mask = 0; /* don't mask IRQ for edge */ 1563 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus()); 1564 entry.delivery_mode = apic->irq_delivery_mode; 1565 entry.polarity = 0; 1566 entry.trigger = 0; 1567 entry.vector = vector; 1568 1569 /* 1570 * The timer IRQ doesn't have to know that behind the 1571 * scene we may have a 8259A-master in AEOI mode ... 1572 */ 1573 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, 1574 "edge"); 1575 1576 /* 1577 * Add it to the IO-APIC irq-routing table: 1578 */ 1579 ioapic_write_entry(apic_id, pin, entry); 1580 } 1581 1582 1583 __apicdebuginit(void) print_IO_APIC(void) 1584 { 1585 int apic, i; 1586 union IO_APIC_reg_00 reg_00; 1587 union IO_APIC_reg_01 reg_01; 1588 union IO_APIC_reg_02 reg_02; 1589 union IO_APIC_reg_03 reg_03; 1590 unsigned long flags; 1591 struct irq_cfg *cfg; 1592 unsigned int irq; 1593 1594 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); 1595 for (i = 0; i < nr_ioapics; i++) 1596 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", 1597 mpc_ioapic_id(i), ioapics[i].nr_registers); 1598 1599 /* 1600 * We are a bit conservative about what we expect. We have to 1601 * know about every hardware change ASAP. 1602 */ 1603 printk(KERN_INFO "testing the IO APIC.......................\n"); 1604 1605 for (apic = 0; apic < nr_ioapics; apic++) { 1606 1607 raw_spin_lock_irqsave(&ioapic_lock, flags); 1608 reg_00.raw = io_apic_read(apic, 0); 1609 reg_01.raw = io_apic_read(apic, 1); 1610 if (reg_01.bits.version >= 0x10) 1611 reg_02.raw = io_apic_read(apic, 2); 1612 if (reg_01.bits.version >= 0x20) 1613 reg_03.raw = io_apic_read(apic, 3); 1614 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 1615 1616 printk("\n"); 1617 printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(apic)); 1618 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); 1619 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); 1620 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); 1621 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); 1622 1623 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); 1624 printk(KERN_DEBUG "....... : max redirection entries: %02X\n", 1625 reg_01.bits.entries); 1626 1627 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); 1628 printk(KERN_DEBUG "....... : IO APIC version: %02X\n", 1629 reg_01.bits.version); 1630 1631 /* 1632 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, 1633 * but the value of reg_02 is read as the previous read register 1634 * value, so ignore it if reg_02 == reg_01. 1635 */ 1636 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { 1637 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); 1638 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); 1639 } 1640 1641 /* 1642 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 1643 * or reg_03, but the value of reg_0[23] is read as the previous read 1644 * register value, so ignore it if reg_03 == reg_0[12]. 1645 */ 1646 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && 1647 reg_03.raw != reg_01.raw) { 1648 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); 1649 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); 1650 } 1651 1652 printk(KERN_DEBUG ".... IRQ redirection table:\n"); 1653 1654 if (intr_remapping_enabled) { 1655 printk(KERN_DEBUG " NR Indx Fmt Mask Trig IRR" 1656 " Pol Stat Indx2 Zero Vect:\n"); 1657 } else { 1658 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol" 1659 " Stat Dmod Deli Vect:\n"); 1660 } 1661 1662 for (i = 0; i <= reg_01.bits.entries; i++) { 1663 if (intr_remapping_enabled) { 1664 struct IO_APIC_route_entry entry; 1665 struct IR_IO_APIC_route_entry *ir_entry; 1666 1667 entry = ioapic_read_entry(apic, i); 1668 ir_entry = (struct IR_IO_APIC_route_entry *) &entry; 1669 printk(KERN_DEBUG " %02x %04X ", 1670 i, 1671 ir_entry->index 1672 ); 1673 printk("%1d %1d %1d %1d %1d " 1674 "%1d %1d %X %02X\n", 1675 ir_entry->format, 1676 ir_entry->mask, 1677 ir_entry->trigger, 1678 ir_entry->irr, 1679 ir_entry->polarity, 1680 ir_entry->delivery_status, 1681 ir_entry->index2, 1682 ir_entry->zero, 1683 ir_entry->vector 1684 ); 1685 } else { 1686 struct IO_APIC_route_entry entry; 1687 1688 entry = ioapic_read_entry(apic, i); 1689 printk(KERN_DEBUG " %02x %02X ", 1690 i, 1691 entry.dest 1692 ); 1693 printk("%1d %1d %1d %1d %1d " 1694 "%1d %1d %02X\n", 1695 entry.mask, 1696 entry.trigger, 1697 entry.irr, 1698 entry.polarity, 1699 entry.delivery_status, 1700 entry.dest_mode, 1701 entry.delivery_mode, 1702 entry.vector 1703 ); 1704 } 1705 } 1706 } 1707 1708 printk(KERN_DEBUG "IRQ to pin mappings:\n"); 1709 for_each_active_irq(irq) { 1710 struct irq_pin_list *entry; 1711 1712 cfg = irq_get_chip_data(irq); 1713 if (!cfg) 1714 continue; 1715 entry = cfg->irq_2_pin; 1716 if (!entry) 1717 continue; 1718 printk(KERN_DEBUG "IRQ%d ", irq); 1719 for_each_irq_pin(entry, cfg->irq_2_pin) 1720 printk("-> %d:%d", entry->apic, entry->pin); 1721 printk("\n"); 1722 } 1723 1724 printk(KERN_INFO ".................................... done.\n"); 1725 1726 return; 1727 } 1728 1729 __apicdebuginit(void) print_APIC_field(int base) 1730 { 1731 int i; 1732 1733 printk(KERN_DEBUG); 1734 1735 for (i = 0; i < 8; i++) 1736 printk(KERN_CONT "%08x", apic_read(base + i*0x10)); 1737 1738 printk(KERN_CONT "\n"); 1739 } 1740 1741 __apicdebuginit(void) print_local_APIC(void *dummy) 1742 { 1743 unsigned int i, v, ver, maxlvt; 1744 u64 icr; 1745 1746 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", 1747 smp_processor_id(), hard_smp_processor_id()); 1748 v = apic_read(APIC_ID); 1749 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); 1750 v = apic_read(APIC_LVR); 1751 printk(KERN_INFO "... APIC VERSION: %08x\n", v); 1752 ver = GET_APIC_VERSION(v); 1753 maxlvt = lapic_get_maxlvt(); 1754 1755 v = apic_read(APIC_TASKPRI); 1756 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); 1757 1758 if (APIC_INTEGRATED(ver)) { /* !82489DX */ 1759 if (!APIC_XAPIC(ver)) { 1760 v = apic_read(APIC_ARBPRI); 1761 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, 1762 v & APIC_ARBPRI_MASK); 1763 } 1764 v = apic_read(APIC_PROCPRI); 1765 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); 1766 } 1767 1768 /* 1769 * Remote read supported only in the 82489DX and local APIC for 1770 * Pentium processors. 1771 */ 1772 if (!APIC_INTEGRATED(ver) || maxlvt == 3) { 1773 v = apic_read(APIC_RRR); 1774 printk(KERN_DEBUG "... APIC RRR: %08x\n", v); 1775 } 1776 1777 v = apic_read(APIC_LDR); 1778 printk(KERN_DEBUG "... APIC LDR: %08x\n", v); 1779 if (!x2apic_enabled()) { 1780 v = apic_read(APIC_DFR); 1781 printk(KERN_DEBUG "... APIC DFR: %08x\n", v); 1782 } 1783 v = apic_read(APIC_SPIV); 1784 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); 1785 1786 printk(KERN_DEBUG "... APIC ISR field:\n"); 1787 print_APIC_field(APIC_ISR); 1788 printk(KERN_DEBUG "... APIC TMR field:\n"); 1789 print_APIC_field(APIC_TMR); 1790 printk(KERN_DEBUG "... APIC IRR field:\n"); 1791 print_APIC_field(APIC_IRR); 1792 1793 if (APIC_INTEGRATED(ver)) { /* !82489DX */ 1794 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1795 apic_write(APIC_ESR, 0); 1796 1797 v = apic_read(APIC_ESR); 1798 printk(KERN_DEBUG "... APIC ESR: %08x\n", v); 1799 } 1800 1801 icr = apic_icr_read(); 1802 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); 1803 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); 1804 1805 v = apic_read(APIC_LVTT); 1806 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); 1807 1808 if (maxlvt > 3) { /* PC is LVT#4. */ 1809 v = apic_read(APIC_LVTPC); 1810 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); 1811 } 1812 v = apic_read(APIC_LVT0); 1813 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); 1814 v = apic_read(APIC_LVT1); 1815 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); 1816 1817 if (maxlvt > 2) { /* ERR is LVT#3. */ 1818 v = apic_read(APIC_LVTERR); 1819 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); 1820 } 1821 1822 v = apic_read(APIC_TMICT); 1823 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); 1824 v = apic_read(APIC_TMCCT); 1825 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); 1826 v = apic_read(APIC_TDCR); 1827 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); 1828 1829 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { 1830 v = apic_read(APIC_EFEAT); 1831 maxlvt = (v >> 16) & 0xff; 1832 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v); 1833 v = apic_read(APIC_ECTRL); 1834 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v); 1835 for (i = 0; i < maxlvt; i++) { 1836 v = apic_read(APIC_EILVTn(i)); 1837 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v); 1838 } 1839 } 1840 printk("\n"); 1841 } 1842 1843 __apicdebuginit(void) print_local_APICs(int maxcpu) 1844 { 1845 int cpu; 1846 1847 if (!maxcpu) 1848 return; 1849 1850 preempt_disable(); 1851 for_each_online_cpu(cpu) { 1852 if (cpu >= maxcpu) 1853 break; 1854 smp_call_function_single(cpu, print_local_APIC, NULL, 1); 1855 } 1856 preempt_enable(); 1857 } 1858 1859 __apicdebuginit(void) print_PIC(void) 1860 { 1861 unsigned int v; 1862 unsigned long flags; 1863 1864 if (!legacy_pic->nr_legacy_irqs) 1865 return; 1866 1867 printk(KERN_DEBUG "\nprinting PIC contents\n"); 1868 1869 raw_spin_lock_irqsave(&i8259A_lock, flags); 1870 1871 v = inb(0xa1) << 8 | inb(0x21); 1872 printk(KERN_DEBUG "... PIC IMR: %04x\n", v); 1873 1874 v = inb(0xa0) << 8 | inb(0x20); 1875 printk(KERN_DEBUG "... PIC IRR: %04x\n", v); 1876 1877 outb(0x0b,0xa0); 1878 outb(0x0b,0x20); 1879 v = inb(0xa0) << 8 | inb(0x20); 1880 outb(0x0a,0xa0); 1881 outb(0x0a,0x20); 1882 1883 raw_spin_unlock_irqrestore(&i8259A_lock, flags); 1884 1885 printk(KERN_DEBUG "... PIC ISR: %04x\n", v); 1886 1887 v = inb(0x4d1) << 8 | inb(0x4d0); 1888 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); 1889 } 1890 1891 static int __initdata show_lapic = 1; 1892 static __init int setup_show_lapic(char *arg) 1893 { 1894 int num = -1; 1895 1896 if (strcmp(arg, "all") == 0) { 1897 show_lapic = CONFIG_NR_CPUS; 1898 } else { 1899 get_option(&arg, &num); 1900 if (num >= 0) 1901 show_lapic = num; 1902 } 1903 1904 return 1; 1905 } 1906 __setup("show_lapic=", setup_show_lapic); 1907 1908 __apicdebuginit(int) print_ICs(void) 1909 { 1910 if (apic_verbosity == APIC_QUIET) 1911 return 0; 1912 1913 print_PIC(); 1914 1915 /* don't print out if apic is not there */ 1916 if (!cpu_has_apic && !apic_from_smp_config()) 1917 return 0; 1918 1919 print_local_APICs(show_lapic); 1920 print_IO_APIC(); 1921 1922 return 0; 1923 } 1924 1925 late_initcall(print_ICs); 1926 1927 1928 /* Where if anywhere is the i8259 connect in external int mode */ 1929 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; 1930 1931 void __init enable_IO_APIC(void) 1932 { 1933 int i8259_apic, i8259_pin; 1934 int apic; 1935 1936 if (!legacy_pic->nr_legacy_irqs) 1937 return; 1938 1939 for(apic = 0; apic < nr_ioapics; apic++) { 1940 int pin; 1941 /* See if any of the pins is in ExtINT mode */ 1942 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) { 1943 struct IO_APIC_route_entry entry; 1944 entry = ioapic_read_entry(apic, pin); 1945 1946 /* If the interrupt line is enabled and in ExtInt mode 1947 * I have found the pin where the i8259 is connected. 1948 */ 1949 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { 1950 ioapic_i8259.apic = apic; 1951 ioapic_i8259.pin = pin; 1952 goto found_i8259; 1953 } 1954 } 1955 } 1956 found_i8259: 1957 /* Look to see what if the MP table has reported the ExtINT */ 1958 /* If we could not find the appropriate pin by looking at the ioapic 1959 * the i8259 probably is not connected the ioapic but give the 1960 * mptable a chance anyway. 1961 */ 1962 i8259_pin = find_isa_irq_pin(0, mp_ExtINT); 1963 i8259_apic = find_isa_irq_apic(0, mp_ExtINT); 1964 /* Trust the MP table if nothing is setup in the hardware */ 1965 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { 1966 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); 1967 ioapic_i8259.pin = i8259_pin; 1968 ioapic_i8259.apic = i8259_apic; 1969 } 1970 /* Complain if the MP table and the hardware disagree */ 1971 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && 1972 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) 1973 { 1974 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); 1975 } 1976 1977 /* 1978 * Do not trust the IO-APIC being empty at bootup 1979 */ 1980 clear_IO_APIC(); 1981 } 1982 1983 /* 1984 * Not an __init, needed by the reboot code 1985 */ 1986 void disable_IO_APIC(void) 1987 { 1988 /* 1989 * Clear the IO-APIC before rebooting: 1990 */ 1991 clear_IO_APIC(); 1992 1993 if (!legacy_pic->nr_legacy_irqs) 1994 return; 1995 1996 /* 1997 * If the i8259 is routed through an IOAPIC 1998 * Put that IOAPIC in virtual wire mode 1999 * so legacy interrupts can be delivered. 2000 * 2001 * With interrupt-remapping, for now we will use virtual wire A mode, 2002 * as virtual wire B is little complex (need to configure both 2003 * IOAPIC RTE as well as interrupt-remapping table entry). 2004 * As this gets called during crash dump, keep this simple for now. 2005 */ 2006 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) { 2007 struct IO_APIC_route_entry entry; 2008 2009 memset(&entry, 0, sizeof(entry)); 2010 entry.mask = 0; /* Enabled */ 2011 entry.trigger = 0; /* Edge */ 2012 entry.irr = 0; 2013 entry.polarity = 0; /* High */ 2014 entry.delivery_status = 0; 2015 entry.dest_mode = 0; /* Physical */ 2016 entry.delivery_mode = dest_ExtINT; /* ExtInt */ 2017 entry.vector = 0; 2018 entry.dest = read_apic_id(); 2019 2020 /* 2021 * Add it to the IO-APIC irq-routing table: 2022 */ 2023 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); 2024 } 2025 2026 /* 2027 * Use virtual wire A mode when interrupt remapping is enabled. 2028 */ 2029 if (cpu_has_apic || apic_from_smp_config()) 2030 disconnect_bsp_APIC(!intr_remapping_enabled && 2031 ioapic_i8259.pin != -1); 2032 } 2033 2034 #ifdef CONFIG_X86_32 2035 /* 2036 * function to set the IO-APIC physical IDs based on the 2037 * values stored in the MPC table. 2038 * 2039 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 2040 */ 2041 void __init setup_ioapic_ids_from_mpc_nocheck(void) 2042 { 2043 union IO_APIC_reg_00 reg_00; 2044 physid_mask_t phys_id_present_map; 2045 int apic_id; 2046 int i; 2047 unsigned char old_id; 2048 unsigned long flags; 2049 2050 /* 2051 * This is broken; anything with a real cpu count has to 2052 * circumvent this idiocy regardless. 2053 */ 2054 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map); 2055 2056 /* 2057 * Set the IOAPIC ID to the value stored in the MPC table. 2058 */ 2059 for (apic_id = 0; apic_id < nr_ioapics; apic_id++) { 2060 2061 /* Read the register 0 value */ 2062 raw_spin_lock_irqsave(&ioapic_lock, flags); 2063 reg_00.raw = io_apic_read(apic_id, 0); 2064 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 2065 2066 old_id = mpc_ioapic_id(apic_id); 2067 2068 if (mpc_ioapic_id(apic_id) >= get_physical_broadcast()) { 2069 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", 2070 apic_id, mpc_ioapic_id(apic_id)); 2071 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", 2072 reg_00.bits.ID); 2073 ioapics[apic_id].mp_config.apicid = reg_00.bits.ID; 2074 } 2075 2076 /* 2077 * Sanity check, is the ID really free? Every APIC in a 2078 * system must have a unique ID or we get lots of nice 2079 * 'stuck on smp_invalidate_needed IPI wait' messages. 2080 */ 2081 if (apic->check_apicid_used(&phys_id_present_map, 2082 mpc_ioapic_id(apic_id))) { 2083 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", 2084 apic_id, mpc_ioapic_id(apic_id)); 2085 for (i = 0; i < get_physical_broadcast(); i++) 2086 if (!physid_isset(i, phys_id_present_map)) 2087 break; 2088 if (i >= get_physical_broadcast()) 2089 panic("Max APIC ID exceeded!\n"); 2090 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", 2091 i); 2092 physid_set(i, phys_id_present_map); 2093 ioapics[apic_id].mp_config.apicid = i; 2094 } else { 2095 physid_mask_t tmp; 2096 apic->apicid_to_cpu_present(mpc_ioapic_id(apic_id), 2097 &tmp); 2098 apic_printk(APIC_VERBOSE, "Setting %d in the " 2099 "phys_id_present_map\n", 2100 mpc_ioapic_id(apic_id)); 2101 physids_or(phys_id_present_map, phys_id_present_map, tmp); 2102 } 2103 2104 /* 2105 * We need to adjust the IRQ routing table 2106 * if the ID changed. 2107 */ 2108 if (old_id != mpc_ioapic_id(apic_id)) 2109 for (i = 0; i < mp_irq_entries; i++) 2110 if (mp_irqs[i].dstapic == old_id) 2111 mp_irqs[i].dstapic 2112 = mpc_ioapic_id(apic_id); 2113 2114 /* 2115 * Update the ID register according to the right value 2116 * from the MPC table if they are different. 2117 */ 2118 if (mpc_ioapic_id(apic_id) == reg_00.bits.ID) 2119 continue; 2120 2121 apic_printk(APIC_VERBOSE, KERN_INFO 2122 "...changing IO-APIC physical APIC ID to %d ...", 2123 mpc_ioapic_id(apic_id)); 2124 2125 reg_00.bits.ID = mpc_ioapic_id(apic_id); 2126 raw_spin_lock_irqsave(&ioapic_lock, flags); 2127 io_apic_write(apic_id, 0, reg_00.raw); 2128 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 2129 2130 /* 2131 * Sanity check 2132 */ 2133 raw_spin_lock_irqsave(&ioapic_lock, flags); 2134 reg_00.raw = io_apic_read(apic_id, 0); 2135 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 2136 if (reg_00.bits.ID != mpc_ioapic_id(apic_id)) 2137 printk("could not set ID!\n"); 2138 else 2139 apic_printk(APIC_VERBOSE, " ok.\n"); 2140 } 2141 } 2142 2143 void __init setup_ioapic_ids_from_mpc(void) 2144 { 2145 2146 if (acpi_ioapic) 2147 return; 2148 /* 2149 * Don't check I/O APIC IDs for xAPIC systems. They have 2150 * no meaning without the serial APIC bus. 2151 */ 2152 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 2153 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) 2154 return; 2155 setup_ioapic_ids_from_mpc_nocheck(); 2156 } 2157 #endif 2158 2159 int no_timer_check __initdata; 2160 2161 static int __init notimercheck(char *s) 2162 { 2163 no_timer_check = 1; 2164 return 1; 2165 } 2166 __setup("no_timer_check", notimercheck); 2167 2168 /* 2169 * There is a nasty bug in some older SMP boards, their mptable lies 2170 * about the timer IRQ. We do the following to work around the situation: 2171 * 2172 * - timer IRQ defaults to IO-APIC IRQ 2173 * - if this function detects that timer IRQs are defunct, then we fall 2174 * back to ISA timer IRQs 2175 */ 2176 static int __init timer_irq_works(void) 2177 { 2178 unsigned long t1 = jiffies; 2179 unsigned long flags; 2180 2181 if (no_timer_check) 2182 return 1; 2183 2184 local_save_flags(flags); 2185 local_irq_enable(); 2186 /* Let ten ticks pass... */ 2187 mdelay((10 * 1000) / HZ); 2188 local_irq_restore(flags); 2189 2190 /* 2191 * Expect a few ticks at least, to be sure some possible 2192 * glue logic does not lock up after one or two first 2193 * ticks in a non-ExtINT mode. Also the local APIC 2194 * might have cached one ExtINT interrupt. Finally, at 2195 * least one tick may be lost due to delays. 2196 */ 2197 2198 /* jiffies wrap? */ 2199 if (time_after(jiffies, t1 + 4)) 2200 return 1; 2201 return 0; 2202 } 2203 2204 /* 2205 * In the SMP+IOAPIC case it might happen that there are an unspecified 2206 * number of pending IRQ events unhandled. These cases are very rare, 2207 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much 2208 * better to do it this way as thus we do not have to be aware of 2209 * 'pending' interrupts in the IRQ path, except at this point. 2210 */ 2211 /* 2212 * Edge triggered needs to resend any interrupt 2213 * that was delayed but this is now handled in the device 2214 * independent code. 2215 */ 2216 2217 /* 2218 * Starting up a edge-triggered IO-APIC interrupt is 2219 * nasty - we need to make sure that we get the edge. 2220 * If it is already asserted for some reason, we need 2221 * return 1 to indicate that is was pending. 2222 * 2223 * This is not complete - we should be able to fake 2224 * an edge even if it isn't on the 8259A... 2225 */ 2226 2227 static unsigned int startup_ioapic_irq(struct irq_data *data) 2228 { 2229 int was_pending = 0, irq = data->irq; 2230 unsigned long flags; 2231 2232 raw_spin_lock_irqsave(&ioapic_lock, flags); 2233 if (irq < legacy_pic->nr_legacy_irqs) { 2234 legacy_pic->mask(irq); 2235 if (legacy_pic->irq_pending(irq)) 2236 was_pending = 1; 2237 } 2238 __unmask_ioapic(data->chip_data); 2239 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 2240 2241 return was_pending; 2242 } 2243 2244 static int ioapic_retrigger_irq(struct irq_data *data) 2245 { 2246 struct irq_cfg *cfg = data->chip_data; 2247 unsigned long flags; 2248 2249 raw_spin_lock_irqsave(&vector_lock, flags); 2250 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector); 2251 raw_spin_unlock_irqrestore(&vector_lock, flags); 2252 2253 return 1; 2254 } 2255 2256 /* 2257 * Level and edge triggered IO-APIC interrupts need different handling, 2258 * so we use two separate IRQ descriptors. Edge triggered IRQs can be 2259 * handled with the level-triggered descriptor, but that one has slightly 2260 * more overhead. Level-triggered interrupts cannot be handled with the 2261 * edge-triggered handler, without risking IRQ storms and other ugly 2262 * races. 2263 */ 2264 2265 #ifdef CONFIG_SMP 2266 void send_cleanup_vector(struct irq_cfg *cfg) 2267 { 2268 cpumask_var_t cleanup_mask; 2269 2270 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { 2271 unsigned int i; 2272 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) 2273 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); 2274 } else { 2275 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); 2276 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); 2277 free_cpumask_var(cleanup_mask); 2278 } 2279 cfg->move_in_progress = 0; 2280 } 2281 2282 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) 2283 { 2284 int apic, pin; 2285 struct irq_pin_list *entry; 2286 u8 vector = cfg->vector; 2287 2288 for_each_irq_pin(entry, cfg->irq_2_pin) { 2289 unsigned int reg; 2290 2291 apic = entry->apic; 2292 pin = entry->pin; 2293 /* 2294 * With interrupt-remapping, destination information comes 2295 * from interrupt-remapping table entry. 2296 */ 2297 if (!irq_remapped(cfg)) 2298 io_apic_write(apic, 0x11 + pin*2, dest); 2299 reg = io_apic_read(apic, 0x10 + pin*2); 2300 reg &= ~IO_APIC_REDIR_VECTOR_MASK; 2301 reg |= vector; 2302 io_apic_modify(apic, 0x10 + pin*2, reg); 2303 } 2304 } 2305 2306 /* 2307 * Either sets data->affinity to a valid value, and returns 2308 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and 2309 * leaves data->affinity untouched. 2310 */ 2311 int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, 2312 unsigned int *dest_id) 2313 { 2314 struct irq_cfg *cfg = data->chip_data; 2315 2316 if (!cpumask_intersects(mask, cpu_online_mask)) 2317 return -1; 2318 2319 if (assign_irq_vector(data->irq, data->chip_data, mask)) 2320 return -1; 2321 2322 cpumask_copy(data->affinity, mask); 2323 2324 *dest_id = apic->cpu_mask_to_apicid_and(mask, cfg->domain); 2325 return 0; 2326 } 2327 2328 static int 2329 ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, 2330 bool force) 2331 { 2332 unsigned int dest, irq = data->irq; 2333 unsigned long flags; 2334 int ret; 2335 2336 raw_spin_lock_irqsave(&ioapic_lock, flags); 2337 ret = __ioapic_set_affinity(data, mask, &dest); 2338 if (!ret) { 2339 /* Only the high 8 bits are valid. */ 2340 dest = SET_APIC_LOGICAL_ID(dest); 2341 __target_IO_APIC_irq(irq, dest, data->chip_data); 2342 } 2343 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 2344 return ret; 2345 } 2346 2347 #ifdef CONFIG_IRQ_REMAP 2348 2349 /* 2350 * Migrate the IO-APIC irq in the presence of intr-remapping. 2351 * 2352 * For both level and edge triggered, irq migration is a simple atomic 2353 * update(of vector and cpu destination) of IRTE and flush the hardware cache. 2354 * 2355 * For level triggered, we eliminate the io-apic RTE modification (with the 2356 * updated vector information), by using a virtual vector (io-apic pin number). 2357 * Real vector that is used for interrupting cpu will be coming from 2358 * the interrupt-remapping table entry. 2359 * 2360 * As the migration is a simple atomic update of IRTE, the same mechanism 2361 * is used to migrate MSI irq's in the presence of interrupt-remapping. 2362 */ 2363 static int 2364 ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, 2365 bool force) 2366 { 2367 struct irq_cfg *cfg = data->chip_data; 2368 unsigned int dest, irq = data->irq; 2369 struct irte irte; 2370 2371 if (!cpumask_intersects(mask, cpu_online_mask)) 2372 return -EINVAL; 2373 2374 if (get_irte(irq, &irte)) 2375 return -EBUSY; 2376 2377 if (assign_irq_vector(irq, cfg, mask)) 2378 return -EBUSY; 2379 2380 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask); 2381 2382 irte.vector = cfg->vector; 2383 irte.dest_id = IRTE_DEST(dest); 2384 2385 /* 2386 * Atomically updates the IRTE with the new destination, vector 2387 * and flushes the interrupt entry cache. 2388 */ 2389 modify_irte(irq, &irte); 2390 2391 /* 2392 * After this point, all the interrupts will start arriving 2393 * at the new destination. So, time to cleanup the previous 2394 * vector allocation. 2395 */ 2396 if (cfg->move_in_progress) 2397 send_cleanup_vector(cfg); 2398 2399 cpumask_copy(data->affinity, mask); 2400 return 0; 2401 } 2402 2403 #else 2404 static inline int 2405 ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, 2406 bool force) 2407 { 2408 return 0; 2409 } 2410 #endif 2411 2412 asmlinkage void smp_irq_move_cleanup_interrupt(void) 2413 { 2414 unsigned vector, me; 2415 2416 ack_APIC_irq(); 2417 exit_idle(); 2418 irq_enter(); 2419 2420 me = smp_processor_id(); 2421 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { 2422 unsigned int irq; 2423 unsigned int irr; 2424 struct irq_desc *desc; 2425 struct irq_cfg *cfg; 2426 irq = __this_cpu_read(vector_irq[vector]); 2427 2428 if (irq == -1) 2429 continue; 2430 2431 desc = irq_to_desc(irq); 2432 if (!desc) 2433 continue; 2434 2435 cfg = irq_cfg(irq); 2436 raw_spin_lock(&desc->lock); 2437 2438 /* 2439 * Check if the irq migration is in progress. If so, we 2440 * haven't received the cleanup request yet for this irq. 2441 */ 2442 if (cfg->move_in_progress) 2443 goto unlock; 2444 2445 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) 2446 goto unlock; 2447 2448 irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); 2449 /* 2450 * Check if the vector that needs to be cleanedup is 2451 * registered at the cpu's IRR. If so, then this is not 2452 * the best time to clean it up. Lets clean it up in the 2453 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR 2454 * to myself. 2455 */ 2456 if (irr & (1 << (vector % 32))) { 2457 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); 2458 goto unlock; 2459 } 2460 __this_cpu_write(vector_irq[vector], -1); 2461 unlock: 2462 raw_spin_unlock(&desc->lock); 2463 } 2464 2465 irq_exit(); 2466 } 2467 2468 static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) 2469 { 2470 unsigned me; 2471 2472 if (likely(!cfg->move_in_progress)) 2473 return; 2474 2475 me = smp_processor_id(); 2476 2477 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) 2478 send_cleanup_vector(cfg); 2479 } 2480 2481 static void irq_complete_move(struct irq_cfg *cfg) 2482 { 2483 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); 2484 } 2485 2486 void irq_force_complete_move(int irq) 2487 { 2488 struct irq_cfg *cfg = irq_get_chip_data(irq); 2489 2490 if (!cfg) 2491 return; 2492 2493 __irq_complete_move(cfg, cfg->vector); 2494 } 2495 #else 2496 static inline void irq_complete_move(struct irq_cfg *cfg) { } 2497 #endif 2498 2499 static void ack_apic_edge(struct irq_data *data) 2500 { 2501 irq_complete_move(data->chip_data); 2502 irq_move_irq(data); 2503 ack_APIC_irq(); 2504 } 2505 2506 atomic_t irq_mis_count; 2507 2508 static void ack_apic_level(struct irq_data *data) 2509 { 2510 struct irq_cfg *cfg = data->chip_data; 2511 int i, do_unmask_irq = 0, irq = data->irq; 2512 unsigned long v; 2513 2514 irq_complete_move(cfg); 2515 #ifdef CONFIG_GENERIC_PENDING_IRQ 2516 /* If we are moving the irq we need to mask it */ 2517 if (unlikely(irqd_is_setaffinity_pending(data))) { 2518 do_unmask_irq = 1; 2519 mask_ioapic(cfg); 2520 } 2521 #endif 2522 2523 /* 2524 * It appears there is an erratum which affects at least version 0x11 2525 * of I/O APIC (that's the 82093AA and cores integrated into various 2526 * chipsets). Under certain conditions a level-triggered interrupt is 2527 * erroneously delivered as edge-triggered one but the respective IRR 2528 * bit gets set nevertheless. As a result the I/O unit expects an EOI 2529 * message but it will never arrive and further interrupts are blocked 2530 * from the source. The exact reason is so far unknown, but the 2531 * phenomenon was observed when two consecutive interrupt requests 2532 * from a given source get delivered to the same CPU and the source is 2533 * temporarily disabled in between. 2534 * 2535 * A workaround is to simulate an EOI message manually. We achieve it 2536 * by setting the trigger mode to edge and then to level when the edge 2537 * trigger mode gets detected in the TMR of a local APIC for a 2538 * level-triggered interrupt. We mask the source for the time of the 2539 * operation to prevent an edge-triggered interrupt escaping meanwhile. 2540 * The idea is from Manfred Spraul. --macro 2541 * 2542 * Also in the case when cpu goes offline, fixup_irqs() will forward 2543 * any unhandled interrupt on the offlined cpu to the new cpu 2544 * destination that is handling the corresponding interrupt. This 2545 * interrupt forwarding is done via IPI's. Hence, in this case also 2546 * level-triggered io-apic interrupt will be seen as an edge 2547 * interrupt in the IRR. And we can't rely on the cpu's EOI 2548 * to be broadcasted to the IO-APIC's which will clear the remoteIRR 2549 * corresponding to the level-triggered interrupt. Hence on IO-APIC's 2550 * supporting EOI register, we do an explicit EOI to clear the 2551 * remote IRR and on IO-APIC's which don't have an EOI register, 2552 * we use the above logic (mask+edge followed by unmask+level) from 2553 * Manfred Spraul to clear the remote IRR. 2554 */ 2555 i = cfg->vector; 2556 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); 2557 2558 /* 2559 * We must acknowledge the irq before we move it or the acknowledge will 2560 * not propagate properly. 2561 */ 2562 ack_APIC_irq(); 2563 2564 /* 2565 * Tail end of clearing remote IRR bit (either by delivering the EOI 2566 * message via io-apic EOI register write or simulating it using 2567 * mask+edge followed by unnask+level logic) manually when the 2568 * level triggered interrupt is seen as the edge triggered interrupt 2569 * at the cpu. 2570 */ 2571 if (!(v & (1 << (i & 0x1f)))) { 2572 atomic_inc(&irq_mis_count); 2573 2574 eoi_ioapic_irq(irq, cfg); 2575 } 2576 2577 /* Now we can move and renable the irq */ 2578 if (unlikely(do_unmask_irq)) { 2579 /* Only migrate the irq if the ack has been received. 2580 * 2581 * On rare occasions the broadcast level triggered ack gets 2582 * delayed going to ioapics, and if we reprogram the 2583 * vector while Remote IRR is still set the irq will never 2584 * fire again. 2585 * 2586 * To prevent this scenario we read the Remote IRR bit 2587 * of the ioapic. This has two effects. 2588 * - On any sane system the read of the ioapic will 2589 * flush writes (and acks) going to the ioapic from 2590 * this cpu. 2591 * - We get to see if the ACK has actually been delivered. 2592 * 2593 * Based on failed experiments of reprogramming the 2594 * ioapic entry from outside of irq context starting 2595 * with masking the ioapic entry and then polling until 2596 * Remote IRR was clear before reprogramming the 2597 * ioapic I don't trust the Remote IRR bit to be 2598 * completey accurate. 2599 * 2600 * However there appears to be no other way to plug 2601 * this race, so if the Remote IRR bit is not 2602 * accurate and is causing problems then it is a hardware bug 2603 * and you can go talk to the chipset vendor about it. 2604 */ 2605 if (!io_apic_level_ack_pending(cfg)) 2606 irq_move_masked_irq(data); 2607 unmask_ioapic(cfg); 2608 } 2609 } 2610 2611 #ifdef CONFIG_IRQ_REMAP 2612 static void ir_ack_apic_edge(struct irq_data *data) 2613 { 2614 ack_APIC_irq(); 2615 } 2616 2617 static void ir_ack_apic_level(struct irq_data *data) 2618 { 2619 ack_APIC_irq(); 2620 eoi_ioapic_irq(data->irq, data->chip_data); 2621 } 2622 2623 static void ir_print_prefix(struct irq_data *data, struct seq_file *p) 2624 { 2625 seq_printf(p, " IR-%s", data->chip->name); 2626 } 2627 2628 static void irq_remap_modify_chip_defaults(struct irq_chip *chip) 2629 { 2630 chip->irq_print_chip = ir_print_prefix; 2631 chip->irq_ack = ir_ack_apic_edge; 2632 chip->irq_eoi = ir_ack_apic_level; 2633 2634 #ifdef CONFIG_SMP 2635 chip->irq_set_affinity = ir_ioapic_set_affinity; 2636 #endif 2637 } 2638 #endif /* CONFIG_IRQ_REMAP */ 2639 2640 static struct irq_chip ioapic_chip __read_mostly = { 2641 .name = "IO-APIC", 2642 .irq_startup = startup_ioapic_irq, 2643 .irq_mask = mask_ioapic_irq, 2644 .irq_unmask = unmask_ioapic_irq, 2645 .irq_ack = ack_apic_edge, 2646 .irq_eoi = ack_apic_level, 2647 #ifdef CONFIG_SMP 2648 .irq_set_affinity = ioapic_set_affinity, 2649 #endif 2650 .irq_retrigger = ioapic_retrigger_irq, 2651 }; 2652 2653 static inline void init_IO_APIC_traps(void) 2654 { 2655 struct irq_cfg *cfg; 2656 unsigned int irq; 2657 2658 /* 2659 * NOTE! The local APIC isn't very good at handling 2660 * multiple interrupts at the same interrupt level. 2661 * As the interrupt level is determined by taking the 2662 * vector number and shifting that right by 4, we 2663 * want to spread these out a bit so that they don't 2664 * all fall in the same interrupt level. 2665 * 2666 * Also, we've got to be careful not to trash gate 2667 * 0x80, because int 0x80 is hm, kind of importantish. ;) 2668 */ 2669 for_each_active_irq(irq) { 2670 cfg = irq_get_chip_data(irq); 2671 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { 2672 /* 2673 * Hmm.. We don't have an entry for this, 2674 * so default to an old-fashioned 8259 2675 * interrupt if we can.. 2676 */ 2677 if (irq < legacy_pic->nr_legacy_irqs) 2678 legacy_pic->make_irq(irq); 2679 else 2680 /* Strange. Oh, well.. */ 2681 irq_set_chip(irq, &no_irq_chip); 2682 } 2683 } 2684 } 2685 2686 /* 2687 * The local APIC irq-chip implementation: 2688 */ 2689 2690 static void mask_lapic_irq(struct irq_data *data) 2691 { 2692 unsigned long v; 2693 2694 v = apic_read(APIC_LVT0); 2695 apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 2696 } 2697 2698 static void unmask_lapic_irq(struct irq_data *data) 2699 { 2700 unsigned long v; 2701 2702 v = apic_read(APIC_LVT0); 2703 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); 2704 } 2705 2706 static void ack_lapic_irq(struct irq_data *data) 2707 { 2708 ack_APIC_irq(); 2709 } 2710 2711 static struct irq_chip lapic_chip __read_mostly = { 2712 .name = "local-APIC", 2713 .irq_mask = mask_lapic_irq, 2714 .irq_unmask = unmask_lapic_irq, 2715 .irq_ack = ack_lapic_irq, 2716 }; 2717 2718 static void lapic_register_intr(int irq) 2719 { 2720 irq_clear_status_flags(irq, IRQ_LEVEL); 2721 irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, 2722 "edge"); 2723 } 2724 2725 /* 2726 * This looks a bit hackish but it's about the only one way of sending 2727 * a few INTA cycles to 8259As and any associated glue logic. ICR does 2728 * not support the ExtINT mode, unfortunately. We need to send these 2729 * cycles as some i82489DX-based boards have glue logic that keeps the 2730 * 8259A interrupt line asserted until INTA. --macro 2731 */ 2732 static inline void __init unlock_ExtINT_logic(void) 2733 { 2734 int apic, pin, i; 2735 struct IO_APIC_route_entry entry0, entry1; 2736 unsigned char save_control, save_freq_select; 2737 2738 pin = find_isa_irq_pin(8, mp_INT); 2739 if (pin == -1) { 2740 WARN_ON_ONCE(1); 2741 return; 2742 } 2743 apic = find_isa_irq_apic(8, mp_INT); 2744 if (apic == -1) { 2745 WARN_ON_ONCE(1); 2746 return; 2747 } 2748 2749 entry0 = ioapic_read_entry(apic, pin); 2750 clear_IO_APIC_pin(apic, pin); 2751 2752 memset(&entry1, 0, sizeof(entry1)); 2753 2754 entry1.dest_mode = 0; /* physical delivery */ 2755 entry1.mask = 0; /* unmask IRQ now */ 2756 entry1.dest = hard_smp_processor_id(); 2757 entry1.delivery_mode = dest_ExtINT; 2758 entry1.polarity = entry0.polarity; 2759 entry1.trigger = 0; 2760 entry1.vector = 0; 2761 2762 ioapic_write_entry(apic, pin, entry1); 2763 2764 save_control = CMOS_READ(RTC_CONTROL); 2765 save_freq_select = CMOS_READ(RTC_FREQ_SELECT); 2766 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, 2767 RTC_FREQ_SELECT); 2768 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); 2769 2770 i = 100; 2771 while (i-- > 0) { 2772 mdelay(10); 2773 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) 2774 i -= 10; 2775 } 2776 2777 CMOS_WRITE(save_control, RTC_CONTROL); 2778 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); 2779 clear_IO_APIC_pin(apic, pin); 2780 2781 ioapic_write_entry(apic, pin, entry0); 2782 } 2783 2784 static int disable_timer_pin_1 __initdata; 2785 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ 2786 static int __init disable_timer_pin_setup(char *arg) 2787 { 2788 disable_timer_pin_1 = 1; 2789 return 0; 2790 } 2791 early_param("disable_timer_pin_1", disable_timer_pin_setup); 2792 2793 int timer_through_8259 __initdata; 2794 2795 /* 2796 * This code may look a bit paranoid, but it's supposed to cooperate with 2797 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ 2798 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast 2799 * fanatically on his truly buggy board. 2800 * 2801 * FIXME: really need to revamp this for all platforms. 2802 */ 2803 static inline void __init check_timer(void) 2804 { 2805 struct irq_cfg *cfg = irq_get_chip_data(0); 2806 int node = cpu_to_node(0); 2807 int apic1, pin1, apic2, pin2; 2808 unsigned long flags; 2809 int no_pin1 = 0; 2810 2811 local_irq_save(flags); 2812 2813 /* 2814 * get/set the timer IRQ vector: 2815 */ 2816 legacy_pic->mask(0); 2817 assign_irq_vector(0, cfg, apic->target_cpus()); 2818 2819 /* 2820 * As IRQ0 is to be enabled in the 8259A, the virtual 2821 * wire has to be disabled in the local APIC. Also 2822 * timer interrupts need to be acknowledged manually in 2823 * the 8259A for the i82489DX when using the NMI 2824 * watchdog as that APIC treats NMIs as level-triggered. 2825 * The AEOI mode will finish them in the 8259A 2826 * automatically. 2827 */ 2828 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); 2829 legacy_pic->init(1); 2830 2831 pin1 = find_isa_irq_pin(0, mp_INT); 2832 apic1 = find_isa_irq_apic(0, mp_INT); 2833 pin2 = ioapic_i8259.pin; 2834 apic2 = ioapic_i8259.apic; 2835 2836 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " 2837 "apic1=%d pin1=%d apic2=%d pin2=%d\n", 2838 cfg->vector, apic1, pin1, apic2, pin2); 2839 2840 /* 2841 * Some BIOS writers are clueless and report the ExtINTA 2842 * I/O APIC input from the cascaded 8259A as the timer 2843 * interrupt input. So just in case, if only one pin 2844 * was found above, try it both directly and through the 2845 * 8259A. 2846 */ 2847 if (pin1 == -1) { 2848 if (intr_remapping_enabled) 2849 panic("BIOS bug: timer not connected to IO-APIC"); 2850 pin1 = pin2; 2851 apic1 = apic2; 2852 no_pin1 = 1; 2853 } else if (pin2 == -1) { 2854 pin2 = pin1; 2855 apic2 = apic1; 2856 } 2857 2858 if (pin1 != -1) { 2859 /* 2860 * Ok, does IRQ0 through the IOAPIC work? 2861 */ 2862 if (no_pin1) { 2863 add_pin_to_irq_node(cfg, node, apic1, pin1); 2864 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); 2865 } else { 2866 /* for edge trigger, setup_ioapic_irq already 2867 * leave it unmasked. 2868 * so only need to unmask if it is level-trigger 2869 * do we really have level trigger timer? 2870 */ 2871 int idx; 2872 idx = find_irq_entry(apic1, pin1, mp_INT); 2873 if (idx != -1 && irq_trigger(idx)) 2874 unmask_ioapic(cfg); 2875 } 2876 if (timer_irq_works()) { 2877 if (disable_timer_pin_1 > 0) 2878 clear_IO_APIC_pin(0, pin1); 2879 goto out; 2880 } 2881 if (intr_remapping_enabled) 2882 panic("timer doesn't work through Interrupt-remapped IO-APIC"); 2883 local_irq_disable(); 2884 clear_IO_APIC_pin(apic1, pin1); 2885 if (!no_pin1) 2886 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " 2887 "8254 timer not connected to IO-APIC\n"); 2888 2889 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " 2890 "(IRQ0) through the 8259A ...\n"); 2891 apic_printk(APIC_QUIET, KERN_INFO 2892 "..... (found apic %d pin %d) ...\n", apic2, pin2); 2893 /* 2894 * legacy devices should be connected to IO APIC #0 2895 */ 2896 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2); 2897 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); 2898 legacy_pic->unmask(0); 2899 if (timer_irq_works()) { 2900 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); 2901 timer_through_8259 = 1; 2902 goto out; 2903 } 2904 /* 2905 * Cleanup, just in case ... 2906 */ 2907 local_irq_disable(); 2908 legacy_pic->mask(0); 2909 clear_IO_APIC_pin(apic2, pin2); 2910 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); 2911 } 2912 2913 apic_printk(APIC_QUIET, KERN_INFO 2914 "...trying to set up timer as Virtual Wire IRQ...\n"); 2915 2916 lapic_register_intr(0); 2917 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ 2918 legacy_pic->unmask(0); 2919 2920 if (timer_irq_works()) { 2921 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); 2922 goto out; 2923 } 2924 local_irq_disable(); 2925 legacy_pic->mask(0); 2926 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); 2927 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); 2928 2929 apic_printk(APIC_QUIET, KERN_INFO 2930 "...trying to set up timer as ExtINT IRQ...\n"); 2931 2932 legacy_pic->init(0); 2933 legacy_pic->make_irq(0); 2934 apic_write(APIC_LVT0, APIC_DM_EXTINT); 2935 2936 unlock_ExtINT_logic(); 2937 2938 if (timer_irq_works()) { 2939 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); 2940 goto out; 2941 } 2942 local_irq_disable(); 2943 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); 2944 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " 2945 "report. Then try booting with the 'noapic' option.\n"); 2946 out: 2947 local_irq_restore(flags); 2948 } 2949 2950 /* 2951 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available 2952 * to devices. However there may be an I/O APIC pin available for 2953 * this interrupt regardless. The pin may be left unconnected, but 2954 * typically it will be reused as an ExtINT cascade interrupt for 2955 * the master 8259A. In the MPS case such a pin will normally be 2956 * reported as an ExtINT interrupt in the MP table. With ACPI 2957 * there is no provision for ExtINT interrupts, and in the absence 2958 * of an override it would be treated as an ordinary ISA I/O APIC 2959 * interrupt, that is edge-triggered and unmasked by default. We 2960 * used to do this, but it caused problems on some systems because 2961 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using 2962 * the same ExtINT cascade interrupt to drive the local APIC of the 2963 * bootstrap processor. Therefore we refrain from routing IRQ2 to 2964 * the I/O APIC in all cases now. No actual device should request 2965 * it anyway. --macro 2966 */ 2967 #define PIC_IRQS (1UL << PIC_CASCADE_IR) 2968 2969 void __init setup_IO_APIC(void) 2970 { 2971 2972 /* 2973 * calling enable_IO_APIC() is moved to setup_local_APIC for BP 2974 */ 2975 io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL; 2976 2977 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); 2978 /* 2979 * Set up IO-APIC IRQ routing. 2980 */ 2981 x86_init.mpparse.setup_ioapic_ids(); 2982 2983 sync_Arb_IDs(); 2984 setup_IO_APIC_irqs(); 2985 init_IO_APIC_traps(); 2986 if (legacy_pic->nr_legacy_irqs) 2987 check_timer(); 2988 } 2989 2990 /* 2991 * Called after all the initialization is done. If we didn't find any 2992 * APIC bugs then we can allow the modify fast path 2993 */ 2994 2995 static int __init io_apic_bug_finalize(void) 2996 { 2997 if (sis_apic_bug == -1) 2998 sis_apic_bug = 0; 2999 return 0; 3000 } 3001 3002 late_initcall(io_apic_bug_finalize); 3003 3004 static void resume_ioapic_id(int ioapic_id) 3005 { 3006 unsigned long flags; 3007 union IO_APIC_reg_00 reg_00; 3008 3009 3010 raw_spin_lock_irqsave(&ioapic_lock, flags); 3011 reg_00.raw = io_apic_read(ioapic_id, 0); 3012 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_id)) { 3013 reg_00.bits.ID = mpc_ioapic_id(ioapic_id); 3014 io_apic_write(ioapic_id, 0, reg_00.raw); 3015 } 3016 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 3017 } 3018 3019 static void ioapic_resume(void) 3020 { 3021 int ioapic_id; 3022 3023 for (ioapic_id = nr_ioapics - 1; ioapic_id >= 0; ioapic_id--) 3024 resume_ioapic_id(ioapic_id); 3025 3026 restore_ioapic_entries(); 3027 } 3028 3029 static struct syscore_ops ioapic_syscore_ops = { 3030 .suspend = save_ioapic_entries, 3031 .resume = ioapic_resume, 3032 }; 3033 3034 static int __init ioapic_init_ops(void) 3035 { 3036 register_syscore_ops(&ioapic_syscore_ops); 3037 3038 return 0; 3039 } 3040 3041 device_initcall(ioapic_init_ops); 3042 3043 /* 3044 * Dynamic irq allocate and deallocation 3045 */ 3046 unsigned int create_irq_nr(unsigned int from, int node) 3047 { 3048 struct irq_cfg *cfg; 3049 unsigned long flags; 3050 unsigned int ret = 0; 3051 int irq; 3052 3053 if (from < nr_irqs_gsi) 3054 from = nr_irqs_gsi; 3055 3056 irq = alloc_irq_from(from, node); 3057 if (irq < 0) 3058 return 0; 3059 cfg = alloc_irq_cfg(irq, node); 3060 if (!cfg) { 3061 free_irq_at(irq, NULL); 3062 return 0; 3063 } 3064 3065 raw_spin_lock_irqsave(&vector_lock, flags); 3066 if (!__assign_irq_vector(irq, cfg, apic->target_cpus())) 3067 ret = irq; 3068 raw_spin_unlock_irqrestore(&vector_lock, flags); 3069 3070 if (ret) { 3071 irq_set_chip_data(irq, cfg); 3072 irq_clear_status_flags(irq, IRQ_NOREQUEST); 3073 } else { 3074 free_irq_at(irq, cfg); 3075 } 3076 return ret; 3077 } 3078 3079 int create_irq(void) 3080 { 3081 int node = cpu_to_node(0); 3082 unsigned int irq_want; 3083 int irq; 3084 3085 irq_want = nr_irqs_gsi; 3086 irq = create_irq_nr(irq_want, node); 3087 3088 if (irq == 0) 3089 irq = -1; 3090 3091 return irq; 3092 } 3093 3094 void destroy_irq(unsigned int irq) 3095 { 3096 struct irq_cfg *cfg = irq_get_chip_data(irq); 3097 unsigned long flags; 3098 3099 irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE); 3100 3101 if (irq_remapped(cfg)) 3102 free_irte(irq); 3103 raw_spin_lock_irqsave(&vector_lock, flags); 3104 __clear_irq_vector(irq, cfg); 3105 raw_spin_unlock_irqrestore(&vector_lock, flags); 3106 free_irq_at(irq, cfg); 3107 } 3108 3109 /* 3110 * MSI message composition 3111 */ 3112 #ifdef CONFIG_PCI_MSI 3113 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, 3114 struct msi_msg *msg, u8 hpet_id) 3115 { 3116 struct irq_cfg *cfg; 3117 int err; 3118 unsigned dest; 3119 3120 if (disable_apic) 3121 return -ENXIO; 3122 3123 cfg = irq_cfg(irq); 3124 err = assign_irq_vector(irq, cfg, apic->target_cpus()); 3125 if (err) 3126 return err; 3127 3128 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus()); 3129 3130 if (irq_remapped(cfg)) { 3131 struct irte irte; 3132 int ir_index; 3133 u16 sub_handle; 3134 3135 ir_index = map_irq_to_irte_handle(irq, &sub_handle); 3136 BUG_ON(ir_index == -1); 3137 3138 prepare_irte(&irte, cfg->vector, dest); 3139 3140 /* Set source-id of interrupt request */ 3141 if (pdev) 3142 set_msi_sid(&irte, pdev); 3143 else 3144 set_hpet_sid(&irte, hpet_id); 3145 3146 modify_irte(irq, &irte); 3147 3148 msg->address_hi = MSI_ADDR_BASE_HI; 3149 msg->data = sub_handle; 3150 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT | 3151 MSI_ADDR_IR_SHV | 3152 MSI_ADDR_IR_INDEX1(ir_index) | 3153 MSI_ADDR_IR_INDEX2(ir_index); 3154 } else { 3155 if (x2apic_enabled()) 3156 msg->address_hi = MSI_ADDR_BASE_HI | 3157 MSI_ADDR_EXT_DEST_ID(dest); 3158 else 3159 msg->address_hi = MSI_ADDR_BASE_HI; 3160 3161 msg->address_lo = 3162 MSI_ADDR_BASE_LO | 3163 ((apic->irq_dest_mode == 0) ? 3164 MSI_ADDR_DEST_MODE_PHYSICAL: 3165 MSI_ADDR_DEST_MODE_LOGICAL) | 3166 ((apic->irq_delivery_mode != dest_LowestPrio) ? 3167 MSI_ADDR_REDIRECTION_CPU: 3168 MSI_ADDR_REDIRECTION_LOWPRI) | 3169 MSI_ADDR_DEST_ID(dest); 3170 3171 msg->data = 3172 MSI_DATA_TRIGGER_EDGE | 3173 MSI_DATA_LEVEL_ASSERT | 3174 ((apic->irq_delivery_mode != dest_LowestPrio) ? 3175 MSI_DATA_DELIVERY_FIXED: 3176 MSI_DATA_DELIVERY_LOWPRI) | 3177 MSI_DATA_VECTOR(cfg->vector); 3178 } 3179 return err; 3180 } 3181 3182 #ifdef CONFIG_SMP 3183 static int 3184 msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) 3185 { 3186 struct irq_cfg *cfg = data->chip_data; 3187 struct msi_msg msg; 3188 unsigned int dest; 3189 3190 if (__ioapic_set_affinity(data, mask, &dest)) 3191 return -1; 3192 3193 __get_cached_msi_msg(data->msi_desc, &msg); 3194 3195 msg.data &= ~MSI_DATA_VECTOR_MASK; 3196 msg.data |= MSI_DATA_VECTOR(cfg->vector); 3197 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; 3198 msg.address_lo |= MSI_ADDR_DEST_ID(dest); 3199 3200 __write_msi_msg(data->msi_desc, &msg); 3201 3202 return 0; 3203 } 3204 #endif /* CONFIG_SMP */ 3205 3206 /* 3207 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, 3208 * which implement the MSI or MSI-X Capability Structure. 3209 */ 3210 static struct irq_chip msi_chip = { 3211 .name = "PCI-MSI", 3212 .irq_unmask = unmask_msi_irq, 3213 .irq_mask = mask_msi_irq, 3214 .irq_ack = ack_apic_edge, 3215 #ifdef CONFIG_SMP 3216 .irq_set_affinity = msi_set_affinity, 3217 #endif 3218 .irq_retrigger = ioapic_retrigger_irq, 3219 }; 3220 3221 /* 3222 * Map the PCI dev to the corresponding remapping hardware unit 3223 * and allocate 'nvec' consecutive interrupt-remapping table entries 3224 * in it. 3225 */ 3226 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec) 3227 { 3228 struct intel_iommu *iommu; 3229 int index; 3230 3231 iommu = map_dev_to_ir(dev); 3232 if (!iommu) { 3233 printk(KERN_ERR 3234 "Unable to map PCI %s to iommu\n", pci_name(dev)); 3235 return -ENOENT; 3236 } 3237 3238 index = alloc_irte(iommu, irq, nvec); 3239 if (index < 0) { 3240 printk(KERN_ERR 3241 "Unable to allocate %d IRTE for PCI %s\n", nvec, 3242 pci_name(dev)); 3243 return -ENOSPC; 3244 } 3245 return index; 3246 } 3247 3248 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq) 3249 { 3250 struct irq_chip *chip = &msi_chip; 3251 struct msi_msg msg; 3252 int ret; 3253 3254 ret = msi_compose_msg(dev, irq, &msg, -1); 3255 if (ret < 0) 3256 return ret; 3257 3258 irq_set_msi_desc(irq, msidesc); 3259 write_msi_msg(irq, &msg); 3260 3261 if (irq_remapped(irq_get_chip_data(irq))) { 3262 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); 3263 irq_remap_modify_chip_defaults(chip); 3264 } 3265 3266 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge"); 3267 3268 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); 3269 3270 return 0; 3271 } 3272 3273 int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) 3274 { 3275 int node, ret, sub_handle, index = 0; 3276 unsigned int irq, irq_want; 3277 struct msi_desc *msidesc; 3278 struct intel_iommu *iommu = NULL; 3279 3280 /* x86 doesn't support multiple MSI yet */ 3281 if (type == PCI_CAP_ID_MSI && nvec > 1) 3282 return 1; 3283 3284 node = dev_to_node(&dev->dev); 3285 irq_want = nr_irqs_gsi; 3286 sub_handle = 0; 3287 list_for_each_entry(msidesc, &dev->msi_list, list) { 3288 irq = create_irq_nr(irq_want, node); 3289 if (irq == 0) 3290 return -1; 3291 irq_want = irq + 1; 3292 if (!intr_remapping_enabled) 3293 goto no_ir; 3294 3295 if (!sub_handle) { 3296 /* 3297 * allocate the consecutive block of IRTE's 3298 * for 'nvec' 3299 */ 3300 index = msi_alloc_irte(dev, irq, nvec); 3301 if (index < 0) { 3302 ret = index; 3303 goto error; 3304 } 3305 } else { 3306 iommu = map_dev_to_ir(dev); 3307 if (!iommu) { 3308 ret = -ENOENT; 3309 goto error; 3310 } 3311 /* 3312 * setup the mapping between the irq and the IRTE 3313 * base index, the sub_handle pointing to the 3314 * appropriate interrupt remap table entry. 3315 */ 3316 set_irte_irq(irq, iommu, index, sub_handle); 3317 } 3318 no_ir: 3319 ret = setup_msi_irq(dev, msidesc, irq); 3320 if (ret < 0) 3321 goto error; 3322 sub_handle++; 3323 } 3324 return 0; 3325 3326 error: 3327 destroy_irq(irq); 3328 return ret; 3329 } 3330 3331 void native_teardown_msi_irq(unsigned int irq) 3332 { 3333 destroy_irq(irq); 3334 } 3335 3336 #ifdef CONFIG_DMAR_TABLE 3337 #ifdef CONFIG_SMP 3338 static int 3339 dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask, 3340 bool force) 3341 { 3342 struct irq_cfg *cfg = data->chip_data; 3343 unsigned int dest, irq = data->irq; 3344 struct msi_msg msg; 3345 3346 if (__ioapic_set_affinity(data, mask, &dest)) 3347 return -1; 3348 3349 dmar_msi_read(irq, &msg); 3350 3351 msg.data &= ~MSI_DATA_VECTOR_MASK; 3352 msg.data |= MSI_DATA_VECTOR(cfg->vector); 3353 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; 3354 msg.address_lo |= MSI_ADDR_DEST_ID(dest); 3355 msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest); 3356 3357 dmar_msi_write(irq, &msg); 3358 3359 return 0; 3360 } 3361 3362 #endif /* CONFIG_SMP */ 3363 3364 static struct irq_chip dmar_msi_type = { 3365 .name = "DMAR_MSI", 3366 .irq_unmask = dmar_msi_unmask, 3367 .irq_mask = dmar_msi_mask, 3368 .irq_ack = ack_apic_edge, 3369 #ifdef CONFIG_SMP 3370 .irq_set_affinity = dmar_msi_set_affinity, 3371 #endif 3372 .irq_retrigger = ioapic_retrigger_irq, 3373 }; 3374 3375 int arch_setup_dmar_msi(unsigned int irq) 3376 { 3377 int ret; 3378 struct msi_msg msg; 3379 3380 ret = msi_compose_msg(NULL, irq, &msg, -1); 3381 if (ret < 0) 3382 return ret; 3383 dmar_msi_write(irq, &msg); 3384 irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, 3385 "edge"); 3386 return 0; 3387 } 3388 #endif 3389 3390 #ifdef CONFIG_HPET_TIMER 3391 3392 #ifdef CONFIG_SMP 3393 static int hpet_msi_set_affinity(struct irq_data *data, 3394 const struct cpumask *mask, bool force) 3395 { 3396 struct irq_cfg *cfg = data->chip_data; 3397 struct msi_msg msg; 3398 unsigned int dest; 3399 3400 if (__ioapic_set_affinity(data, mask, &dest)) 3401 return -1; 3402 3403 hpet_msi_read(data->handler_data, &msg); 3404 3405 msg.data &= ~MSI_DATA_VECTOR_MASK; 3406 msg.data |= MSI_DATA_VECTOR(cfg->vector); 3407 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; 3408 msg.address_lo |= MSI_ADDR_DEST_ID(dest); 3409 3410 hpet_msi_write(data->handler_data, &msg); 3411 3412 return 0; 3413 } 3414 3415 #endif /* CONFIG_SMP */ 3416 3417 static struct irq_chip hpet_msi_type = { 3418 .name = "HPET_MSI", 3419 .irq_unmask = hpet_msi_unmask, 3420 .irq_mask = hpet_msi_mask, 3421 .irq_ack = ack_apic_edge, 3422 #ifdef CONFIG_SMP 3423 .irq_set_affinity = hpet_msi_set_affinity, 3424 #endif 3425 .irq_retrigger = ioapic_retrigger_irq, 3426 }; 3427 3428 int arch_setup_hpet_msi(unsigned int irq, unsigned int id) 3429 { 3430 struct irq_chip *chip = &hpet_msi_type; 3431 struct msi_msg msg; 3432 int ret; 3433 3434 if (intr_remapping_enabled) { 3435 struct intel_iommu *iommu = map_hpet_to_ir(id); 3436 int index; 3437 3438 if (!iommu) 3439 return -1; 3440 3441 index = alloc_irte(iommu, irq, 1); 3442 if (index < 0) 3443 return -1; 3444 } 3445 3446 ret = msi_compose_msg(NULL, irq, &msg, id); 3447 if (ret < 0) 3448 return ret; 3449 3450 hpet_msi_write(irq_get_handler_data(irq), &msg); 3451 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); 3452 if (irq_remapped(irq_get_chip_data(irq))) 3453 irq_remap_modify_chip_defaults(chip); 3454 3455 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge"); 3456 return 0; 3457 } 3458 #endif 3459 3460 #endif /* CONFIG_PCI_MSI */ 3461 /* 3462 * Hypertransport interrupt support 3463 */ 3464 #ifdef CONFIG_HT_IRQ 3465 3466 #ifdef CONFIG_SMP 3467 3468 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) 3469 { 3470 struct ht_irq_msg msg; 3471 fetch_ht_irq_msg(irq, &msg); 3472 3473 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); 3474 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); 3475 3476 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); 3477 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); 3478 3479 write_ht_irq_msg(irq, &msg); 3480 } 3481 3482 static int 3483 ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) 3484 { 3485 struct irq_cfg *cfg = data->chip_data; 3486 unsigned int dest; 3487 3488 if (__ioapic_set_affinity(data, mask, &dest)) 3489 return -1; 3490 3491 target_ht_irq(data->irq, dest, cfg->vector); 3492 return 0; 3493 } 3494 3495 #endif 3496 3497 static struct irq_chip ht_irq_chip = { 3498 .name = "PCI-HT", 3499 .irq_mask = mask_ht_irq, 3500 .irq_unmask = unmask_ht_irq, 3501 .irq_ack = ack_apic_edge, 3502 #ifdef CONFIG_SMP 3503 .irq_set_affinity = ht_set_affinity, 3504 #endif 3505 .irq_retrigger = ioapic_retrigger_irq, 3506 }; 3507 3508 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) 3509 { 3510 struct irq_cfg *cfg; 3511 int err; 3512 3513 if (disable_apic) 3514 return -ENXIO; 3515 3516 cfg = irq_cfg(irq); 3517 err = assign_irq_vector(irq, cfg, apic->target_cpus()); 3518 if (!err) { 3519 struct ht_irq_msg msg; 3520 unsigned dest; 3521 3522 dest = apic->cpu_mask_to_apicid_and(cfg->domain, 3523 apic->target_cpus()); 3524 3525 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); 3526 3527 msg.address_lo = 3528 HT_IRQ_LOW_BASE | 3529 HT_IRQ_LOW_DEST_ID(dest) | 3530 HT_IRQ_LOW_VECTOR(cfg->vector) | 3531 ((apic->irq_dest_mode == 0) ? 3532 HT_IRQ_LOW_DM_PHYSICAL : 3533 HT_IRQ_LOW_DM_LOGICAL) | 3534 HT_IRQ_LOW_RQEOI_EDGE | 3535 ((apic->irq_delivery_mode != dest_LowestPrio) ? 3536 HT_IRQ_LOW_MT_FIXED : 3537 HT_IRQ_LOW_MT_ARBITRATED) | 3538 HT_IRQ_LOW_IRQ_MASKED; 3539 3540 write_ht_irq_msg(irq, &msg); 3541 3542 irq_set_chip_and_handler_name(irq, &ht_irq_chip, 3543 handle_edge_irq, "edge"); 3544 3545 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); 3546 } 3547 return err; 3548 } 3549 #endif /* CONFIG_HT_IRQ */ 3550 3551 static int 3552 io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr) 3553 { 3554 struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node); 3555 int ret; 3556 3557 if (!cfg) 3558 return -EINVAL; 3559 ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin); 3560 if (!ret) 3561 setup_ioapic_irq(attr->ioapic, attr->ioapic_pin, irq, cfg, 3562 attr->trigger, attr->polarity); 3563 return ret; 3564 } 3565 3566 int io_apic_setup_irq_pin_once(unsigned int irq, int node, 3567 struct io_apic_irq_attr *attr) 3568 { 3569 unsigned int id = attr->ioapic, pin = attr->ioapic_pin; 3570 int ret; 3571 3572 /* Avoid redundant programming */ 3573 if (test_bit(pin, ioapics[id].pin_programmed)) { 3574 pr_debug("Pin %d-%d already programmed\n", 3575 mpc_ioapic_id(id), pin); 3576 return 0; 3577 } 3578 ret = io_apic_setup_irq_pin(irq, node, attr); 3579 if (!ret) 3580 set_bit(pin, ioapics[id].pin_programmed); 3581 return ret; 3582 } 3583 3584 static int __init io_apic_get_redir_entries(int ioapic) 3585 { 3586 union IO_APIC_reg_01 reg_01; 3587 unsigned long flags; 3588 3589 raw_spin_lock_irqsave(&ioapic_lock, flags); 3590 reg_01.raw = io_apic_read(ioapic, 1); 3591 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 3592 3593 /* The register returns the maximum index redir index 3594 * supported, which is one less than the total number of redir 3595 * entries. 3596 */ 3597 return reg_01.bits.entries + 1; 3598 } 3599 3600 static void __init probe_nr_irqs_gsi(void) 3601 { 3602 int nr; 3603 3604 nr = gsi_top + NR_IRQS_LEGACY; 3605 if (nr > nr_irqs_gsi) 3606 nr_irqs_gsi = nr; 3607 3608 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi); 3609 } 3610 3611 int get_nr_irqs_gsi(void) 3612 { 3613 return nr_irqs_gsi; 3614 } 3615 3616 #ifdef CONFIG_SPARSE_IRQ 3617 int __init arch_probe_nr_irqs(void) 3618 { 3619 int nr; 3620 3621 if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) 3622 nr_irqs = NR_VECTORS * nr_cpu_ids; 3623 3624 nr = nr_irqs_gsi + 8 * nr_cpu_ids; 3625 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) 3626 /* 3627 * for MSI and HT dyn irq 3628 */ 3629 nr += nr_irqs_gsi * 16; 3630 #endif 3631 if (nr < nr_irqs) 3632 nr_irqs = nr; 3633 3634 return NR_IRQS_LEGACY; 3635 } 3636 #endif 3637 3638 int io_apic_set_pci_routing(struct device *dev, int irq, 3639 struct io_apic_irq_attr *irq_attr) 3640 { 3641 int node; 3642 3643 if (!IO_APIC_IRQ(irq)) { 3644 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", 3645 irq_attr->ioapic); 3646 return -EINVAL; 3647 } 3648 3649 node = dev ? dev_to_node(dev) : cpu_to_node(0); 3650 3651 return io_apic_setup_irq_pin_once(irq, node, irq_attr); 3652 } 3653 3654 #ifdef CONFIG_X86_32 3655 static int __init io_apic_get_unique_id(int ioapic, int apic_id) 3656 { 3657 union IO_APIC_reg_00 reg_00; 3658 static physid_mask_t apic_id_map = PHYSID_MASK_NONE; 3659 physid_mask_t tmp; 3660 unsigned long flags; 3661 int i = 0; 3662 3663 /* 3664 * The P4 platform supports up to 256 APIC IDs on two separate APIC 3665 * buses (one for LAPICs, one for IOAPICs), where predecessors only 3666 * supports up to 16 on one shared APIC bus. 3667 * 3668 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full 3669 * advantage of new APIC bus architecture. 3670 */ 3671 3672 if (physids_empty(apic_id_map)) 3673 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map); 3674 3675 raw_spin_lock_irqsave(&ioapic_lock, flags); 3676 reg_00.raw = io_apic_read(ioapic, 0); 3677 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 3678 3679 if (apic_id >= get_physical_broadcast()) { 3680 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " 3681 "%d\n", ioapic, apic_id, reg_00.bits.ID); 3682 apic_id = reg_00.bits.ID; 3683 } 3684 3685 /* 3686 * Every APIC in a system must have a unique ID or we get lots of nice 3687 * 'stuck on smp_invalidate_needed IPI wait' messages. 3688 */ 3689 if (apic->check_apicid_used(&apic_id_map, apic_id)) { 3690 3691 for (i = 0; i < get_physical_broadcast(); i++) { 3692 if (!apic->check_apicid_used(&apic_id_map, i)) 3693 break; 3694 } 3695 3696 if (i == get_physical_broadcast()) 3697 panic("Max apic_id exceeded!\n"); 3698 3699 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " 3700 "trying %d\n", ioapic, apic_id, i); 3701 3702 apic_id = i; 3703 } 3704 3705 apic->apicid_to_cpu_present(apic_id, &tmp); 3706 physids_or(apic_id_map, apic_id_map, tmp); 3707 3708 if (reg_00.bits.ID != apic_id) { 3709 reg_00.bits.ID = apic_id; 3710 3711 raw_spin_lock_irqsave(&ioapic_lock, flags); 3712 io_apic_write(ioapic, 0, reg_00.raw); 3713 reg_00.raw = io_apic_read(ioapic, 0); 3714 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 3715 3716 /* Sanity check */ 3717 if (reg_00.bits.ID != apic_id) { 3718 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic); 3719 return -1; 3720 } 3721 } 3722 3723 apic_printk(APIC_VERBOSE, KERN_INFO 3724 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); 3725 3726 return apic_id; 3727 } 3728 3729 static u8 __init io_apic_unique_id(u8 id) 3730 { 3731 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 3732 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) 3733 return io_apic_get_unique_id(nr_ioapics, id); 3734 else 3735 return id; 3736 } 3737 #else 3738 static u8 __init io_apic_unique_id(u8 id) 3739 { 3740 int i; 3741 DECLARE_BITMAP(used, 256); 3742 3743 bitmap_zero(used, 256); 3744 for (i = 0; i < nr_ioapics; i++) { 3745 __set_bit(mpc_ioapic_id(i), used); 3746 } 3747 if (!test_bit(id, used)) 3748 return id; 3749 return find_first_zero_bit(used, 256); 3750 } 3751 #endif 3752 3753 static int __init io_apic_get_version(int ioapic) 3754 { 3755 union IO_APIC_reg_01 reg_01; 3756 unsigned long flags; 3757 3758 raw_spin_lock_irqsave(&ioapic_lock, flags); 3759 reg_01.raw = io_apic_read(ioapic, 1); 3760 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 3761 3762 return reg_01.bits.version; 3763 } 3764 3765 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity) 3766 { 3767 int ioapic, pin, idx; 3768 3769 if (skip_ioapic_setup) 3770 return -1; 3771 3772 ioapic = mp_find_ioapic(gsi); 3773 if (ioapic < 0) 3774 return -1; 3775 3776 pin = mp_find_ioapic_pin(ioapic, gsi); 3777 if (pin < 0) 3778 return -1; 3779 3780 idx = find_irq_entry(ioapic, pin, mp_INT); 3781 if (idx < 0) 3782 return -1; 3783 3784 *trigger = irq_trigger(idx); 3785 *polarity = irq_polarity(idx); 3786 return 0; 3787 } 3788 3789 /* 3790 * This function currently is only a helper for the i386 smp boot process where 3791 * we need to reprogram the ioredtbls to cater for the cpus which have come online 3792 * so mask in all cases should simply be apic->target_cpus() 3793 */ 3794 #ifdef CONFIG_SMP 3795 void __init setup_ioapic_dest(void) 3796 { 3797 int pin, ioapic, irq, irq_entry; 3798 const struct cpumask *mask; 3799 struct irq_data *idata; 3800 3801 if (skip_ioapic_setup == 1) 3802 return; 3803 3804 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) 3805 for (pin = 0; pin < ioapics[ioapic].nr_registers; pin++) { 3806 irq_entry = find_irq_entry(ioapic, pin, mp_INT); 3807 if (irq_entry == -1) 3808 continue; 3809 irq = pin_2_irq(irq_entry, ioapic, pin); 3810 3811 if ((ioapic > 0) && (irq > 16)) 3812 continue; 3813 3814 idata = irq_get_irq_data(irq); 3815 3816 /* 3817 * Honour affinities which have been set in early boot 3818 */ 3819 if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata)) 3820 mask = idata->affinity; 3821 else 3822 mask = apic->target_cpus(); 3823 3824 if (intr_remapping_enabled) 3825 ir_ioapic_set_affinity(idata, mask, false); 3826 else 3827 ioapic_set_affinity(idata, mask, false); 3828 } 3829 3830 } 3831 #endif 3832 3833 #define IOAPIC_RESOURCE_NAME_SIZE 11 3834 3835 static struct resource *ioapic_resources; 3836 3837 static struct resource * __init ioapic_setup_resources(int nr_ioapics) 3838 { 3839 unsigned long n; 3840 struct resource *res; 3841 char *mem; 3842 int i; 3843 3844 if (nr_ioapics <= 0) 3845 return NULL; 3846 3847 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); 3848 n *= nr_ioapics; 3849 3850 mem = alloc_bootmem(n); 3851 res = (void *)mem; 3852 3853 mem += sizeof(struct resource) * nr_ioapics; 3854 3855 for (i = 0; i < nr_ioapics; i++) { 3856 res[i].name = mem; 3857 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; 3858 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i); 3859 mem += IOAPIC_RESOURCE_NAME_SIZE; 3860 } 3861 3862 ioapic_resources = res; 3863 3864 return res; 3865 } 3866 3867 void __init ioapic_and_gsi_init(void) 3868 { 3869 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; 3870 struct resource *ioapic_res; 3871 int i; 3872 3873 ioapic_res = ioapic_setup_resources(nr_ioapics); 3874 for (i = 0; i < nr_ioapics; i++) { 3875 if (smp_found_config) { 3876 ioapic_phys = mpc_ioapic_addr(i); 3877 #ifdef CONFIG_X86_32 3878 if (!ioapic_phys) { 3879 printk(KERN_ERR 3880 "WARNING: bogus zero IO-APIC " 3881 "address found in MPTABLE, " 3882 "disabling IO/APIC support!\n"); 3883 smp_found_config = 0; 3884 skip_ioapic_setup = 1; 3885 goto fake_ioapic_page; 3886 } 3887 #endif 3888 } else { 3889 #ifdef CONFIG_X86_32 3890 fake_ioapic_page: 3891 #endif 3892 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE); 3893 ioapic_phys = __pa(ioapic_phys); 3894 } 3895 set_fixmap_nocache(idx, ioapic_phys); 3896 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n", 3897 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), 3898 ioapic_phys); 3899 idx++; 3900 3901 ioapic_res->start = ioapic_phys; 3902 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1; 3903 ioapic_res++; 3904 } 3905 3906 probe_nr_irqs_gsi(); 3907 } 3908 3909 void __init ioapic_insert_resources(void) 3910 { 3911 int i; 3912 struct resource *r = ioapic_resources; 3913 3914 if (!r) { 3915 if (nr_ioapics > 0) 3916 printk(KERN_ERR 3917 "IO APIC resources couldn't be allocated.\n"); 3918 return; 3919 } 3920 3921 for (i = 0; i < nr_ioapics; i++) { 3922 insert_resource(&iomem_resource, r); 3923 r++; 3924 } 3925 } 3926 3927 int mp_find_ioapic(u32 gsi) 3928 { 3929 int i = 0; 3930 3931 if (nr_ioapics == 0) 3932 return -1; 3933 3934 /* Find the IOAPIC that manages this GSI. */ 3935 for (i = 0; i < nr_ioapics; i++) { 3936 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i); 3937 if ((gsi >= gsi_cfg->gsi_base) 3938 && (gsi <= gsi_cfg->gsi_end)) 3939 return i; 3940 } 3941 3942 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); 3943 return -1; 3944 } 3945 3946 int mp_find_ioapic_pin(int ioapic, u32 gsi) 3947 { 3948 struct mp_ioapic_gsi *gsi_cfg; 3949 3950 if (WARN_ON(ioapic == -1)) 3951 return -1; 3952 3953 gsi_cfg = mp_ioapic_gsi_routing(ioapic); 3954 if (WARN_ON(gsi > gsi_cfg->gsi_end)) 3955 return -1; 3956 3957 return gsi - gsi_cfg->gsi_base; 3958 } 3959 3960 static __init int bad_ioapic(unsigned long address) 3961 { 3962 if (nr_ioapics >= MAX_IO_APICS) { 3963 printk(KERN_WARNING "WARNING: Max # of I/O APICs (%d) exceeded " 3964 "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics); 3965 return 1; 3966 } 3967 if (!address) { 3968 printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address" 3969 " found in table, skipping!\n"); 3970 return 1; 3971 } 3972 return 0; 3973 } 3974 3975 void __init mp_register_ioapic(int id, u32 address, u32 gsi_base) 3976 { 3977 int idx = 0; 3978 int entries; 3979 struct mp_ioapic_gsi *gsi_cfg; 3980 3981 if (bad_ioapic(address)) 3982 return; 3983 3984 idx = nr_ioapics; 3985 3986 ioapics[idx].mp_config.type = MP_IOAPIC; 3987 ioapics[idx].mp_config.flags = MPC_APIC_USABLE; 3988 ioapics[idx].mp_config.apicaddr = address; 3989 3990 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); 3991 ioapics[idx].mp_config.apicid = io_apic_unique_id(id); 3992 ioapics[idx].mp_config.apicver = io_apic_get_version(idx); 3993 3994 /* 3995 * Build basic GSI lookup table to facilitate gsi->io_apic lookups 3996 * and to prevent reprogramming of IOAPIC pins (PCI GSIs). 3997 */ 3998 entries = io_apic_get_redir_entries(idx); 3999 gsi_cfg = mp_ioapic_gsi_routing(idx); 4000 gsi_cfg->gsi_base = gsi_base; 4001 gsi_cfg->gsi_end = gsi_base + entries - 1; 4002 4003 /* 4004 * The number of IO-APIC IRQ registers (== #pins): 4005 */ 4006 ioapics[idx].nr_registers = entries; 4007 4008 if (gsi_cfg->gsi_end >= gsi_top) 4009 gsi_top = gsi_cfg->gsi_end + 1; 4010 4011 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, " 4012 "GSI %d-%d\n", idx, mpc_ioapic_id(idx), 4013 mpc_ioapic_ver(idx), mpc_ioapic_addr(idx), 4014 gsi_cfg->gsi_base, gsi_cfg->gsi_end); 4015 4016 nr_ioapics++; 4017 } 4018 4019 /* Enable IOAPIC early just for system timer */ 4020 void __init pre_init_apic_IRQ0(void) 4021 { 4022 struct io_apic_irq_attr attr = { 0, 0, 0, 0 }; 4023 4024 printk(KERN_INFO "Early APIC setup for system timer0\n"); 4025 #ifndef CONFIG_SMP 4026 physid_set_mask_of_physid(boot_cpu_physical_apicid, 4027 &phys_cpu_present_map); 4028 #endif 4029 setup_local_APIC(); 4030 4031 io_apic_setup_irq_pin(0, 0, &attr); 4032 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, 4033 "edge"); 4034 } 4035