1 /* 2 * Intel IO-APIC support for multi-Pentium hosts. 3 * 4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo 5 * 6 * Many thanks to Stig Venaas for trying out countless experimental 7 * patches and reporting/debugging problems patiently! 8 * 9 * (c) 1999, Multiple IO-APIC support, developed by 10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and 11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, 12 * further tested and cleaned up by Zach Brown <zab@redhat.com> 13 * and Ingo Molnar <mingo@redhat.com> 14 * 15 * Fixes 16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 17 * thanks to Eric Gilmore 18 * and Rolf G. Tews 19 * for testing these extensively 20 * Paul Diefenbaugh : Added full ACPI support 21 */ 22 23 #include <linux/mm.h> 24 #include <linux/interrupt.h> 25 #include <linux/init.h> 26 #include <linux/delay.h> 27 #include <linux/sched.h> 28 #include <linux/pci.h> 29 #include <linux/mc146818rtc.h> 30 #include <linux/compiler.h> 31 #include <linux/acpi.h> 32 #include <linux/module.h> 33 #include <linux/syscore_ops.h> 34 #include <linux/msi.h> 35 #include <linux/htirq.h> 36 #include <linux/freezer.h> 37 #include <linux/kthread.h> 38 #include <linux/jiffies.h> /* time_after() */ 39 #include <linux/slab.h> 40 #ifdef CONFIG_ACPI 41 #include <acpi/acpi_bus.h> 42 #endif 43 #include <linux/bootmem.h> 44 #include <linux/dmar.h> 45 #include <linux/hpet.h> 46 47 #include <asm/idle.h> 48 #include <asm/io.h> 49 #include <asm/smp.h> 50 #include <asm/cpu.h> 51 #include <asm/desc.h> 52 #include <asm/proto.h> 53 #include <asm/acpi.h> 54 #include <asm/dma.h> 55 #include <asm/timer.h> 56 #include <asm/i8259.h> 57 #include <asm/msidef.h> 58 #include <asm/hypertransport.h> 59 #include <asm/setup.h> 60 #include <asm/irq_remapping.h> 61 #include <asm/hpet.h> 62 #include <asm/hw_irq.h> 63 64 #include <asm/apic.h> 65 66 #define __apicdebuginit(type) static type __init 67 68 #define for_each_irq_pin(entry, head) \ 69 for (entry = head; entry; entry = entry->next) 70 71 /* 72 * Is the SiS APIC rmw bug present ? 73 * -1 = don't know, 0 = no, 1 = yes 74 */ 75 int sis_apic_bug = -1; 76 77 static DEFINE_RAW_SPINLOCK(ioapic_lock); 78 static DEFINE_RAW_SPINLOCK(vector_lock); 79 80 static struct ioapic { 81 /* 82 * # of IRQ routing registers 83 */ 84 int nr_registers; 85 /* 86 * Saved state during suspend/resume, or while enabling intr-remap. 87 */ 88 struct IO_APIC_route_entry *saved_registers; 89 /* I/O APIC config */ 90 struct mpc_ioapic mp_config; 91 /* IO APIC gsi routing info */ 92 struct mp_ioapic_gsi gsi_config; 93 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1); 94 } ioapics[MAX_IO_APICS]; 95 96 #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver 97 98 int mpc_ioapic_id(int ioapic_idx) 99 { 100 return ioapics[ioapic_idx].mp_config.apicid; 101 } 102 103 unsigned int mpc_ioapic_addr(int ioapic_idx) 104 { 105 return ioapics[ioapic_idx].mp_config.apicaddr; 106 } 107 108 struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx) 109 { 110 return &ioapics[ioapic_idx].gsi_config; 111 } 112 113 int nr_ioapics; 114 115 /* The one past the highest gsi number used */ 116 u32 gsi_top; 117 118 /* MP IRQ source entries */ 119 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES]; 120 121 /* # of MP IRQ source entries */ 122 int mp_irq_entries; 123 124 /* GSI interrupts */ 125 static int nr_irqs_gsi = NR_IRQS_LEGACY; 126 127 #ifdef CONFIG_EISA 128 int mp_bus_id_to_type[MAX_MP_BUSSES]; 129 #endif 130 131 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); 132 133 int skip_ioapic_setup; 134 135 /** 136 * disable_ioapic_support() - disables ioapic support at runtime 137 */ 138 void disable_ioapic_support(void) 139 { 140 #ifdef CONFIG_PCI 141 noioapicquirk = 1; 142 noioapicreroute = -1; 143 #endif 144 skip_ioapic_setup = 1; 145 } 146 147 static int __init parse_noapic(char *str) 148 { 149 /* disable IO-APIC */ 150 disable_ioapic_support(); 151 return 0; 152 } 153 early_param("noapic", parse_noapic); 154 155 static int io_apic_setup_irq_pin(unsigned int irq, int node, 156 struct io_apic_irq_attr *attr); 157 158 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */ 159 void mp_save_irq(struct mpc_intsrc *m) 160 { 161 int i; 162 163 apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x," 164 " IRQ %02x, APIC ID %x, APIC INT %02x\n", 165 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus, 166 m->srcbusirq, m->dstapic, m->dstirq); 167 168 for (i = 0; i < mp_irq_entries; i++) { 169 if (!memcmp(&mp_irqs[i], m, sizeof(*m))) 170 return; 171 } 172 173 memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m)); 174 if (++mp_irq_entries == MAX_IRQ_SOURCES) 175 panic("Max # of irq sources exceeded!!\n"); 176 } 177 178 struct irq_pin_list { 179 int apic, pin; 180 struct irq_pin_list *next; 181 }; 182 183 static struct irq_pin_list *alloc_irq_pin_list(int node) 184 { 185 return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node); 186 } 187 188 189 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */ 190 static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY]; 191 192 int __init arch_early_irq_init(void) 193 { 194 struct irq_cfg *cfg; 195 int count, node, i; 196 197 if (!legacy_pic->nr_legacy_irqs) 198 io_apic_irqs = ~0UL; 199 200 for (i = 0; i < nr_ioapics; i++) { 201 ioapics[i].saved_registers = 202 kzalloc(sizeof(struct IO_APIC_route_entry) * 203 ioapics[i].nr_registers, GFP_KERNEL); 204 if (!ioapics[i].saved_registers) 205 pr_err("IOAPIC %d: suspend/resume impossible!\n", i); 206 } 207 208 cfg = irq_cfgx; 209 count = ARRAY_SIZE(irq_cfgx); 210 node = cpu_to_node(0); 211 212 /* Make sure the legacy interrupts are marked in the bitmap */ 213 irq_reserve_irqs(0, legacy_pic->nr_legacy_irqs); 214 215 for (i = 0; i < count; i++) { 216 irq_set_chip_data(i, &cfg[i]); 217 zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node); 218 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node); 219 /* 220 * For legacy IRQ's, start with assigning irq0 to irq15 to 221 * IRQ0_VECTOR to IRQ15_VECTOR for all cpu's. 222 */ 223 if (i < legacy_pic->nr_legacy_irqs) { 224 cfg[i].vector = IRQ0_VECTOR + i; 225 cpumask_setall(cfg[i].domain); 226 } 227 } 228 229 return 0; 230 } 231 232 static struct irq_cfg *irq_cfg(unsigned int irq) 233 { 234 return irq_get_chip_data(irq); 235 } 236 237 static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node) 238 { 239 struct irq_cfg *cfg; 240 241 cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node); 242 if (!cfg) 243 return NULL; 244 if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node)) 245 goto out_cfg; 246 if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node)) 247 goto out_domain; 248 return cfg; 249 out_domain: 250 free_cpumask_var(cfg->domain); 251 out_cfg: 252 kfree(cfg); 253 return NULL; 254 } 255 256 static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg) 257 { 258 if (!cfg) 259 return; 260 irq_set_chip_data(at, NULL); 261 free_cpumask_var(cfg->domain); 262 free_cpumask_var(cfg->old_domain); 263 kfree(cfg); 264 } 265 266 static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node) 267 { 268 int res = irq_alloc_desc_at(at, node); 269 struct irq_cfg *cfg; 270 271 if (res < 0) { 272 if (res != -EEXIST) 273 return NULL; 274 cfg = irq_get_chip_data(at); 275 if (cfg) 276 return cfg; 277 } 278 279 cfg = alloc_irq_cfg(at, node); 280 if (cfg) 281 irq_set_chip_data(at, cfg); 282 else 283 irq_free_desc(at); 284 return cfg; 285 } 286 287 static int alloc_irqs_from(unsigned int from, unsigned int count, int node) 288 { 289 return irq_alloc_descs_from(from, count, node); 290 } 291 292 static void free_irq_at(unsigned int at, struct irq_cfg *cfg) 293 { 294 free_irq_cfg(at, cfg); 295 irq_free_desc(at); 296 } 297 298 299 struct io_apic { 300 unsigned int index; 301 unsigned int unused[3]; 302 unsigned int data; 303 unsigned int unused2[11]; 304 unsigned int eoi; 305 }; 306 307 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx) 308 { 309 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx) 310 + (mpc_ioapic_addr(idx) & ~PAGE_MASK); 311 } 312 313 static inline void io_apic_eoi(unsigned int apic, unsigned int vector) 314 { 315 struct io_apic __iomem *io_apic = io_apic_base(apic); 316 writel(vector, &io_apic->eoi); 317 } 318 319 unsigned int native_io_apic_read(unsigned int apic, unsigned int reg) 320 { 321 struct io_apic __iomem *io_apic = io_apic_base(apic); 322 writel(reg, &io_apic->index); 323 return readl(&io_apic->data); 324 } 325 326 void native_io_apic_write(unsigned int apic, unsigned int reg, unsigned int value) 327 { 328 struct io_apic __iomem *io_apic = io_apic_base(apic); 329 330 writel(reg, &io_apic->index); 331 writel(value, &io_apic->data); 332 } 333 334 /* 335 * Re-write a value: to be used for read-modify-write 336 * cycles where the read already set up the index register. 337 * 338 * Older SiS APIC requires we rewrite the index register 339 */ 340 void native_io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value) 341 { 342 struct io_apic __iomem *io_apic = io_apic_base(apic); 343 344 if (sis_apic_bug) 345 writel(reg, &io_apic->index); 346 writel(value, &io_apic->data); 347 } 348 349 union entry_union { 350 struct { u32 w1, w2; }; 351 struct IO_APIC_route_entry entry; 352 }; 353 354 static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin) 355 { 356 union entry_union eu; 357 358 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); 359 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); 360 361 return eu.entry; 362 } 363 364 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) 365 { 366 union entry_union eu; 367 unsigned long flags; 368 369 raw_spin_lock_irqsave(&ioapic_lock, flags); 370 eu.entry = __ioapic_read_entry(apic, pin); 371 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 372 373 return eu.entry; 374 } 375 376 /* 377 * When we write a new IO APIC routing entry, we need to write the high 378 * word first! If the mask bit in the low word is clear, we will enable 379 * the interrupt, and we need to make sure the entry is fully populated 380 * before that happens. 381 */ 382 static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) 383 { 384 union entry_union eu = {{0, 0}}; 385 386 eu.entry = e; 387 io_apic_write(apic, 0x11 + 2*pin, eu.w2); 388 io_apic_write(apic, 0x10 + 2*pin, eu.w1); 389 } 390 391 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e) 392 { 393 unsigned long flags; 394 395 raw_spin_lock_irqsave(&ioapic_lock, flags); 396 __ioapic_write_entry(apic, pin, e); 397 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 398 } 399 400 /* 401 * When we mask an IO APIC routing entry, we need to write the low 402 * word first, in order to set the mask bit before we change the 403 * high bits! 404 */ 405 static void ioapic_mask_entry(int apic, int pin) 406 { 407 unsigned long flags; 408 union entry_union eu = { .entry.mask = 1 }; 409 410 raw_spin_lock_irqsave(&ioapic_lock, flags); 411 io_apic_write(apic, 0x10 + 2*pin, eu.w1); 412 io_apic_write(apic, 0x11 + 2*pin, eu.w2); 413 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 414 } 415 416 /* 417 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are 418 * shared ISA-space IRQs, so we have to support them. We are super 419 * fast in the common case, and fast for shared ISA-space IRQs. 420 */ 421 static int __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) 422 { 423 struct irq_pin_list **last, *entry; 424 425 /* don't allow duplicates */ 426 last = &cfg->irq_2_pin; 427 for_each_irq_pin(entry, cfg->irq_2_pin) { 428 if (entry->apic == apic && entry->pin == pin) 429 return 0; 430 last = &entry->next; 431 } 432 433 entry = alloc_irq_pin_list(node); 434 if (!entry) { 435 pr_err("can not alloc irq_pin_list (%d,%d,%d)\n", 436 node, apic, pin); 437 return -ENOMEM; 438 } 439 entry->apic = apic; 440 entry->pin = pin; 441 442 *last = entry; 443 return 0; 444 } 445 446 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin) 447 { 448 if (__add_pin_to_irq_node(cfg, node, apic, pin)) 449 panic("IO-APIC: failed to add irq-pin. Can not proceed\n"); 450 } 451 452 /* 453 * Reroute an IRQ to a different pin. 454 */ 455 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node, 456 int oldapic, int oldpin, 457 int newapic, int newpin) 458 { 459 struct irq_pin_list *entry; 460 461 for_each_irq_pin(entry, cfg->irq_2_pin) { 462 if (entry->apic == oldapic && entry->pin == oldpin) { 463 entry->apic = newapic; 464 entry->pin = newpin; 465 /* every one is different, right? */ 466 return; 467 } 468 } 469 470 /* old apic/pin didn't exist, so just add new ones */ 471 add_pin_to_irq_node(cfg, node, newapic, newpin); 472 } 473 474 static void __io_apic_modify_irq(struct irq_pin_list *entry, 475 int mask_and, int mask_or, 476 void (*final)(struct irq_pin_list *entry)) 477 { 478 unsigned int reg, pin; 479 480 pin = entry->pin; 481 reg = io_apic_read(entry->apic, 0x10 + pin * 2); 482 reg &= mask_and; 483 reg |= mask_or; 484 io_apic_modify(entry->apic, 0x10 + pin * 2, reg); 485 if (final) 486 final(entry); 487 } 488 489 static void io_apic_modify_irq(struct irq_cfg *cfg, 490 int mask_and, int mask_or, 491 void (*final)(struct irq_pin_list *entry)) 492 { 493 struct irq_pin_list *entry; 494 495 for_each_irq_pin(entry, cfg->irq_2_pin) 496 __io_apic_modify_irq(entry, mask_and, mask_or, final); 497 } 498 499 static void io_apic_sync(struct irq_pin_list *entry) 500 { 501 /* 502 * Synchronize the IO-APIC and the CPU by doing 503 * a dummy read from the IO-APIC 504 */ 505 struct io_apic __iomem *io_apic; 506 507 io_apic = io_apic_base(entry->apic); 508 readl(&io_apic->data); 509 } 510 511 static void mask_ioapic(struct irq_cfg *cfg) 512 { 513 unsigned long flags; 514 515 raw_spin_lock_irqsave(&ioapic_lock, flags); 516 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync); 517 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 518 } 519 520 static void mask_ioapic_irq(struct irq_data *data) 521 { 522 mask_ioapic(data->chip_data); 523 } 524 525 static void __unmask_ioapic(struct irq_cfg *cfg) 526 { 527 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL); 528 } 529 530 static void unmask_ioapic(struct irq_cfg *cfg) 531 { 532 unsigned long flags; 533 534 raw_spin_lock_irqsave(&ioapic_lock, flags); 535 __unmask_ioapic(cfg); 536 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 537 } 538 539 static void unmask_ioapic_irq(struct irq_data *data) 540 { 541 unmask_ioapic(data->chip_data); 542 } 543 544 /* 545 * IO-APIC versions below 0x20 don't support EOI register. 546 * For the record, here is the information about various versions: 547 * 0Xh 82489DX 548 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant 549 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant 550 * 30h-FFh Reserved 551 * 552 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic 553 * version as 0x2. This is an error with documentation and these ICH chips 554 * use io-apic's of version 0x20. 555 * 556 * For IO-APIC's with EOI register, we use that to do an explicit EOI. 557 * Otherwise, we simulate the EOI message manually by changing the trigger 558 * mode to edge and then back to level, with RTE being masked during this. 559 */ 560 static void __eoi_ioapic_pin(int apic, int pin, int vector, struct irq_cfg *cfg) 561 { 562 if (mpc_ioapic_ver(apic) >= 0x20) { 563 /* 564 * Intr-remapping uses pin number as the virtual vector 565 * in the RTE. Actual vector is programmed in 566 * intr-remapping table entry. Hence for the io-apic 567 * EOI we use the pin number. 568 */ 569 if (cfg && irq_remapped(cfg)) 570 io_apic_eoi(apic, pin); 571 else 572 io_apic_eoi(apic, vector); 573 } else { 574 struct IO_APIC_route_entry entry, entry1; 575 576 entry = entry1 = __ioapic_read_entry(apic, pin); 577 578 /* 579 * Mask the entry and change the trigger mode to edge. 580 */ 581 entry1.mask = 1; 582 entry1.trigger = IOAPIC_EDGE; 583 584 __ioapic_write_entry(apic, pin, entry1); 585 586 /* 587 * Restore the previous level triggered entry. 588 */ 589 __ioapic_write_entry(apic, pin, entry); 590 } 591 } 592 593 void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg) 594 { 595 struct irq_pin_list *entry; 596 unsigned long flags; 597 598 raw_spin_lock_irqsave(&ioapic_lock, flags); 599 for_each_irq_pin(entry, cfg->irq_2_pin) 600 __eoi_ioapic_pin(entry->apic, entry->pin, cfg->vector, cfg); 601 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 602 } 603 604 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) 605 { 606 struct IO_APIC_route_entry entry; 607 608 /* Check delivery_mode to be sure we're not clearing an SMI pin */ 609 entry = ioapic_read_entry(apic, pin); 610 if (entry.delivery_mode == dest_SMI) 611 return; 612 613 /* 614 * Make sure the entry is masked and re-read the contents to check 615 * if it is a level triggered pin and if the remote-IRR is set. 616 */ 617 if (!entry.mask) { 618 entry.mask = 1; 619 ioapic_write_entry(apic, pin, entry); 620 entry = ioapic_read_entry(apic, pin); 621 } 622 623 if (entry.irr) { 624 unsigned long flags; 625 626 /* 627 * Make sure the trigger mode is set to level. Explicit EOI 628 * doesn't clear the remote-IRR if the trigger mode is not 629 * set to level. 630 */ 631 if (!entry.trigger) { 632 entry.trigger = IOAPIC_LEVEL; 633 ioapic_write_entry(apic, pin, entry); 634 } 635 636 raw_spin_lock_irqsave(&ioapic_lock, flags); 637 __eoi_ioapic_pin(apic, pin, entry.vector, NULL); 638 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 639 } 640 641 /* 642 * Clear the rest of the bits in the IO-APIC RTE except for the mask 643 * bit. 644 */ 645 ioapic_mask_entry(apic, pin); 646 entry = ioapic_read_entry(apic, pin); 647 if (entry.irr) 648 pr_err("Unable to reset IRR for apic: %d, pin :%d\n", 649 mpc_ioapic_id(apic), pin); 650 } 651 652 static void clear_IO_APIC (void) 653 { 654 int apic, pin; 655 656 for (apic = 0; apic < nr_ioapics; apic++) 657 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) 658 clear_IO_APIC_pin(apic, pin); 659 } 660 661 #ifdef CONFIG_X86_32 662 /* 663 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to 664 * specific CPU-side IRQs. 665 */ 666 667 #define MAX_PIRQS 8 668 static int pirq_entries[MAX_PIRQS] = { 669 [0 ... MAX_PIRQS - 1] = -1 670 }; 671 672 static int __init ioapic_pirq_setup(char *str) 673 { 674 int i, max; 675 int ints[MAX_PIRQS+1]; 676 677 get_options(str, ARRAY_SIZE(ints), ints); 678 679 apic_printk(APIC_VERBOSE, KERN_INFO 680 "PIRQ redirection, working around broken MP-BIOS.\n"); 681 max = MAX_PIRQS; 682 if (ints[0] < MAX_PIRQS) 683 max = ints[0]; 684 685 for (i = 0; i < max; i++) { 686 apic_printk(APIC_VERBOSE, KERN_DEBUG 687 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); 688 /* 689 * PIRQs are mapped upside down, usually. 690 */ 691 pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; 692 } 693 return 1; 694 } 695 696 __setup("pirq=", ioapic_pirq_setup); 697 #endif /* CONFIG_X86_32 */ 698 699 /* 700 * Saves all the IO-APIC RTE's 701 */ 702 int save_ioapic_entries(void) 703 { 704 int apic, pin; 705 int err = 0; 706 707 for (apic = 0; apic < nr_ioapics; apic++) { 708 if (!ioapics[apic].saved_registers) { 709 err = -ENOMEM; 710 continue; 711 } 712 713 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) 714 ioapics[apic].saved_registers[pin] = 715 ioapic_read_entry(apic, pin); 716 } 717 718 return err; 719 } 720 721 /* 722 * Mask all IO APIC entries. 723 */ 724 void mask_ioapic_entries(void) 725 { 726 int apic, pin; 727 728 for (apic = 0; apic < nr_ioapics; apic++) { 729 if (!ioapics[apic].saved_registers) 730 continue; 731 732 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) { 733 struct IO_APIC_route_entry entry; 734 735 entry = ioapics[apic].saved_registers[pin]; 736 if (!entry.mask) { 737 entry.mask = 1; 738 ioapic_write_entry(apic, pin, entry); 739 } 740 } 741 } 742 } 743 744 /* 745 * Restore IO APIC entries which was saved in the ioapic structure. 746 */ 747 int restore_ioapic_entries(void) 748 { 749 int apic, pin; 750 751 for (apic = 0; apic < nr_ioapics; apic++) { 752 if (!ioapics[apic].saved_registers) 753 continue; 754 755 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) 756 ioapic_write_entry(apic, pin, 757 ioapics[apic].saved_registers[pin]); 758 } 759 return 0; 760 } 761 762 /* 763 * Find the IRQ entry number of a certain pin. 764 */ 765 static int find_irq_entry(int ioapic_idx, int pin, int type) 766 { 767 int i; 768 769 for (i = 0; i < mp_irq_entries; i++) 770 if (mp_irqs[i].irqtype == type && 771 (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) || 772 mp_irqs[i].dstapic == MP_APIC_ALL) && 773 mp_irqs[i].dstirq == pin) 774 return i; 775 776 return -1; 777 } 778 779 /* 780 * Find the pin to which IRQ[irq] (ISA) is connected 781 */ 782 static int __init find_isa_irq_pin(int irq, int type) 783 { 784 int i; 785 786 for (i = 0; i < mp_irq_entries; i++) { 787 int lbus = mp_irqs[i].srcbus; 788 789 if (test_bit(lbus, mp_bus_not_pci) && 790 (mp_irqs[i].irqtype == type) && 791 (mp_irqs[i].srcbusirq == irq)) 792 793 return mp_irqs[i].dstirq; 794 } 795 return -1; 796 } 797 798 static int __init find_isa_irq_apic(int irq, int type) 799 { 800 int i; 801 802 for (i = 0; i < mp_irq_entries; i++) { 803 int lbus = mp_irqs[i].srcbus; 804 805 if (test_bit(lbus, mp_bus_not_pci) && 806 (mp_irqs[i].irqtype == type) && 807 (mp_irqs[i].srcbusirq == irq)) 808 break; 809 } 810 811 if (i < mp_irq_entries) { 812 int ioapic_idx; 813 814 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) 815 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic) 816 return ioapic_idx; 817 } 818 819 return -1; 820 } 821 822 #ifdef CONFIG_EISA 823 /* 824 * EISA Edge/Level control register, ELCR 825 */ 826 static int EISA_ELCR(unsigned int irq) 827 { 828 if (irq < legacy_pic->nr_legacy_irqs) { 829 unsigned int port = 0x4d0 + (irq >> 3); 830 return (inb(port) >> (irq & 7)) & 1; 831 } 832 apic_printk(APIC_VERBOSE, KERN_INFO 833 "Broken MPtable reports ISA irq %d\n", irq); 834 return 0; 835 } 836 837 #endif 838 839 /* ISA interrupts are always polarity zero edge triggered, 840 * when listed as conforming in the MP table. */ 841 842 #define default_ISA_trigger(idx) (0) 843 #define default_ISA_polarity(idx) (0) 844 845 /* EISA interrupts are always polarity zero and can be edge or level 846 * trigger depending on the ELCR value. If an interrupt is listed as 847 * EISA conforming in the MP table, that means its trigger type must 848 * be read in from the ELCR */ 849 850 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq)) 851 #define default_EISA_polarity(idx) default_ISA_polarity(idx) 852 853 /* PCI interrupts are always polarity one level triggered, 854 * when listed as conforming in the MP table. */ 855 856 #define default_PCI_trigger(idx) (1) 857 #define default_PCI_polarity(idx) (1) 858 859 static int irq_polarity(int idx) 860 { 861 int bus = mp_irqs[idx].srcbus; 862 int polarity; 863 864 /* 865 * Determine IRQ line polarity (high active or low active): 866 */ 867 switch (mp_irqs[idx].irqflag & 3) 868 { 869 case 0: /* conforms, ie. bus-type dependent polarity */ 870 if (test_bit(bus, mp_bus_not_pci)) 871 polarity = default_ISA_polarity(idx); 872 else 873 polarity = default_PCI_polarity(idx); 874 break; 875 case 1: /* high active */ 876 { 877 polarity = 0; 878 break; 879 } 880 case 2: /* reserved */ 881 { 882 pr_warn("broken BIOS!!\n"); 883 polarity = 1; 884 break; 885 } 886 case 3: /* low active */ 887 { 888 polarity = 1; 889 break; 890 } 891 default: /* invalid */ 892 { 893 pr_warn("broken BIOS!!\n"); 894 polarity = 1; 895 break; 896 } 897 } 898 return polarity; 899 } 900 901 static int irq_trigger(int idx) 902 { 903 int bus = mp_irqs[idx].srcbus; 904 int trigger; 905 906 /* 907 * Determine IRQ trigger mode (edge or level sensitive): 908 */ 909 switch ((mp_irqs[idx].irqflag>>2) & 3) 910 { 911 case 0: /* conforms, ie. bus-type dependent */ 912 if (test_bit(bus, mp_bus_not_pci)) 913 trigger = default_ISA_trigger(idx); 914 else 915 trigger = default_PCI_trigger(idx); 916 #ifdef CONFIG_EISA 917 switch (mp_bus_id_to_type[bus]) { 918 case MP_BUS_ISA: /* ISA pin */ 919 { 920 /* set before the switch */ 921 break; 922 } 923 case MP_BUS_EISA: /* EISA pin */ 924 { 925 trigger = default_EISA_trigger(idx); 926 break; 927 } 928 case MP_BUS_PCI: /* PCI pin */ 929 { 930 /* set before the switch */ 931 break; 932 } 933 default: 934 { 935 pr_warn("broken BIOS!!\n"); 936 trigger = 1; 937 break; 938 } 939 } 940 #endif 941 break; 942 case 1: /* edge */ 943 { 944 trigger = 0; 945 break; 946 } 947 case 2: /* reserved */ 948 { 949 pr_warn("broken BIOS!!\n"); 950 trigger = 1; 951 break; 952 } 953 case 3: /* level */ 954 { 955 trigger = 1; 956 break; 957 } 958 default: /* invalid */ 959 { 960 pr_warn("broken BIOS!!\n"); 961 trigger = 0; 962 break; 963 } 964 } 965 return trigger; 966 } 967 968 static int pin_2_irq(int idx, int apic, int pin) 969 { 970 int irq; 971 int bus = mp_irqs[idx].srcbus; 972 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(apic); 973 974 /* 975 * Debugging check, we are in big trouble if this message pops up! 976 */ 977 if (mp_irqs[idx].dstirq != pin) 978 pr_err("broken BIOS or MPTABLE parser, ayiee!!\n"); 979 980 if (test_bit(bus, mp_bus_not_pci)) { 981 irq = mp_irqs[idx].srcbusirq; 982 } else { 983 u32 gsi = gsi_cfg->gsi_base + pin; 984 985 if (gsi >= NR_IRQS_LEGACY) 986 irq = gsi; 987 else 988 irq = gsi_top + gsi; 989 } 990 991 #ifdef CONFIG_X86_32 992 /* 993 * PCI IRQ command line redirection. Yes, limits are hardcoded. 994 */ 995 if ((pin >= 16) && (pin <= 23)) { 996 if (pirq_entries[pin-16] != -1) { 997 if (!pirq_entries[pin-16]) { 998 apic_printk(APIC_VERBOSE, KERN_DEBUG 999 "disabling PIRQ%d\n", pin-16); 1000 } else { 1001 irq = pirq_entries[pin-16]; 1002 apic_printk(APIC_VERBOSE, KERN_DEBUG 1003 "using PIRQ%d -> IRQ %d\n", 1004 pin-16, irq); 1005 } 1006 } 1007 } 1008 #endif 1009 1010 return irq; 1011 } 1012 1013 /* 1014 * Find a specific PCI IRQ entry. 1015 * Not an __init, possibly needed by modules 1016 */ 1017 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin, 1018 struct io_apic_irq_attr *irq_attr) 1019 { 1020 int ioapic_idx, i, best_guess = -1; 1021 1022 apic_printk(APIC_DEBUG, 1023 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", 1024 bus, slot, pin); 1025 if (test_bit(bus, mp_bus_not_pci)) { 1026 apic_printk(APIC_VERBOSE, 1027 "PCI BIOS passed nonexistent PCI bus %d!\n", bus); 1028 return -1; 1029 } 1030 for (i = 0; i < mp_irq_entries; i++) { 1031 int lbus = mp_irqs[i].srcbus; 1032 1033 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) 1034 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic || 1035 mp_irqs[i].dstapic == MP_APIC_ALL) 1036 break; 1037 1038 if (!test_bit(lbus, mp_bus_not_pci) && 1039 !mp_irqs[i].irqtype && 1040 (bus == lbus) && 1041 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) { 1042 int irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq); 1043 1044 if (!(ioapic_idx || IO_APIC_IRQ(irq))) 1045 continue; 1046 1047 if (pin == (mp_irqs[i].srcbusirq & 3)) { 1048 set_io_apic_irq_attr(irq_attr, ioapic_idx, 1049 mp_irqs[i].dstirq, 1050 irq_trigger(i), 1051 irq_polarity(i)); 1052 return irq; 1053 } 1054 /* 1055 * Use the first all-but-pin matching entry as a 1056 * best-guess fuzzy result for broken mptables. 1057 */ 1058 if (best_guess < 0) { 1059 set_io_apic_irq_attr(irq_attr, ioapic_idx, 1060 mp_irqs[i].dstirq, 1061 irq_trigger(i), 1062 irq_polarity(i)); 1063 best_guess = irq; 1064 } 1065 } 1066 } 1067 return best_guess; 1068 } 1069 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector); 1070 1071 void lock_vector_lock(void) 1072 { 1073 /* Used to the online set of cpus does not change 1074 * during assign_irq_vector. 1075 */ 1076 raw_spin_lock(&vector_lock); 1077 } 1078 1079 void unlock_vector_lock(void) 1080 { 1081 raw_spin_unlock(&vector_lock); 1082 } 1083 1084 static int 1085 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) 1086 { 1087 /* 1088 * NOTE! The local APIC isn't very good at handling 1089 * multiple interrupts at the same interrupt level. 1090 * As the interrupt level is determined by taking the 1091 * vector number and shifting that right by 4, we 1092 * want to spread these out a bit so that they don't 1093 * all fall in the same interrupt level. 1094 * 1095 * Also, we've got to be careful not to trash gate 1096 * 0x80, because int 0x80 is hm, kind of importantish. ;) 1097 */ 1098 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START; 1099 static int current_offset = VECTOR_OFFSET_START % 16; 1100 int cpu, err; 1101 cpumask_var_t tmp_mask; 1102 1103 if (cfg->move_in_progress) 1104 return -EBUSY; 1105 1106 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC)) 1107 return -ENOMEM; 1108 1109 /* Only try and allocate irqs on cpus that are present */ 1110 err = -ENOSPC; 1111 cpumask_clear(cfg->old_domain); 1112 cpu = cpumask_first_and(mask, cpu_online_mask); 1113 while (cpu < nr_cpu_ids) { 1114 int new_cpu, vector, offset; 1115 1116 apic->vector_allocation_domain(cpu, tmp_mask, mask); 1117 1118 if (cpumask_subset(tmp_mask, cfg->domain)) { 1119 err = 0; 1120 if (cpumask_equal(tmp_mask, cfg->domain)) 1121 break; 1122 /* 1123 * New cpumask using the vector is a proper subset of 1124 * the current in use mask. So cleanup the vector 1125 * allocation for the members that are not used anymore. 1126 */ 1127 cpumask_andnot(cfg->old_domain, cfg->domain, tmp_mask); 1128 cfg->move_in_progress = 1129 cpumask_intersects(cfg->old_domain, cpu_online_mask); 1130 cpumask_and(cfg->domain, cfg->domain, tmp_mask); 1131 break; 1132 } 1133 1134 vector = current_vector; 1135 offset = current_offset; 1136 next: 1137 vector += 16; 1138 if (vector >= first_system_vector) { 1139 offset = (offset + 1) % 16; 1140 vector = FIRST_EXTERNAL_VECTOR + offset; 1141 } 1142 1143 if (unlikely(current_vector == vector)) { 1144 cpumask_or(cfg->old_domain, cfg->old_domain, tmp_mask); 1145 cpumask_andnot(tmp_mask, mask, cfg->old_domain); 1146 cpu = cpumask_first_and(tmp_mask, cpu_online_mask); 1147 continue; 1148 } 1149 1150 if (test_bit(vector, used_vectors)) 1151 goto next; 1152 1153 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) 1154 if (per_cpu(vector_irq, new_cpu)[vector] != -1) 1155 goto next; 1156 /* Found one! */ 1157 current_vector = vector; 1158 current_offset = offset; 1159 if (cfg->vector) { 1160 cpumask_copy(cfg->old_domain, cfg->domain); 1161 cfg->move_in_progress = 1162 cpumask_intersects(cfg->old_domain, cpu_online_mask); 1163 } 1164 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask) 1165 per_cpu(vector_irq, new_cpu)[vector] = irq; 1166 cfg->vector = vector; 1167 cpumask_copy(cfg->domain, tmp_mask); 1168 err = 0; 1169 break; 1170 } 1171 free_cpumask_var(tmp_mask); 1172 return err; 1173 } 1174 1175 int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask) 1176 { 1177 int err; 1178 unsigned long flags; 1179 1180 raw_spin_lock_irqsave(&vector_lock, flags); 1181 err = __assign_irq_vector(irq, cfg, mask); 1182 raw_spin_unlock_irqrestore(&vector_lock, flags); 1183 return err; 1184 } 1185 1186 static void __clear_irq_vector(int irq, struct irq_cfg *cfg) 1187 { 1188 int cpu, vector; 1189 1190 BUG_ON(!cfg->vector); 1191 1192 vector = cfg->vector; 1193 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask) 1194 per_cpu(vector_irq, cpu)[vector] = -1; 1195 1196 cfg->vector = 0; 1197 cpumask_clear(cfg->domain); 1198 1199 if (likely(!cfg->move_in_progress)) 1200 return; 1201 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) { 1202 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; 1203 vector++) { 1204 if (per_cpu(vector_irq, cpu)[vector] != irq) 1205 continue; 1206 per_cpu(vector_irq, cpu)[vector] = -1; 1207 break; 1208 } 1209 } 1210 cfg->move_in_progress = 0; 1211 } 1212 1213 void __setup_vector_irq(int cpu) 1214 { 1215 /* Initialize vector_irq on a new cpu */ 1216 int irq, vector; 1217 struct irq_cfg *cfg; 1218 1219 /* 1220 * vector_lock will make sure that we don't run into irq vector 1221 * assignments that might be happening on another cpu in parallel, 1222 * while we setup our initial vector to irq mappings. 1223 */ 1224 raw_spin_lock(&vector_lock); 1225 /* Mark the inuse vectors */ 1226 for_each_active_irq(irq) { 1227 cfg = irq_get_chip_data(irq); 1228 if (!cfg) 1229 continue; 1230 1231 if (!cpumask_test_cpu(cpu, cfg->domain)) 1232 continue; 1233 vector = cfg->vector; 1234 per_cpu(vector_irq, cpu)[vector] = irq; 1235 } 1236 /* Mark the free vectors */ 1237 for (vector = 0; vector < NR_VECTORS; ++vector) { 1238 irq = per_cpu(vector_irq, cpu)[vector]; 1239 if (irq < 0) 1240 continue; 1241 1242 cfg = irq_cfg(irq); 1243 if (!cpumask_test_cpu(cpu, cfg->domain)) 1244 per_cpu(vector_irq, cpu)[vector] = -1; 1245 } 1246 raw_spin_unlock(&vector_lock); 1247 } 1248 1249 static struct irq_chip ioapic_chip; 1250 1251 #ifdef CONFIG_X86_32 1252 static inline int IO_APIC_irq_trigger(int irq) 1253 { 1254 int apic, idx, pin; 1255 1256 for (apic = 0; apic < nr_ioapics; apic++) { 1257 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) { 1258 idx = find_irq_entry(apic, pin, mp_INT); 1259 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin))) 1260 return irq_trigger(idx); 1261 } 1262 } 1263 /* 1264 * nonexistent IRQs are edge default 1265 */ 1266 return 0; 1267 } 1268 #else 1269 static inline int IO_APIC_irq_trigger(int irq) 1270 { 1271 return 1; 1272 } 1273 #endif 1274 1275 static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg, 1276 unsigned long trigger) 1277 { 1278 struct irq_chip *chip = &ioapic_chip; 1279 irq_flow_handler_t hdl; 1280 bool fasteoi; 1281 1282 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) || 1283 trigger == IOAPIC_LEVEL) { 1284 irq_set_status_flags(irq, IRQ_LEVEL); 1285 fasteoi = true; 1286 } else { 1287 irq_clear_status_flags(irq, IRQ_LEVEL); 1288 fasteoi = false; 1289 } 1290 1291 if (setup_remapped_irq(irq, cfg, chip)) 1292 fasteoi = trigger != 0; 1293 1294 hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq; 1295 irq_set_chip_and_handler_name(irq, chip, hdl, 1296 fasteoi ? "fasteoi" : "edge"); 1297 } 1298 1299 int native_setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry, 1300 unsigned int destination, int vector, 1301 struct io_apic_irq_attr *attr) 1302 { 1303 memset(entry, 0, sizeof(*entry)); 1304 1305 entry->delivery_mode = apic->irq_delivery_mode; 1306 entry->dest_mode = apic->irq_dest_mode; 1307 entry->dest = destination; 1308 entry->vector = vector; 1309 entry->mask = 0; /* enable IRQ */ 1310 entry->trigger = attr->trigger; 1311 entry->polarity = attr->polarity; 1312 1313 /* 1314 * Mask level triggered irqs. 1315 * Use IRQ_DELAYED_DISABLE for edge triggered irqs. 1316 */ 1317 if (attr->trigger) 1318 entry->mask = 1; 1319 1320 return 0; 1321 } 1322 1323 static void setup_ioapic_irq(unsigned int irq, struct irq_cfg *cfg, 1324 struct io_apic_irq_attr *attr) 1325 { 1326 struct IO_APIC_route_entry entry; 1327 unsigned int dest; 1328 1329 if (!IO_APIC_IRQ(irq)) 1330 return; 1331 1332 if (assign_irq_vector(irq, cfg, apic->target_cpus())) 1333 return; 1334 1335 if (apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus(), 1336 &dest)) { 1337 pr_warn("Failed to obtain apicid for ioapic %d, pin %d\n", 1338 mpc_ioapic_id(attr->ioapic), attr->ioapic_pin); 1339 __clear_irq_vector(irq, cfg); 1340 1341 return; 1342 } 1343 1344 apic_printk(APIC_VERBOSE,KERN_DEBUG 1345 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> " 1346 "IRQ %d Mode:%i Active:%i Dest:%d)\n", 1347 attr->ioapic, mpc_ioapic_id(attr->ioapic), attr->ioapic_pin, 1348 cfg->vector, irq, attr->trigger, attr->polarity, dest); 1349 1350 if (x86_io_apic_ops.setup_entry(irq, &entry, dest, cfg->vector, attr)) { 1351 pr_warn("Failed to setup ioapic entry for ioapic %d, pin %d\n", 1352 mpc_ioapic_id(attr->ioapic), attr->ioapic_pin); 1353 __clear_irq_vector(irq, cfg); 1354 1355 return; 1356 } 1357 1358 ioapic_register_intr(irq, cfg, attr->trigger); 1359 if (irq < legacy_pic->nr_legacy_irqs) 1360 legacy_pic->mask(irq); 1361 1362 ioapic_write_entry(attr->ioapic, attr->ioapic_pin, entry); 1363 } 1364 1365 static bool __init io_apic_pin_not_connected(int idx, int ioapic_idx, int pin) 1366 { 1367 if (idx != -1) 1368 return false; 1369 1370 apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n", 1371 mpc_ioapic_id(ioapic_idx), pin); 1372 return true; 1373 } 1374 1375 static void __init __io_apic_setup_irqs(unsigned int ioapic_idx) 1376 { 1377 int idx, node = cpu_to_node(0); 1378 struct io_apic_irq_attr attr; 1379 unsigned int pin, irq; 1380 1381 for (pin = 0; pin < ioapics[ioapic_idx].nr_registers; pin++) { 1382 idx = find_irq_entry(ioapic_idx, pin, mp_INT); 1383 if (io_apic_pin_not_connected(idx, ioapic_idx, pin)) 1384 continue; 1385 1386 irq = pin_2_irq(idx, ioapic_idx, pin); 1387 1388 if ((ioapic_idx > 0) && (irq > 16)) 1389 continue; 1390 1391 /* 1392 * Skip the timer IRQ if there's a quirk handler 1393 * installed and if it returns 1: 1394 */ 1395 if (apic->multi_timer_check && 1396 apic->multi_timer_check(ioapic_idx, irq)) 1397 continue; 1398 1399 set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx), 1400 irq_polarity(idx)); 1401 1402 io_apic_setup_irq_pin(irq, node, &attr); 1403 } 1404 } 1405 1406 static void __init setup_IO_APIC_irqs(void) 1407 { 1408 unsigned int ioapic_idx; 1409 1410 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n"); 1411 1412 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) 1413 __io_apic_setup_irqs(ioapic_idx); 1414 } 1415 1416 /* 1417 * for the gsit that is not in first ioapic 1418 * but could not use acpi_register_gsi() 1419 * like some special sci in IBM x3330 1420 */ 1421 void setup_IO_APIC_irq_extra(u32 gsi) 1422 { 1423 int ioapic_idx = 0, pin, idx, irq, node = cpu_to_node(0); 1424 struct io_apic_irq_attr attr; 1425 1426 /* 1427 * Convert 'gsi' to 'ioapic.pin'. 1428 */ 1429 ioapic_idx = mp_find_ioapic(gsi); 1430 if (ioapic_idx < 0) 1431 return; 1432 1433 pin = mp_find_ioapic_pin(ioapic_idx, gsi); 1434 idx = find_irq_entry(ioapic_idx, pin, mp_INT); 1435 if (idx == -1) 1436 return; 1437 1438 irq = pin_2_irq(idx, ioapic_idx, pin); 1439 1440 /* Only handle the non legacy irqs on secondary ioapics */ 1441 if (ioapic_idx == 0 || irq < NR_IRQS_LEGACY) 1442 return; 1443 1444 set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx), 1445 irq_polarity(idx)); 1446 1447 io_apic_setup_irq_pin_once(irq, node, &attr); 1448 } 1449 1450 /* 1451 * Set up the timer pin, possibly with the 8259A-master behind. 1452 */ 1453 static void __init setup_timer_IRQ0_pin(unsigned int ioapic_idx, 1454 unsigned int pin, int vector) 1455 { 1456 struct IO_APIC_route_entry entry; 1457 unsigned int dest; 1458 1459 memset(&entry, 0, sizeof(entry)); 1460 1461 /* 1462 * We use logical delivery to get the timer IRQ 1463 * to the first CPU. 1464 */ 1465 if (unlikely(apic->cpu_mask_to_apicid_and(apic->target_cpus(), 1466 apic->target_cpus(), &dest))) 1467 dest = BAD_APICID; 1468 1469 entry.dest_mode = apic->irq_dest_mode; 1470 entry.mask = 0; /* don't mask IRQ for edge */ 1471 entry.dest = dest; 1472 entry.delivery_mode = apic->irq_delivery_mode; 1473 entry.polarity = 0; 1474 entry.trigger = 0; 1475 entry.vector = vector; 1476 1477 /* 1478 * The timer IRQ doesn't have to know that behind the 1479 * scene we may have a 8259A-master in AEOI mode ... 1480 */ 1481 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, 1482 "edge"); 1483 1484 /* 1485 * Add it to the IO-APIC irq-routing table: 1486 */ 1487 ioapic_write_entry(ioapic_idx, pin, entry); 1488 } 1489 1490 void native_io_apic_print_entries(unsigned int apic, unsigned int nr_entries) 1491 { 1492 int i; 1493 1494 pr_debug(" NR Dst Mask Trig IRR Pol Stat Dmod Deli Vect:\n"); 1495 1496 for (i = 0; i <= nr_entries; i++) { 1497 struct IO_APIC_route_entry entry; 1498 1499 entry = ioapic_read_entry(apic, i); 1500 1501 pr_debug(" %02x %02X ", i, entry.dest); 1502 pr_cont("%1d %1d %1d %1d %1d " 1503 "%1d %1d %02X\n", 1504 entry.mask, 1505 entry.trigger, 1506 entry.irr, 1507 entry.polarity, 1508 entry.delivery_status, 1509 entry.dest_mode, 1510 entry.delivery_mode, 1511 entry.vector); 1512 } 1513 } 1514 1515 void intel_ir_io_apic_print_entries(unsigned int apic, 1516 unsigned int nr_entries) 1517 { 1518 int i; 1519 1520 pr_debug(" NR Indx Fmt Mask Trig IRR Pol Stat Indx2 Zero Vect:\n"); 1521 1522 for (i = 0; i <= nr_entries; i++) { 1523 struct IR_IO_APIC_route_entry *ir_entry; 1524 struct IO_APIC_route_entry entry; 1525 1526 entry = ioapic_read_entry(apic, i); 1527 1528 ir_entry = (struct IR_IO_APIC_route_entry *)&entry; 1529 1530 pr_debug(" %02x %04X ", i, ir_entry->index); 1531 pr_cont("%1d %1d %1d %1d %1d " 1532 "%1d %1d %X %02X\n", 1533 ir_entry->format, 1534 ir_entry->mask, 1535 ir_entry->trigger, 1536 ir_entry->irr, 1537 ir_entry->polarity, 1538 ir_entry->delivery_status, 1539 ir_entry->index2, 1540 ir_entry->zero, 1541 ir_entry->vector); 1542 } 1543 } 1544 1545 __apicdebuginit(void) print_IO_APIC(int ioapic_idx) 1546 { 1547 union IO_APIC_reg_00 reg_00; 1548 union IO_APIC_reg_01 reg_01; 1549 union IO_APIC_reg_02 reg_02; 1550 union IO_APIC_reg_03 reg_03; 1551 unsigned long flags; 1552 1553 raw_spin_lock_irqsave(&ioapic_lock, flags); 1554 reg_00.raw = io_apic_read(ioapic_idx, 0); 1555 reg_01.raw = io_apic_read(ioapic_idx, 1); 1556 if (reg_01.bits.version >= 0x10) 1557 reg_02.raw = io_apic_read(ioapic_idx, 2); 1558 if (reg_01.bits.version >= 0x20) 1559 reg_03.raw = io_apic_read(ioapic_idx, 3); 1560 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 1561 1562 printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx)); 1563 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw); 1564 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID); 1565 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type); 1566 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS); 1567 1568 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); 1569 printk(KERN_DEBUG "....... : max redirection entries: %02X\n", 1570 reg_01.bits.entries); 1571 1572 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ); 1573 printk(KERN_DEBUG "....... : IO APIC version: %02X\n", 1574 reg_01.bits.version); 1575 1576 /* 1577 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02, 1578 * but the value of reg_02 is read as the previous read register 1579 * value, so ignore it if reg_02 == reg_01. 1580 */ 1581 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) { 1582 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw); 1583 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration); 1584 } 1585 1586 /* 1587 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02 1588 * or reg_03, but the value of reg_0[23] is read as the previous read 1589 * register value, so ignore it if reg_03 == reg_0[12]. 1590 */ 1591 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw && 1592 reg_03.raw != reg_01.raw) { 1593 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw); 1594 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT); 1595 } 1596 1597 printk(KERN_DEBUG ".... IRQ redirection table:\n"); 1598 1599 x86_io_apic_ops.print_entries(ioapic_idx, reg_01.bits.entries); 1600 } 1601 1602 __apicdebuginit(void) print_IO_APICs(void) 1603 { 1604 int ioapic_idx; 1605 struct irq_cfg *cfg; 1606 unsigned int irq; 1607 struct irq_chip *chip; 1608 1609 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); 1610 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) 1611 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", 1612 mpc_ioapic_id(ioapic_idx), 1613 ioapics[ioapic_idx].nr_registers); 1614 1615 /* 1616 * We are a bit conservative about what we expect. We have to 1617 * know about every hardware change ASAP. 1618 */ 1619 printk(KERN_INFO "testing the IO APIC.......................\n"); 1620 1621 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) 1622 print_IO_APIC(ioapic_idx); 1623 1624 printk(KERN_DEBUG "IRQ to pin mappings:\n"); 1625 for_each_active_irq(irq) { 1626 struct irq_pin_list *entry; 1627 1628 chip = irq_get_chip(irq); 1629 if (chip != &ioapic_chip) 1630 continue; 1631 1632 cfg = irq_get_chip_data(irq); 1633 if (!cfg) 1634 continue; 1635 entry = cfg->irq_2_pin; 1636 if (!entry) 1637 continue; 1638 printk(KERN_DEBUG "IRQ%d ", irq); 1639 for_each_irq_pin(entry, cfg->irq_2_pin) 1640 pr_cont("-> %d:%d", entry->apic, entry->pin); 1641 pr_cont("\n"); 1642 } 1643 1644 printk(KERN_INFO ".................................... done.\n"); 1645 } 1646 1647 __apicdebuginit(void) print_APIC_field(int base) 1648 { 1649 int i; 1650 1651 printk(KERN_DEBUG); 1652 1653 for (i = 0; i < 8; i++) 1654 pr_cont("%08x", apic_read(base + i*0x10)); 1655 1656 pr_cont("\n"); 1657 } 1658 1659 __apicdebuginit(void) print_local_APIC(void *dummy) 1660 { 1661 unsigned int i, v, ver, maxlvt; 1662 u64 icr; 1663 1664 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", 1665 smp_processor_id(), hard_smp_processor_id()); 1666 v = apic_read(APIC_ID); 1667 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id()); 1668 v = apic_read(APIC_LVR); 1669 printk(KERN_INFO "... APIC VERSION: %08x\n", v); 1670 ver = GET_APIC_VERSION(v); 1671 maxlvt = lapic_get_maxlvt(); 1672 1673 v = apic_read(APIC_TASKPRI); 1674 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); 1675 1676 if (APIC_INTEGRATED(ver)) { /* !82489DX */ 1677 if (!APIC_XAPIC(ver)) { 1678 v = apic_read(APIC_ARBPRI); 1679 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, 1680 v & APIC_ARBPRI_MASK); 1681 } 1682 v = apic_read(APIC_PROCPRI); 1683 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); 1684 } 1685 1686 /* 1687 * Remote read supported only in the 82489DX and local APIC for 1688 * Pentium processors. 1689 */ 1690 if (!APIC_INTEGRATED(ver) || maxlvt == 3) { 1691 v = apic_read(APIC_RRR); 1692 printk(KERN_DEBUG "... APIC RRR: %08x\n", v); 1693 } 1694 1695 v = apic_read(APIC_LDR); 1696 printk(KERN_DEBUG "... APIC LDR: %08x\n", v); 1697 if (!x2apic_enabled()) { 1698 v = apic_read(APIC_DFR); 1699 printk(KERN_DEBUG "... APIC DFR: %08x\n", v); 1700 } 1701 v = apic_read(APIC_SPIV); 1702 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); 1703 1704 printk(KERN_DEBUG "... APIC ISR field:\n"); 1705 print_APIC_field(APIC_ISR); 1706 printk(KERN_DEBUG "... APIC TMR field:\n"); 1707 print_APIC_field(APIC_TMR); 1708 printk(KERN_DEBUG "... APIC IRR field:\n"); 1709 print_APIC_field(APIC_IRR); 1710 1711 if (APIC_INTEGRATED(ver)) { /* !82489DX */ 1712 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1713 apic_write(APIC_ESR, 0); 1714 1715 v = apic_read(APIC_ESR); 1716 printk(KERN_DEBUG "... APIC ESR: %08x\n", v); 1717 } 1718 1719 icr = apic_icr_read(); 1720 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr); 1721 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32)); 1722 1723 v = apic_read(APIC_LVTT); 1724 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); 1725 1726 if (maxlvt > 3) { /* PC is LVT#4. */ 1727 v = apic_read(APIC_LVTPC); 1728 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); 1729 } 1730 v = apic_read(APIC_LVT0); 1731 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); 1732 v = apic_read(APIC_LVT1); 1733 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); 1734 1735 if (maxlvt > 2) { /* ERR is LVT#3. */ 1736 v = apic_read(APIC_LVTERR); 1737 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); 1738 } 1739 1740 v = apic_read(APIC_TMICT); 1741 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); 1742 v = apic_read(APIC_TMCCT); 1743 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); 1744 v = apic_read(APIC_TDCR); 1745 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); 1746 1747 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) { 1748 v = apic_read(APIC_EFEAT); 1749 maxlvt = (v >> 16) & 0xff; 1750 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v); 1751 v = apic_read(APIC_ECTRL); 1752 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v); 1753 for (i = 0; i < maxlvt; i++) { 1754 v = apic_read(APIC_EILVTn(i)); 1755 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v); 1756 } 1757 } 1758 pr_cont("\n"); 1759 } 1760 1761 __apicdebuginit(void) print_local_APICs(int maxcpu) 1762 { 1763 int cpu; 1764 1765 if (!maxcpu) 1766 return; 1767 1768 preempt_disable(); 1769 for_each_online_cpu(cpu) { 1770 if (cpu >= maxcpu) 1771 break; 1772 smp_call_function_single(cpu, print_local_APIC, NULL, 1); 1773 } 1774 preempt_enable(); 1775 } 1776 1777 __apicdebuginit(void) print_PIC(void) 1778 { 1779 unsigned int v; 1780 unsigned long flags; 1781 1782 if (!legacy_pic->nr_legacy_irqs) 1783 return; 1784 1785 printk(KERN_DEBUG "\nprinting PIC contents\n"); 1786 1787 raw_spin_lock_irqsave(&i8259A_lock, flags); 1788 1789 v = inb(0xa1) << 8 | inb(0x21); 1790 printk(KERN_DEBUG "... PIC IMR: %04x\n", v); 1791 1792 v = inb(0xa0) << 8 | inb(0x20); 1793 printk(KERN_DEBUG "... PIC IRR: %04x\n", v); 1794 1795 outb(0x0b,0xa0); 1796 outb(0x0b,0x20); 1797 v = inb(0xa0) << 8 | inb(0x20); 1798 outb(0x0a,0xa0); 1799 outb(0x0a,0x20); 1800 1801 raw_spin_unlock_irqrestore(&i8259A_lock, flags); 1802 1803 printk(KERN_DEBUG "... PIC ISR: %04x\n", v); 1804 1805 v = inb(0x4d1) << 8 | inb(0x4d0); 1806 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); 1807 } 1808 1809 static int __initdata show_lapic = 1; 1810 static __init int setup_show_lapic(char *arg) 1811 { 1812 int num = -1; 1813 1814 if (strcmp(arg, "all") == 0) { 1815 show_lapic = CONFIG_NR_CPUS; 1816 } else { 1817 get_option(&arg, &num); 1818 if (num >= 0) 1819 show_lapic = num; 1820 } 1821 1822 return 1; 1823 } 1824 __setup("show_lapic=", setup_show_lapic); 1825 1826 __apicdebuginit(int) print_ICs(void) 1827 { 1828 if (apic_verbosity == APIC_QUIET) 1829 return 0; 1830 1831 print_PIC(); 1832 1833 /* don't print out if apic is not there */ 1834 if (!cpu_has_apic && !apic_from_smp_config()) 1835 return 0; 1836 1837 print_local_APICs(show_lapic); 1838 print_IO_APICs(); 1839 1840 return 0; 1841 } 1842 1843 late_initcall(print_ICs); 1844 1845 1846 /* Where if anywhere is the i8259 connect in external int mode */ 1847 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 }; 1848 1849 void __init enable_IO_APIC(void) 1850 { 1851 int i8259_apic, i8259_pin; 1852 int apic; 1853 1854 if (!legacy_pic->nr_legacy_irqs) 1855 return; 1856 1857 for(apic = 0; apic < nr_ioapics; apic++) { 1858 int pin; 1859 /* See if any of the pins is in ExtINT mode */ 1860 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) { 1861 struct IO_APIC_route_entry entry; 1862 entry = ioapic_read_entry(apic, pin); 1863 1864 /* If the interrupt line is enabled and in ExtInt mode 1865 * I have found the pin where the i8259 is connected. 1866 */ 1867 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) { 1868 ioapic_i8259.apic = apic; 1869 ioapic_i8259.pin = pin; 1870 goto found_i8259; 1871 } 1872 } 1873 } 1874 found_i8259: 1875 /* Look to see what if the MP table has reported the ExtINT */ 1876 /* If we could not find the appropriate pin by looking at the ioapic 1877 * the i8259 probably is not connected the ioapic but give the 1878 * mptable a chance anyway. 1879 */ 1880 i8259_pin = find_isa_irq_pin(0, mp_ExtINT); 1881 i8259_apic = find_isa_irq_apic(0, mp_ExtINT); 1882 /* Trust the MP table if nothing is setup in the hardware */ 1883 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) { 1884 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n"); 1885 ioapic_i8259.pin = i8259_pin; 1886 ioapic_i8259.apic = i8259_apic; 1887 } 1888 /* Complain if the MP table and the hardware disagree */ 1889 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) && 1890 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0)) 1891 { 1892 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n"); 1893 } 1894 1895 /* 1896 * Do not trust the IO-APIC being empty at bootup 1897 */ 1898 clear_IO_APIC(); 1899 } 1900 1901 void native_disable_io_apic(void) 1902 { 1903 /* 1904 * If the i8259 is routed through an IOAPIC 1905 * Put that IOAPIC in virtual wire mode 1906 * so legacy interrupts can be delivered. 1907 */ 1908 if (ioapic_i8259.pin != -1) { 1909 struct IO_APIC_route_entry entry; 1910 1911 memset(&entry, 0, sizeof(entry)); 1912 entry.mask = 0; /* Enabled */ 1913 entry.trigger = 0; /* Edge */ 1914 entry.irr = 0; 1915 entry.polarity = 0; /* High */ 1916 entry.delivery_status = 0; 1917 entry.dest_mode = 0; /* Physical */ 1918 entry.delivery_mode = dest_ExtINT; /* ExtInt */ 1919 entry.vector = 0; 1920 entry.dest = read_apic_id(); 1921 1922 /* 1923 * Add it to the IO-APIC irq-routing table: 1924 */ 1925 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry); 1926 } 1927 1928 if (cpu_has_apic || apic_from_smp_config()) 1929 disconnect_bsp_APIC(ioapic_i8259.pin != -1); 1930 1931 } 1932 1933 /* 1934 * Not an __init, needed by the reboot code 1935 */ 1936 void disable_IO_APIC(void) 1937 { 1938 /* 1939 * Clear the IO-APIC before rebooting: 1940 */ 1941 clear_IO_APIC(); 1942 1943 if (!legacy_pic->nr_legacy_irqs) 1944 return; 1945 1946 x86_io_apic_ops.disable(); 1947 } 1948 1949 #ifdef CONFIG_X86_32 1950 /* 1951 * function to set the IO-APIC physical IDs based on the 1952 * values stored in the MPC table. 1953 * 1954 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 1955 */ 1956 void __init setup_ioapic_ids_from_mpc_nocheck(void) 1957 { 1958 union IO_APIC_reg_00 reg_00; 1959 physid_mask_t phys_id_present_map; 1960 int ioapic_idx; 1961 int i; 1962 unsigned char old_id; 1963 unsigned long flags; 1964 1965 /* 1966 * This is broken; anything with a real cpu count has to 1967 * circumvent this idiocy regardless. 1968 */ 1969 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map); 1970 1971 /* 1972 * Set the IOAPIC ID to the value stored in the MPC table. 1973 */ 1974 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) { 1975 /* Read the register 0 value */ 1976 raw_spin_lock_irqsave(&ioapic_lock, flags); 1977 reg_00.raw = io_apic_read(ioapic_idx, 0); 1978 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 1979 1980 old_id = mpc_ioapic_id(ioapic_idx); 1981 1982 if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) { 1983 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", 1984 ioapic_idx, mpc_ioapic_id(ioapic_idx)); 1985 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", 1986 reg_00.bits.ID); 1987 ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID; 1988 } 1989 1990 /* 1991 * Sanity check, is the ID really free? Every APIC in a 1992 * system must have a unique ID or we get lots of nice 1993 * 'stuck on smp_invalidate_needed IPI wait' messages. 1994 */ 1995 if (apic->check_apicid_used(&phys_id_present_map, 1996 mpc_ioapic_id(ioapic_idx))) { 1997 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", 1998 ioapic_idx, mpc_ioapic_id(ioapic_idx)); 1999 for (i = 0; i < get_physical_broadcast(); i++) 2000 if (!physid_isset(i, phys_id_present_map)) 2001 break; 2002 if (i >= get_physical_broadcast()) 2003 panic("Max APIC ID exceeded!\n"); 2004 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", 2005 i); 2006 physid_set(i, phys_id_present_map); 2007 ioapics[ioapic_idx].mp_config.apicid = i; 2008 } else { 2009 physid_mask_t tmp; 2010 apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx), 2011 &tmp); 2012 apic_printk(APIC_VERBOSE, "Setting %d in the " 2013 "phys_id_present_map\n", 2014 mpc_ioapic_id(ioapic_idx)); 2015 physids_or(phys_id_present_map, phys_id_present_map, tmp); 2016 } 2017 2018 /* 2019 * We need to adjust the IRQ routing table 2020 * if the ID changed. 2021 */ 2022 if (old_id != mpc_ioapic_id(ioapic_idx)) 2023 for (i = 0; i < mp_irq_entries; i++) 2024 if (mp_irqs[i].dstapic == old_id) 2025 mp_irqs[i].dstapic 2026 = mpc_ioapic_id(ioapic_idx); 2027 2028 /* 2029 * Update the ID register according to the right value 2030 * from the MPC table if they are different. 2031 */ 2032 if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID) 2033 continue; 2034 2035 apic_printk(APIC_VERBOSE, KERN_INFO 2036 "...changing IO-APIC physical APIC ID to %d ...", 2037 mpc_ioapic_id(ioapic_idx)); 2038 2039 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx); 2040 raw_spin_lock_irqsave(&ioapic_lock, flags); 2041 io_apic_write(ioapic_idx, 0, reg_00.raw); 2042 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 2043 2044 /* 2045 * Sanity check 2046 */ 2047 raw_spin_lock_irqsave(&ioapic_lock, flags); 2048 reg_00.raw = io_apic_read(ioapic_idx, 0); 2049 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 2050 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) 2051 pr_cont("could not set ID!\n"); 2052 else 2053 apic_printk(APIC_VERBOSE, " ok.\n"); 2054 } 2055 } 2056 2057 void __init setup_ioapic_ids_from_mpc(void) 2058 { 2059 2060 if (acpi_ioapic) 2061 return; 2062 /* 2063 * Don't check I/O APIC IDs for xAPIC systems. They have 2064 * no meaning without the serial APIC bus. 2065 */ 2066 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 2067 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) 2068 return; 2069 setup_ioapic_ids_from_mpc_nocheck(); 2070 } 2071 #endif 2072 2073 int no_timer_check __initdata; 2074 2075 static int __init notimercheck(char *s) 2076 { 2077 no_timer_check = 1; 2078 return 1; 2079 } 2080 __setup("no_timer_check", notimercheck); 2081 2082 /* 2083 * There is a nasty bug in some older SMP boards, their mptable lies 2084 * about the timer IRQ. We do the following to work around the situation: 2085 * 2086 * - timer IRQ defaults to IO-APIC IRQ 2087 * - if this function detects that timer IRQs are defunct, then we fall 2088 * back to ISA timer IRQs 2089 */ 2090 static int __init timer_irq_works(void) 2091 { 2092 unsigned long t1 = jiffies; 2093 unsigned long flags; 2094 2095 if (no_timer_check) 2096 return 1; 2097 2098 local_save_flags(flags); 2099 local_irq_enable(); 2100 /* Let ten ticks pass... */ 2101 mdelay((10 * 1000) / HZ); 2102 local_irq_restore(flags); 2103 2104 /* 2105 * Expect a few ticks at least, to be sure some possible 2106 * glue logic does not lock up after one or two first 2107 * ticks in a non-ExtINT mode. Also the local APIC 2108 * might have cached one ExtINT interrupt. Finally, at 2109 * least one tick may be lost due to delays. 2110 */ 2111 2112 /* jiffies wrap? */ 2113 if (time_after(jiffies, t1 + 4)) 2114 return 1; 2115 return 0; 2116 } 2117 2118 /* 2119 * In the SMP+IOAPIC case it might happen that there are an unspecified 2120 * number of pending IRQ events unhandled. These cases are very rare, 2121 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much 2122 * better to do it this way as thus we do not have to be aware of 2123 * 'pending' interrupts in the IRQ path, except at this point. 2124 */ 2125 /* 2126 * Edge triggered needs to resend any interrupt 2127 * that was delayed but this is now handled in the device 2128 * independent code. 2129 */ 2130 2131 /* 2132 * Starting up a edge-triggered IO-APIC interrupt is 2133 * nasty - we need to make sure that we get the edge. 2134 * If it is already asserted for some reason, we need 2135 * return 1 to indicate that is was pending. 2136 * 2137 * This is not complete - we should be able to fake 2138 * an edge even if it isn't on the 8259A... 2139 */ 2140 2141 static unsigned int startup_ioapic_irq(struct irq_data *data) 2142 { 2143 int was_pending = 0, irq = data->irq; 2144 unsigned long flags; 2145 2146 raw_spin_lock_irqsave(&ioapic_lock, flags); 2147 if (irq < legacy_pic->nr_legacy_irqs) { 2148 legacy_pic->mask(irq); 2149 if (legacy_pic->irq_pending(irq)) 2150 was_pending = 1; 2151 } 2152 __unmask_ioapic(data->chip_data); 2153 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 2154 2155 return was_pending; 2156 } 2157 2158 static int ioapic_retrigger_irq(struct irq_data *data) 2159 { 2160 struct irq_cfg *cfg = data->chip_data; 2161 unsigned long flags; 2162 int cpu; 2163 2164 raw_spin_lock_irqsave(&vector_lock, flags); 2165 cpu = cpumask_first_and(cfg->domain, cpu_online_mask); 2166 apic->send_IPI_mask(cpumask_of(cpu), cfg->vector); 2167 raw_spin_unlock_irqrestore(&vector_lock, flags); 2168 2169 return 1; 2170 } 2171 2172 /* 2173 * Level and edge triggered IO-APIC interrupts need different handling, 2174 * so we use two separate IRQ descriptors. Edge triggered IRQs can be 2175 * handled with the level-triggered descriptor, but that one has slightly 2176 * more overhead. Level-triggered interrupts cannot be handled with the 2177 * edge-triggered handler, without risking IRQ storms and other ugly 2178 * races. 2179 */ 2180 2181 #ifdef CONFIG_SMP 2182 void send_cleanup_vector(struct irq_cfg *cfg) 2183 { 2184 cpumask_var_t cleanup_mask; 2185 2186 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) { 2187 unsigned int i; 2188 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask) 2189 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR); 2190 } else { 2191 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask); 2192 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR); 2193 free_cpumask_var(cleanup_mask); 2194 } 2195 cfg->move_in_progress = 0; 2196 } 2197 2198 asmlinkage void smp_irq_move_cleanup_interrupt(void) 2199 { 2200 unsigned vector, me; 2201 2202 ack_APIC_irq(); 2203 irq_enter(); 2204 exit_idle(); 2205 2206 me = smp_processor_id(); 2207 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) { 2208 unsigned int irq; 2209 unsigned int irr; 2210 struct irq_desc *desc; 2211 struct irq_cfg *cfg; 2212 irq = __this_cpu_read(vector_irq[vector]); 2213 2214 if (irq == -1) 2215 continue; 2216 2217 desc = irq_to_desc(irq); 2218 if (!desc) 2219 continue; 2220 2221 cfg = irq_cfg(irq); 2222 if (!cfg) 2223 continue; 2224 2225 raw_spin_lock(&desc->lock); 2226 2227 /* 2228 * Check if the irq migration is in progress. If so, we 2229 * haven't received the cleanup request yet for this irq. 2230 */ 2231 if (cfg->move_in_progress) 2232 goto unlock; 2233 2234 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) 2235 goto unlock; 2236 2237 irr = apic_read(APIC_IRR + (vector / 32 * 0x10)); 2238 /* 2239 * Check if the vector that needs to be cleanedup is 2240 * registered at the cpu's IRR. If so, then this is not 2241 * the best time to clean it up. Lets clean it up in the 2242 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR 2243 * to myself. 2244 */ 2245 if (irr & (1 << (vector % 32))) { 2246 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR); 2247 goto unlock; 2248 } 2249 __this_cpu_write(vector_irq[vector], -1); 2250 unlock: 2251 raw_spin_unlock(&desc->lock); 2252 } 2253 2254 irq_exit(); 2255 } 2256 2257 static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector) 2258 { 2259 unsigned me; 2260 2261 if (likely(!cfg->move_in_progress)) 2262 return; 2263 2264 me = smp_processor_id(); 2265 2266 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) 2267 send_cleanup_vector(cfg); 2268 } 2269 2270 static void irq_complete_move(struct irq_cfg *cfg) 2271 { 2272 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax); 2273 } 2274 2275 void irq_force_complete_move(int irq) 2276 { 2277 struct irq_cfg *cfg = irq_get_chip_data(irq); 2278 2279 if (!cfg) 2280 return; 2281 2282 __irq_complete_move(cfg, cfg->vector); 2283 } 2284 #else 2285 static inline void irq_complete_move(struct irq_cfg *cfg) { } 2286 #endif 2287 2288 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg) 2289 { 2290 int apic, pin; 2291 struct irq_pin_list *entry; 2292 u8 vector = cfg->vector; 2293 2294 for_each_irq_pin(entry, cfg->irq_2_pin) { 2295 unsigned int reg; 2296 2297 apic = entry->apic; 2298 pin = entry->pin; 2299 2300 io_apic_write(apic, 0x11 + pin*2, dest); 2301 reg = io_apic_read(apic, 0x10 + pin*2); 2302 reg &= ~IO_APIC_REDIR_VECTOR_MASK; 2303 reg |= vector; 2304 io_apic_modify(apic, 0x10 + pin*2, reg); 2305 } 2306 } 2307 2308 /* 2309 * Either sets data->affinity to a valid value, and returns 2310 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and 2311 * leaves data->affinity untouched. 2312 */ 2313 int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask, 2314 unsigned int *dest_id) 2315 { 2316 struct irq_cfg *cfg = data->chip_data; 2317 unsigned int irq = data->irq; 2318 int err; 2319 2320 if (!config_enabled(CONFIG_SMP)) 2321 return -1; 2322 2323 if (!cpumask_intersects(mask, cpu_online_mask)) 2324 return -EINVAL; 2325 2326 err = assign_irq_vector(irq, cfg, mask); 2327 if (err) 2328 return err; 2329 2330 err = apic->cpu_mask_to_apicid_and(mask, cfg->domain, dest_id); 2331 if (err) { 2332 if (assign_irq_vector(irq, cfg, data->affinity)) 2333 pr_err("Failed to recover vector for irq %d\n", irq); 2334 return err; 2335 } 2336 2337 cpumask_copy(data->affinity, mask); 2338 2339 return 0; 2340 } 2341 2342 2343 int native_ioapic_set_affinity(struct irq_data *data, 2344 const struct cpumask *mask, 2345 bool force) 2346 { 2347 unsigned int dest, irq = data->irq; 2348 unsigned long flags; 2349 int ret; 2350 2351 if (!config_enabled(CONFIG_SMP)) 2352 return -1; 2353 2354 raw_spin_lock_irqsave(&ioapic_lock, flags); 2355 ret = __ioapic_set_affinity(data, mask, &dest); 2356 if (!ret) { 2357 /* Only the high 8 bits are valid. */ 2358 dest = SET_APIC_LOGICAL_ID(dest); 2359 __target_IO_APIC_irq(irq, dest, data->chip_data); 2360 ret = IRQ_SET_MASK_OK_NOCOPY; 2361 } 2362 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 2363 return ret; 2364 } 2365 2366 static void ack_apic_edge(struct irq_data *data) 2367 { 2368 irq_complete_move(data->chip_data); 2369 irq_move_irq(data); 2370 ack_APIC_irq(); 2371 } 2372 2373 atomic_t irq_mis_count; 2374 2375 #ifdef CONFIG_GENERIC_PENDING_IRQ 2376 static bool io_apic_level_ack_pending(struct irq_cfg *cfg) 2377 { 2378 struct irq_pin_list *entry; 2379 unsigned long flags; 2380 2381 raw_spin_lock_irqsave(&ioapic_lock, flags); 2382 for_each_irq_pin(entry, cfg->irq_2_pin) { 2383 unsigned int reg; 2384 int pin; 2385 2386 pin = entry->pin; 2387 reg = io_apic_read(entry->apic, 0x10 + pin*2); 2388 /* Is the remote IRR bit set? */ 2389 if (reg & IO_APIC_REDIR_REMOTE_IRR) { 2390 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 2391 return true; 2392 } 2393 } 2394 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 2395 2396 return false; 2397 } 2398 2399 static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg) 2400 { 2401 /* If we are moving the irq we need to mask it */ 2402 if (unlikely(irqd_is_setaffinity_pending(data))) { 2403 mask_ioapic(cfg); 2404 return true; 2405 } 2406 return false; 2407 } 2408 2409 static inline void ioapic_irqd_unmask(struct irq_data *data, 2410 struct irq_cfg *cfg, bool masked) 2411 { 2412 if (unlikely(masked)) { 2413 /* Only migrate the irq if the ack has been received. 2414 * 2415 * On rare occasions the broadcast level triggered ack gets 2416 * delayed going to ioapics, and if we reprogram the 2417 * vector while Remote IRR is still set the irq will never 2418 * fire again. 2419 * 2420 * To prevent this scenario we read the Remote IRR bit 2421 * of the ioapic. This has two effects. 2422 * - On any sane system the read of the ioapic will 2423 * flush writes (and acks) going to the ioapic from 2424 * this cpu. 2425 * - We get to see if the ACK has actually been delivered. 2426 * 2427 * Based on failed experiments of reprogramming the 2428 * ioapic entry from outside of irq context starting 2429 * with masking the ioapic entry and then polling until 2430 * Remote IRR was clear before reprogramming the 2431 * ioapic I don't trust the Remote IRR bit to be 2432 * completey accurate. 2433 * 2434 * However there appears to be no other way to plug 2435 * this race, so if the Remote IRR bit is not 2436 * accurate and is causing problems then it is a hardware bug 2437 * and you can go talk to the chipset vendor about it. 2438 */ 2439 if (!io_apic_level_ack_pending(cfg)) 2440 irq_move_masked_irq(data); 2441 unmask_ioapic(cfg); 2442 } 2443 } 2444 #else 2445 static inline bool ioapic_irqd_mask(struct irq_data *data, struct irq_cfg *cfg) 2446 { 2447 return false; 2448 } 2449 static inline void ioapic_irqd_unmask(struct irq_data *data, 2450 struct irq_cfg *cfg, bool masked) 2451 { 2452 } 2453 #endif 2454 2455 static void ack_apic_level(struct irq_data *data) 2456 { 2457 struct irq_cfg *cfg = data->chip_data; 2458 int i, irq = data->irq; 2459 unsigned long v; 2460 bool masked; 2461 2462 irq_complete_move(cfg); 2463 masked = ioapic_irqd_mask(data, cfg); 2464 2465 /* 2466 * It appears there is an erratum which affects at least version 0x11 2467 * of I/O APIC (that's the 82093AA and cores integrated into various 2468 * chipsets). Under certain conditions a level-triggered interrupt is 2469 * erroneously delivered as edge-triggered one but the respective IRR 2470 * bit gets set nevertheless. As a result the I/O unit expects an EOI 2471 * message but it will never arrive and further interrupts are blocked 2472 * from the source. The exact reason is so far unknown, but the 2473 * phenomenon was observed when two consecutive interrupt requests 2474 * from a given source get delivered to the same CPU and the source is 2475 * temporarily disabled in between. 2476 * 2477 * A workaround is to simulate an EOI message manually. We achieve it 2478 * by setting the trigger mode to edge and then to level when the edge 2479 * trigger mode gets detected in the TMR of a local APIC for a 2480 * level-triggered interrupt. We mask the source for the time of the 2481 * operation to prevent an edge-triggered interrupt escaping meanwhile. 2482 * The idea is from Manfred Spraul. --macro 2483 * 2484 * Also in the case when cpu goes offline, fixup_irqs() will forward 2485 * any unhandled interrupt on the offlined cpu to the new cpu 2486 * destination that is handling the corresponding interrupt. This 2487 * interrupt forwarding is done via IPI's. Hence, in this case also 2488 * level-triggered io-apic interrupt will be seen as an edge 2489 * interrupt in the IRR. And we can't rely on the cpu's EOI 2490 * to be broadcasted to the IO-APIC's which will clear the remoteIRR 2491 * corresponding to the level-triggered interrupt. Hence on IO-APIC's 2492 * supporting EOI register, we do an explicit EOI to clear the 2493 * remote IRR and on IO-APIC's which don't have an EOI register, 2494 * we use the above logic (mask+edge followed by unmask+level) from 2495 * Manfred Spraul to clear the remote IRR. 2496 */ 2497 i = cfg->vector; 2498 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); 2499 2500 /* 2501 * We must acknowledge the irq before we move it or the acknowledge will 2502 * not propagate properly. 2503 */ 2504 ack_APIC_irq(); 2505 2506 /* 2507 * Tail end of clearing remote IRR bit (either by delivering the EOI 2508 * message via io-apic EOI register write or simulating it using 2509 * mask+edge followed by unnask+level logic) manually when the 2510 * level triggered interrupt is seen as the edge triggered interrupt 2511 * at the cpu. 2512 */ 2513 if (!(v & (1 << (i & 0x1f)))) { 2514 atomic_inc(&irq_mis_count); 2515 2516 eoi_ioapic_irq(irq, cfg); 2517 } 2518 2519 ioapic_irqd_unmask(data, cfg, masked); 2520 } 2521 2522 static struct irq_chip ioapic_chip __read_mostly = { 2523 .name = "IO-APIC", 2524 .irq_startup = startup_ioapic_irq, 2525 .irq_mask = mask_ioapic_irq, 2526 .irq_unmask = unmask_ioapic_irq, 2527 .irq_ack = ack_apic_edge, 2528 .irq_eoi = ack_apic_level, 2529 .irq_set_affinity = native_ioapic_set_affinity, 2530 .irq_retrigger = ioapic_retrigger_irq, 2531 }; 2532 2533 static inline void init_IO_APIC_traps(void) 2534 { 2535 struct irq_cfg *cfg; 2536 unsigned int irq; 2537 2538 /* 2539 * NOTE! The local APIC isn't very good at handling 2540 * multiple interrupts at the same interrupt level. 2541 * As the interrupt level is determined by taking the 2542 * vector number and shifting that right by 4, we 2543 * want to spread these out a bit so that they don't 2544 * all fall in the same interrupt level. 2545 * 2546 * Also, we've got to be careful not to trash gate 2547 * 0x80, because int 0x80 is hm, kind of importantish. ;) 2548 */ 2549 for_each_active_irq(irq) { 2550 cfg = irq_get_chip_data(irq); 2551 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) { 2552 /* 2553 * Hmm.. We don't have an entry for this, 2554 * so default to an old-fashioned 8259 2555 * interrupt if we can.. 2556 */ 2557 if (irq < legacy_pic->nr_legacy_irqs) 2558 legacy_pic->make_irq(irq); 2559 else 2560 /* Strange. Oh, well.. */ 2561 irq_set_chip(irq, &no_irq_chip); 2562 } 2563 } 2564 } 2565 2566 /* 2567 * The local APIC irq-chip implementation: 2568 */ 2569 2570 static void mask_lapic_irq(struct irq_data *data) 2571 { 2572 unsigned long v; 2573 2574 v = apic_read(APIC_LVT0); 2575 apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 2576 } 2577 2578 static void unmask_lapic_irq(struct irq_data *data) 2579 { 2580 unsigned long v; 2581 2582 v = apic_read(APIC_LVT0); 2583 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED); 2584 } 2585 2586 static void ack_lapic_irq(struct irq_data *data) 2587 { 2588 ack_APIC_irq(); 2589 } 2590 2591 static struct irq_chip lapic_chip __read_mostly = { 2592 .name = "local-APIC", 2593 .irq_mask = mask_lapic_irq, 2594 .irq_unmask = unmask_lapic_irq, 2595 .irq_ack = ack_lapic_irq, 2596 }; 2597 2598 static void lapic_register_intr(int irq) 2599 { 2600 irq_clear_status_flags(irq, IRQ_LEVEL); 2601 irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq, 2602 "edge"); 2603 } 2604 2605 /* 2606 * This looks a bit hackish but it's about the only one way of sending 2607 * a few INTA cycles to 8259As and any associated glue logic. ICR does 2608 * not support the ExtINT mode, unfortunately. We need to send these 2609 * cycles as some i82489DX-based boards have glue logic that keeps the 2610 * 8259A interrupt line asserted until INTA. --macro 2611 */ 2612 static inline void __init unlock_ExtINT_logic(void) 2613 { 2614 int apic, pin, i; 2615 struct IO_APIC_route_entry entry0, entry1; 2616 unsigned char save_control, save_freq_select; 2617 2618 pin = find_isa_irq_pin(8, mp_INT); 2619 if (pin == -1) { 2620 WARN_ON_ONCE(1); 2621 return; 2622 } 2623 apic = find_isa_irq_apic(8, mp_INT); 2624 if (apic == -1) { 2625 WARN_ON_ONCE(1); 2626 return; 2627 } 2628 2629 entry0 = ioapic_read_entry(apic, pin); 2630 clear_IO_APIC_pin(apic, pin); 2631 2632 memset(&entry1, 0, sizeof(entry1)); 2633 2634 entry1.dest_mode = 0; /* physical delivery */ 2635 entry1.mask = 0; /* unmask IRQ now */ 2636 entry1.dest = hard_smp_processor_id(); 2637 entry1.delivery_mode = dest_ExtINT; 2638 entry1.polarity = entry0.polarity; 2639 entry1.trigger = 0; 2640 entry1.vector = 0; 2641 2642 ioapic_write_entry(apic, pin, entry1); 2643 2644 save_control = CMOS_READ(RTC_CONTROL); 2645 save_freq_select = CMOS_READ(RTC_FREQ_SELECT); 2646 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, 2647 RTC_FREQ_SELECT); 2648 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); 2649 2650 i = 100; 2651 while (i-- > 0) { 2652 mdelay(10); 2653 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) 2654 i -= 10; 2655 } 2656 2657 CMOS_WRITE(save_control, RTC_CONTROL); 2658 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); 2659 clear_IO_APIC_pin(apic, pin); 2660 2661 ioapic_write_entry(apic, pin, entry0); 2662 } 2663 2664 static int disable_timer_pin_1 __initdata; 2665 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */ 2666 static int __init disable_timer_pin_setup(char *arg) 2667 { 2668 disable_timer_pin_1 = 1; 2669 return 0; 2670 } 2671 early_param("disable_timer_pin_1", disable_timer_pin_setup); 2672 2673 int timer_through_8259 __initdata; 2674 2675 /* 2676 * This code may look a bit paranoid, but it's supposed to cooperate with 2677 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ 2678 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast 2679 * fanatically on his truly buggy board. 2680 * 2681 * FIXME: really need to revamp this for all platforms. 2682 */ 2683 static inline void __init check_timer(void) 2684 { 2685 struct irq_cfg *cfg = irq_get_chip_data(0); 2686 int node = cpu_to_node(0); 2687 int apic1, pin1, apic2, pin2; 2688 unsigned long flags; 2689 int no_pin1 = 0; 2690 2691 local_irq_save(flags); 2692 2693 /* 2694 * get/set the timer IRQ vector: 2695 */ 2696 legacy_pic->mask(0); 2697 assign_irq_vector(0, cfg, apic->target_cpus()); 2698 2699 /* 2700 * As IRQ0 is to be enabled in the 8259A, the virtual 2701 * wire has to be disabled in the local APIC. Also 2702 * timer interrupts need to be acknowledged manually in 2703 * the 8259A for the i82489DX when using the NMI 2704 * watchdog as that APIC treats NMIs as level-triggered. 2705 * The AEOI mode will finish them in the 8259A 2706 * automatically. 2707 */ 2708 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); 2709 legacy_pic->init(1); 2710 2711 pin1 = find_isa_irq_pin(0, mp_INT); 2712 apic1 = find_isa_irq_apic(0, mp_INT); 2713 pin2 = ioapic_i8259.pin; 2714 apic2 = ioapic_i8259.apic; 2715 2716 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X " 2717 "apic1=%d pin1=%d apic2=%d pin2=%d\n", 2718 cfg->vector, apic1, pin1, apic2, pin2); 2719 2720 /* 2721 * Some BIOS writers are clueless and report the ExtINTA 2722 * I/O APIC input from the cascaded 8259A as the timer 2723 * interrupt input. So just in case, if only one pin 2724 * was found above, try it both directly and through the 2725 * 8259A. 2726 */ 2727 if (pin1 == -1) { 2728 panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC"); 2729 pin1 = pin2; 2730 apic1 = apic2; 2731 no_pin1 = 1; 2732 } else if (pin2 == -1) { 2733 pin2 = pin1; 2734 apic2 = apic1; 2735 } 2736 2737 if (pin1 != -1) { 2738 /* 2739 * Ok, does IRQ0 through the IOAPIC work? 2740 */ 2741 if (no_pin1) { 2742 add_pin_to_irq_node(cfg, node, apic1, pin1); 2743 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector); 2744 } else { 2745 /* for edge trigger, setup_ioapic_irq already 2746 * leave it unmasked. 2747 * so only need to unmask if it is level-trigger 2748 * do we really have level trigger timer? 2749 */ 2750 int idx; 2751 idx = find_irq_entry(apic1, pin1, mp_INT); 2752 if (idx != -1 && irq_trigger(idx)) 2753 unmask_ioapic(cfg); 2754 } 2755 if (timer_irq_works()) { 2756 if (disable_timer_pin_1 > 0) 2757 clear_IO_APIC_pin(0, pin1); 2758 goto out; 2759 } 2760 panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC"); 2761 local_irq_disable(); 2762 clear_IO_APIC_pin(apic1, pin1); 2763 if (!no_pin1) 2764 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: " 2765 "8254 timer not connected to IO-APIC\n"); 2766 2767 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer " 2768 "(IRQ0) through the 8259A ...\n"); 2769 apic_printk(APIC_QUIET, KERN_INFO 2770 "..... (found apic %d pin %d) ...\n", apic2, pin2); 2771 /* 2772 * legacy devices should be connected to IO APIC #0 2773 */ 2774 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2); 2775 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); 2776 legacy_pic->unmask(0); 2777 if (timer_irq_works()) { 2778 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); 2779 timer_through_8259 = 1; 2780 goto out; 2781 } 2782 /* 2783 * Cleanup, just in case ... 2784 */ 2785 local_irq_disable(); 2786 legacy_pic->mask(0); 2787 clear_IO_APIC_pin(apic2, pin2); 2788 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); 2789 } 2790 2791 apic_printk(APIC_QUIET, KERN_INFO 2792 "...trying to set up timer as Virtual Wire IRQ...\n"); 2793 2794 lapic_register_intr(0); 2795 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ 2796 legacy_pic->unmask(0); 2797 2798 if (timer_irq_works()) { 2799 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); 2800 goto out; 2801 } 2802 local_irq_disable(); 2803 legacy_pic->mask(0); 2804 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); 2805 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); 2806 2807 apic_printk(APIC_QUIET, KERN_INFO 2808 "...trying to set up timer as ExtINT IRQ...\n"); 2809 2810 legacy_pic->init(0); 2811 legacy_pic->make_irq(0); 2812 apic_write(APIC_LVT0, APIC_DM_EXTINT); 2813 2814 unlock_ExtINT_logic(); 2815 2816 if (timer_irq_works()) { 2817 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); 2818 goto out; 2819 } 2820 local_irq_disable(); 2821 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n"); 2822 if (x2apic_preenabled) 2823 apic_printk(APIC_QUIET, KERN_INFO 2824 "Perhaps problem with the pre-enabled x2apic mode\n" 2825 "Try booting with x2apic and interrupt-remapping disabled in the bios.\n"); 2826 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a " 2827 "report. Then try booting with the 'noapic' option.\n"); 2828 out: 2829 local_irq_restore(flags); 2830 } 2831 2832 /* 2833 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available 2834 * to devices. However there may be an I/O APIC pin available for 2835 * this interrupt regardless. The pin may be left unconnected, but 2836 * typically it will be reused as an ExtINT cascade interrupt for 2837 * the master 8259A. In the MPS case such a pin will normally be 2838 * reported as an ExtINT interrupt in the MP table. With ACPI 2839 * there is no provision for ExtINT interrupts, and in the absence 2840 * of an override it would be treated as an ordinary ISA I/O APIC 2841 * interrupt, that is edge-triggered and unmasked by default. We 2842 * used to do this, but it caused problems on some systems because 2843 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using 2844 * the same ExtINT cascade interrupt to drive the local APIC of the 2845 * bootstrap processor. Therefore we refrain from routing IRQ2 to 2846 * the I/O APIC in all cases now. No actual device should request 2847 * it anyway. --macro 2848 */ 2849 #define PIC_IRQS (1UL << PIC_CASCADE_IR) 2850 2851 void __init setup_IO_APIC(void) 2852 { 2853 2854 /* 2855 * calling enable_IO_APIC() is moved to setup_local_APIC for BP 2856 */ 2857 io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL; 2858 2859 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); 2860 /* 2861 * Set up IO-APIC IRQ routing. 2862 */ 2863 x86_init.mpparse.setup_ioapic_ids(); 2864 2865 sync_Arb_IDs(); 2866 setup_IO_APIC_irqs(); 2867 init_IO_APIC_traps(); 2868 if (legacy_pic->nr_legacy_irqs) 2869 check_timer(); 2870 } 2871 2872 /* 2873 * Called after all the initialization is done. If we didn't find any 2874 * APIC bugs then we can allow the modify fast path 2875 */ 2876 2877 static int __init io_apic_bug_finalize(void) 2878 { 2879 if (sis_apic_bug == -1) 2880 sis_apic_bug = 0; 2881 return 0; 2882 } 2883 2884 late_initcall(io_apic_bug_finalize); 2885 2886 static void resume_ioapic_id(int ioapic_idx) 2887 { 2888 unsigned long flags; 2889 union IO_APIC_reg_00 reg_00; 2890 2891 raw_spin_lock_irqsave(&ioapic_lock, flags); 2892 reg_00.raw = io_apic_read(ioapic_idx, 0); 2893 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) { 2894 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx); 2895 io_apic_write(ioapic_idx, 0, reg_00.raw); 2896 } 2897 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 2898 } 2899 2900 static void ioapic_resume(void) 2901 { 2902 int ioapic_idx; 2903 2904 for (ioapic_idx = nr_ioapics - 1; ioapic_idx >= 0; ioapic_idx--) 2905 resume_ioapic_id(ioapic_idx); 2906 2907 restore_ioapic_entries(); 2908 } 2909 2910 static struct syscore_ops ioapic_syscore_ops = { 2911 .suspend = save_ioapic_entries, 2912 .resume = ioapic_resume, 2913 }; 2914 2915 static int __init ioapic_init_ops(void) 2916 { 2917 register_syscore_ops(&ioapic_syscore_ops); 2918 2919 return 0; 2920 } 2921 2922 device_initcall(ioapic_init_ops); 2923 2924 /* 2925 * Dynamic irq allocate and deallocation 2926 */ 2927 unsigned int __create_irqs(unsigned int from, unsigned int count, int node) 2928 { 2929 struct irq_cfg **cfg; 2930 unsigned long flags; 2931 int irq, i; 2932 2933 if (from < nr_irqs_gsi) 2934 from = nr_irqs_gsi; 2935 2936 cfg = kzalloc_node(count * sizeof(cfg[0]), GFP_KERNEL, node); 2937 if (!cfg) 2938 return 0; 2939 2940 irq = alloc_irqs_from(from, count, node); 2941 if (irq < 0) 2942 goto out_cfgs; 2943 2944 for (i = 0; i < count; i++) { 2945 cfg[i] = alloc_irq_cfg(irq + i, node); 2946 if (!cfg[i]) 2947 goto out_irqs; 2948 } 2949 2950 raw_spin_lock_irqsave(&vector_lock, flags); 2951 for (i = 0; i < count; i++) 2952 if (__assign_irq_vector(irq + i, cfg[i], apic->target_cpus())) 2953 goto out_vecs; 2954 raw_spin_unlock_irqrestore(&vector_lock, flags); 2955 2956 for (i = 0; i < count; i++) { 2957 irq_set_chip_data(irq + i, cfg[i]); 2958 irq_clear_status_flags(irq + i, IRQ_NOREQUEST); 2959 } 2960 2961 kfree(cfg); 2962 return irq; 2963 2964 out_vecs: 2965 for (i--; i >= 0; i--) 2966 __clear_irq_vector(irq + i, cfg[i]); 2967 raw_spin_unlock_irqrestore(&vector_lock, flags); 2968 out_irqs: 2969 for (i = 0; i < count; i++) 2970 free_irq_at(irq + i, cfg[i]); 2971 out_cfgs: 2972 kfree(cfg); 2973 return 0; 2974 } 2975 2976 unsigned int create_irq_nr(unsigned int from, int node) 2977 { 2978 return __create_irqs(from, 1, node); 2979 } 2980 2981 int create_irq(void) 2982 { 2983 int node = cpu_to_node(0); 2984 unsigned int irq_want; 2985 int irq; 2986 2987 irq_want = nr_irqs_gsi; 2988 irq = create_irq_nr(irq_want, node); 2989 2990 if (irq == 0) 2991 irq = -1; 2992 2993 return irq; 2994 } 2995 2996 void destroy_irq(unsigned int irq) 2997 { 2998 struct irq_cfg *cfg = irq_get_chip_data(irq); 2999 unsigned long flags; 3000 3001 irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE); 3002 3003 free_remapped_irq(irq); 3004 3005 raw_spin_lock_irqsave(&vector_lock, flags); 3006 __clear_irq_vector(irq, cfg); 3007 raw_spin_unlock_irqrestore(&vector_lock, flags); 3008 free_irq_at(irq, cfg); 3009 } 3010 3011 void destroy_irqs(unsigned int irq, unsigned int count) 3012 { 3013 unsigned int i; 3014 3015 for (i = 0; i < count; i++) 3016 destroy_irq(irq + i); 3017 } 3018 3019 /* 3020 * MSI message composition 3021 */ 3022 void native_compose_msi_msg(struct pci_dev *pdev, 3023 unsigned int irq, unsigned int dest, 3024 struct msi_msg *msg, u8 hpet_id) 3025 { 3026 struct irq_cfg *cfg = irq_cfg(irq); 3027 3028 msg->address_hi = MSI_ADDR_BASE_HI; 3029 3030 if (x2apic_enabled()) 3031 msg->address_hi |= MSI_ADDR_EXT_DEST_ID(dest); 3032 3033 msg->address_lo = 3034 MSI_ADDR_BASE_LO | 3035 ((apic->irq_dest_mode == 0) ? 3036 MSI_ADDR_DEST_MODE_PHYSICAL: 3037 MSI_ADDR_DEST_MODE_LOGICAL) | 3038 ((apic->irq_delivery_mode != dest_LowestPrio) ? 3039 MSI_ADDR_REDIRECTION_CPU: 3040 MSI_ADDR_REDIRECTION_LOWPRI) | 3041 MSI_ADDR_DEST_ID(dest); 3042 3043 msg->data = 3044 MSI_DATA_TRIGGER_EDGE | 3045 MSI_DATA_LEVEL_ASSERT | 3046 ((apic->irq_delivery_mode != dest_LowestPrio) ? 3047 MSI_DATA_DELIVERY_FIXED: 3048 MSI_DATA_DELIVERY_LOWPRI) | 3049 MSI_DATA_VECTOR(cfg->vector); 3050 } 3051 3052 #ifdef CONFIG_PCI_MSI 3053 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, 3054 struct msi_msg *msg, u8 hpet_id) 3055 { 3056 struct irq_cfg *cfg; 3057 int err; 3058 unsigned dest; 3059 3060 if (disable_apic) 3061 return -ENXIO; 3062 3063 cfg = irq_cfg(irq); 3064 err = assign_irq_vector(irq, cfg, apic->target_cpus()); 3065 if (err) 3066 return err; 3067 3068 err = apic->cpu_mask_to_apicid_and(cfg->domain, 3069 apic->target_cpus(), &dest); 3070 if (err) 3071 return err; 3072 3073 x86_msi.compose_msi_msg(pdev, irq, dest, msg, hpet_id); 3074 3075 return 0; 3076 } 3077 3078 static int 3079 msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) 3080 { 3081 struct irq_cfg *cfg = data->chip_data; 3082 struct msi_msg msg; 3083 unsigned int dest; 3084 3085 if (__ioapic_set_affinity(data, mask, &dest)) 3086 return -1; 3087 3088 __get_cached_msi_msg(data->msi_desc, &msg); 3089 3090 msg.data &= ~MSI_DATA_VECTOR_MASK; 3091 msg.data |= MSI_DATA_VECTOR(cfg->vector); 3092 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; 3093 msg.address_lo |= MSI_ADDR_DEST_ID(dest); 3094 3095 __write_msi_msg(data->msi_desc, &msg); 3096 3097 return IRQ_SET_MASK_OK_NOCOPY; 3098 } 3099 3100 /* 3101 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices, 3102 * which implement the MSI or MSI-X Capability Structure. 3103 */ 3104 static struct irq_chip msi_chip = { 3105 .name = "PCI-MSI", 3106 .irq_unmask = unmask_msi_irq, 3107 .irq_mask = mask_msi_irq, 3108 .irq_ack = ack_apic_edge, 3109 .irq_set_affinity = msi_set_affinity, 3110 .irq_retrigger = ioapic_retrigger_irq, 3111 }; 3112 3113 int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, 3114 unsigned int irq_base, unsigned int irq_offset) 3115 { 3116 struct irq_chip *chip = &msi_chip; 3117 struct msi_msg msg; 3118 unsigned int irq = irq_base + irq_offset; 3119 int ret; 3120 3121 ret = msi_compose_msg(dev, irq, &msg, -1); 3122 if (ret < 0) 3123 return ret; 3124 3125 irq_set_msi_desc_off(irq_base, irq_offset, msidesc); 3126 3127 /* 3128 * MSI-X message is written per-IRQ, the offset is always 0. 3129 * MSI message denotes a contiguous group of IRQs, written for 0th IRQ. 3130 */ 3131 if (!irq_offset) 3132 write_msi_msg(irq, &msg); 3133 3134 setup_remapped_irq(irq, irq_get_chip_data(irq), chip); 3135 3136 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge"); 3137 3138 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq); 3139 3140 return 0; 3141 } 3142 3143 int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) 3144 { 3145 unsigned int irq, irq_want; 3146 struct msi_desc *msidesc; 3147 int node, ret; 3148 3149 /* Multiple MSI vectors only supported with interrupt remapping */ 3150 if (type == PCI_CAP_ID_MSI && nvec > 1) 3151 return 1; 3152 3153 node = dev_to_node(&dev->dev); 3154 irq_want = nr_irqs_gsi; 3155 list_for_each_entry(msidesc, &dev->msi_list, list) { 3156 irq = create_irq_nr(irq_want, node); 3157 if (irq == 0) 3158 return -ENOSPC; 3159 3160 irq_want = irq + 1; 3161 3162 ret = setup_msi_irq(dev, msidesc, irq, 0); 3163 if (ret < 0) 3164 goto error; 3165 } 3166 return 0; 3167 3168 error: 3169 destroy_irq(irq); 3170 return ret; 3171 } 3172 3173 void native_teardown_msi_irq(unsigned int irq) 3174 { 3175 destroy_irq(irq); 3176 } 3177 3178 #ifdef CONFIG_DMAR_TABLE 3179 static int 3180 dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask, 3181 bool force) 3182 { 3183 struct irq_cfg *cfg = data->chip_data; 3184 unsigned int dest, irq = data->irq; 3185 struct msi_msg msg; 3186 3187 if (__ioapic_set_affinity(data, mask, &dest)) 3188 return -1; 3189 3190 dmar_msi_read(irq, &msg); 3191 3192 msg.data &= ~MSI_DATA_VECTOR_MASK; 3193 msg.data |= MSI_DATA_VECTOR(cfg->vector); 3194 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; 3195 msg.address_lo |= MSI_ADDR_DEST_ID(dest); 3196 msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest); 3197 3198 dmar_msi_write(irq, &msg); 3199 3200 return IRQ_SET_MASK_OK_NOCOPY; 3201 } 3202 3203 static struct irq_chip dmar_msi_type = { 3204 .name = "DMAR_MSI", 3205 .irq_unmask = dmar_msi_unmask, 3206 .irq_mask = dmar_msi_mask, 3207 .irq_ack = ack_apic_edge, 3208 .irq_set_affinity = dmar_msi_set_affinity, 3209 .irq_retrigger = ioapic_retrigger_irq, 3210 }; 3211 3212 int arch_setup_dmar_msi(unsigned int irq) 3213 { 3214 int ret; 3215 struct msi_msg msg; 3216 3217 ret = msi_compose_msg(NULL, irq, &msg, -1); 3218 if (ret < 0) 3219 return ret; 3220 dmar_msi_write(irq, &msg); 3221 irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq, 3222 "edge"); 3223 return 0; 3224 } 3225 #endif 3226 3227 #ifdef CONFIG_HPET_TIMER 3228 3229 static int hpet_msi_set_affinity(struct irq_data *data, 3230 const struct cpumask *mask, bool force) 3231 { 3232 struct irq_cfg *cfg = data->chip_data; 3233 struct msi_msg msg; 3234 unsigned int dest; 3235 3236 if (__ioapic_set_affinity(data, mask, &dest)) 3237 return -1; 3238 3239 hpet_msi_read(data->handler_data, &msg); 3240 3241 msg.data &= ~MSI_DATA_VECTOR_MASK; 3242 msg.data |= MSI_DATA_VECTOR(cfg->vector); 3243 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK; 3244 msg.address_lo |= MSI_ADDR_DEST_ID(dest); 3245 3246 hpet_msi_write(data->handler_data, &msg); 3247 3248 return IRQ_SET_MASK_OK_NOCOPY; 3249 } 3250 3251 static struct irq_chip hpet_msi_type = { 3252 .name = "HPET_MSI", 3253 .irq_unmask = hpet_msi_unmask, 3254 .irq_mask = hpet_msi_mask, 3255 .irq_ack = ack_apic_edge, 3256 .irq_set_affinity = hpet_msi_set_affinity, 3257 .irq_retrigger = ioapic_retrigger_irq, 3258 }; 3259 3260 int default_setup_hpet_msi(unsigned int irq, unsigned int id) 3261 { 3262 struct irq_chip *chip = &hpet_msi_type; 3263 struct msi_msg msg; 3264 int ret; 3265 3266 ret = msi_compose_msg(NULL, irq, &msg, id); 3267 if (ret < 0) 3268 return ret; 3269 3270 hpet_msi_write(irq_get_handler_data(irq), &msg); 3271 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); 3272 setup_remapped_irq(irq, irq_get_chip_data(irq), chip); 3273 3274 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge"); 3275 return 0; 3276 } 3277 #endif 3278 3279 #endif /* CONFIG_PCI_MSI */ 3280 /* 3281 * Hypertransport interrupt support 3282 */ 3283 #ifdef CONFIG_HT_IRQ 3284 3285 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) 3286 { 3287 struct ht_irq_msg msg; 3288 fetch_ht_irq_msg(irq, &msg); 3289 3290 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); 3291 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK); 3292 3293 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); 3294 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest); 3295 3296 write_ht_irq_msg(irq, &msg); 3297 } 3298 3299 static int 3300 ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force) 3301 { 3302 struct irq_cfg *cfg = data->chip_data; 3303 unsigned int dest; 3304 3305 if (__ioapic_set_affinity(data, mask, &dest)) 3306 return -1; 3307 3308 target_ht_irq(data->irq, dest, cfg->vector); 3309 return IRQ_SET_MASK_OK_NOCOPY; 3310 } 3311 3312 static struct irq_chip ht_irq_chip = { 3313 .name = "PCI-HT", 3314 .irq_mask = mask_ht_irq, 3315 .irq_unmask = unmask_ht_irq, 3316 .irq_ack = ack_apic_edge, 3317 .irq_set_affinity = ht_set_affinity, 3318 .irq_retrigger = ioapic_retrigger_irq, 3319 }; 3320 3321 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) 3322 { 3323 struct irq_cfg *cfg; 3324 struct ht_irq_msg msg; 3325 unsigned dest; 3326 int err; 3327 3328 if (disable_apic) 3329 return -ENXIO; 3330 3331 cfg = irq_cfg(irq); 3332 err = assign_irq_vector(irq, cfg, apic->target_cpus()); 3333 if (err) 3334 return err; 3335 3336 err = apic->cpu_mask_to_apicid_and(cfg->domain, 3337 apic->target_cpus(), &dest); 3338 if (err) 3339 return err; 3340 3341 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest); 3342 3343 msg.address_lo = 3344 HT_IRQ_LOW_BASE | 3345 HT_IRQ_LOW_DEST_ID(dest) | 3346 HT_IRQ_LOW_VECTOR(cfg->vector) | 3347 ((apic->irq_dest_mode == 0) ? 3348 HT_IRQ_LOW_DM_PHYSICAL : 3349 HT_IRQ_LOW_DM_LOGICAL) | 3350 HT_IRQ_LOW_RQEOI_EDGE | 3351 ((apic->irq_delivery_mode != dest_LowestPrio) ? 3352 HT_IRQ_LOW_MT_FIXED : 3353 HT_IRQ_LOW_MT_ARBITRATED) | 3354 HT_IRQ_LOW_IRQ_MASKED; 3355 3356 write_ht_irq_msg(irq, &msg); 3357 3358 irq_set_chip_and_handler_name(irq, &ht_irq_chip, 3359 handle_edge_irq, "edge"); 3360 3361 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq); 3362 3363 return 0; 3364 } 3365 #endif /* CONFIG_HT_IRQ */ 3366 3367 static int 3368 io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr) 3369 { 3370 struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node); 3371 int ret; 3372 3373 if (!cfg) 3374 return -EINVAL; 3375 ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin); 3376 if (!ret) 3377 setup_ioapic_irq(irq, cfg, attr); 3378 return ret; 3379 } 3380 3381 int io_apic_setup_irq_pin_once(unsigned int irq, int node, 3382 struct io_apic_irq_attr *attr) 3383 { 3384 unsigned int ioapic_idx = attr->ioapic, pin = attr->ioapic_pin; 3385 int ret; 3386 3387 /* Avoid redundant programming */ 3388 if (test_bit(pin, ioapics[ioapic_idx].pin_programmed)) { 3389 pr_debug("Pin %d-%d already programmed\n", 3390 mpc_ioapic_id(ioapic_idx), pin); 3391 return 0; 3392 } 3393 ret = io_apic_setup_irq_pin(irq, node, attr); 3394 if (!ret) 3395 set_bit(pin, ioapics[ioapic_idx].pin_programmed); 3396 return ret; 3397 } 3398 3399 static int __init io_apic_get_redir_entries(int ioapic) 3400 { 3401 union IO_APIC_reg_01 reg_01; 3402 unsigned long flags; 3403 3404 raw_spin_lock_irqsave(&ioapic_lock, flags); 3405 reg_01.raw = io_apic_read(ioapic, 1); 3406 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 3407 3408 /* The register returns the maximum index redir index 3409 * supported, which is one less than the total number of redir 3410 * entries. 3411 */ 3412 return reg_01.bits.entries + 1; 3413 } 3414 3415 static void __init probe_nr_irqs_gsi(void) 3416 { 3417 int nr; 3418 3419 nr = gsi_top + NR_IRQS_LEGACY; 3420 if (nr > nr_irqs_gsi) 3421 nr_irqs_gsi = nr; 3422 3423 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi); 3424 } 3425 3426 int get_nr_irqs_gsi(void) 3427 { 3428 return nr_irqs_gsi; 3429 } 3430 3431 int __init arch_probe_nr_irqs(void) 3432 { 3433 int nr; 3434 3435 if (nr_irqs > (NR_VECTORS * nr_cpu_ids)) 3436 nr_irqs = NR_VECTORS * nr_cpu_ids; 3437 3438 nr = nr_irqs_gsi + 8 * nr_cpu_ids; 3439 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ) 3440 /* 3441 * for MSI and HT dyn irq 3442 */ 3443 nr += nr_irqs_gsi * 16; 3444 #endif 3445 if (nr < nr_irqs) 3446 nr_irqs = nr; 3447 3448 return NR_IRQS_LEGACY; 3449 } 3450 3451 int io_apic_set_pci_routing(struct device *dev, int irq, 3452 struct io_apic_irq_attr *irq_attr) 3453 { 3454 int node; 3455 3456 if (!IO_APIC_IRQ(irq)) { 3457 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n", 3458 irq_attr->ioapic); 3459 return -EINVAL; 3460 } 3461 3462 node = dev ? dev_to_node(dev) : cpu_to_node(0); 3463 3464 return io_apic_setup_irq_pin_once(irq, node, irq_attr); 3465 } 3466 3467 #ifdef CONFIG_X86_32 3468 static int __init io_apic_get_unique_id(int ioapic, int apic_id) 3469 { 3470 union IO_APIC_reg_00 reg_00; 3471 static physid_mask_t apic_id_map = PHYSID_MASK_NONE; 3472 physid_mask_t tmp; 3473 unsigned long flags; 3474 int i = 0; 3475 3476 /* 3477 * The P4 platform supports up to 256 APIC IDs on two separate APIC 3478 * buses (one for LAPICs, one for IOAPICs), where predecessors only 3479 * supports up to 16 on one shared APIC bus. 3480 * 3481 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full 3482 * advantage of new APIC bus architecture. 3483 */ 3484 3485 if (physids_empty(apic_id_map)) 3486 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map); 3487 3488 raw_spin_lock_irqsave(&ioapic_lock, flags); 3489 reg_00.raw = io_apic_read(ioapic, 0); 3490 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 3491 3492 if (apic_id >= get_physical_broadcast()) { 3493 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying " 3494 "%d\n", ioapic, apic_id, reg_00.bits.ID); 3495 apic_id = reg_00.bits.ID; 3496 } 3497 3498 /* 3499 * Every APIC in a system must have a unique ID or we get lots of nice 3500 * 'stuck on smp_invalidate_needed IPI wait' messages. 3501 */ 3502 if (apic->check_apicid_used(&apic_id_map, apic_id)) { 3503 3504 for (i = 0; i < get_physical_broadcast(); i++) { 3505 if (!apic->check_apicid_used(&apic_id_map, i)) 3506 break; 3507 } 3508 3509 if (i == get_physical_broadcast()) 3510 panic("Max apic_id exceeded!\n"); 3511 3512 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, " 3513 "trying %d\n", ioapic, apic_id, i); 3514 3515 apic_id = i; 3516 } 3517 3518 apic->apicid_to_cpu_present(apic_id, &tmp); 3519 physids_or(apic_id_map, apic_id_map, tmp); 3520 3521 if (reg_00.bits.ID != apic_id) { 3522 reg_00.bits.ID = apic_id; 3523 3524 raw_spin_lock_irqsave(&ioapic_lock, flags); 3525 io_apic_write(ioapic, 0, reg_00.raw); 3526 reg_00.raw = io_apic_read(ioapic, 0); 3527 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 3528 3529 /* Sanity check */ 3530 if (reg_00.bits.ID != apic_id) { 3531 pr_err("IOAPIC[%d]: Unable to change apic_id!\n", 3532 ioapic); 3533 return -1; 3534 } 3535 } 3536 3537 apic_printk(APIC_VERBOSE, KERN_INFO 3538 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id); 3539 3540 return apic_id; 3541 } 3542 3543 static u8 __init io_apic_unique_id(u8 id) 3544 { 3545 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 3546 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid])) 3547 return io_apic_get_unique_id(nr_ioapics, id); 3548 else 3549 return id; 3550 } 3551 #else 3552 static u8 __init io_apic_unique_id(u8 id) 3553 { 3554 int i; 3555 DECLARE_BITMAP(used, 256); 3556 3557 bitmap_zero(used, 256); 3558 for (i = 0; i < nr_ioapics; i++) { 3559 __set_bit(mpc_ioapic_id(i), used); 3560 } 3561 if (!test_bit(id, used)) 3562 return id; 3563 return find_first_zero_bit(used, 256); 3564 } 3565 #endif 3566 3567 static int __init io_apic_get_version(int ioapic) 3568 { 3569 union IO_APIC_reg_01 reg_01; 3570 unsigned long flags; 3571 3572 raw_spin_lock_irqsave(&ioapic_lock, flags); 3573 reg_01.raw = io_apic_read(ioapic, 1); 3574 raw_spin_unlock_irqrestore(&ioapic_lock, flags); 3575 3576 return reg_01.bits.version; 3577 } 3578 3579 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity) 3580 { 3581 int ioapic, pin, idx; 3582 3583 if (skip_ioapic_setup) 3584 return -1; 3585 3586 ioapic = mp_find_ioapic(gsi); 3587 if (ioapic < 0) 3588 return -1; 3589 3590 pin = mp_find_ioapic_pin(ioapic, gsi); 3591 if (pin < 0) 3592 return -1; 3593 3594 idx = find_irq_entry(ioapic, pin, mp_INT); 3595 if (idx < 0) 3596 return -1; 3597 3598 *trigger = irq_trigger(idx); 3599 *polarity = irq_polarity(idx); 3600 return 0; 3601 } 3602 3603 /* 3604 * This function currently is only a helper for the i386 smp boot process where 3605 * we need to reprogram the ioredtbls to cater for the cpus which have come online 3606 * so mask in all cases should simply be apic->target_cpus() 3607 */ 3608 #ifdef CONFIG_SMP 3609 void __init setup_ioapic_dest(void) 3610 { 3611 int pin, ioapic, irq, irq_entry; 3612 const struct cpumask *mask; 3613 struct irq_data *idata; 3614 3615 if (skip_ioapic_setup == 1) 3616 return; 3617 3618 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) 3619 for (pin = 0; pin < ioapics[ioapic].nr_registers; pin++) { 3620 irq_entry = find_irq_entry(ioapic, pin, mp_INT); 3621 if (irq_entry == -1) 3622 continue; 3623 irq = pin_2_irq(irq_entry, ioapic, pin); 3624 3625 if ((ioapic > 0) && (irq > 16)) 3626 continue; 3627 3628 idata = irq_get_irq_data(irq); 3629 3630 /* 3631 * Honour affinities which have been set in early boot 3632 */ 3633 if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata)) 3634 mask = idata->affinity; 3635 else 3636 mask = apic->target_cpus(); 3637 3638 x86_io_apic_ops.set_affinity(idata, mask, false); 3639 } 3640 3641 } 3642 #endif 3643 3644 #define IOAPIC_RESOURCE_NAME_SIZE 11 3645 3646 static struct resource *ioapic_resources; 3647 3648 static struct resource * __init ioapic_setup_resources(int nr_ioapics) 3649 { 3650 unsigned long n; 3651 struct resource *res; 3652 char *mem; 3653 int i; 3654 3655 if (nr_ioapics <= 0) 3656 return NULL; 3657 3658 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource); 3659 n *= nr_ioapics; 3660 3661 mem = alloc_bootmem(n); 3662 res = (void *)mem; 3663 3664 mem += sizeof(struct resource) * nr_ioapics; 3665 3666 for (i = 0; i < nr_ioapics; i++) { 3667 res[i].name = mem; 3668 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY; 3669 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i); 3670 mem += IOAPIC_RESOURCE_NAME_SIZE; 3671 } 3672 3673 ioapic_resources = res; 3674 3675 return res; 3676 } 3677 3678 void __init native_io_apic_init_mappings(void) 3679 { 3680 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0; 3681 struct resource *ioapic_res; 3682 int i; 3683 3684 ioapic_res = ioapic_setup_resources(nr_ioapics); 3685 for (i = 0; i < nr_ioapics; i++) { 3686 if (smp_found_config) { 3687 ioapic_phys = mpc_ioapic_addr(i); 3688 #ifdef CONFIG_X86_32 3689 if (!ioapic_phys) { 3690 printk(KERN_ERR 3691 "WARNING: bogus zero IO-APIC " 3692 "address found in MPTABLE, " 3693 "disabling IO/APIC support!\n"); 3694 smp_found_config = 0; 3695 skip_ioapic_setup = 1; 3696 goto fake_ioapic_page; 3697 } 3698 #endif 3699 } else { 3700 #ifdef CONFIG_X86_32 3701 fake_ioapic_page: 3702 #endif 3703 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE); 3704 ioapic_phys = __pa(ioapic_phys); 3705 } 3706 set_fixmap_nocache(idx, ioapic_phys); 3707 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n", 3708 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK), 3709 ioapic_phys); 3710 idx++; 3711 3712 ioapic_res->start = ioapic_phys; 3713 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1; 3714 ioapic_res++; 3715 } 3716 3717 probe_nr_irqs_gsi(); 3718 } 3719 3720 void __init ioapic_insert_resources(void) 3721 { 3722 int i; 3723 struct resource *r = ioapic_resources; 3724 3725 if (!r) { 3726 if (nr_ioapics > 0) 3727 printk(KERN_ERR 3728 "IO APIC resources couldn't be allocated.\n"); 3729 return; 3730 } 3731 3732 for (i = 0; i < nr_ioapics; i++) { 3733 insert_resource(&iomem_resource, r); 3734 r++; 3735 } 3736 } 3737 3738 int mp_find_ioapic(u32 gsi) 3739 { 3740 int i = 0; 3741 3742 if (nr_ioapics == 0) 3743 return -1; 3744 3745 /* Find the IOAPIC that manages this GSI. */ 3746 for (i = 0; i < nr_ioapics; i++) { 3747 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i); 3748 if ((gsi >= gsi_cfg->gsi_base) 3749 && (gsi <= gsi_cfg->gsi_end)) 3750 return i; 3751 } 3752 3753 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi); 3754 return -1; 3755 } 3756 3757 int mp_find_ioapic_pin(int ioapic, u32 gsi) 3758 { 3759 struct mp_ioapic_gsi *gsi_cfg; 3760 3761 if (WARN_ON(ioapic == -1)) 3762 return -1; 3763 3764 gsi_cfg = mp_ioapic_gsi_routing(ioapic); 3765 if (WARN_ON(gsi > gsi_cfg->gsi_end)) 3766 return -1; 3767 3768 return gsi - gsi_cfg->gsi_base; 3769 } 3770 3771 static __init int bad_ioapic(unsigned long address) 3772 { 3773 if (nr_ioapics >= MAX_IO_APICS) { 3774 pr_warn("WARNING: Max # of I/O APICs (%d) exceeded (found %d), skipping\n", 3775 MAX_IO_APICS, nr_ioapics); 3776 return 1; 3777 } 3778 if (!address) { 3779 pr_warn("WARNING: Bogus (zero) I/O APIC address found in table, skipping!\n"); 3780 return 1; 3781 } 3782 return 0; 3783 } 3784 3785 static __init int bad_ioapic_register(int idx) 3786 { 3787 union IO_APIC_reg_00 reg_00; 3788 union IO_APIC_reg_01 reg_01; 3789 union IO_APIC_reg_02 reg_02; 3790 3791 reg_00.raw = io_apic_read(idx, 0); 3792 reg_01.raw = io_apic_read(idx, 1); 3793 reg_02.raw = io_apic_read(idx, 2); 3794 3795 if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) { 3796 pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n", 3797 mpc_ioapic_addr(idx)); 3798 return 1; 3799 } 3800 3801 return 0; 3802 } 3803 3804 void __init mp_register_ioapic(int id, u32 address, u32 gsi_base) 3805 { 3806 int idx = 0; 3807 int entries; 3808 struct mp_ioapic_gsi *gsi_cfg; 3809 3810 if (bad_ioapic(address)) 3811 return; 3812 3813 idx = nr_ioapics; 3814 3815 ioapics[idx].mp_config.type = MP_IOAPIC; 3816 ioapics[idx].mp_config.flags = MPC_APIC_USABLE; 3817 ioapics[idx].mp_config.apicaddr = address; 3818 3819 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address); 3820 3821 if (bad_ioapic_register(idx)) { 3822 clear_fixmap(FIX_IO_APIC_BASE_0 + idx); 3823 return; 3824 } 3825 3826 ioapics[idx].mp_config.apicid = io_apic_unique_id(id); 3827 ioapics[idx].mp_config.apicver = io_apic_get_version(idx); 3828 3829 /* 3830 * Build basic GSI lookup table to facilitate gsi->io_apic lookups 3831 * and to prevent reprogramming of IOAPIC pins (PCI GSIs). 3832 */ 3833 entries = io_apic_get_redir_entries(idx); 3834 gsi_cfg = mp_ioapic_gsi_routing(idx); 3835 gsi_cfg->gsi_base = gsi_base; 3836 gsi_cfg->gsi_end = gsi_base + entries - 1; 3837 3838 /* 3839 * The number of IO-APIC IRQ registers (== #pins): 3840 */ 3841 ioapics[idx].nr_registers = entries; 3842 3843 if (gsi_cfg->gsi_end >= gsi_top) 3844 gsi_top = gsi_cfg->gsi_end + 1; 3845 3846 pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n", 3847 idx, mpc_ioapic_id(idx), 3848 mpc_ioapic_ver(idx), mpc_ioapic_addr(idx), 3849 gsi_cfg->gsi_base, gsi_cfg->gsi_end); 3850 3851 nr_ioapics++; 3852 } 3853 3854 /* Enable IOAPIC early just for system timer */ 3855 void __init pre_init_apic_IRQ0(void) 3856 { 3857 struct io_apic_irq_attr attr = { 0, 0, 0, 0 }; 3858 3859 printk(KERN_INFO "Early APIC setup for system timer0\n"); 3860 #ifndef CONFIG_SMP 3861 physid_set_mask_of_physid(boot_cpu_physical_apicid, 3862 &phys_cpu_present_map); 3863 #endif 3864 setup_local_APIC(); 3865 3866 io_apic_setup_irq_pin(0, 0, &attr); 3867 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, 3868 "edge"); 3869 } 3870