xref: /openbmc/linux/arch/x86/kernel/apic/io_apic.c (revision 0edbfea5)
1 /*
2  *	Intel IO-APIC support for multi-Pentium hosts.
3  *
4  *	Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
5  *
6  *	Many thanks to Stig Venaas for trying out countless experimental
7  *	patches and reporting/debugging problems patiently!
8  *
9  *	(c) 1999, Multiple IO-APIC support, developed by
10  *	Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12  *	further tested and cleaned up by Zach Brown <zab@redhat.com>
13  *	and Ingo Molnar <mingo@redhat.com>
14  *
15  *	Fixes
16  *	Maciej W. Rozycki	:	Bits for genuine 82489DX APICs;
17  *					thanks to Eric Gilmore
18  *					and Rolf G. Tews
19  *					for testing these extensively
20  *	Paul Diefenbaugh	:	Added full ACPI support
21  *
22  * Historical information which is worth to be preserved:
23  *
24  * - SiS APIC rmw bug:
25  *
26  *	We used to have a workaround for a bug in SiS chips which
27  *	required to rewrite the index register for a read-modify-write
28  *	operation as the chip lost the index information which was
29  *	setup for the read already. We cache the data now, so that
30  *	workaround has been removed.
31  */
32 
33 #include <linux/mm.h>
34 #include <linux/interrupt.h>
35 #include <linux/init.h>
36 #include <linux/delay.h>
37 #include <linux/sched.h>
38 #include <linux/pci.h>
39 #include <linux/mc146818rtc.h>
40 #include <linux/compiler.h>
41 #include <linux/acpi.h>
42 #include <linux/module.h>
43 #include <linux/syscore_ops.h>
44 #include <linux/freezer.h>
45 #include <linux/kthread.h>
46 #include <linux/jiffies.h>	/* time_after() */
47 #include <linux/slab.h>
48 #include <linux/bootmem.h>
49 
50 #include <asm/irqdomain.h>
51 #include <asm/idle.h>
52 #include <asm/io.h>
53 #include <asm/smp.h>
54 #include <asm/cpu.h>
55 #include <asm/desc.h>
56 #include <asm/proto.h>
57 #include <asm/acpi.h>
58 #include <asm/dma.h>
59 #include <asm/timer.h>
60 #include <asm/i8259.h>
61 #include <asm/setup.h>
62 #include <asm/irq_remapping.h>
63 #include <asm/hw_irq.h>
64 
65 #include <asm/apic.h>
66 
67 #define	for_each_ioapic(idx)		\
68 	for ((idx) = 0; (idx) < nr_ioapics; (idx)++)
69 #define	for_each_ioapic_reverse(idx)	\
70 	for ((idx) = nr_ioapics - 1; (idx) >= 0; (idx)--)
71 #define	for_each_pin(idx, pin)		\
72 	for ((pin) = 0; (pin) < ioapics[(idx)].nr_registers; (pin)++)
73 #define	for_each_ioapic_pin(idx, pin)	\
74 	for_each_ioapic((idx))		\
75 		for_each_pin((idx), (pin))
76 #define for_each_irq_pin(entry, head) \
77 	list_for_each_entry(entry, &head, list)
78 
79 static DEFINE_RAW_SPINLOCK(ioapic_lock);
80 static DEFINE_MUTEX(ioapic_mutex);
81 static unsigned int ioapic_dynirq_base;
82 static int ioapic_initialized;
83 
84 struct irq_pin_list {
85 	struct list_head list;
86 	int apic, pin;
87 };
88 
89 struct mp_chip_data {
90 	struct list_head irq_2_pin;
91 	struct IO_APIC_route_entry entry;
92 	int trigger;
93 	int polarity;
94 	u32 count;
95 	bool isa_irq;
96 };
97 
98 struct mp_ioapic_gsi {
99 	u32 gsi_base;
100 	u32 gsi_end;
101 };
102 
103 static struct ioapic {
104 	/*
105 	 * # of IRQ routing registers
106 	 */
107 	int nr_registers;
108 	/*
109 	 * Saved state during suspend/resume, or while enabling intr-remap.
110 	 */
111 	struct IO_APIC_route_entry *saved_registers;
112 	/* I/O APIC config */
113 	struct mpc_ioapic mp_config;
114 	/* IO APIC gsi routing info */
115 	struct mp_ioapic_gsi  gsi_config;
116 	struct ioapic_domain_cfg irqdomain_cfg;
117 	struct irq_domain *irqdomain;
118 	struct resource *iomem_res;
119 } ioapics[MAX_IO_APICS];
120 
121 #define mpc_ioapic_ver(ioapic_idx)	ioapics[ioapic_idx].mp_config.apicver
122 
123 int mpc_ioapic_id(int ioapic_idx)
124 {
125 	return ioapics[ioapic_idx].mp_config.apicid;
126 }
127 
128 unsigned int mpc_ioapic_addr(int ioapic_idx)
129 {
130 	return ioapics[ioapic_idx].mp_config.apicaddr;
131 }
132 
133 static inline struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
134 {
135 	return &ioapics[ioapic_idx].gsi_config;
136 }
137 
138 static inline int mp_ioapic_pin_count(int ioapic)
139 {
140 	struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
141 
142 	return gsi_cfg->gsi_end - gsi_cfg->gsi_base + 1;
143 }
144 
145 static inline u32 mp_pin_to_gsi(int ioapic, int pin)
146 {
147 	return mp_ioapic_gsi_routing(ioapic)->gsi_base + pin;
148 }
149 
150 static inline bool mp_is_legacy_irq(int irq)
151 {
152 	return irq >= 0 && irq < nr_legacy_irqs();
153 }
154 
155 /*
156  * Initialize all legacy IRQs and all pins on the first IOAPIC
157  * if we have legacy interrupt controller. Kernel boot option "pirq="
158  * may rely on non-legacy pins on the first IOAPIC.
159  */
160 static inline int mp_init_irq_at_boot(int ioapic, int irq)
161 {
162 	if (!nr_legacy_irqs())
163 		return 0;
164 
165 	return ioapic == 0 || mp_is_legacy_irq(irq);
166 }
167 
168 static inline struct irq_domain *mp_ioapic_irqdomain(int ioapic)
169 {
170 	return ioapics[ioapic].irqdomain;
171 }
172 
173 int nr_ioapics;
174 
175 /* The one past the highest gsi number used */
176 u32 gsi_top;
177 
178 /* MP IRQ source entries */
179 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
180 
181 /* # of MP IRQ source entries */
182 int mp_irq_entries;
183 
184 #ifdef CONFIG_EISA
185 int mp_bus_id_to_type[MAX_MP_BUSSES];
186 #endif
187 
188 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
189 
190 int skip_ioapic_setup;
191 
192 /**
193  * disable_ioapic_support() - disables ioapic support at runtime
194  */
195 void disable_ioapic_support(void)
196 {
197 #ifdef CONFIG_PCI
198 	noioapicquirk = 1;
199 	noioapicreroute = -1;
200 #endif
201 	skip_ioapic_setup = 1;
202 }
203 
204 static int __init parse_noapic(char *str)
205 {
206 	/* disable IO-APIC */
207 	disable_ioapic_support();
208 	return 0;
209 }
210 early_param("noapic", parse_noapic);
211 
212 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
213 void mp_save_irq(struct mpc_intsrc *m)
214 {
215 	int i;
216 
217 	apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
218 		" IRQ %02x, APIC ID %x, APIC INT %02x\n",
219 		m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
220 		m->srcbusirq, m->dstapic, m->dstirq);
221 
222 	for (i = 0; i < mp_irq_entries; i++) {
223 		if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
224 			return;
225 	}
226 
227 	memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
228 	if (++mp_irq_entries == MAX_IRQ_SOURCES)
229 		panic("Max # of irq sources exceeded!!\n");
230 }
231 
232 static void alloc_ioapic_saved_registers(int idx)
233 {
234 	size_t size;
235 
236 	if (ioapics[idx].saved_registers)
237 		return;
238 
239 	size = sizeof(struct IO_APIC_route_entry) * ioapics[idx].nr_registers;
240 	ioapics[idx].saved_registers = kzalloc(size, GFP_KERNEL);
241 	if (!ioapics[idx].saved_registers)
242 		pr_err("IOAPIC %d: suspend/resume impossible!\n", idx);
243 }
244 
245 static void free_ioapic_saved_registers(int idx)
246 {
247 	kfree(ioapics[idx].saved_registers);
248 	ioapics[idx].saved_registers = NULL;
249 }
250 
251 int __init arch_early_ioapic_init(void)
252 {
253 	int i;
254 
255 	if (!nr_legacy_irqs())
256 		io_apic_irqs = ~0UL;
257 
258 	for_each_ioapic(i)
259 		alloc_ioapic_saved_registers(i);
260 
261 	return 0;
262 }
263 
264 struct io_apic {
265 	unsigned int index;
266 	unsigned int unused[3];
267 	unsigned int data;
268 	unsigned int unused2[11];
269 	unsigned int eoi;
270 };
271 
272 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
273 {
274 	return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
275 		+ (mpc_ioapic_addr(idx) & ~PAGE_MASK);
276 }
277 
278 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
279 {
280 	struct io_apic __iomem *io_apic = io_apic_base(apic);
281 	writel(vector, &io_apic->eoi);
282 }
283 
284 unsigned int native_io_apic_read(unsigned int apic, unsigned int reg)
285 {
286 	struct io_apic __iomem *io_apic = io_apic_base(apic);
287 	writel(reg, &io_apic->index);
288 	return readl(&io_apic->data);
289 }
290 
291 static void io_apic_write(unsigned int apic, unsigned int reg,
292 			  unsigned int value)
293 {
294 	struct io_apic __iomem *io_apic = io_apic_base(apic);
295 
296 	writel(reg, &io_apic->index);
297 	writel(value, &io_apic->data);
298 }
299 
300 union entry_union {
301 	struct { u32 w1, w2; };
302 	struct IO_APIC_route_entry entry;
303 };
304 
305 static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
306 {
307 	union entry_union eu;
308 
309 	eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
310 	eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
311 
312 	return eu.entry;
313 }
314 
315 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
316 {
317 	union entry_union eu;
318 	unsigned long flags;
319 
320 	raw_spin_lock_irqsave(&ioapic_lock, flags);
321 	eu.entry = __ioapic_read_entry(apic, pin);
322 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
323 
324 	return eu.entry;
325 }
326 
327 /*
328  * When we write a new IO APIC routing entry, we need to write the high
329  * word first! If the mask bit in the low word is clear, we will enable
330  * the interrupt, and we need to make sure the entry is fully populated
331  * before that happens.
332  */
333 static void __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
334 {
335 	union entry_union eu = {{0, 0}};
336 
337 	eu.entry = e;
338 	io_apic_write(apic, 0x11 + 2*pin, eu.w2);
339 	io_apic_write(apic, 0x10 + 2*pin, eu.w1);
340 }
341 
342 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
343 {
344 	unsigned long flags;
345 
346 	raw_spin_lock_irqsave(&ioapic_lock, flags);
347 	__ioapic_write_entry(apic, pin, e);
348 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
349 }
350 
351 /*
352  * When we mask an IO APIC routing entry, we need to write the low
353  * word first, in order to set the mask bit before we change the
354  * high bits!
355  */
356 static void ioapic_mask_entry(int apic, int pin)
357 {
358 	unsigned long flags;
359 	union entry_union eu = { .entry.mask = IOAPIC_MASKED };
360 
361 	raw_spin_lock_irqsave(&ioapic_lock, flags);
362 	io_apic_write(apic, 0x10 + 2*pin, eu.w1);
363 	io_apic_write(apic, 0x11 + 2*pin, eu.w2);
364 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
365 }
366 
367 /*
368  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
369  * shared ISA-space IRQs, so we have to support them. We are super
370  * fast in the common case, and fast for shared ISA-space IRQs.
371  */
372 static int __add_pin_to_irq_node(struct mp_chip_data *data,
373 				 int node, int apic, int pin)
374 {
375 	struct irq_pin_list *entry;
376 
377 	/* don't allow duplicates */
378 	for_each_irq_pin(entry, data->irq_2_pin)
379 		if (entry->apic == apic && entry->pin == pin)
380 			return 0;
381 
382 	entry = kzalloc_node(sizeof(struct irq_pin_list), GFP_ATOMIC, node);
383 	if (!entry) {
384 		pr_err("can not alloc irq_pin_list (%d,%d,%d)\n",
385 		       node, apic, pin);
386 		return -ENOMEM;
387 	}
388 	entry->apic = apic;
389 	entry->pin = pin;
390 	list_add_tail(&entry->list, &data->irq_2_pin);
391 
392 	return 0;
393 }
394 
395 static void __remove_pin_from_irq(struct mp_chip_data *data, int apic, int pin)
396 {
397 	struct irq_pin_list *tmp, *entry;
398 
399 	list_for_each_entry_safe(entry, tmp, &data->irq_2_pin, list)
400 		if (entry->apic == apic && entry->pin == pin) {
401 			list_del(&entry->list);
402 			kfree(entry);
403 			return;
404 		}
405 }
406 
407 static void add_pin_to_irq_node(struct mp_chip_data *data,
408 				int node, int apic, int pin)
409 {
410 	if (__add_pin_to_irq_node(data, node, apic, pin))
411 		panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
412 }
413 
414 /*
415  * Reroute an IRQ to a different pin.
416  */
417 static void __init replace_pin_at_irq_node(struct mp_chip_data *data, int node,
418 					   int oldapic, int oldpin,
419 					   int newapic, int newpin)
420 {
421 	struct irq_pin_list *entry;
422 
423 	for_each_irq_pin(entry, data->irq_2_pin) {
424 		if (entry->apic == oldapic && entry->pin == oldpin) {
425 			entry->apic = newapic;
426 			entry->pin = newpin;
427 			/* every one is different, right? */
428 			return;
429 		}
430 	}
431 
432 	/* old apic/pin didn't exist, so just add new ones */
433 	add_pin_to_irq_node(data, node, newapic, newpin);
434 }
435 
436 static void io_apic_modify_irq(struct mp_chip_data *data,
437 			       int mask_and, int mask_or,
438 			       void (*final)(struct irq_pin_list *entry))
439 {
440 	union entry_union eu;
441 	struct irq_pin_list *entry;
442 
443 	eu.entry = data->entry;
444 	eu.w1 &= mask_and;
445 	eu.w1 |= mask_or;
446 	data->entry = eu.entry;
447 
448 	for_each_irq_pin(entry, data->irq_2_pin) {
449 		io_apic_write(entry->apic, 0x10 + 2 * entry->pin, eu.w1);
450 		if (final)
451 			final(entry);
452 	}
453 }
454 
455 static void io_apic_sync(struct irq_pin_list *entry)
456 {
457 	/*
458 	 * Synchronize the IO-APIC and the CPU by doing
459 	 * a dummy read from the IO-APIC
460 	 */
461 	struct io_apic __iomem *io_apic;
462 
463 	io_apic = io_apic_base(entry->apic);
464 	readl(&io_apic->data);
465 }
466 
467 static void mask_ioapic_irq(struct irq_data *irq_data)
468 {
469 	struct mp_chip_data *data = irq_data->chip_data;
470 	unsigned long flags;
471 
472 	raw_spin_lock_irqsave(&ioapic_lock, flags);
473 	io_apic_modify_irq(data, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
474 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
475 }
476 
477 static void __unmask_ioapic(struct mp_chip_data *data)
478 {
479 	io_apic_modify_irq(data, ~IO_APIC_REDIR_MASKED, 0, NULL);
480 }
481 
482 static void unmask_ioapic_irq(struct irq_data *irq_data)
483 {
484 	struct mp_chip_data *data = irq_data->chip_data;
485 	unsigned long flags;
486 
487 	raw_spin_lock_irqsave(&ioapic_lock, flags);
488 	__unmask_ioapic(data);
489 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
490 }
491 
492 /*
493  * IO-APIC versions below 0x20 don't support EOI register.
494  * For the record, here is the information about various versions:
495  *     0Xh     82489DX
496  *     1Xh     I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
497  *     2Xh     I/O(x)APIC which is PCI 2.2 Compliant
498  *     30h-FFh Reserved
499  *
500  * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
501  * version as 0x2. This is an error with documentation and these ICH chips
502  * use io-apic's of version 0x20.
503  *
504  * For IO-APIC's with EOI register, we use that to do an explicit EOI.
505  * Otherwise, we simulate the EOI message manually by changing the trigger
506  * mode to edge and then back to level, with RTE being masked during this.
507  */
508 static void __eoi_ioapic_pin(int apic, int pin, int vector)
509 {
510 	if (mpc_ioapic_ver(apic) >= 0x20) {
511 		io_apic_eoi(apic, vector);
512 	} else {
513 		struct IO_APIC_route_entry entry, entry1;
514 
515 		entry = entry1 = __ioapic_read_entry(apic, pin);
516 
517 		/*
518 		 * Mask the entry and change the trigger mode to edge.
519 		 */
520 		entry1.mask = IOAPIC_MASKED;
521 		entry1.trigger = IOAPIC_EDGE;
522 
523 		__ioapic_write_entry(apic, pin, entry1);
524 
525 		/*
526 		 * Restore the previous level triggered entry.
527 		 */
528 		__ioapic_write_entry(apic, pin, entry);
529 	}
530 }
531 
532 static void eoi_ioapic_pin(int vector, struct mp_chip_data *data)
533 {
534 	unsigned long flags;
535 	struct irq_pin_list *entry;
536 
537 	raw_spin_lock_irqsave(&ioapic_lock, flags);
538 	for_each_irq_pin(entry, data->irq_2_pin)
539 		__eoi_ioapic_pin(entry->apic, entry->pin, vector);
540 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
541 }
542 
543 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
544 {
545 	struct IO_APIC_route_entry entry;
546 
547 	/* Check delivery_mode to be sure we're not clearing an SMI pin */
548 	entry = ioapic_read_entry(apic, pin);
549 	if (entry.delivery_mode == dest_SMI)
550 		return;
551 
552 	/*
553 	 * Make sure the entry is masked and re-read the contents to check
554 	 * if it is a level triggered pin and if the remote-IRR is set.
555 	 */
556 	if (entry.mask == IOAPIC_UNMASKED) {
557 		entry.mask = IOAPIC_MASKED;
558 		ioapic_write_entry(apic, pin, entry);
559 		entry = ioapic_read_entry(apic, pin);
560 	}
561 
562 	if (entry.irr) {
563 		unsigned long flags;
564 
565 		/*
566 		 * Make sure the trigger mode is set to level. Explicit EOI
567 		 * doesn't clear the remote-IRR if the trigger mode is not
568 		 * set to level.
569 		 */
570 		if (entry.trigger == IOAPIC_EDGE) {
571 			entry.trigger = IOAPIC_LEVEL;
572 			ioapic_write_entry(apic, pin, entry);
573 		}
574 		raw_spin_lock_irqsave(&ioapic_lock, flags);
575 		__eoi_ioapic_pin(apic, pin, entry.vector);
576 		raw_spin_unlock_irqrestore(&ioapic_lock, flags);
577 	}
578 
579 	/*
580 	 * Clear the rest of the bits in the IO-APIC RTE except for the mask
581 	 * bit.
582 	 */
583 	ioapic_mask_entry(apic, pin);
584 	entry = ioapic_read_entry(apic, pin);
585 	if (entry.irr)
586 		pr_err("Unable to reset IRR for apic: %d, pin :%d\n",
587 		       mpc_ioapic_id(apic), pin);
588 }
589 
590 static void clear_IO_APIC (void)
591 {
592 	int apic, pin;
593 
594 	for_each_ioapic_pin(apic, pin)
595 		clear_IO_APIC_pin(apic, pin);
596 }
597 
598 #ifdef CONFIG_X86_32
599 /*
600  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
601  * specific CPU-side IRQs.
602  */
603 
604 #define MAX_PIRQS 8
605 static int pirq_entries[MAX_PIRQS] = {
606 	[0 ... MAX_PIRQS - 1] = -1
607 };
608 
609 static int __init ioapic_pirq_setup(char *str)
610 {
611 	int i, max;
612 	int ints[MAX_PIRQS+1];
613 
614 	get_options(str, ARRAY_SIZE(ints), ints);
615 
616 	apic_printk(APIC_VERBOSE, KERN_INFO
617 			"PIRQ redirection, working around broken MP-BIOS.\n");
618 	max = MAX_PIRQS;
619 	if (ints[0] < MAX_PIRQS)
620 		max = ints[0];
621 
622 	for (i = 0; i < max; i++) {
623 		apic_printk(APIC_VERBOSE, KERN_DEBUG
624 				"... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
625 		/*
626 		 * PIRQs are mapped upside down, usually.
627 		 */
628 		pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
629 	}
630 	return 1;
631 }
632 
633 __setup("pirq=", ioapic_pirq_setup);
634 #endif /* CONFIG_X86_32 */
635 
636 /*
637  * Saves all the IO-APIC RTE's
638  */
639 int save_ioapic_entries(void)
640 {
641 	int apic, pin;
642 	int err = 0;
643 
644 	for_each_ioapic(apic) {
645 		if (!ioapics[apic].saved_registers) {
646 			err = -ENOMEM;
647 			continue;
648 		}
649 
650 		for_each_pin(apic, pin)
651 			ioapics[apic].saved_registers[pin] =
652 				ioapic_read_entry(apic, pin);
653 	}
654 
655 	return err;
656 }
657 
658 /*
659  * Mask all IO APIC entries.
660  */
661 void mask_ioapic_entries(void)
662 {
663 	int apic, pin;
664 
665 	for_each_ioapic(apic) {
666 		if (!ioapics[apic].saved_registers)
667 			continue;
668 
669 		for_each_pin(apic, pin) {
670 			struct IO_APIC_route_entry entry;
671 
672 			entry = ioapics[apic].saved_registers[pin];
673 			if (entry.mask == IOAPIC_UNMASKED) {
674 				entry.mask = IOAPIC_MASKED;
675 				ioapic_write_entry(apic, pin, entry);
676 			}
677 		}
678 	}
679 }
680 
681 /*
682  * Restore IO APIC entries which was saved in the ioapic structure.
683  */
684 int restore_ioapic_entries(void)
685 {
686 	int apic, pin;
687 
688 	for_each_ioapic(apic) {
689 		if (!ioapics[apic].saved_registers)
690 			continue;
691 
692 		for_each_pin(apic, pin)
693 			ioapic_write_entry(apic, pin,
694 					   ioapics[apic].saved_registers[pin]);
695 	}
696 	return 0;
697 }
698 
699 /*
700  * Find the IRQ entry number of a certain pin.
701  */
702 static int find_irq_entry(int ioapic_idx, int pin, int type)
703 {
704 	int i;
705 
706 	for (i = 0; i < mp_irq_entries; i++)
707 		if (mp_irqs[i].irqtype == type &&
708 		    (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
709 		     mp_irqs[i].dstapic == MP_APIC_ALL) &&
710 		    mp_irqs[i].dstirq == pin)
711 			return i;
712 
713 	return -1;
714 }
715 
716 /*
717  * Find the pin to which IRQ[irq] (ISA) is connected
718  */
719 static int __init find_isa_irq_pin(int irq, int type)
720 {
721 	int i;
722 
723 	for (i = 0; i < mp_irq_entries; i++) {
724 		int lbus = mp_irqs[i].srcbus;
725 
726 		if (test_bit(lbus, mp_bus_not_pci) &&
727 		    (mp_irqs[i].irqtype == type) &&
728 		    (mp_irqs[i].srcbusirq == irq))
729 
730 			return mp_irqs[i].dstirq;
731 	}
732 	return -1;
733 }
734 
735 static int __init find_isa_irq_apic(int irq, int type)
736 {
737 	int i;
738 
739 	for (i = 0; i < mp_irq_entries; i++) {
740 		int lbus = mp_irqs[i].srcbus;
741 
742 		if (test_bit(lbus, mp_bus_not_pci) &&
743 		    (mp_irqs[i].irqtype == type) &&
744 		    (mp_irqs[i].srcbusirq == irq))
745 			break;
746 	}
747 
748 	if (i < mp_irq_entries) {
749 		int ioapic_idx;
750 
751 		for_each_ioapic(ioapic_idx)
752 			if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
753 				return ioapic_idx;
754 	}
755 
756 	return -1;
757 }
758 
759 #ifdef CONFIG_EISA
760 /*
761  * EISA Edge/Level control register, ELCR
762  */
763 static int EISA_ELCR(unsigned int irq)
764 {
765 	if (irq < nr_legacy_irqs()) {
766 		unsigned int port = 0x4d0 + (irq >> 3);
767 		return (inb(port) >> (irq & 7)) & 1;
768 	}
769 	apic_printk(APIC_VERBOSE, KERN_INFO
770 			"Broken MPtable reports ISA irq %d\n", irq);
771 	return 0;
772 }
773 
774 #endif
775 
776 /* ISA interrupts are always active high edge triggered,
777  * when listed as conforming in the MP table. */
778 
779 #define default_ISA_trigger(idx)	(IOAPIC_EDGE)
780 #define default_ISA_polarity(idx)	(IOAPIC_POL_HIGH)
781 
782 /* EISA interrupts are always polarity zero and can be edge or level
783  * trigger depending on the ELCR value.  If an interrupt is listed as
784  * EISA conforming in the MP table, that means its trigger type must
785  * be read in from the ELCR */
786 
787 #define default_EISA_trigger(idx)	(EISA_ELCR(mp_irqs[idx].srcbusirq))
788 #define default_EISA_polarity(idx)	default_ISA_polarity(idx)
789 
790 /* PCI interrupts are always active low level triggered,
791  * when listed as conforming in the MP table. */
792 
793 #define default_PCI_trigger(idx)	(IOAPIC_LEVEL)
794 #define default_PCI_polarity(idx)	(IOAPIC_POL_LOW)
795 
796 static int irq_polarity(int idx)
797 {
798 	int bus = mp_irqs[idx].srcbus;
799 
800 	/*
801 	 * Determine IRQ line polarity (high active or low active):
802 	 */
803 	switch (mp_irqs[idx].irqflag & 0x03) {
804 	case 0:
805 		/* conforms to spec, ie. bus-type dependent polarity */
806 		if (test_bit(bus, mp_bus_not_pci))
807 			return default_ISA_polarity(idx);
808 		else
809 			return default_PCI_polarity(idx);
810 	case 1:
811 		return IOAPIC_POL_HIGH;
812 	case 2:
813 		pr_warn("IOAPIC: Invalid polarity: 2, defaulting to low\n");
814 	case 3:
815 	default: /* Pointless default required due to do gcc stupidity */
816 		return IOAPIC_POL_LOW;
817 	}
818 }
819 
820 #ifdef CONFIG_EISA
821 static int eisa_irq_trigger(int idx, int bus, int trigger)
822 {
823 	switch (mp_bus_id_to_type[bus]) {
824 	case MP_BUS_PCI:
825 	case MP_BUS_ISA:
826 		return trigger;
827 	case MP_BUS_EISA:
828 		return default_EISA_trigger(idx);
829 	}
830 	pr_warn("IOAPIC: Invalid srcbus: %d defaulting to level\n", bus);
831 	return IOAPIC_LEVEL;
832 }
833 #else
834 static inline int eisa_irq_trigger(int idx, int bus, int trigger)
835 {
836 	return trigger;
837 }
838 #endif
839 
840 static int irq_trigger(int idx)
841 {
842 	int bus = mp_irqs[idx].srcbus;
843 	int trigger;
844 
845 	/*
846 	 * Determine IRQ trigger mode (edge or level sensitive):
847 	 */
848 	switch ((mp_irqs[idx].irqflag >> 2) & 0x03) {
849 	case 0:
850 		/* conforms to spec, ie. bus-type dependent trigger mode */
851 		if (test_bit(bus, mp_bus_not_pci))
852 			trigger = default_ISA_trigger(idx);
853 		else
854 			trigger = default_PCI_trigger(idx);
855 		/* Take EISA into account */
856 		return eisa_irq_trigger(idx, bus, trigger);
857 	case 1:
858 		return IOAPIC_EDGE;
859 	case 2:
860 		pr_warn("IOAPIC: Invalid trigger mode 2 defaulting to level\n");
861 	case 3:
862 	default: /* Pointless default required due to do gcc stupidity */
863 		return IOAPIC_LEVEL;
864 	}
865 }
866 
867 void ioapic_set_alloc_attr(struct irq_alloc_info *info, int node,
868 			   int trigger, int polarity)
869 {
870 	init_irq_alloc_info(info, NULL);
871 	info->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
872 	info->ioapic_node = node;
873 	info->ioapic_trigger = trigger;
874 	info->ioapic_polarity = polarity;
875 	info->ioapic_valid = 1;
876 }
877 
878 #ifndef CONFIG_ACPI
879 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity);
880 #endif
881 
882 static void ioapic_copy_alloc_attr(struct irq_alloc_info *dst,
883 				   struct irq_alloc_info *src,
884 				   u32 gsi, int ioapic_idx, int pin)
885 {
886 	int trigger, polarity;
887 
888 	copy_irq_alloc_info(dst, src);
889 	dst->type = X86_IRQ_ALLOC_TYPE_IOAPIC;
890 	dst->ioapic_id = mpc_ioapic_id(ioapic_idx);
891 	dst->ioapic_pin = pin;
892 	dst->ioapic_valid = 1;
893 	if (src && src->ioapic_valid) {
894 		dst->ioapic_node = src->ioapic_node;
895 		dst->ioapic_trigger = src->ioapic_trigger;
896 		dst->ioapic_polarity = src->ioapic_polarity;
897 	} else {
898 		dst->ioapic_node = NUMA_NO_NODE;
899 		if (acpi_get_override_irq(gsi, &trigger, &polarity) >= 0) {
900 			dst->ioapic_trigger = trigger;
901 			dst->ioapic_polarity = polarity;
902 		} else {
903 			/*
904 			 * PCI interrupts are always active low level
905 			 * triggered.
906 			 */
907 			dst->ioapic_trigger = IOAPIC_LEVEL;
908 			dst->ioapic_polarity = IOAPIC_POL_LOW;
909 		}
910 	}
911 }
912 
913 static int ioapic_alloc_attr_node(struct irq_alloc_info *info)
914 {
915 	return (info && info->ioapic_valid) ? info->ioapic_node : NUMA_NO_NODE;
916 }
917 
918 static void mp_register_handler(unsigned int irq, unsigned long trigger)
919 {
920 	irq_flow_handler_t hdl;
921 	bool fasteoi;
922 
923 	if (trigger) {
924 		irq_set_status_flags(irq, IRQ_LEVEL);
925 		fasteoi = true;
926 	} else {
927 		irq_clear_status_flags(irq, IRQ_LEVEL);
928 		fasteoi = false;
929 	}
930 
931 	hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
932 	__irq_set_handler(irq, hdl, 0, fasteoi ? "fasteoi" : "edge");
933 }
934 
935 static bool mp_check_pin_attr(int irq, struct irq_alloc_info *info)
936 {
937 	struct mp_chip_data *data = irq_get_chip_data(irq);
938 
939 	/*
940 	 * setup_IO_APIC_irqs() programs all legacy IRQs with default trigger
941 	 * and polarity attirbutes. So allow the first user to reprogram the
942 	 * pin with real trigger and polarity attributes.
943 	 */
944 	if (irq < nr_legacy_irqs() && data->count == 1) {
945 		if (info->ioapic_trigger != data->trigger)
946 			mp_register_handler(irq, info->ioapic_trigger);
947 		data->entry.trigger = data->trigger = info->ioapic_trigger;
948 		data->entry.polarity = data->polarity = info->ioapic_polarity;
949 	}
950 
951 	return data->trigger == info->ioapic_trigger &&
952 	       data->polarity == info->ioapic_polarity;
953 }
954 
955 static int alloc_irq_from_domain(struct irq_domain *domain, int ioapic, u32 gsi,
956 				 struct irq_alloc_info *info)
957 {
958 	bool legacy = false;
959 	int irq = -1;
960 	int type = ioapics[ioapic].irqdomain_cfg.type;
961 
962 	switch (type) {
963 	case IOAPIC_DOMAIN_LEGACY:
964 		/*
965 		 * Dynamically allocate IRQ number for non-ISA IRQs in the first
966 		 * 16 GSIs on some weird platforms.
967 		 */
968 		if (!ioapic_initialized || gsi >= nr_legacy_irqs())
969 			irq = gsi;
970 		legacy = mp_is_legacy_irq(irq);
971 		break;
972 	case IOAPIC_DOMAIN_STRICT:
973 		irq = gsi;
974 		break;
975 	case IOAPIC_DOMAIN_DYNAMIC:
976 		break;
977 	default:
978 		WARN(1, "ioapic: unknown irqdomain type %d\n", type);
979 		return -1;
980 	}
981 
982 	return __irq_domain_alloc_irqs(domain, irq, 1,
983 				       ioapic_alloc_attr_node(info),
984 				       info, legacy);
985 }
986 
987 /*
988  * Need special handling for ISA IRQs because there may be multiple IOAPIC pins
989  * sharing the same ISA IRQ number and irqdomain only supports 1:1 mapping
990  * between IOAPIC pin and IRQ number. A typical IOAPIC has 24 pins, pin 0-15 are
991  * used for legacy IRQs and pin 16-23 are used for PCI IRQs (PIRQ A-H).
992  * When ACPI is disabled, only legacy IRQ numbers (IRQ0-15) are available, and
993  * some BIOSes may use MP Interrupt Source records to override IRQ numbers for
994  * PIRQs instead of reprogramming the interrupt routing logic. Thus there may be
995  * multiple pins sharing the same legacy IRQ number when ACPI is disabled.
996  */
997 static int alloc_isa_irq_from_domain(struct irq_domain *domain,
998 				     int irq, int ioapic, int pin,
999 				     struct irq_alloc_info *info)
1000 {
1001 	struct mp_chip_data *data;
1002 	struct irq_data *irq_data = irq_get_irq_data(irq);
1003 	int node = ioapic_alloc_attr_node(info);
1004 
1005 	/*
1006 	 * Legacy ISA IRQ has already been allocated, just add pin to
1007 	 * the pin list assoicated with this IRQ and program the IOAPIC
1008 	 * entry. The IOAPIC entry
1009 	 */
1010 	if (irq_data && irq_data->parent_data) {
1011 		if (!mp_check_pin_attr(irq, info))
1012 			return -EBUSY;
1013 		if (__add_pin_to_irq_node(irq_data->chip_data, node, ioapic,
1014 					  info->ioapic_pin))
1015 			return -ENOMEM;
1016 	} else {
1017 		irq = __irq_domain_alloc_irqs(domain, irq, 1, node, info, true);
1018 		if (irq >= 0) {
1019 			irq_data = irq_domain_get_irq_data(domain, irq);
1020 			data = irq_data->chip_data;
1021 			data->isa_irq = true;
1022 		}
1023 	}
1024 
1025 	return irq;
1026 }
1027 
1028 static int mp_map_pin_to_irq(u32 gsi, int idx, int ioapic, int pin,
1029 			     unsigned int flags, struct irq_alloc_info *info)
1030 {
1031 	int irq;
1032 	bool legacy = false;
1033 	struct irq_alloc_info tmp;
1034 	struct mp_chip_data *data;
1035 	struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
1036 
1037 	if (!domain)
1038 		return -ENOSYS;
1039 
1040 	if (idx >= 0 && test_bit(mp_irqs[idx].srcbus, mp_bus_not_pci)) {
1041 		irq = mp_irqs[idx].srcbusirq;
1042 		legacy = mp_is_legacy_irq(irq);
1043 	}
1044 
1045 	mutex_lock(&ioapic_mutex);
1046 	if (!(flags & IOAPIC_MAP_ALLOC)) {
1047 		if (!legacy) {
1048 			irq = irq_find_mapping(domain, pin);
1049 			if (irq == 0)
1050 				irq = -ENOENT;
1051 		}
1052 	} else {
1053 		ioapic_copy_alloc_attr(&tmp, info, gsi, ioapic, pin);
1054 		if (legacy)
1055 			irq = alloc_isa_irq_from_domain(domain, irq,
1056 							ioapic, pin, &tmp);
1057 		else if ((irq = irq_find_mapping(domain, pin)) == 0)
1058 			irq = alloc_irq_from_domain(domain, ioapic, gsi, &tmp);
1059 		else if (!mp_check_pin_attr(irq, &tmp))
1060 			irq = -EBUSY;
1061 		if (irq >= 0) {
1062 			data = irq_get_chip_data(irq);
1063 			data->count++;
1064 		}
1065 	}
1066 	mutex_unlock(&ioapic_mutex);
1067 
1068 	return irq;
1069 }
1070 
1071 static int pin_2_irq(int idx, int ioapic, int pin, unsigned int flags)
1072 {
1073 	u32 gsi = mp_pin_to_gsi(ioapic, pin);
1074 
1075 	/*
1076 	 * Debugging check, we are in big trouble if this message pops up!
1077 	 */
1078 	if (mp_irqs[idx].dstirq != pin)
1079 		pr_err("broken BIOS or MPTABLE parser, ayiee!!\n");
1080 
1081 #ifdef CONFIG_X86_32
1082 	/*
1083 	 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1084 	 */
1085 	if ((pin >= 16) && (pin <= 23)) {
1086 		if (pirq_entries[pin-16] != -1) {
1087 			if (!pirq_entries[pin-16]) {
1088 				apic_printk(APIC_VERBOSE, KERN_DEBUG
1089 						"disabling PIRQ%d\n", pin-16);
1090 			} else {
1091 				int irq = pirq_entries[pin-16];
1092 				apic_printk(APIC_VERBOSE, KERN_DEBUG
1093 						"using PIRQ%d -> IRQ %d\n",
1094 						pin-16, irq);
1095 				return irq;
1096 			}
1097 		}
1098 	}
1099 #endif
1100 
1101 	return  mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, NULL);
1102 }
1103 
1104 int mp_map_gsi_to_irq(u32 gsi, unsigned int flags, struct irq_alloc_info *info)
1105 {
1106 	int ioapic, pin, idx;
1107 
1108 	ioapic = mp_find_ioapic(gsi);
1109 	if (ioapic < 0)
1110 		return -1;
1111 
1112 	pin = mp_find_ioapic_pin(ioapic, gsi);
1113 	idx = find_irq_entry(ioapic, pin, mp_INT);
1114 	if ((flags & IOAPIC_MAP_CHECK) && idx < 0)
1115 		return -1;
1116 
1117 	return mp_map_pin_to_irq(gsi, idx, ioapic, pin, flags, info);
1118 }
1119 
1120 void mp_unmap_irq(int irq)
1121 {
1122 	struct irq_data *irq_data = irq_get_irq_data(irq);
1123 	struct mp_chip_data *data;
1124 
1125 	if (!irq_data || !irq_data->domain)
1126 		return;
1127 
1128 	data = irq_data->chip_data;
1129 	if (!data || data->isa_irq)
1130 		return;
1131 
1132 	mutex_lock(&ioapic_mutex);
1133 	if (--data->count == 0)
1134 		irq_domain_free_irqs(irq, 1);
1135 	mutex_unlock(&ioapic_mutex);
1136 }
1137 
1138 /*
1139  * Find a specific PCI IRQ entry.
1140  * Not an __init, possibly needed by modules
1141  */
1142 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1143 {
1144 	int irq, i, best_ioapic = -1, best_idx = -1;
1145 
1146 	apic_printk(APIC_DEBUG,
1147 		    "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1148 		    bus, slot, pin);
1149 	if (test_bit(bus, mp_bus_not_pci)) {
1150 		apic_printk(APIC_VERBOSE,
1151 			    "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1152 		return -1;
1153 	}
1154 
1155 	for (i = 0; i < mp_irq_entries; i++) {
1156 		int lbus = mp_irqs[i].srcbus;
1157 		int ioapic_idx, found = 0;
1158 
1159 		if (bus != lbus || mp_irqs[i].irqtype != mp_INT ||
1160 		    slot != ((mp_irqs[i].srcbusirq >> 2) & 0x1f))
1161 			continue;
1162 
1163 		for_each_ioapic(ioapic_idx)
1164 			if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1165 			    mp_irqs[i].dstapic == MP_APIC_ALL) {
1166 				found = 1;
1167 				break;
1168 			}
1169 		if (!found)
1170 			continue;
1171 
1172 		/* Skip ISA IRQs */
1173 		irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq, 0);
1174 		if (irq > 0 && !IO_APIC_IRQ(irq))
1175 			continue;
1176 
1177 		if (pin == (mp_irqs[i].srcbusirq & 3)) {
1178 			best_idx = i;
1179 			best_ioapic = ioapic_idx;
1180 			goto out;
1181 		}
1182 
1183 		/*
1184 		 * Use the first all-but-pin matching entry as a
1185 		 * best-guess fuzzy result for broken mptables.
1186 		 */
1187 		if (best_idx < 0) {
1188 			best_idx = i;
1189 			best_ioapic = ioapic_idx;
1190 		}
1191 	}
1192 	if (best_idx < 0)
1193 		return -1;
1194 
1195 out:
1196 	return pin_2_irq(best_idx, best_ioapic, mp_irqs[best_idx].dstirq,
1197 			 IOAPIC_MAP_ALLOC);
1198 }
1199 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1200 
1201 static struct irq_chip ioapic_chip, ioapic_ir_chip;
1202 
1203 #ifdef CONFIG_X86_32
1204 static inline int IO_APIC_irq_trigger(int irq)
1205 {
1206 	int apic, idx, pin;
1207 
1208 	for_each_ioapic_pin(apic, pin) {
1209 		idx = find_irq_entry(apic, pin, mp_INT);
1210 		if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin, 0)))
1211 			return irq_trigger(idx);
1212 	}
1213 	/*
1214          * nonexistent IRQs are edge default
1215          */
1216 	return 0;
1217 }
1218 #else
1219 static inline int IO_APIC_irq_trigger(int irq)
1220 {
1221 	return 1;
1222 }
1223 #endif
1224 
1225 static void __init setup_IO_APIC_irqs(void)
1226 {
1227 	unsigned int ioapic, pin;
1228 	int idx;
1229 
1230 	apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1231 
1232 	for_each_ioapic_pin(ioapic, pin) {
1233 		idx = find_irq_entry(ioapic, pin, mp_INT);
1234 		if (idx < 0)
1235 			apic_printk(APIC_VERBOSE,
1236 				    KERN_DEBUG " apic %d pin %d not connected\n",
1237 				    mpc_ioapic_id(ioapic), pin);
1238 		else
1239 			pin_2_irq(idx, ioapic, pin,
1240 				  ioapic ? 0 : IOAPIC_MAP_ALLOC);
1241 	}
1242 }
1243 
1244 void ioapic_zap_locks(void)
1245 {
1246 	raw_spin_lock_init(&ioapic_lock);
1247 }
1248 
1249 static void io_apic_print_entries(unsigned int apic, unsigned int nr_entries)
1250 {
1251 	int i;
1252 	char buf[256];
1253 	struct IO_APIC_route_entry entry;
1254 	struct IR_IO_APIC_route_entry *ir_entry = (void *)&entry;
1255 
1256 	printk(KERN_DEBUG "IOAPIC %d:\n", apic);
1257 	for (i = 0; i <= nr_entries; i++) {
1258 		entry = ioapic_read_entry(apic, i);
1259 		snprintf(buf, sizeof(buf),
1260 			 " pin%02x, %s, %s, %s, V(%02X), IRR(%1d), S(%1d)",
1261 			 i,
1262 			 entry.mask == IOAPIC_MASKED ? "disabled" : "enabled ",
1263 			 entry.trigger == IOAPIC_LEVEL ? "level" : "edge ",
1264 			 entry.polarity == IOAPIC_POL_LOW ? "low " : "high",
1265 			 entry.vector, entry.irr, entry.delivery_status);
1266 		if (ir_entry->format)
1267 			printk(KERN_DEBUG "%s, remapped, I(%04X),  Z(%X)\n",
1268 			       buf, (ir_entry->index << 15) | ir_entry->index,
1269 			       ir_entry->zero);
1270 		else
1271 			printk(KERN_DEBUG "%s, %s, D(%02X), M(%1d)\n",
1272 			       buf,
1273 			       entry.dest_mode == IOAPIC_DEST_MODE_LOGICAL ?
1274 			       "logical " : "physical",
1275 			       entry.dest, entry.delivery_mode);
1276 	}
1277 }
1278 
1279 static void __init print_IO_APIC(int ioapic_idx)
1280 {
1281 	union IO_APIC_reg_00 reg_00;
1282 	union IO_APIC_reg_01 reg_01;
1283 	union IO_APIC_reg_02 reg_02;
1284 	union IO_APIC_reg_03 reg_03;
1285 	unsigned long flags;
1286 
1287 	raw_spin_lock_irqsave(&ioapic_lock, flags);
1288 	reg_00.raw = io_apic_read(ioapic_idx, 0);
1289 	reg_01.raw = io_apic_read(ioapic_idx, 1);
1290 	if (reg_01.bits.version >= 0x10)
1291 		reg_02.raw = io_apic_read(ioapic_idx, 2);
1292 	if (reg_01.bits.version >= 0x20)
1293 		reg_03.raw = io_apic_read(ioapic_idx, 3);
1294 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1295 
1296 	printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
1297 	printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1298 	printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1299 	printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1300 	printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1301 
1302 	printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1303 	printk(KERN_DEBUG ".......     : max redirection entries: %02X\n",
1304 		reg_01.bits.entries);
1305 
1306 	printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1307 	printk(KERN_DEBUG ".......     : IO APIC version: %02X\n",
1308 		reg_01.bits.version);
1309 
1310 	/*
1311 	 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1312 	 * but the value of reg_02 is read as the previous read register
1313 	 * value, so ignore it if reg_02 == reg_01.
1314 	 */
1315 	if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1316 		printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1317 		printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1318 	}
1319 
1320 	/*
1321 	 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1322 	 * or reg_03, but the value of reg_0[23] is read as the previous read
1323 	 * register value, so ignore it if reg_03 == reg_0[12].
1324 	 */
1325 	if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1326 	    reg_03.raw != reg_01.raw) {
1327 		printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1328 		printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1329 	}
1330 
1331 	printk(KERN_DEBUG ".... IRQ redirection table:\n");
1332 	io_apic_print_entries(ioapic_idx, reg_01.bits.entries);
1333 }
1334 
1335 void __init print_IO_APICs(void)
1336 {
1337 	int ioapic_idx;
1338 	unsigned int irq;
1339 
1340 	printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1341 	for_each_ioapic(ioapic_idx)
1342 		printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1343 		       mpc_ioapic_id(ioapic_idx),
1344 		       ioapics[ioapic_idx].nr_registers);
1345 
1346 	/*
1347 	 * We are a bit conservative about what we expect.  We have to
1348 	 * know about every hardware change ASAP.
1349 	 */
1350 	printk(KERN_INFO "testing the IO APIC.......................\n");
1351 
1352 	for_each_ioapic(ioapic_idx)
1353 		print_IO_APIC(ioapic_idx);
1354 
1355 	printk(KERN_DEBUG "IRQ to pin mappings:\n");
1356 	for_each_active_irq(irq) {
1357 		struct irq_pin_list *entry;
1358 		struct irq_chip *chip;
1359 		struct mp_chip_data *data;
1360 
1361 		chip = irq_get_chip(irq);
1362 		if (chip != &ioapic_chip && chip != &ioapic_ir_chip)
1363 			continue;
1364 		data = irq_get_chip_data(irq);
1365 		if (!data)
1366 			continue;
1367 		if (list_empty(&data->irq_2_pin))
1368 			continue;
1369 
1370 		printk(KERN_DEBUG "IRQ%d ", irq);
1371 		for_each_irq_pin(entry, data->irq_2_pin)
1372 			pr_cont("-> %d:%d", entry->apic, entry->pin);
1373 		pr_cont("\n");
1374 	}
1375 
1376 	printk(KERN_INFO ".................................... done.\n");
1377 }
1378 
1379 /* Where if anywhere is the i8259 connect in external int mode */
1380 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1381 
1382 void __init enable_IO_APIC(void)
1383 {
1384 	int i8259_apic, i8259_pin;
1385 	int apic, pin;
1386 
1387 	if (skip_ioapic_setup)
1388 		nr_ioapics = 0;
1389 
1390 	if (!nr_legacy_irqs() || !nr_ioapics)
1391 		return;
1392 
1393 	for_each_ioapic_pin(apic, pin) {
1394 		/* See if any of the pins is in ExtINT mode */
1395 		struct IO_APIC_route_entry entry = ioapic_read_entry(apic, pin);
1396 
1397 		/* If the interrupt line is enabled and in ExtInt mode
1398 		 * I have found the pin where the i8259 is connected.
1399 		 */
1400 		if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1401 			ioapic_i8259.apic = apic;
1402 			ioapic_i8259.pin  = pin;
1403 			goto found_i8259;
1404 		}
1405 	}
1406  found_i8259:
1407 	/* Look to see what if the MP table has reported the ExtINT */
1408 	/* If we could not find the appropriate pin by looking at the ioapic
1409 	 * the i8259 probably is not connected the ioapic but give the
1410 	 * mptable a chance anyway.
1411 	 */
1412 	i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
1413 	i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1414 	/* Trust the MP table if nothing is setup in the hardware */
1415 	if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1416 		printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1417 		ioapic_i8259.pin  = i8259_pin;
1418 		ioapic_i8259.apic = i8259_apic;
1419 	}
1420 	/* Complain if the MP table and the hardware disagree */
1421 	if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1422 		(i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1423 	{
1424 		printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1425 	}
1426 
1427 	/*
1428 	 * Do not trust the IO-APIC being empty at bootup
1429 	 */
1430 	clear_IO_APIC();
1431 }
1432 
1433 void native_disable_io_apic(void)
1434 {
1435 	/*
1436 	 * If the i8259 is routed through an IOAPIC
1437 	 * Put that IOAPIC in virtual wire mode
1438 	 * so legacy interrupts can be delivered.
1439 	 */
1440 	if (ioapic_i8259.pin != -1) {
1441 		struct IO_APIC_route_entry entry;
1442 
1443 		memset(&entry, 0, sizeof(entry));
1444 		entry.mask		= IOAPIC_UNMASKED;
1445 		entry.trigger		= IOAPIC_EDGE;
1446 		entry.polarity		= IOAPIC_POL_HIGH;
1447 		entry.dest_mode		= IOAPIC_DEST_MODE_PHYSICAL;
1448 		entry.delivery_mode	= dest_ExtINT;
1449 		entry.dest		= read_apic_id();
1450 
1451 		/*
1452 		 * Add it to the IO-APIC irq-routing table:
1453 		 */
1454 		ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1455 	}
1456 
1457 	if (boot_cpu_has(X86_FEATURE_APIC) || apic_from_smp_config())
1458 		disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1459 }
1460 
1461 /*
1462  * Not an __init, needed by the reboot code
1463  */
1464 void disable_IO_APIC(void)
1465 {
1466 	/*
1467 	 * Clear the IO-APIC before rebooting:
1468 	 */
1469 	clear_IO_APIC();
1470 
1471 	if (!nr_legacy_irqs())
1472 		return;
1473 
1474 	x86_io_apic_ops.disable();
1475 }
1476 
1477 #ifdef CONFIG_X86_32
1478 /*
1479  * function to set the IO-APIC physical IDs based on the
1480  * values stored in the MPC table.
1481  *
1482  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1483  */
1484 void __init setup_ioapic_ids_from_mpc_nocheck(void)
1485 {
1486 	union IO_APIC_reg_00 reg_00;
1487 	physid_mask_t phys_id_present_map;
1488 	int ioapic_idx;
1489 	int i;
1490 	unsigned char old_id;
1491 	unsigned long flags;
1492 
1493 	/*
1494 	 * This is broken; anything with a real cpu count has to
1495 	 * circumvent this idiocy regardless.
1496 	 */
1497 	apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
1498 
1499 	/*
1500 	 * Set the IOAPIC ID to the value stored in the MPC table.
1501 	 */
1502 	for_each_ioapic(ioapic_idx) {
1503 		/* Read the register 0 value */
1504 		raw_spin_lock_irqsave(&ioapic_lock, flags);
1505 		reg_00.raw = io_apic_read(ioapic_idx, 0);
1506 		raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1507 
1508 		old_id = mpc_ioapic_id(ioapic_idx);
1509 
1510 		if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) {
1511 			printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1512 				ioapic_idx, mpc_ioapic_id(ioapic_idx));
1513 			printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1514 				reg_00.bits.ID);
1515 			ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
1516 		}
1517 
1518 		/*
1519 		 * Sanity check, is the ID really free? Every APIC in a
1520 		 * system must have a unique ID or we get lots of nice
1521 		 * 'stuck on smp_invalidate_needed IPI wait' messages.
1522 		 */
1523 		if (apic->check_apicid_used(&phys_id_present_map,
1524 					    mpc_ioapic_id(ioapic_idx))) {
1525 			printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1526 				ioapic_idx, mpc_ioapic_id(ioapic_idx));
1527 			for (i = 0; i < get_physical_broadcast(); i++)
1528 				if (!physid_isset(i, phys_id_present_map))
1529 					break;
1530 			if (i >= get_physical_broadcast())
1531 				panic("Max APIC ID exceeded!\n");
1532 			printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1533 				i);
1534 			physid_set(i, phys_id_present_map);
1535 			ioapics[ioapic_idx].mp_config.apicid = i;
1536 		} else {
1537 			physid_mask_t tmp;
1538 			apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx),
1539 						    &tmp);
1540 			apic_printk(APIC_VERBOSE, "Setting %d in the "
1541 					"phys_id_present_map\n",
1542 					mpc_ioapic_id(ioapic_idx));
1543 			physids_or(phys_id_present_map, phys_id_present_map, tmp);
1544 		}
1545 
1546 		/*
1547 		 * We need to adjust the IRQ routing table
1548 		 * if the ID changed.
1549 		 */
1550 		if (old_id != mpc_ioapic_id(ioapic_idx))
1551 			for (i = 0; i < mp_irq_entries; i++)
1552 				if (mp_irqs[i].dstapic == old_id)
1553 					mp_irqs[i].dstapic
1554 						= mpc_ioapic_id(ioapic_idx);
1555 
1556 		/*
1557 		 * Update the ID register according to the right value
1558 		 * from the MPC table if they are different.
1559 		 */
1560 		if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
1561 			continue;
1562 
1563 		apic_printk(APIC_VERBOSE, KERN_INFO
1564 			"...changing IO-APIC physical APIC ID to %d ...",
1565 			mpc_ioapic_id(ioapic_idx));
1566 
1567 		reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
1568 		raw_spin_lock_irqsave(&ioapic_lock, flags);
1569 		io_apic_write(ioapic_idx, 0, reg_00.raw);
1570 		raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1571 
1572 		/*
1573 		 * Sanity check
1574 		 */
1575 		raw_spin_lock_irqsave(&ioapic_lock, flags);
1576 		reg_00.raw = io_apic_read(ioapic_idx, 0);
1577 		raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1578 		if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
1579 			pr_cont("could not set ID!\n");
1580 		else
1581 			apic_printk(APIC_VERBOSE, " ok.\n");
1582 	}
1583 }
1584 
1585 void __init setup_ioapic_ids_from_mpc(void)
1586 {
1587 
1588 	if (acpi_ioapic)
1589 		return;
1590 	/*
1591 	 * Don't check I/O APIC IDs for xAPIC systems.  They have
1592 	 * no meaning without the serial APIC bus.
1593 	 */
1594 	if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
1595 		|| APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
1596 		return;
1597 	setup_ioapic_ids_from_mpc_nocheck();
1598 }
1599 #endif
1600 
1601 int no_timer_check __initdata;
1602 
1603 static int __init notimercheck(char *s)
1604 {
1605 	no_timer_check = 1;
1606 	return 1;
1607 }
1608 __setup("no_timer_check", notimercheck);
1609 
1610 /*
1611  * There is a nasty bug in some older SMP boards, their mptable lies
1612  * about the timer IRQ. We do the following to work around the situation:
1613  *
1614  *	- timer IRQ defaults to IO-APIC IRQ
1615  *	- if this function detects that timer IRQs are defunct, then we fall
1616  *	  back to ISA timer IRQs
1617  */
1618 static int __init timer_irq_works(void)
1619 {
1620 	unsigned long t1 = jiffies;
1621 	unsigned long flags;
1622 
1623 	if (no_timer_check)
1624 		return 1;
1625 
1626 	local_save_flags(flags);
1627 	local_irq_enable();
1628 	/* Let ten ticks pass... */
1629 	mdelay((10 * 1000) / HZ);
1630 	local_irq_restore(flags);
1631 
1632 	/*
1633 	 * Expect a few ticks at least, to be sure some possible
1634 	 * glue logic does not lock up after one or two first
1635 	 * ticks in a non-ExtINT mode.  Also the local APIC
1636 	 * might have cached one ExtINT interrupt.  Finally, at
1637 	 * least one tick may be lost due to delays.
1638 	 */
1639 
1640 	/* jiffies wrap? */
1641 	if (time_after(jiffies, t1 + 4))
1642 		return 1;
1643 	return 0;
1644 }
1645 
1646 /*
1647  * In the SMP+IOAPIC case it might happen that there are an unspecified
1648  * number of pending IRQ events unhandled. These cases are very rare,
1649  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1650  * better to do it this way as thus we do not have to be aware of
1651  * 'pending' interrupts in the IRQ path, except at this point.
1652  */
1653 /*
1654  * Edge triggered needs to resend any interrupt
1655  * that was delayed but this is now handled in the device
1656  * independent code.
1657  */
1658 
1659 /*
1660  * Starting up a edge-triggered IO-APIC interrupt is
1661  * nasty - we need to make sure that we get the edge.
1662  * If it is already asserted for some reason, we need
1663  * return 1 to indicate that is was pending.
1664  *
1665  * This is not complete - we should be able to fake
1666  * an edge even if it isn't on the 8259A...
1667  */
1668 static unsigned int startup_ioapic_irq(struct irq_data *data)
1669 {
1670 	int was_pending = 0, irq = data->irq;
1671 	unsigned long flags;
1672 
1673 	raw_spin_lock_irqsave(&ioapic_lock, flags);
1674 	if (irq < nr_legacy_irqs()) {
1675 		legacy_pic->mask(irq);
1676 		if (legacy_pic->irq_pending(irq))
1677 			was_pending = 1;
1678 	}
1679 	__unmask_ioapic(data->chip_data);
1680 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1681 
1682 	return was_pending;
1683 }
1684 
1685 atomic_t irq_mis_count;
1686 
1687 #ifdef CONFIG_GENERIC_PENDING_IRQ
1688 static bool io_apic_level_ack_pending(struct mp_chip_data *data)
1689 {
1690 	struct irq_pin_list *entry;
1691 	unsigned long flags;
1692 
1693 	raw_spin_lock_irqsave(&ioapic_lock, flags);
1694 	for_each_irq_pin(entry, data->irq_2_pin) {
1695 		unsigned int reg;
1696 		int pin;
1697 
1698 		pin = entry->pin;
1699 		reg = io_apic_read(entry->apic, 0x10 + pin*2);
1700 		/* Is the remote IRR bit set? */
1701 		if (reg & IO_APIC_REDIR_REMOTE_IRR) {
1702 			raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1703 			return true;
1704 		}
1705 	}
1706 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1707 
1708 	return false;
1709 }
1710 
1711 static inline bool ioapic_irqd_mask(struct irq_data *data)
1712 {
1713 	/* If we are moving the irq we need to mask it */
1714 	if (unlikely(irqd_is_setaffinity_pending(data))) {
1715 		mask_ioapic_irq(data);
1716 		return true;
1717 	}
1718 	return false;
1719 }
1720 
1721 static inline void ioapic_irqd_unmask(struct irq_data *data, bool masked)
1722 {
1723 	if (unlikely(masked)) {
1724 		/* Only migrate the irq if the ack has been received.
1725 		 *
1726 		 * On rare occasions the broadcast level triggered ack gets
1727 		 * delayed going to ioapics, and if we reprogram the
1728 		 * vector while Remote IRR is still set the irq will never
1729 		 * fire again.
1730 		 *
1731 		 * To prevent this scenario we read the Remote IRR bit
1732 		 * of the ioapic.  This has two effects.
1733 		 * - On any sane system the read of the ioapic will
1734 		 *   flush writes (and acks) going to the ioapic from
1735 		 *   this cpu.
1736 		 * - We get to see if the ACK has actually been delivered.
1737 		 *
1738 		 * Based on failed experiments of reprogramming the
1739 		 * ioapic entry from outside of irq context starting
1740 		 * with masking the ioapic entry and then polling until
1741 		 * Remote IRR was clear before reprogramming the
1742 		 * ioapic I don't trust the Remote IRR bit to be
1743 		 * completey accurate.
1744 		 *
1745 		 * However there appears to be no other way to plug
1746 		 * this race, so if the Remote IRR bit is not
1747 		 * accurate and is causing problems then it is a hardware bug
1748 		 * and you can go talk to the chipset vendor about it.
1749 		 */
1750 		if (!io_apic_level_ack_pending(data->chip_data))
1751 			irq_move_masked_irq(data);
1752 		unmask_ioapic_irq(data);
1753 	}
1754 }
1755 #else
1756 static inline bool ioapic_irqd_mask(struct irq_data *data)
1757 {
1758 	return false;
1759 }
1760 static inline void ioapic_irqd_unmask(struct irq_data *data, bool masked)
1761 {
1762 }
1763 #endif
1764 
1765 static void ioapic_ack_level(struct irq_data *irq_data)
1766 {
1767 	struct irq_cfg *cfg = irqd_cfg(irq_data);
1768 	unsigned long v;
1769 	bool masked;
1770 	int i;
1771 
1772 	irq_complete_move(cfg);
1773 	masked = ioapic_irqd_mask(irq_data);
1774 
1775 	/*
1776 	 * It appears there is an erratum which affects at least version 0x11
1777 	 * of I/O APIC (that's the 82093AA and cores integrated into various
1778 	 * chipsets).  Under certain conditions a level-triggered interrupt is
1779 	 * erroneously delivered as edge-triggered one but the respective IRR
1780 	 * bit gets set nevertheless.  As a result the I/O unit expects an EOI
1781 	 * message but it will never arrive and further interrupts are blocked
1782 	 * from the source.  The exact reason is so far unknown, but the
1783 	 * phenomenon was observed when two consecutive interrupt requests
1784 	 * from a given source get delivered to the same CPU and the source is
1785 	 * temporarily disabled in between.
1786 	 *
1787 	 * A workaround is to simulate an EOI message manually.  We achieve it
1788 	 * by setting the trigger mode to edge and then to level when the edge
1789 	 * trigger mode gets detected in the TMR of a local APIC for a
1790 	 * level-triggered interrupt.  We mask the source for the time of the
1791 	 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1792 	 * The idea is from Manfred Spraul.  --macro
1793 	 *
1794 	 * Also in the case when cpu goes offline, fixup_irqs() will forward
1795 	 * any unhandled interrupt on the offlined cpu to the new cpu
1796 	 * destination that is handling the corresponding interrupt. This
1797 	 * interrupt forwarding is done via IPI's. Hence, in this case also
1798 	 * level-triggered io-apic interrupt will be seen as an edge
1799 	 * interrupt in the IRR. And we can't rely on the cpu's EOI
1800 	 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
1801 	 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
1802 	 * supporting EOI register, we do an explicit EOI to clear the
1803 	 * remote IRR and on IO-APIC's which don't have an EOI register,
1804 	 * we use the above logic (mask+edge followed by unmask+level) from
1805 	 * Manfred Spraul to clear the remote IRR.
1806 	 */
1807 	i = cfg->vector;
1808 	v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1809 
1810 	/*
1811 	 * We must acknowledge the irq before we move it or the acknowledge will
1812 	 * not propagate properly.
1813 	 */
1814 	ack_APIC_irq();
1815 
1816 	/*
1817 	 * Tail end of clearing remote IRR bit (either by delivering the EOI
1818 	 * message via io-apic EOI register write or simulating it using
1819 	 * mask+edge followed by unnask+level logic) manually when the
1820 	 * level triggered interrupt is seen as the edge triggered interrupt
1821 	 * at the cpu.
1822 	 */
1823 	if (!(v & (1 << (i & 0x1f)))) {
1824 		atomic_inc(&irq_mis_count);
1825 		eoi_ioapic_pin(cfg->vector, irq_data->chip_data);
1826 	}
1827 
1828 	ioapic_irqd_unmask(irq_data, masked);
1829 }
1830 
1831 static void ioapic_ir_ack_level(struct irq_data *irq_data)
1832 {
1833 	struct mp_chip_data *data = irq_data->chip_data;
1834 
1835 	/*
1836 	 * Intr-remapping uses pin number as the virtual vector
1837 	 * in the RTE. Actual vector is programmed in
1838 	 * intr-remapping table entry. Hence for the io-apic
1839 	 * EOI we use the pin number.
1840 	 */
1841 	ack_APIC_irq();
1842 	eoi_ioapic_pin(data->entry.vector, data);
1843 }
1844 
1845 static int ioapic_set_affinity(struct irq_data *irq_data,
1846 			       const struct cpumask *mask, bool force)
1847 {
1848 	struct irq_data *parent = irq_data->parent_data;
1849 	struct mp_chip_data *data = irq_data->chip_data;
1850 	struct irq_pin_list *entry;
1851 	struct irq_cfg *cfg;
1852 	unsigned long flags;
1853 	int ret;
1854 
1855 	ret = parent->chip->irq_set_affinity(parent, mask, force);
1856 	raw_spin_lock_irqsave(&ioapic_lock, flags);
1857 	if (ret >= 0 && ret != IRQ_SET_MASK_OK_DONE) {
1858 		cfg = irqd_cfg(irq_data);
1859 		data->entry.dest = cfg->dest_apicid;
1860 		data->entry.vector = cfg->vector;
1861 		for_each_irq_pin(entry, data->irq_2_pin)
1862 			__ioapic_write_entry(entry->apic, entry->pin,
1863 					     data->entry);
1864 	}
1865 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1866 
1867 	return ret;
1868 }
1869 
1870 static struct irq_chip ioapic_chip __read_mostly = {
1871 	.name			= "IO-APIC",
1872 	.irq_startup		= startup_ioapic_irq,
1873 	.irq_mask		= mask_ioapic_irq,
1874 	.irq_unmask		= unmask_ioapic_irq,
1875 	.irq_ack		= irq_chip_ack_parent,
1876 	.irq_eoi		= ioapic_ack_level,
1877 	.irq_set_affinity	= ioapic_set_affinity,
1878 	.flags			= IRQCHIP_SKIP_SET_WAKE,
1879 };
1880 
1881 static struct irq_chip ioapic_ir_chip __read_mostly = {
1882 	.name			= "IR-IO-APIC",
1883 	.irq_startup		= startup_ioapic_irq,
1884 	.irq_mask		= mask_ioapic_irq,
1885 	.irq_unmask		= unmask_ioapic_irq,
1886 	.irq_ack		= irq_chip_ack_parent,
1887 	.irq_eoi		= ioapic_ir_ack_level,
1888 	.irq_set_affinity	= ioapic_set_affinity,
1889 	.flags			= IRQCHIP_SKIP_SET_WAKE,
1890 };
1891 
1892 static inline void init_IO_APIC_traps(void)
1893 {
1894 	struct irq_cfg *cfg;
1895 	unsigned int irq;
1896 
1897 	for_each_active_irq(irq) {
1898 		cfg = irq_cfg(irq);
1899 		if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
1900 			/*
1901 			 * Hmm.. We don't have an entry for this,
1902 			 * so default to an old-fashioned 8259
1903 			 * interrupt if we can..
1904 			 */
1905 			if (irq < nr_legacy_irqs())
1906 				legacy_pic->make_irq(irq);
1907 			else
1908 				/* Strange. Oh, well.. */
1909 				irq_set_chip(irq, &no_irq_chip);
1910 		}
1911 	}
1912 }
1913 
1914 /*
1915  * The local APIC irq-chip implementation:
1916  */
1917 
1918 static void mask_lapic_irq(struct irq_data *data)
1919 {
1920 	unsigned long v;
1921 
1922 	v = apic_read(APIC_LVT0);
1923 	apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1924 }
1925 
1926 static void unmask_lapic_irq(struct irq_data *data)
1927 {
1928 	unsigned long v;
1929 
1930 	v = apic_read(APIC_LVT0);
1931 	apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1932 }
1933 
1934 static void ack_lapic_irq(struct irq_data *data)
1935 {
1936 	ack_APIC_irq();
1937 }
1938 
1939 static struct irq_chip lapic_chip __read_mostly = {
1940 	.name		= "local-APIC",
1941 	.irq_mask	= mask_lapic_irq,
1942 	.irq_unmask	= unmask_lapic_irq,
1943 	.irq_ack	= ack_lapic_irq,
1944 };
1945 
1946 static void lapic_register_intr(int irq)
1947 {
1948 	irq_clear_status_flags(irq, IRQ_LEVEL);
1949 	irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
1950 				      "edge");
1951 }
1952 
1953 /*
1954  * This looks a bit hackish but it's about the only one way of sending
1955  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
1956  * not support the ExtINT mode, unfortunately.  We need to send these
1957  * cycles as some i82489DX-based boards have glue logic that keeps the
1958  * 8259A interrupt line asserted until INTA.  --macro
1959  */
1960 static inline void __init unlock_ExtINT_logic(void)
1961 {
1962 	int apic, pin, i;
1963 	struct IO_APIC_route_entry entry0, entry1;
1964 	unsigned char save_control, save_freq_select;
1965 
1966 	pin  = find_isa_irq_pin(8, mp_INT);
1967 	if (pin == -1) {
1968 		WARN_ON_ONCE(1);
1969 		return;
1970 	}
1971 	apic = find_isa_irq_apic(8, mp_INT);
1972 	if (apic == -1) {
1973 		WARN_ON_ONCE(1);
1974 		return;
1975 	}
1976 
1977 	entry0 = ioapic_read_entry(apic, pin);
1978 	clear_IO_APIC_pin(apic, pin);
1979 
1980 	memset(&entry1, 0, sizeof(entry1));
1981 
1982 	entry1.dest_mode = IOAPIC_DEST_MODE_PHYSICAL;
1983 	entry1.mask = IOAPIC_UNMASKED;
1984 	entry1.dest = hard_smp_processor_id();
1985 	entry1.delivery_mode = dest_ExtINT;
1986 	entry1.polarity = entry0.polarity;
1987 	entry1.trigger = IOAPIC_EDGE;
1988 	entry1.vector = 0;
1989 
1990 	ioapic_write_entry(apic, pin, entry1);
1991 
1992 	save_control = CMOS_READ(RTC_CONTROL);
1993 	save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1994 	CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1995 		   RTC_FREQ_SELECT);
1996 	CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1997 
1998 	i = 100;
1999 	while (i-- > 0) {
2000 		mdelay(10);
2001 		if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2002 			i -= 10;
2003 	}
2004 
2005 	CMOS_WRITE(save_control, RTC_CONTROL);
2006 	CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2007 	clear_IO_APIC_pin(apic, pin);
2008 
2009 	ioapic_write_entry(apic, pin, entry0);
2010 }
2011 
2012 static int disable_timer_pin_1 __initdata;
2013 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2014 static int __init disable_timer_pin_setup(char *arg)
2015 {
2016 	disable_timer_pin_1 = 1;
2017 	return 0;
2018 }
2019 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2020 
2021 static int mp_alloc_timer_irq(int ioapic, int pin)
2022 {
2023 	int irq = -1;
2024 	struct irq_domain *domain = mp_ioapic_irqdomain(ioapic);
2025 
2026 	if (domain) {
2027 		struct irq_alloc_info info;
2028 
2029 		ioapic_set_alloc_attr(&info, NUMA_NO_NODE, 0, 0);
2030 		info.ioapic_id = mpc_ioapic_id(ioapic);
2031 		info.ioapic_pin = pin;
2032 		mutex_lock(&ioapic_mutex);
2033 		irq = alloc_isa_irq_from_domain(domain, 0, ioapic, pin, &info);
2034 		mutex_unlock(&ioapic_mutex);
2035 	}
2036 
2037 	return irq;
2038 }
2039 
2040 /*
2041  * This code may look a bit paranoid, but it's supposed to cooperate with
2042  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2043  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2044  * fanatically on his truly buggy board.
2045  *
2046  * FIXME: really need to revamp this for all platforms.
2047  */
2048 static inline void __init check_timer(void)
2049 {
2050 	struct irq_data *irq_data = irq_get_irq_data(0);
2051 	struct mp_chip_data *data = irq_data->chip_data;
2052 	struct irq_cfg *cfg = irqd_cfg(irq_data);
2053 	int node = cpu_to_node(0);
2054 	int apic1, pin1, apic2, pin2;
2055 	unsigned long flags;
2056 	int no_pin1 = 0;
2057 
2058 	local_irq_save(flags);
2059 
2060 	/*
2061 	 * get/set the timer IRQ vector:
2062 	 */
2063 	legacy_pic->mask(0);
2064 
2065 	/*
2066 	 * As IRQ0 is to be enabled in the 8259A, the virtual
2067 	 * wire has to be disabled in the local APIC.  Also
2068 	 * timer interrupts need to be acknowledged manually in
2069 	 * the 8259A for the i82489DX when using the NMI
2070 	 * watchdog as that APIC treats NMIs as level-triggered.
2071 	 * The AEOI mode will finish them in the 8259A
2072 	 * automatically.
2073 	 */
2074 	apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2075 	legacy_pic->init(1);
2076 
2077 	pin1  = find_isa_irq_pin(0, mp_INT);
2078 	apic1 = find_isa_irq_apic(0, mp_INT);
2079 	pin2  = ioapic_i8259.pin;
2080 	apic2 = ioapic_i8259.apic;
2081 
2082 	apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2083 		    "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2084 		    cfg->vector, apic1, pin1, apic2, pin2);
2085 
2086 	/*
2087 	 * Some BIOS writers are clueless and report the ExtINTA
2088 	 * I/O APIC input from the cascaded 8259A as the timer
2089 	 * interrupt input.  So just in case, if only one pin
2090 	 * was found above, try it both directly and through the
2091 	 * 8259A.
2092 	 */
2093 	if (pin1 == -1) {
2094 		panic_if_irq_remap("BIOS bug: timer not connected to IO-APIC");
2095 		pin1 = pin2;
2096 		apic1 = apic2;
2097 		no_pin1 = 1;
2098 	} else if (pin2 == -1) {
2099 		pin2 = pin1;
2100 		apic2 = apic1;
2101 	}
2102 
2103 	if (pin1 != -1) {
2104 		/* Ok, does IRQ0 through the IOAPIC work? */
2105 		if (no_pin1) {
2106 			mp_alloc_timer_irq(apic1, pin1);
2107 		} else {
2108 			/*
2109 			 * for edge trigger, it's already unmasked,
2110 			 * so only need to unmask if it is level-trigger
2111 			 * do we really have level trigger timer?
2112 			 */
2113 			int idx;
2114 			idx = find_irq_entry(apic1, pin1, mp_INT);
2115 			if (idx != -1 && irq_trigger(idx))
2116 				unmask_ioapic_irq(irq_get_chip_data(0));
2117 		}
2118 		irq_domain_activate_irq(irq_data);
2119 		if (timer_irq_works()) {
2120 			if (disable_timer_pin_1 > 0)
2121 				clear_IO_APIC_pin(0, pin1);
2122 			goto out;
2123 		}
2124 		panic_if_irq_remap("timer doesn't work through Interrupt-remapped IO-APIC");
2125 		local_irq_disable();
2126 		clear_IO_APIC_pin(apic1, pin1);
2127 		if (!no_pin1)
2128 			apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2129 				    "8254 timer not connected to IO-APIC\n");
2130 
2131 		apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2132 			    "(IRQ0) through the 8259A ...\n");
2133 		apic_printk(APIC_QUIET, KERN_INFO
2134 			    "..... (found apic %d pin %d) ...\n", apic2, pin2);
2135 		/*
2136 		 * legacy devices should be connected to IO APIC #0
2137 		 */
2138 		replace_pin_at_irq_node(data, node, apic1, pin1, apic2, pin2);
2139 		irq_domain_activate_irq(irq_data);
2140 		legacy_pic->unmask(0);
2141 		if (timer_irq_works()) {
2142 			apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2143 			goto out;
2144 		}
2145 		/*
2146 		 * Cleanup, just in case ...
2147 		 */
2148 		local_irq_disable();
2149 		legacy_pic->mask(0);
2150 		clear_IO_APIC_pin(apic2, pin2);
2151 		apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2152 	}
2153 
2154 	apic_printk(APIC_QUIET, KERN_INFO
2155 		    "...trying to set up timer as Virtual Wire IRQ...\n");
2156 
2157 	lapic_register_intr(0);
2158 	apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector);	/* Fixed mode */
2159 	legacy_pic->unmask(0);
2160 
2161 	if (timer_irq_works()) {
2162 		apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2163 		goto out;
2164 	}
2165 	local_irq_disable();
2166 	legacy_pic->mask(0);
2167 	apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2168 	apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2169 
2170 	apic_printk(APIC_QUIET, KERN_INFO
2171 		    "...trying to set up timer as ExtINT IRQ...\n");
2172 
2173 	legacy_pic->init(0);
2174 	legacy_pic->make_irq(0);
2175 	apic_write(APIC_LVT0, APIC_DM_EXTINT);
2176 
2177 	unlock_ExtINT_logic();
2178 
2179 	if (timer_irq_works()) {
2180 		apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2181 		goto out;
2182 	}
2183 	local_irq_disable();
2184 	apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2185 	if (apic_is_x2apic_enabled())
2186 		apic_printk(APIC_QUIET, KERN_INFO
2187 			    "Perhaps problem with the pre-enabled x2apic mode\n"
2188 			    "Try booting with x2apic and interrupt-remapping disabled in the bios.\n");
2189 	panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
2190 		"report.  Then try booting with the 'noapic' option.\n");
2191 out:
2192 	local_irq_restore(flags);
2193 }
2194 
2195 /*
2196  * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2197  * to devices.  However there may be an I/O APIC pin available for
2198  * this interrupt regardless.  The pin may be left unconnected, but
2199  * typically it will be reused as an ExtINT cascade interrupt for
2200  * the master 8259A.  In the MPS case such a pin will normally be
2201  * reported as an ExtINT interrupt in the MP table.  With ACPI
2202  * there is no provision for ExtINT interrupts, and in the absence
2203  * of an override it would be treated as an ordinary ISA I/O APIC
2204  * interrupt, that is edge-triggered and unmasked by default.  We
2205  * used to do this, but it caused problems on some systems because
2206  * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2207  * the same ExtINT cascade interrupt to drive the local APIC of the
2208  * bootstrap processor.  Therefore we refrain from routing IRQ2 to
2209  * the I/O APIC in all cases now.  No actual device should request
2210  * it anyway.  --macro
2211  */
2212 #define PIC_IRQS	(1UL << PIC_CASCADE_IR)
2213 
2214 static int mp_irqdomain_create(int ioapic)
2215 {
2216 	struct irq_alloc_info info;
2217 	struct irq_domain *parent;
2218 	int hwirqs = mp_ioapic_pin_count(ioapic);
2219 	struct ioapic *ip = &ioapics[ioapic];
2220 	struct ioapic_domain_cfg *cfg = &ip->irqdomain_cfg;
2221 	struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2222 
2223 	if (cfg->type == IOAPIC_DOMAIN_INVALID)
2224 		return 0;
2225 
2226 	init_irq_alloc_info(&info, NULL);
2227 	info.type = X86_IRQ_ALLOC_TYPE_IOAPIC;
2228 	info.ioapic_id = mpc_ioapic_id(ioapic);
2229 	parent = irq_remapping_get_ir_irq_domain(&info);
2230 	if (!parent)
2231 		parent = x86_vector_domain;
2232 
2233 	ip->irqdomain = irq_domain_add_linear(cfg->dev, hwirqs, cfg->ops,
2234 					      (void *)(long)ioapic);
2235 	if (!ip->irqdomain)
2236 		return -ENOMEM;
2237 
2238 	ip->irqdomain->parent = parent;
2239 
2240 	if (cfg->type == IOAPIC_DOMAIN_LEGACY ||
2241 	    cfg->type == IOAPIC_DOMAIN_STRICT)
2242 		ioapic_dynirq_base = max(ioapic_dynirq_base,
2243 					 gsi_cfg->gsi_end + 1);
2244 
2245 	return 0;
2246 }
2247 
2248 static void ioapic_destroy_irqdomain(int idx)
2249 {
2250 	if (ioapics[idx].irqdomain) {
2251 		irq_domain_remove(ioapics[idx].irqdomain);
2252 		ioapics[idx].irqdomain = NULL;
2253 	}
2254 }
2255 
2256 void __init setup_IO_APIC(void)
2257 {
2258 	int ioapic;
2259 
2260 	if (skip_ioapic_setup || !nr_ioapics)
2261 		return;
2262 
2263 	io_apic_irqs = nr_legacy_irqs() ? ~PIC_IRQS : ~0UL;
2264 
2265 	apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2266 	for_each_ioapic(ioapic)
2267 		BUG_ON(mp_irqdomain_create(ioapic));
2268 
2269 	/*
2270          * Set up IO-APIC IRQ routing.
2271          */
2272 	x86_init.mpparse.setup_ioapic_ids();
2273 
2274 	sync_Arb_IDs();
2275 	setup_IO_APIC_irqs();
2276 	init_IO_APIC_traps();
2277 	if (nr_legacy_irqs())
2278 		check_timer();
2279 
2280 	ioapic_initialized = 1;
2281 }
2282 
2283 static void resume_ioapic_id(int ioapic_idx)
2284 {
2285 	unsigned long flags;
2286 	union IO_APIC_reg_00 reg_00;
2287 
2288 	raw_spin_lock_irqsave(&ioapic_lock, flags);
2289 	reg_00.raw = io_apic_read(ioapic_idx, 0);
2290 	if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
2291 		reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2292 		io_apic_write(ioapic_idx, 0, reg_00.raw);
2293 	}
2294 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2295 }
2296 
2297 static void ioapic_resume(void)
2298 {
2299 	int ioapic_idx;
2300 
2301 	for_each_ioapic_reverse(ioapic_idx)
2302 		resume_ioapic_id(ioapic_idx);
2303 
2304 	restore_ioapic_entries();
2305 }
2306 
2307 static struct syscore_ops ioapic_syscore_ops = {
2308 	.suspend = save_ioapic_entries,
2309 	.resume = ioapic_resume,
2310 };
2311 
2312 static int __init ioapic_init_ops(void)
2313 {
2314 	register_syscore_ops(&ioapic_syscore_ops);
2315 
2316 	return 0;
2317 }
2318 
2319 device_initcall(ioapic_init_ops);
2320 
2321 static int io_apic_get_redir_entries(int ioapic)
2322 {
2323 	union IO_APIC_reg_01	reg_01;
2324 	unsigned long flags;
2325 
2326 	raw_spin_lock_irqsave(&ioapic_lock, flags);
2327 	reg_01.raw = io_apic_read(ioapic, 1);
2328 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2329 
2330 	/* The register returns the maximum index redir index
2331 	 * supported, which is one less than the total number of redir
2332 	 * entries.
2333 	 */
2334 	return reg_01.bits.entries + 1;
2335 }
2336 
2337 unsigned int arch_dynirq_lower_bound(unsigned int from)
2338 {
2339 	/*
2340 	 * dmar_alloc_hwirq() may be called before setup_IO_APIC(), so use
2341 	 * gsi_top if ioapic_dynirq_base hasn't been initialized yet.
2342 	 */
2343 	return ioapic_initialized ? ioapic_dynirq_base : gsi_top;
2344 }
2345 
2346 #ifdef CONFIG_X86_32
2347 static int io_apic_get_unique_id(int ioapic, int apic_id)
2348 {
2349 	union IO_APIC_reg_00 reg_00;
2350 	static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
2351 	physid_mask_t tmp;
2352 	unsigned long flags;
2353 	int i = 0;
2354 
2355 	/*
2356 	 * The P4 platform supports up to 256 APIC IDs on two separate APIC
2357 	 * buses (one for LAPICs, one for IOAPICs), where predecessors only
2358 	 * supports up to 16 on one shared APIC bus.
2359 	 *
2360 	 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
2361 	 *      advantage of new APIC bus architecture.
2362 	 */
2363 
2364 	if (physids_empty(apic_id_map))
2365 		apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
2366 
2367 	raw_spin_lock_irqsave(&ioapic_lock, flags);
2368 	reg_00.raw = io_apic_read(ioapic, 0);
2369 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2370 
2371 	if (apic_id >= get_physical_broadcast()) {
2372 		printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
2373 			"%d\n", ioapic, apic_id, reg_00.bits.ID);
2374 		apic_id = reg_00.bits.ID;
2375 	}
2376 
2377 	/*
2378 	 * Every APIC in a system must have a unique ID or we get lots of nice
2379 	 * 'stuck on smp_invalidate_needed IPI wait' messages.
2380 	 */
2381 	if (apic->check_apicid_used(&apic_id_map, apic_id)) {
2382 
2383 		for (i = 0; i < get_physical_broadcast(); i++) {
2384 			if (!apic->check_apicid_used(&apic_id_map, i))
2385 				break;
2386 		}
2387 
2388 		if (i == get_physical_broadcast())
2389 			panic("Max apic_id exceeded!\n");
2390 
2391 		printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
2392 			"trying %d\n", ioapic, apic_id, i);
2393 
2394 		apic_id = i;
2395 	}
2396 
2397 	apic->apicid_to_cpu_present(apic_id, &tmp);
2398 	physids_or(apic_id_map, apic_id_map, tmp);
2399 
2400 	if (reg_00.bits.ID != apic_id) {
2401 		reg_00.bits.ID = apic_id;
2402 
2403 		raw_spin_lock_irqsave(&ioapic_lock, flags);
2404 		io_apic_write(ioapic, 0, reg_00.raw);
2405 		reg_00.raw = io_apic_read(ioapic, 0);
2406 		raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2407 
2408 		/* Sanity check */
2409 		if (reg_00.bits.ID != apic_id) {
2410 			pr_err("IOAPIC[%d]: Unable to change apic_id!\n",
2411 			       ioapic);
2412 			return -1;
2413 		}
2414 	}
2415 
2416 	apic_printk(APIC_VERBOSE, KERN_INFO
2417 			"IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
2418 
2419 	return apic_id;
2420 }
2421 
2422 static u8 io_apic_unique_id(int idx, u8 id)
2423 {
2424 	if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
2425 	    !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2426 		return io_apic_get_unique_id(idx, id);
2427 	else
2428 		return id;
2429 }
2430 #else
2431 static u8 io_apic_unique_id(int idx, u8 id)
2432 {
2433 	union IO_APIC_reg_00 reg_00;
2434 	DECLARE_BITMAP(used, 256);
2435 	unsigned long flags;
2436 	u8 new_id;
2437 	int i;
2438 
2439 	bitmap_zero(used, 256);
2440 	for_each_ioapic(i)
2441 		__set_bit(mpc_ioapic_id(i), used);
2442 
2443 	/* Hand out the requested id if available */
2444 	if (!test_bit(id, used))
2445 		return id;
2446 
2447 	/*
2448 	 * Read the current id from the ioapic and keep it if
2449 	 * available.
2450 	 */
2451 	raw_spin_lock_irqsave(&ioapic_lock, flags);
2452 	reg_00.raw = io_apic_read(idx, 0);
2453 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2454 	new_id = reg_00.bits.ID;
2455 	if (!test_bit(new_id, used)) {
2456 		apic_printk(APIC_VERBOSE, KERN_INFO
2457 			"IOAPIC[%d]: Using reg apic_id %d instead of %d\n",
2458 			 idx, new_id, id);
2459 		return new_id;
2460 	}
2461 
2462 	/*
2463 	 * Get the next free id and write it to the ioapic.
2464 	 */
2465 	new_id = find_first_zero_bit(used, 256);
2466 	reg_00.bits.ID = new_id;
2467 	raw_spin_lock_irqsave(&ioapic_lock, flags);
2468 	io_apic_write(idx, 0, reg_00.raw);
2469 	reg_00.raw = io_apic_read(idx, 0);
2470 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2471 	/* Sanity check */
2472 	BUG_ON(reg_00.bits.ID != new_id);
2473 
2474 	return new_id;
2475 }
2476 #endif
2477 
2478 static int io_apic_get_version(int ioapic)
2479 {
2480 	union IO_APIC_reg_01	reg_01;
2481 	unsigned long flags;
2482 
2483 	raw_spin_lock_irqsave(&ioapic_lock, flags);
2484 	reg_01.raw = io_apic_read(ioapic, 1);
2485 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2486 
2487 	return reg_01.bits.version;
2488 }
2489 
2490 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
2491 {
2492 	int ioapic, pin, idx;
2493 
2494 	if (skip_ioapic_setup)
2495 		return -1;
2496 
2497 	ioapic = mp_find_ioapic(gsi);
2498 	if (ioapic < 0)
2499 		return -1;
2500 
2501 	pin = mp_find_ioapic_pin(ioapic, gsi);
2502 	if (pin < 0)
2503 		return -1;
2504 
2505 	idx = find_irq_entry(ioapic, pin, mp_INT);
2506 	if (idx < 0)
2507 		return -1;
2508 
2509 	*trigger = irq_trigger(idx);
2510 	*polarity = irq_polarity(idx);
2511 	return 0;
2512 }
2513 
2514 /*
2515  * This function currently is only a helper for the i386 smp boot process where
2516  * we need to reprogram the ioredtbls to cater for the cpus which have come online
2517  * so mask in all cases should simply be apic->target_cpus()
2518  */
2519 #ifdef CONFIG_SMP
2520 void __init setup_ioapic_dest(void)
2521 {
2522 	int pin, ioapic, irq, irq_entry;
2523 	const struct cpumask *mask;
2524 	struct irq_desc *desc;
2525 	struct irq_data *idata;
2526 	struct irq_chip *chip;
2527 
2528 	if (skip_ioapic_setup == 1)
2529 		return;
2530 
2531 	for_each_ioapic_pin(ioapic, pin) {
2532 		irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2533 		if (irq_entry == -1)
2534 			continue;
2535 
2536 		irq = pin_2_irq(irq_entry, ioapic, pin, 0);
2537 		if (irq < 0 || !mp_init_irq_at_boot(ioapic, irq))
2538 			continue;
2539 
2540 		desc = irq_to_desc(irq);
2541 		raw_spin_lock_irq(&desc->lock);
2542 		idata = irq_desc_get_irq_data(desc);
2543 
2544 		/*
2545 		 * Honour affinities which have been set in early boot
2546 		 */
2547 		if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata))
2548 			mask = irq_data_get_affinity_mask(idata);
2549 		else
2550 			mask = apic->target_cpus();
2551 
2552 		chip = irq_data_get_irq_chip(idata);
2553 		/* Might be lapic_chip for irq 0 */
2554 		if (chip->irq_set_affinity)
2555 			chip->irq_set_affinity(idata, mask, false);
2556 		raw_spin_unlock_irq(&desc->lock);
2557 	}
2558 }
2559 #endif
2560 
2561 #define IOAPIC_RESOURCE_NAME_SIZE 11
2562 
2563 static struct resource *ioapic_resources;
2564 
2565 static struct resource * __init ioapic_setup_resources(void)
2566 {
2567 	unsigned long n;
2568 	struct resource *res;
2569 	char *mem;
2570 	int i, num = 0;
2571 
2572 	for_each_ioapic(i)
2573 		num++;
2574 	if (num == 0)
2575 		return NULL;
2576 
2577 	n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2578 	n *= num;
2579 
2580 	mem = alloc_bootmem(n);
2581 	res = (void *)mem;
2582 
2583 	mem += sizeof(struct resource) * num;
2584 
2585 	num = 0;
2586 	for_each_ioapic(i) {
2587 		res[num].name = mem;
2588 		res[num].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2589 		snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
2590 		mem += IOAPIC_RESOURCE_NAME_SIZE;
2591 		num++;
2592 		ioapics[i].iomem_res = res;
2593 	}
2594 
2595 	ioapic_resources = res;
2596 
2597 	return res;
2598 }
2599 
2600 void __init io_apic_init_mappings(void)
2601 {
2602 	unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2603 	struct resource *ioapic_res;
2604 	int i;
2605 
2606 	ioapic_res = ioapic_setup_resources();
2607 	for_each_ioapic(i) {
2608 		if (smp_found_config) {
2609 			ioapic_phys = mpc_ioapic_addr(i);
2610 #ifdef CONFIG_X86_32
2611 			if (!ioapic_phys) {
2612 				printk(KERN_ERR
2613 				       "WARNING: bogus zero IO-APIC "
2614 				       "address found in MPTABLE, "
2615 				       "disabling IO/APIC support!\n");
2616 				smp_found_config = 0;
2617 				skip_ioapic_setup = 1;
2618 				goto fake_ioapic_page;
2619 			}
2620 #endif
2621 		} else {
2622 #ifdef CONFIG_X86_32
2623 fake_ioapic_page:
2624 #endif
2625 			ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
2626 			ioapic_phys = __pa(ioapic_phys);
2627 		}
2628 		set_fixmap_nocache(idx, ioapic_phys);
2629 		apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
2630 			__fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
2631 			ioapic_phys);
2632 		idx++;
2633 
2634 		ioapic_res->start = ioapic_phys;
2635 		ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
2636 		ioapic_res++;
2637 	}
2638 }
2639 
2640 void __init ioapic_insert_resources(void)
2641 {
2642 	int i;
2643 	struct resource *r = ioapic_resources;
2644 
2645 	if (!r) {
2646 		if (nr_ioapics > 0)
2647 			printk(KERN_ERR
2648 				"IO APIC resources couldn't be allocated.\n");
2649 		return;
2650 	}
2651 
2652 	for_each_ioapic(i) {
2653 		insert_resource(&iomem_resource, r);
2654 		r++;
2655 	}
2656 }
2657 
2658 int mp_find_ioapic(u32 gsi)
2659 {
2660 	int i;
2661 
2662 	if (nr_ioapics == 0)
2663 		return -1;
2664 
2665 	/* Find the IOAPIC that manages this GSI. */
2666 	for_each_ioapic(i) {
2667 		struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
2668 		if (gsi >= gsi_cfg->gsi_base && gsi <= gsi_cfg->gsi_end)
2669 			return i;
2670 	}
2671 
2672 	printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
2673 	return -1;
2674 }
2675 
2676 int mp_find_ioapic_pin(int ioapic, u32 gsi)
2677 {
2678 	struct mp_ioapic_gsi *gsi_cfg;
2679 
2680 	if (WARN_ON(ioapic < 0))
2681 		return -1;
2682 
2683 	gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2684 	if (WARN_ON(gsi > gsi_cfg->gsi_end))
2685 		return -1;
2686 
2687 	return gsi - gsi_cfg->gsi_base;
2688 }
2689 
2690 static int bad_ioapic_register(int idx)
2691 {
2692 	union IO_APIC_reg_00 reg_00;
2693 	union IO_APIC_reg_01 reg_01;
2694 	union IO_APIC_reg_02 reg_02;
2695 
2696 	reg_00.raw = io_apic_read(idx, 0);
2697 	reg_01.raw = io_apic_read(idx, 1);
2698 	reg_02.raw = io_apic_read(idx, 2);
2699 
2700 	if (reg_00.raw == -1 && reg_01.raw == -1 && reg_02.raw == -1) {
2701 		pr_warn("I/O APIC 0x%x registers return all ones, skipping!\n",
2702 			mpc_ioapic_addr(idx));
2703 		return 1;
2704 	}
2705 
2706 	return 0;
2707 }
2708 
2709 static int find_free_ioapic_entry(void)
2710 {
2711 	int idx;
2712 
2713 	for (idx = 0; idx < MAX_IO_APICS; idx++)
2714 		if (ioapics[idx].nr_registers == 0)
2715 			return idx;
2716 
2717 	return MAX_IO_APICS;
2718 }
2719 
2720 /**
2721  * mp_register_ioapic - Register an IOAPIC device
2722  * @id:		hardware IOAPIC ID
2723  * @address:	physical address of IOAPIC register area
2724  * @gsi_base:	base of GSI associated with the IOAPIC
2725  * @cfg:	configuration information for the IOAPIC
2726  */
2727 int mp_register_ioapic(int id, u32 address, u32 gsi_base,
2728 		       struct ioapic_domain_cfg *cfg)
2729 {
2730 	bool hotplug = !!ioapic_initialized;
2731 	struct mp_ioapic_gsi *gsi_cfg;
2732 	int idx, ioapic, entries;
2733 	u32 gsi_end;
2734 
2735 	if (!address) {
2736 		pr_warn("Bogus (zero) I/O APIC address found, skipping!\n");
2737 		return -EINVAL;
2738 	}
2739 	for_each_ioapic(ioapic)
2740 		if (ioapics[ioapic].mp_config.apicaddr == address) {
2741 			pr_warn("address 0x%x conflicts with IOAPIC%d\n",
2742 				address, ioapic);
2743 			return -EEXIST;
2744 		}
2745 
2746 	idx = find_free_ioapic_entry();
2747 	if (idx >= MAX_IO_APICS) {
2748 		pr_warn("Max # of I/O APICs (%d) exceeded (found %d), skipping\n",
2749 			MAX_IO_APICS, idx);
2750 		return -ENOSPC;
2751 	}
2752 
2753 	ioapics[idx].mp_config.type = MP_IOAPIC;
2754 	ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
2755 	ioapics[idx].mp_config.apicaddr = address;
2756 
2757 	set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
2758 	if (bad_ioapic_register(idx)) {
2759 		clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2760 		return -ENODEV;
2761 	}
2762 
2763 	ioapics[idx].mp_config.apicid = io_apic_unique_id(idx, id);
2764 	ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
2765 
2766 	/*
2767 	 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
2768 	 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
2769 	 */
2770 	entries = io_apic_get_redir_entries(idx);
2771 	gsi_end = gsi_base + entries - 1;
2772 	for_each_ioapic(ioapic) {
2773 		gsi_cfg = mp_ioapic_gsi_routing(ioapic);
2774 		if ((gsi_base >= gsi_cfg->gsi_base &&
2775 		     gsi_base <= gsi_cfg->gsi_end) ||
2776 		    (gsi_end >= gsi_cfg->gsi_base &&
2777 		     gsi_end <= gsi_cfg->gsi_end)) {
2778 			pr_warn("GSI range [%u-%u] for new IOAPIC conflicts with GSI[%u-%u]\n",
2779 				gsi_base, gsi_end,
2780 				gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2781 			clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2782 			return -ENOSPC;
2783 		}
2784 	}
2785 	gsi_cfg = mp_ioapic_gsi_routing(idx);
2786 	gsi_cfg->gsi_base = gsi_base;
2787 	gsi_cfg->gsi_end = gsi_end;
2788 
2789 	ioapics[idx].irqdomain = NULL;
2790 	ioapics[idx].irqdomain_cfg = *cfg;
2791 
2792 	/*
2793 	 * If mp_register_ioapic() is called during early boot stage when
2794 	 * walking ACPI/SFI/DT tables, it's too early to create irqdomain,
2795 	 * we are still using bootmem allocator. So delay it to setup_IO_APIC().
2796 	 */
2797 	if (hotplug) {
2798 		if (mp_irqdomain_create(idx)) {
2799 			clear_fixmap(FIX_IO_APIC_BASE_0 + idx);
2800 			return -ENOMEM;
2801 		}
2802 		alloc_ioapic_saved_registers(idx);
2803 	}
2804 
2805 	if (gsi_cfg->gsi_end >= gsi_top)
2806 		gsi_top = gsi_cfg->gsi_end + 1;
2807 	if (nr_ioapics <= idx)
2808 		nr_ioapics = idx + 1;
2809 
2810 	/* Set nr_registers to mark entry present */
2811 	ioapics[idx].nr_registers = entries;
2812 
2813 	pr_info("IOAPIC[%d]: apic_id %d, version %d, address 0x%x, GSI %d-%d\n",
2814 		idx, mpc_ioapic_id(idx),
2815 		mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
2816 		gsi_cfg->gsi_base, gsi_cfg->gsi_end);
2817 
2818 	return 0;
2819 }
2820 
2821 int mp_unregister_ioapic(u32 gsi_base)
2822 {
2823 	int ioapic, pin;
2824 	int found = 0;
2825 
2826 	for_each_ioapic(ioapic)
2827 		if (ioapics[ioapic].gsi_config.gsi_base == gsi_base) {
2828 			found = 1;
2829 			break;
2830 		}
2831 	if (!found) {
2832 		pr_warn("can't find IOAPIC for GSI %d\n", gsi_base);
2833 		return -ENODEV;
2834 	}
2835 
2836 	for_each_pin(ioapic, pin) {
2837 		u32 gsi = mp_pin_to_gsi(ioapic, pin);
2838 		int irq = mp_map_gsi_to_irq(gsi, 0, NULL);
2839 		struct mp_chip_data *data;
2840 
2841 		if (irq >= 0) {
2842 			data = irq_get_chip_data(irq);
2843 			if (data && data->count) {
2844 				pr_warn("pin%d on IOAPIC%d is still in use.\n",
2845 					pin, ioapic);
2846 				return -EBUSY;
2847 			}
2848 		}
2849 	}
2850 
2851 	/* Mark entry not present */
2852 	ioapics[ioapic].nr_registers  = 0;
2853 	ioapic_destroy_irqdomain(ioapic);
2854 	free_ioapic_saved_registers(ioapic);
2855 	if (ioapics[ioapic].iomem_res)
2856 		release_resource(ioapics[ioapic].iomem_res);
2857 	clear_fixmap(FIX_IO_APIC_BASE_0 + ioapic);
2858 	memset(&ioapics[ioapic], 0, sizeof(ioapics[ioapic]));
2859 
2860 	return 0;
2861 }
2862 
2863 int mp_ioapic_registered(u32 gsi_base)
2864 {
2865 	int ioapic;
2866 
2867 	for_each_ioapic(ioapic)
2868 		if (ioapics[ioapic].gsi_config.gsi_base == gsi_base)
2869 			return 1;
2870 
2871 	return 0;
2872 }
2873 
2874 static void mp_irqdomain_get_attr(u32 gsi, struct mp_chip_data *data,
2875 				  struct irq_alloc_info *info)
2876 {
2877 	if (info && info->ioapic_valid) {
2878 		data->trigger = info->ioapic_trigger;
2879 		data->polarity = info->ioapic_polarity;
2880 	} else if (acpi_get_override_irq(gsi, &data->trigger,
2881 					 &data->polarity) < 0) {
2882 		/* PCI interrupts are always active low level triggered. */
2883 		data->trigger = IOAPIC_LEVEL;
2884 		data->polarity = IOAPIC_POL_LOW;
2885 	}
2886 }
2887 
2888 static void mp_setup_entry(struct irq_cfg *cfg, struct mp_chip_data *data,
2889 			   struct IO_APIC_route_entry *entry)
2890 {
2891 	memset(entry, 0, sizeof(*entry));
2892 	entry->delivery_mode = apic->irq_delivery_mode;
2893 	entry->dest_mode     = apic->irq_dest_mode;
2894 	entry->dest	     = cfg->dest_apicid;
2895 	entry->vector	     = cfg->vector;
2896 	entry->trigger	     = data->trigger;
2897 	entry->polarity	     = data->polarity;
2898 	/*
2899 	 * Mask level triggered irqs. Edge triggered irqs are masked
2900 	 * by the irq core code in case they fire.
2901 	 */
2902 	if (data->trigger == IOAPIC_LEVEL)
2903 		entry->mask = IOAPIC_MASKED;
2904 	else
2905 		entry->mask = IOAPIC_UNMASKED;
2906 }
2907 
2908 int mp_irqdomain_alloc(struct irq_domain *domain, unsigned int virq,
2909 		       unsigned int nr_irqs, void *arg)
2910 {
2911 	int ret, ioapic, pin;
2912 	struct irq_cfg *cfg;
2913 	struct irq_data *irq_data;
2914 	struct mp_chip_data *data;
2915 	struct irq_alloc_info *info = arg;
2916 	unsigned long flags;
2917 
2918 	if (!info || nr_irqs > 1)
2919 		return -EINVAL;
2920 	irq_data = irq_domain_get_irq_data(domain, virq);
2921 	if (!irq_data)
2922 		return -EINVAL;
2923 
2924 	ioapic = mp_irqdomain_ioapic_idx(domain);
2925 	pin = info->ioapic_pin;
2926 	if (irq_find_mapping(domain, (irq_hw_number_t)pin) > 0)
2927 		return -EEXIST;
2928 
2929 	data = kzalloc(sizeof(*data), GFP_KERNEL);
2930 	if (!data)
2931 		return -ENOMEM;
2932 
2933 	info->ioapic_entry = &data->entry;
2934 	ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, info);
2935 	if (ret < 0) {
2936 		kfree(data);
2937 		return ret;
2938 	}
2939 
2940 	INIT_LIST_HEAD(&data->irq_2_pin);
2941 	irq_data->hwirq = info->ioapic_pin;
2942 	irq_data->chip = (domain->parent == x86_vector_domain) ?
2943 			  &ioapic_chip : &ioapic_ir_chip;
2944 	irq_data->chip_data = data;
2945 	mp_irqdomain_get_attr(mp_pin_to_gsi(ioapic, pin), data, info);
2946 
2947 	cfg = irqd_cfg(irq_data);
2948 	add_pin_to_irq_node(data, ioapic_alloc_attr_node(info), ioapic, pin);
2949 
2950 	local_irq_save(flags);
2951 	if (info->ioapic_entry)
2952 		mp_setup_entry(cfg, data, info->ioapic_entry);
2953 	mp_register_handler(virq, data->trigger);
2954 	if (virq < nr_legacy_irqs())
2955 		legacy_pic->mask(virq);
2956 	local_irq_restore(flags);
2957 
2958 	apic_printk(APIC_VERBOSE, KERN_DEBUG
2959 		    "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> IRQ %d Mode:%i Active:%i Dest:%d)\n",
2960 		    ioapic, mpc_ioapic_id(ioapic), pin, cfg->vector,
2961 		    virq, data->trigger, data->polarity, cfg->dest_apicid);
2962 
2963 	return 0;
2964 }
2965 
2966 void mp_irqdomain_free(struct irq_domain *domain, unsigned int virq,
2967 		       unsigned int nr_irqs)
2968 {
2969 	struct irq_data *irq_data;
2970 	struct mp_chip_data *data;
2971 
2972 	BUG_ON(nr_irqs != 1);
2973 	irq_data = irq_domain_get_irq_data(domain, virq);
2974 	if (irq_data && irq_data->chip_data) {
2975 		data = irq_data->chip_data;
2976 		__remove_pin_from_irq(data, mp_irqdomain_ioapic_idx(domain),
2977 				      (int)irq_data->hwirq);
2978 		WARN_ON(!list_empty(&data->irq_2_pin));
2979 		kfree(irq_data->chip_data);
2980 	}
2981 	irq_domain_free_irqs_top(domain, virq, nr_irqs);
2982 }
2983 
2984 void mp_irqdomain_activate(struct irq_domain *domain,
2985 			   struct irq_data *irq_data)
2986 {
2987 	unsigned long flags;
2988 	struct irq_pin_list *entry;
2989 	struct mp_chip_data *data = irq_data->chip_data;
2990 
2991 	raw_spin_lock_irqsave(&ioapic_lock, flags);
2992 	for_each_irq_pin(entry, data->irq_2_pin)
2993 		__ioapic_write_entry(entry->apic, entry->pin, data->entry);
2994 	raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2995 }
2996 
2997 void mp_irqdomain_deactivate(struct irq_domain *domain,
2998 			     struct irq_data *irq_data)
2999 {
3000 	/* It won't be called for IRQ with multiple IOAPIC pins associated */
3001 	ioapic_mask_entry(mp_irqdomain_ioapic_idx(domain),
3002 			  (int)irq_data->hwirq);
3003 }
3004 
3005 int mp_irqdomain_ioapic_idx(struct irq_domain *domain)
3006 {
3007 	return (int)(long)domain->host_data;
3008 }
3009 
3010 const struct irq_domain_ops mp_ioapic_irqdomain_ops = {
3011 	.alloc		= mp_irqdomain_alloc,
3012 	.free		= mp_irqdomain_free,
3013 	.activate	= mp_irqdomain_activate,
3014 	.deactivate	= mp_irqdomain_deactivate,
3015 };
3016