1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Numascale NumaConnect-Specific APIC Code 7 * 8 * Copyright (C) 2011 Numascale AS. All rights reserved. 9 * 10 * Send feedback to <support@numascale.com> 11 * 12 */ 13 14 #include <linux/errno.h> 15 #include <linux/threads.h> 16 #include <linux/cpumask.h> 17 #include <linux/string.h> 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/ctype.h> 21 #include <linux/init.h> 22 #include <linux/hardirq.h> 23 #include <linux/delay.h> 24 25 #include <asm/numachip/numachip_csr.h> 26 #include <asm/smp.h> 27 #include <asm/apic.h> 28 #include <asm/ipi.h> 29 #include <asm/apic_flat_64.h> 30 31 static int numachip_system __read_mostly; 32 33 static struct apic apic_numachip __read_mostly; 34 35 static unsigned int get_apic_id(unsigned long x) 36 { 37 unsigned long value; 38 unsigned int id; 39 40 rdmsrl(MSR_FAM10H_NODE_ID, value); 41 id = ((x >> 24) & 0xffU) | ((value << 2) & 0x3f00U); 42 43 return id; 44 } 45 46 static unsigned long set_apic_id(unsigned int id) 47 { 48 unsigned long x; 49 50 x = ((id & 0xffU) << 24); 51 return x; 52 } 53 54 static unsigned int read_xapic_id(void) 55 { 56 return get_apic_id(apic_read(APIC_ID)); 57 } 58 59 static int numachip_apic_id_valid(int apicid) 60 { 61 /* Trust what bootloader passes in MADT */ 62 return 1; 63 } 64 65 static int numachip_apic_id_registered(void) 66 { 67 return physid_isset(read_xapic_id(), phys_cpu_present_map); 68 } 69 70 static int numachip_phys_pkg_id(int initial_apic_id, int index_msb) 71 { 72 return initial_apic_id >> index_msb; 73 } 74 75 static const struct cpumask *numachip_target_cpus(void) 76 { 77 return cpu_online_mask; 78 } 79 80 static void numachip_vector_allocation_domain(int cpu, struct cpumask *retmask) 81 { 82 cpumask_clear(retmask); 83 cpumask_set_cpu(cpu, retmask); 84 } 85 86 static int __cpuinit numachip_wakeup_secondary(int phys_apicid, unsigned long start_rip) 87 { 88 union numachip_csr_g3_ext_irq_gen int_gen; 89 90 int_gen.s._destination_apic_id = phys_apicid; 91 int_gen.s._vector = 0; 92 int_gen.s._msgtype = APIC_DM_INIT >> 8; 93 int_gen.s._index = 0; 94 95 write_lcsr(CSR_G3_EXT_IRQ_GEN, int_gen.v); 96 97 int_gen.s._msgtype = APIC_DM_STARTUP >> 8; 98 int_gen.s._vector = start_rip >> 12; 99 100 write_lcsr(CSR_G3_EXT_IRQ_GEN, int_gen.v); 101 102 atomic_set(&init_deasserted, 1); 103 return 0; 104 } 105 106 static void numachip_send_IPI_one(int cpu, int vector) 107 { 108 union numachip_csr_g3_ext_irq_gen int_gen; 109 int apicid = per_cpu(x86_cpu_to_apicid, cpu); 110 111 int_gen.s._destination_apic_id = apicid; 112 int_gen.s._vector = vector; 113 int_gen.s._msgtype = (vector == NMI_VECTOR ? APIC_DM_NMI : APIC_DM_FIXED) >> 8; 114 int_gen.s._index = 0; 115 116 write_lcsr(CSR_G3_EXT_IRQ_GEN, int_gen.v); 117 } 118 119 static void numachip_send_IPI_mask(const struct cpumask *mask, int vector) 120 { 121 unsigned int cpu; 122 123 for_each_cpu(cpu, mask) 124 numachip_send_IPI_one(cpu, vector); 125 } 126 127 static void numachip_send_IPI_mask_allbutself(const struct cpumask *mask, 128 int vector) 129 { 130 unsigned int this_cpu = smp_processor_id(); 131 unsigned int cpu; 132 133 for_each_cpu(cpu, mask) { 134 if (cpu != this_cpu) 135 numachip_send_IPI_one(cpu, vector); 136 } 137 } 138 139 static void numachip_send_IPI_allbutself(int vector) 140 { 141 unsigned int this_cpu = smp_processor_id(); 142 unsigned int cpu; 143 144 for_each_online_cpu(cpu) { 145 if (cpu != this_cpu) 146 numachip_send_IPI_one(cpu, vector); 147 } 148 } 149 150 static void numachip_send_IPI_all(int vector) 151 { 152 numachip_send_IPI_mask(cpu_online_mask, vector); 153 } 154 155 static void numachip_send_IPI_self(int vector) 156 { 157 __default_send_IPI_shortcut(APIC_DEST_SELF, vector, APIC_DEST_PHYSICAL); 158 } 159 160 static unsigned int numachip_cpu_mask_to_apicid(const struct cpumask *cpumask) 161 { 162 int cpu; 163 164 /* 165 * We're using fixed IRQ delivery, can only return one phys APIC ID. 166 * May as well be the first. 167 */ 168 cpu = cpumask_first(cpumask); 169 if (likely((unsigned)cpu < nr_cpu_ids)) 170 return per_cpu(x86_cpu_to_apicid, cpu); 171 172 return BAD_APICID; 173 } 174 175 static unsigned int 176 numachip_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 177 const struct cpumask *andmask) 178 { 179 int cpu; 180 181 /* 182 * We're using fixed IRQ delivery, can only return one phys APIC ID. 183 * May as well be the first. 184 */ 185 for_each_cpu_and(cpu, cpumask, andmask) { 186 if (cpumask_test_cpu(cpu, cpu_online_mask)) 187 break; 188 } 189 return per_cpu(x86_cpu_to_apicid, cpu); 190 } 191 192 static int __init numachip_probe(void) 193 { 194 return apic == &apic_numachip; 195 } 196 197 static void __init map_csrs(void) 198 { 199 printk(KERN_INFO "NumaChip: Mapping local CSR space (%016llx - %016llx)\n", 200 NUMACHIP_LCSR_BASE, NUMACHIP_LCSR_BASE + NUMACHIP_LCSR_SIZE - 1); 201 init_extra_mapping_uc(NUMACHIP_LCSR_BASE, NUMACHIP_LCSR_SIZE); 202 203 printk(KERN_INFO "NumaChip: Mapping global CSR space (%016llx - %016llx)\n", 204 NUMACHIP_GCSR_BASE, NUMACHIP_GCSR_BASE + NUMACHIP_GCSR_SIZE - 1); 205 init_extra_mapping_uc(NUMACHIP_GCSR_BASE, NUMACHIP_GCSR_SIZE); 206 } 207 208 static void fixup_cpu_id(struct cpuinfo_x86 *c, int node) 209 { 210 211 if (c->phys_proc_id != node) { 212 c->phys_proc_id = node; 213 per_cpu(cpu_llc_id, smp_processor_id()) = node; 214 } 215 } 216 217 static int __init numachip_system_init(void) 218 { 219 unsigned int val; 220 221 if (!numachip_system) 222 return 0; 223 224 x86_cpuinit.fixup_cpu_id = fixup_cpu_id; 225 226 map_csrs(); 227 228 val = read_lcsr(CSR_G0_NODE_IDS); 229 printk(KERN_INFO "NumaChip: Local NodeID = %08x\n", val); 230 231 return 0; 232 } 233 early_initcall(numachip_system_init); 234 235 static int numachip_acpi_madt_oem_check(char *oem_id, char *oem_table_id) 236 { 237 if (!strncmp(oem_id, "NUMASC", 6)) { 238 numachip_system = 1; 239 return 1; 240 } 241 242 return 0; 243 } 244 245 static struct apic apic_numachip __refconst = { 246 247 .name = "NumaConnect system", 248 .probe = numachip_probe, 249 .acpi_madt_oem_check = numachip_acpi_madt_oem_check, 250 .apic_id_valid = numachip_apic_id_valid, 251 .apic_id_registered = numachip_apic_id_registered, 252 253 .irq_delivery_mode = dest_Fixed, 254 .irq_dest_mode = 0, /* physical */ 255 256 .target_cpus = numachip_target_cpus, 257 .disable_esr = 0, 258 .dest_logical = 0, 259 .check_apicid_used = NULL, 260 .check_apicid_present = NULL, 261 262 .vector_allocation_domain = numachip_vector_allocation_domain, 263 .init_apic_ldr = flat_init_apic_ldr, 264 265 .ioapic_phys_id_map = NULL, 266 .setup_apic_routing = NULL, 267 .multi_timer_check = NULL, 268 .cpu_present_to_apicid = default_cpu_present_to_apicid, 269 .apicid_to_cpu_present = NULL, 270 .setup_portio_remap = NULL, 271 .check_phys_apicid_present = default_check_phys_apicid_present, 272 .enable_apic_mode = NULL, 273 .phys_pkg_id = numachip_phys_pkg_id, 274 .mps_oem_check = NULL, 275 276 .get_apic_id = get_apic_id, 277 .set_apic_id = set_apic_id, 278 .apic_id_mask = 0xffU << 24, 279 280 .cpu_mask_to_apicid = numachip_cpu_mask_to_apicid, 281 .cpu_mask_to_apicid_and = numachip_cpu_mask_to_apicid_and, 282 283 .send_IPI_mask = numachip_send_IPI_mask, 284 .send_IPI_mask_allbutself = numachip_send_IPI_mask_allbutself, 285 .send_IPI_allbutself = numachip_send_IPI_allbutself, 286 .send_IPI_all = numachip_send_IPI_all, 287 .send_IPI_self = numachip_send_IPI_self, 288 289 .wakeup_secondary_cpu = numachip_wakeup_secondary, 290 .trampoline_phys_low = DEFAULT_TRAMPOLINE_PHYS_LOW, 291 .trampoline_phys_high = DEFAULT_TRAMPOLINE_PHYS_HIGH, 292 .wait_for_init_deassert = NULL, 293 .smp_callin_clear_local_apic = NULL, 294 .inquire_remote_apic = NULL, /* REMRD not supported */ 295 296 .read = native_apic_mem_read, 297 .write = native_apic_mem_write, 298 .icr_read = native_apic_icr_read, 299 .icr_write = native_apic_icr_write, 300 .wait_icr_idle = native_apic_wait_icr_idle, 301 .safe_wait_icr_idle = native_safe_apic_wait_icr_idle, 302 }; 303 apic_driver(apic_numachip); 304 305