1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Local APIC handling, local APIC timers 4 * 5 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * 7 * Fixes 8 * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 9 * thanks to Eric Gilmore 10 * and Rolf G. Tews 11 * for testing these extensively. 12 * Maciej W. Rozycki : Various updates and fixes. 13 * Mikael Pettersson : Power Management for UP-APIC. 14 * Pavel Machek and 15 * Mikael Pettersson : PM converted to driver model. 16 */ 17 18 #include <linux/perf_event.h> 19 #include <linux/kernel_stat.h> 20 #include <linux/mc146818rtc.h> 21 #include <linux/acpi_pmtmr.h> 22 #include <linux/clockchips.h> 23 #include <linux/interrupt.h> 24 #include <linux/memblock.h> 25 #include <linux/ftrace.h> 26 #include <linux/ioport.h> 27 #include <linux/export.h> 28 #include <linux/syscore_ops.h> 29 #include <linux/delay.h> 30 #include <linux/timex.h> 31 #include <linux/i8253.h> 32 #include <linux/dmar.h> 33 #include <linux/init.h> 34 #include <linux/cpu.h> 35 #include <linux/dmi.h> 36 #include <linux/smp.h> 37 #include <linux/mm.h> 38 39 #include <asm/trace/irq_vectors.h> 40 #include <asm/irq_remapping.h> 41 #include <asm/perf_event.h> 42 #include <asm/x86_init.h> 43 #include <asm/pgalloc.h> 44 #include <linux/atomic.h> 45 #include <asm/mpspec.h> 46 #include <asm/i8259.h> 47 #include <asm/proto.h> 48 #include <asm/traps.h> 49 #include <asm/apic.h> 50 #include <asm/io_apic.h> 51 #include <asm/desc.h> 52 #include <asm/hpet.h> 53 #include <asm/mtrr.h> 54 #include <asm/time.h> 55 #include <asm/smp.h> 56 #include <asm/mce.h> 57 #include <asm/tsc.h> 58 #include <asm/hypervisor.h> 59 #include <asm/cpu_device_id.h> 60 #include <asm/intel-family.h> 61 #include <asm/irq_regs.h> 62 63 unsigned int num_processors; 64 65 unsigned disabled_cpus; 66 67 /* Processor that is doing the boot up */ 68 unsigned int boot_cpu_physical_apicid = -1U; 69 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); 70 71 u8 boot_cpu_apic_version; 72 73 /* 74 * The highest APIC ID seen during enumeration. 75 */ 76 static unsigned int max_physical_apicid; 77 78 /* 79 * Bitmask of physically existing CPUs: 80 */ 81 physid_mask_t phys_cpu_present_map; 82 83 /* 84 * Processor to be disabled specified by kernel parameter 85 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to 86 * avoid undefined behaviour caused by sending INIT from AP to BSP. 87 */ 88 static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID; 89 90 /* 91 * This variable controls which CPUs receive external NMIs. By default, 92 * external NMIs are delivered only to the BSP. 93 */ 94 static int apic_extnmi = APIC_EXTNMI_BSP; 95 96 /* 97 * Map cpu index to physical APIC ID 98 */ 99 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); 100 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID); 101 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX); 102 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 103 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 104 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid); 105 106 #ifdef CONFIG_X86_32 107 108 /* 109 * On x86_32, the mapping between cpu and logical apicid may vary 110 * depending on apic in use. The following early percpu variable is 111 * used for the mapping. This is where the behaviors of x86_64 and 32 112 * actually diverge. Let's keep it ugly for now. 113 */ 114 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID); 115 116 /* Local APIC was disabled by the BIOS and enabled by the kernel */ 117 static int enabled_via_apicbase; 118 119 /* 120 * Handle interrupt mode configuration register (IMCR). 121 * This register controls whether the interrupt signals 122 * that reach the BSP come from the master PIC or from the 123 * local APIC. Before entering Symmetric I/O Mode, either 124 * the BIOS or the operating system must switch out of 125 * PIC Mode by changing the IMCR. 126 */ 127 static inline void imcr_pic_to_apic(void) 128 { 129 /* select IMCR register */ 130 outb(0x70, 0x22); 131 /* NMI and 8259 INTR go through APIC */ 132 outb(0x01, 0x23); 133 } 134 135 static inline void imcr_apic_to_pic(void) 136 { 137 /* select IMCR register */ 138 outb(0x70, 0x22); 139 /* NMI and 8259 INTR go directly to BSP */ 140 outb(0x00, 0x23); 141 } 142 #endif 143 144 /* 145 * Knob to control our willingness to enable the local APIC. 146 * 147 * +1=force-enable 148 */ 149 static int force_enable_local_apic __initdata; 150 151 /* 152 * APIC command line parameters 153 */ 154 static int __init parse_lapic(char *arg) 155 { 156 if (IS_ENABLED(CONFIG_X86_32) && !arg) 157 force_enable_local_apic = 1; 158 else if (arg && !strncmp(arg, "notscdeadline", 13)) 159 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 160 return 0; 161 } 162 early_param("lapic", parse_lapic); 163 164 #ifdef CONFIG_X86_64 165 static int apic_calibrate_pmtmr __initdata; 166 static __init int setup_apicpmtimer(char *s) 167 { 168 apic_calibrate_pmtmr = 1; 169 notsc_setup(NULL); 170 return 0; 171 } 172 __setup("apicpmtimer", setup_apicpmtimer); 173 #endif 174 175 unsigned long mp_lapic_addr; 176 int disable_apic; 177 /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 178 static int disable_apic_timer __initdata; 179 /* Local APIC timer works in C2 */ 180 int local_apic_timer_c2_ok; 181 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 182 183 /* 184 * Debug level, exported for io_apic.c 185 */ 186 unsigned int apic_verbosity; 187 188 int pic_mode; 189 190 /* Have we found an MP table */ 191 int smp_found_config; 192 193 static struct resource lapic_resource = { 194 .name = "Local APIC", 195 .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 196 }; 197 198 unsigned int lapic_timer_frequency = 0; 199 200 static void apic_pm_activate(void); 201 202 static unsigned long apic_phys; 203 204 /* 205 * Get the LAPIC version 206 */ 207 static inline int lapic_get_version(void) 208 { 209 return GET_APIC_VERSION(apic_read(APIC_LVR)); 210 } 211 212 /* 213 * Check, if the APIC is integrated or a separate chip 214 */ 215 static inline int lapic_is_integrated(void) 216 { 217 return APIC_INTEGRATED(lapic_get_version()); 218 } 219 220 /* 221 * Check, whether this is a modern or a first generation APIC 222 */ 223 static int modern_apic(void) 224 { 225 /* AMD systems use old APIC versions, so check the CPU */ 226 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 227 boot_cpu_data.x86 >= 0xf) 228 return 1; 229 230 /* Hygon systems use modern APIC */ 231 if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 232 return 1; 233 234 return lapic_get_version() >= 0x14; 235 } 236 237 /* 238 * right after this call apic become NOOP driven 239 * so apic->write/read doesn't do anything 240 */ 241 static void __init apic_disable(void) 242 { 243 pr_info("APIC: switched to apic NOOP\n"); 244 apic = &apic_noop; 245 } 246 247 void native_apic_wait_icr_idle(void) 248 { 249 while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 250 cpu_relax(); 251 } 252 253 u32 native_safe_apic_wait_icr_idle(void) 254 { 255 u32 send_status; 256 int timeout; 257 258 timeout = 0; 259 do { 260 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 261 if (!send_status) 262 break; 263 inc_irq_stat(icr_read_retry_count); 264 udelay(100); 265 } while (timeout++ < 1000); 266 267 return send_status; 268 } 269 270 void native_apic_icr_write(u32 low, u32 id) 271 { 272 unsigned long flags; 273 274 local_irq_save(flags); 275 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 276 apic_write(APIC_ICR, low); 277 local_irq_restore(flags); 278 } 279 280 u64 native_apic_icr_read(void) 281 { 282 u32 icr1, icr2; 283 284 icr2 = apic_read(APIC_ICR2); 285 icr1 = apic_read(APIC_ICR); 286 287 return icr1 | ((u64)icr2 << 32); 288 } 289 290 #ifdef CONFIG_X86_32 291 /** 292 * get_physical_broadcast - Get number of physical broadcast IDs 293 */ 294 int get_physical_broadcast(void) 295 { 296 return modern_apic() ? 0xff : 0xf; 297 } 298 #endif 299 300 /** 301 * lapic_get_maxlvt - get the maximum number of local vector table entries 302 */ 303 int lapic_get_maxlvt(void) 304 { 305 /* 306 * - we always have APIC integrated on 64bit mode 307 * - 82489DXs do not report # of LVT entries 308 */ 309 return lapic_is_integrated() ? GET_APIC_MAXLVT(apic_read(APIC_LVR)) : 2; 310 } 311 312 /* 313 * Local APIC timer 314 */ 315 316 /* Clock divisor */ 317 #define APIC_DIVISOR 16 318 #define TSC_DIVISOR 8 319 320 /* 321 * This function sets up the local APIC timer, with a timeout of 322 * 'clocks' APIC bus clock. During calibration we actually call 323 * this function twice on the boot CPU, once with a bogus timeout 324 * value, second time for real. The other (noncalibrating) CPUs 325 * call this function only once, with the real, calibrated value. 326 * 327 * We do reads before writes even if unnecessary, to get around the 328 * P5 APIC double write bug. 329 */ 330 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 331 { 332 unsigned int lvtt_value, tmp_value; 333 334 lvtt_value = LOCAL_TIMER_VECTOR; 335 if (!oneshot) 336 lvtt_value |= APIC_LVT_TIMER_PERIODIC; 337 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 338 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE; 339 340 if (!lapic_is_integrated()) 341 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 342 343 if (!irqen) 344 lvtt_value |= APIC_LVT_MASKED; 345 346 apic_write(APIC_LVTT, lvtt_value); 347 348 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { 349 /* 350 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, 351 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized. 352 * According to Intel, MFENCE can do the serialization here. 353 */ 354 asm volatile("mfence" : : : "memory"); 355 356 printk_once(KERN_DEBUG "TSC deadline timer enabled\n"); 357 return; 358 } 359 360 /* 361 * Divide PICLK by 16 362 */ 363 tmp_value = apic_read(APIC_TDCR); 364 apic_write(APIC_TDCR, 365 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 366 APIC_TDR_DIV_16); 367 368 if (!oneshot) 369 apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 370 } 371 372 /* 373 * Setup extended LVT, AMD specific 374 * 375 * Software should use the LVT offsets the BIOS provides. The offsets 376 * are determined by the subsystems using it like those for MCE 377 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts 378 * are supported. Beginning with family 10h at least 4 offsets are 379 * available. 380 * 381 * Since the offsets must be consistent for all cores, we keep track 382 * of the LVT offsets in software and reserve the offset for the same 383 * vector also to be used on other cores. An offset is freed by 384 * setting the entry to APIC_EILVT_MASKED. 385 * 386 * If the BIOS is right, there should be no conflicts. Otherwise a 387 * "[Firmware Bug]: ..." error message is generated. However, if 388 * software does not properly determines the offsets, it is not 389 * necessarily a BIOS bug. 390 */ 391 392 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; 393 394 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) 395 { 396 return (old & APIC_EILVT_MASKED) 397 || (new == APIC_EILVT_MASKED) 398 || ((new & ~APIC_EILVT_MASKED) == old); 399 } 400 401 static unsigned int reserve_eilvt_offset(int offset, unsigned int new) 402 { 403 unsigned int rsvd, vector; 404 405 if (offset >= APIC_EILVT_NR_MAX) 406 return ~0; 407 408 rsvd = atomic_read(&eilvt_offsets[offset]); 409 do { 410 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ 411 if (vector && !eilvt_entry_is_changeable(vector, new)) 412 /* may not change if vectors are different */ 413 return rsvd; 414 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); 415 } while (rsvd != new); 416 417 rsvd &= ~APIC_EILVT_MASKED; 418 if (rsvd && rsvd != vector) 419 pr_info("LVT offset %d assigned for vector 0x%02x\n", 420 offset, rsvd); 421 422 return new; 423 } 424 425 /* 426 * If mask=1, the LVT entry does not generate interrupts while mask=0 427 * enables the vector. See also the BKDGs. Must be called with 428 * preemption disabled. 429 */ 430 431 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) 432 { 433 unsigned long reg = APIC_EILVTn(offset); 434 unsigned int new, old, reserved; 435 436 new = (mask << 16) | (msg_type << 8) | vector; 437 old = apic_read(reg); 438 reserved = reserve_eilvt_offset(offset, new); 439 440 if (reserved != new) { 441 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 442 "vector 0x%x, but the register is already in use for " 443 "vector 0x%x on another cpu\n", 444 smp_processor_id(), reg, offset, new, reserved); 445 return -EINVAL; 446 } 447 448 if (!eilvt_entry_is_changeable(old, new)) { 449 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 450 "vector 0x%x, but the register is already in use for " 451 "vector 0x%x on this cpu\n", 452 smp_processor_id(), reg, offset, new, old); 453 return -EBUSY; 454 } 455 456 apic_write(reg, new); 457 458 return 0; 459 } 460 EXPORT_SYMBOL_GPL(setup_APIC_eilvt); 461 462 /* 463 * Program the next event, relative to now 464 */ 465 static int lapic_next_event(unsigned long delta, 466 struct clock_event_device *evt) 467 { 468 apic_write(APIC_TMICT, delta); 469 return 0; 470 } 471 472 static int lapic_next_deadline(unsigned long delta, 473 struct clock_event_device *evt) 474 { 475 u64 tsc; 476 477 tsc = rdtsc(); 478 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); 479 return 0; 480 } 481 482 static int lapic_timer_shutdown(struct clock_event_device *evt) 483 { 484 unsigned int v; 485 486 /* Lapic used as dummy for broadcast ? */ 487 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 488 return 0; 489 490 v = apic_read(APIC_LVTT); 491 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 492 apic_write(APIC_LVTT, v); 493 apic_write(APIC_TMICT, 0); 494 return 0; 495 } 496 497 static inline int 498 lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot) 499 { 500 /* Lapic used as dummy for broadcast ? */ 501 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 502 return 0; 503 504 __setup_APIC_LVTT(lapic_timer_frequency, oneshot, 1); 505 return 0; 506 } 507 508 static int lapic_timer_set_periodic(struct clock_event_device *evt) 509 { 510 return lapic_timer_set_periodic_oneshot(evt, false); 511 } 512 513 static int lapic_timer_set_oneshot(struct clock_event_device *evt) 514 { 515 return lapic_timer_set_periodic_oneshot(evt, true); 516 } 517 518 /* 519 * Local APIC timer broadcast function 520 */ 521 static void lapic_timer_broadcast(const struct cpumask *mask) 522 { 523 #ifdef CONFIG_SMP 524 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 525 #endif 526 } 527 528 529 /* 530 * The local apic timer can be used for any function which is CPU local. 531 */ 532 static struct clock_event_device lapic_clockevent = { 533 .name = "lapic", 534 .features = CLOCK_EVT_FEAT_PERIODIC | 535 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP 536 | CLOCK_EVT_FEAT_DUMMY, 537 .shift = 32, 538 .set_state_shutdown = lapic_timer_shutdown, 539 .set_state_periodic = lapic_timer_set_periodic, 540 .set_state_oneshot = lapic_timer_set_oneshot, 541 .set_state_oneshot_stopped = lapic_timer_shutdown, 542 .set_next_event = lapic_next_event, 543 .broadcast = lapic_timer_broadcast, 544 .rating = 100, 545 .irq = -1, 546 }; 547 static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 548 549 #define DEADLINE_MODEL_MATCH_FUNC(model, func) \ 550 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&func } 551 552 #define DEADLINE_MODEL_MATCH_REV(model, rev) \ 553 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)rev } 554 555 static u32 hsx_deadline_rev(void) 556 { 557 switch (boot_cpu_data.x86_stepping) { 558 case 0x02: return 0x3a; /* EP */ 559 case 0x04: return 0x0f; /* EX */ 560 } 561 562 return ~0U; 563 } 564 565 static u32 bdx_deadline_rev(void) 566 { 567 switch (boot_cpu_data.x86_stepping) { 568 case 0x02: return 0x00000011; 569 case 0x03: return 0x0700000e; 570 case 0x04: return 0x0f00000c; 571 case 0x05: return 0x0e000003; 572 } 573 574 return ~0U; 575 } 576 577 static u32 skx_deadline_rev(void) 578 { 579 switch (boot_cpu_data.x86_stepping) { 580 case 0x03: return 0x01000136; 581 case 0x04: return 0x02000014; 582 } 583 584 if (boot_cpu_data.x86_stepping > 4) 585 return 0; 586 587 return ~0U; 588 } 589 590 static const struct x86_cpu_id deadline_match[] = { 591 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_HASWELL_X, hsx_deadline_rev), 592 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_X, 0x0b000020), 593 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_BROADWELL_XEON_D, bdx_deadline_rev), 594 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_SKYLAKE_X, skx_deadline_rev), 595 596 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_CORE, 0x22), 597 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_ULT, 0x20), 598 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_GT3E, 0x17), 599 600 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_CORE, 0x25), 601 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_GT3E, 0x17), 602 603 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_MOBILE, 0xb2), 604 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_DESKTOP, 0xb2), 605 606 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_MOBILE, 0x52), 607 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_DESKTOP, 0x52), 608 609 {}, 610 }; 611 612 static void apic_check_deadline_errata(void) 613 { 614 const struct x86_cpu_id *m; 615 u32 rev; 616 617 if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER) || 618 boot_cpu_has(X86_FEATURE_HYPERVISOR)) 619 return; 620 621 m = x86_match_cpu(deadline_match); 622 if (!m) 623 return; 624 625 /* 626 * Function pointers will have the MSB set due to address layout, 627 * immediate revisions will not. 628 */ 629 if ((long)m->driver_data < 0) 630 rev = ((u32 (*)(void))(m->driver_data))(); 631 else 632 rev = (u32)m->driver_data; 633 634 if (boot_cpu_data.microcode >= rev) 635 return; 636 637 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 638 pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; " 639 "please update microcode to version: 0x%x (or later)\n", rev); 640 } 641 642 /* 643 * Setup the local APIC timer for this CPU. Copy the initialized values 644 * of the boot CPU and register the clock event in the framework. 645 */ 646 static void setup_APIC_timer(void) 647 { 648 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 649 650 if (this_cpu_has(X86_FEATURE_ARAT)) { 651 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 652 /* Make LAPIC timer preferrable over percpu HPET */ 653 lapic_clockevent.rating = 150; 654 } 655 656 memcpy(levt, &lapic_clockevent, sizeof(*levt)); 657 levt->cpumask = cpumask_of(smp_processor_id()); 658 659 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 660 levt->name = "lapic-deadline"; 661 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | 662 CLOCK_EVT_FEAT_DUMMY); 663 levt->set_next_event = lapic_next_deadline; 664 clockevents_config_and_register(levt, 665 tsc_khz * (1000 / TSC_DIVISOR), 666 0xF, ~0UL); 667 } else 668 clockevents_register_device(levt); 669 } 670 671 /* 672 * Install the updated TSC frequency from recalibration at the TSC 673 * deadline clockevent devices. 674 */ 675 static void __lapic_update_tsc_freq(void *info) 676 { 677 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 678 679 if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 680 return; 681 682 clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR)); 683 } 684 685 void lapic_update_tsc_freq(void) 686 { 687 /* 688 * The clockevent device's ->mult and ->shift can both be 689 * changed. In order to avoid races, schedule the frequency 690 * update code on each CPU. 691 */ 692 on_each_cpu(__lapic_update_tsc_freq, NULL, 0); 693 } 694 695 /* 696 * In this functions we calibrate APIC bus clocks to the external timer. 697 * 698 * We want to do the calibration only once since we want to have local timer 699 * irqs syncron. CPUs connected by the same APIC bus have the very same bus 700 * frequency. 701 * 702 * This was previously done by reading the PIT/HPET and waiting for a wrap 703 * around to find out, that a tick has elapsed. I have a box, where the PIT 704 * readout is broken, so it never gets out of the wait loop again. This was 705 * also reported by others. 706 * 707 * Monitoring the jiffies value is inaccurate and the clockevents 708 * infrastructure allows us to do a simple substitution of the interrupt 709 * handler. 710 * 711 * The calibration routine also uses the pm_timer when possible, as the PIT 712 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 713 * back to normal later in the boot process). 714 */ 715 716 #define LAPIC_CAL_LOOPS (HZ/10) 717 718 static __initdata int lapic_cal_loops = -1; 719 static __initdata long lapic_cal_t1, lapic_cal_t2; 720 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 721 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 722 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 723 724 /* 725 * Temporary interrupt handler. 726 */ 727 static void __init lapic_cal_handler(struct clock_event_device *dev) 728 { 729 unsigned long long tsc = 0; 730 long tapic = apic_read(APIC_TMCCT); 731 unsigned long pm = acpi_pm_read_early(); 732 733 if (boot_cpu_has(X86_FEATURE_TSC)) 734 tsc = rdtsc(); 735 736 switch (lapic_cal_loops++) { 737 case 0: 738 lapic_cal_t1 = tapic; 739 lapic_cal_tsc1 = tsc; 740 lapic_cal_pm1 = pm; 741 lapic_cal_j1 = jiffies; 742 break; 743 744 case LAPIC_CAL_LOOPS: 745 lapic_cal_t2 = tapic; 746 lapic_cal_tsc2 = tsc; 747 if (pm < lapic_cal_pm1) 748 pm += ACPI_PM_OVRRUN; 749 lapic_cal_pm2 = pm; 750 lapic_cal_j2 = jiffies; 751 break; 752 } 753 } 754 755 static int __init 756 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 757 { 758 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 759 const long pm_thresh = pm_100ms / 100; 760 unsigned long mult; 761 u64 res; 762 763 #ifndef CONFIG_X86_PM_TIMER 764 return -1; 765 #endif 766 767 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 768 769 /* Check, if the PM timer is available */ 770 if (!deltapm) 771 return -1; 772 773 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 774 775 if (deltapm > (pm_100ms - pm_thresh) && 776 deltapm < (pm_100ms + pm_thresh)) { 777 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 778 return 0; 779 } 780 781 res = (((u64)deltapm) * mult) >> 22; 782 do_div(res, 1000000); 783 pr_warning("APIC calibration not consistent " 784 "with PM-Timer: %ldms instead of 100ms\n",(long)res); 785 786 /* Correct the lapic counter value */ 787 res = (((u64)(*delta)) * pm_100ms); 788 do_div(res, deltapm); 789 pr_info("APIC delta adjusted to PM-Timer: " 790 "%lu (%ld)\n", (unsigned long)res, *delta); 791 *delta = (long)res; 792 793 /* Correct the tsc counter value */ 794 if (boot_cpu_has(X86_FEATURE_TSC)) { 795 res = (((u64)(*deltatsc)) * pm_100ms); 796 do_div(res, deltapm); 797 apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 798 "PM-Timer: %lu (%ld)\n", 799 (unsigned long)res, *deltatsc); 800 *deltatsc = (long)res; 801 } 802 803 return 0; 804 } 805 806 static int __init lapic_init_clockevent(void) 807 { 808 if (!lapic_timer_frequency) 809 return -1; 810 811 /* Calculate the scaled math multiplication factor */ 812 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR, 813 TICK_NSEC, lapic_clockevent.shift); 814 lapic_clockevent.max_delta_ns = 815 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); 816 lapic_clockevent.max_delta_ticks = 0x7FFFFFFF; 817 lapic_clockevent.min_delta_ns = 818 clockevent_delta2ns(0xF, &lapic_clockevent); 819 lapic_clockevent.min_delta_ticks = 0xF; 820 821 return 0; 822 } 823 824 static int __init calibrate_APIC_clock(void) 825 { 826 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 827 void (*real_handler)(struct clock_event_device *dev); 828 unsigned long deltaj; 829 long delta, deltatsc; 830 int pm_referenced = 0; 831 832 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 833 return 0; 834 835 /* 836 * Check if lapic timer has already been calibrated by platform 837 * specific routine, such as tsc calibration code. If so just fill 838 * in the clockevent structure and return. 839 */ 840 if (!lapic_init_clockevent()) { 841 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", 842 lapic_timer_frequency); 843 /* 844 * Direct calibration methods must have an always running 845 * local APIC timer, no need for broadcast timer. 846 */ 847 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 848 return 0; 849 } 850 851 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 852 "calibrating APIC timer ...\n"); 853 854 local_irq_disable(); 855 856 /* Replace the global interrupt handler */ 857 real_handler = global_clock_event->event_handler; 858 global_clock_event->event_handler = lapic_cal_handler; 859 860 /* 861 * Setup the APIC counter to maximum. There is no way the lapic 862 * can underflow in the 100ms detection time frame 863 */ 864 __setup_APIC_LVTT(0xffffffff, 0, 0); 865 866 /* Let the interrupts run */ 867 local_irq_enable(); 868 869 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 870 cpu_relax(); 871 872 local_irq_disable(); 873 874 /* Restore the real event handler */ 875 global_clock_event->event_handler = real_handler; 876 877 /* Build delta t1-t2 as apic timer counts down */ 878 delta = lapic_cal_t1 - lapic_cal_t2; 879 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 880 881 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 882 883 /* we trust the PM based calibration if possible */ 884 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 885 &delta, &deltatsc); 886 887 lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 888 lapic_init_clockevent(); 889 890 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 891 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); 892 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 893 lapic_timer_frequency); 894 895 if (boot_cpu_has(X86_FEATURE_TSC)) { 896 apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 897 "%ld.%04ld MHz.\n", 898 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 899 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 900 } 901 902 apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 903 "%u.%04u MHz.\n", 904 lapic_timer_frequency / (1000000 / HZ), 905 lapic_timer_frequency % (1000000 / HZ)); 906 907 /* 908 * Do a sanity check on the APIC calibration result 909 */ 910 if (lapic_timer_frequency < (1000000 / HZ)) { 911 local_irq_enable(); 912 pr_warning("APIC frequency too slow, disabling apic timer\n"); 913 return -1; 914 } 915 916 levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 917 918 /* 919 * PM timer calibration failed or not turned on 920 * so lets try APIC timer based calibration 921 */ 922 if (!pm_referenced) { 923 apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 924 925 /* 926 * Setup the apic timer manually 927 */ 928 levt->event_handler = lapic_cal_handler; 929 lapic_timer_set_periodic(levt); 930 lapic_cal_loops = -1; 931 932 /* Let the interrupts run */ 933 local_irq_enable(); 934 935 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 936 cpu_relax(); 937 938 /* Stop the lapic timer */ 939 local_irq_disable(); 940 lapic_timer_shutdown(levt); 941 942 /* Jiffies delta */ 943 deltaj = lapic_cal_j2 - lapic_cal_j1; 944 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 945 946 /* Check, if the jiffies result is consistent */ 947 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 948 apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 949 else 950 levt->features |= CLOCK_EVT_FEAT_DUMMY; 951 } 952 local_irq_enable(); 953 954 if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 955 pr_warning("APIC timer disabled due to verification failure\n"); 956 return -1; 957 } 958 959 return 0; 960 } 961 962 /* 963 * Setup the boot APIC 964 * 965 * Calibrate and verify the result. 966 */ 967 void __init setup_boot_APIC_clock(void) 968 { 969 /* 970 * The local apic timer can be disabled via the kernel 971 * commandline or from the CPU detection code. Register the lapic 972 * timer as a dummy clock event source on SMP systems, so the 973 * broadcast mechanism is used. On UP systems simply ignore it. 974 */ 975 if (disable_apic_timer) { 976 pr_info("Disabling APIC timer\n"); 977 /* No broadcast on UP ! */ 978 if (num_possible_cpus() > 1) { 979 lapic_clockevent.mult = 1; 980 setup_APIC_timer(); 981 } 982 return; 983 } 984 985 if (calibrate_APIC_clock()) { 986 /* No broadcast on UP ! */ 987 if (num_possible_cpus() > 1) 988 setup_APIC_timer(); 989 return; 990 } 991 992 /* 993 * If nmi_watchdog is set to IO_APIC, we need the 994 * PIT/HPET going. Otherwise register lapic as a dummy 995 * device. 996 */ 997 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 998 999 /* Setup the lapic or request the broadcast */ 1000 setup_APIC_timer(); 1001 amd_e400_c1e_apic_setup(); 1002 } 1003 1004 void setup_secondary_APIC_clock(void) 1005 { 1006 setup_APIC_timer(); 1007 amd_e400_c1e_apic_setup(); 1008 } 1009 1010 /* 1011 * The guts of the apic timer interrupt 1012 */ 1013 static void local_apic_timer_interrupt(void) 1014 { 1015 struct clock_event_device *evt = this_cpu_ptr(&lapic_events); 1016 1017 /* 1018 * Normally we should not be here till LAPIC has been initialized but 1019 * in some cases like kdump, its possible that there is a pending LAPIC 1020 * timer interrupt from previous kernel's context and is delivered in 1021 * new kernel the moment interrupts are enabled. 1022 * 1023 * Interrupts are enabled early and LAPIC is setup much later, hence 1024 * its possible that when we get here evt->event_handler is NULL. 1025 * Check for event_handler being NULL and discard the interrupt as 1026 * spurious. 1027 */ 1028 if (!evt->event_handler) { 1029 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", 1030 smp_processor_id()); 1031 /* Switch it off */ 1032 lapic_timer_shutdown(evt); 1033 return; 1034 } 1035 1036 /* 1037 * the NMI deadlock-detector uses this. 1038 */ 1039 inc_irq_stat(apic_timer_irqs); 1040 1041 evt->event_handler(evt); 1042 } 1043 1044 /* 1045 * Local APIC timer interrupt. This is the most natural way for doing 1046 * local interrupts, but local timer interrupts can be emulated by 1047 * broadcast interrupts too. [in case the hw doesn't support APIC timers] 1048 * 1049 * [ if a single-CPU system runs an SMP kernel then we call the local 1050 * interrupt as well. Thus we cannot inline the local irq ... ] 1051 */ 1052 __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) 1053 { 1054 struct pt_regs *old_regs = set_irq_regs(regs); 1055 1056 /* 1057 * NOTE! We'd better ACK the irq immediately, 1058 * because timer handling can be slow. 1059 * 1060 * update_process_times() expects us to have done irq_enter(). 1061 * Besides, if we don't timer interrupts ignore the global 1062 * interrupt lock, which is the WrongThing (tm) to do. 1063 */ 1064 entering_ack_irq(); 1065 trace_local_timer_entry(LOCAL_TIMER_VECTOR); 1066 local_apic_timer_interrupt(); 1067 trace_local_timer_exit(LOCAL_TIMER_VECTOR); 1068 exiting_irq(); 1069 1070 set_irq_regs(old_regs); 1071 } 1072 1073 int setup_profiling_timer(unsigned int multiplier) 1074 { 1075 return -EINVAL; 1076 } 1077 1078 /* 1079 * Local APIC start and shutdown 1080 */ 1081 1082 /** 1083 * clear_local_APIC - shutdown the local APIC 1084 * 1085 * This is called, when a CPU is disabled and before rebooting, so the state of 1086 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 1087 * leftovers during boot. 1088 */ 1089 void clear_local_APIC(void) 1090 { 1091 int maxlvt; 1092 u32 v; 1093 1094 /* APIC hasn't been mapped yet */ 1095 if (!x2apic_mode && !apic_phys) 1096 return; 1097 1098 maxlvt = lapic_get_maxlvt(); 1099 /* 1100 * Masking an LVT entry can trigger a local APIC error 1101 * if the vector is zero. Mask LVTERR first to prevent this. 1102 */ 1103 if (maxlvt >= 3) { 1104 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 1105 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 1106 } 1107 /* 1108 * Careful: we have to set masks only first to deassert 1109 * any level-triggered sources. 1110 */ 1111 v = apic_read(APIC_LVTT); 1112 apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 1113 v = apic_read(APIC_LVT0); 1114 apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 1115 v = apic_read(APIC_LVT1); 1116 apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 1117 if (maxlvt >= 4) { 1118 v = apic_read(APIC_LVTPC); 1119 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 1120 } 1121 1122 /* lets not touch this if we didn't frob it */ 1123 #ifdef CONFIG_X86_THERMAL_VECTOR 1124 if (maxlvt >= 5) { 1125 v = apic_read(APIC_LVTTHMR); 1126 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 1127 } 1128 #endif 1129 #ifdef CONFIG_X86_MCE_INTEL 1130 if (maxlvt >= 6) { 1131 v = apic_read(APIC_LVTCMCI); 1132 if (!(v & APIC_LVT_MASKED)) 1133 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 1134 } 1135 #endif 1136 1137 /* 1138 * Clean APIC state for other OSs: 1139 */ 1140 apic_write(APIC_LVTT, APIC_LVT_MASKED); 1141 apic_write(APIC_LVT0, APIC_LVT_MASKED); 1142 apic_write(APIC_LVT1, APIC_LVT_MASKED); 1143 if (maxlvt >= 3) 1144 apic_write(APIC_LVTERR, APIC_LVT_MASKED); 1145 if (maxlvt >= 4) 1146 apic_write(APIC_LVTPC, APIC_LVT_MASKED); 1147 1148 /* Integrated APIC (!82489DX) ? */ 1149 if (lapic_is_integrated()) { 1150 if (maxlvt > 3) 1151 /* Clear ESR due to Pentium errata 3AP and 11AP */ 1152 apic_write(APIC_ESR, 0); 1153 apic_read(APIC_ESR); 1154 } 1155 } 1156 1157 /** 1158 * disable_local_APIC - clear and disable the local APIC 1159 */ 1160 void disable_local_APIC(void) 1161 { 1162 unsigned int value; 1163 1164 /* APIC hasn't been mapped yet */ 1165 if (!x2apic_mode && !apic_phys) 1166 return; 1167 1168 clear_local_APIC(); 1169 1170 /* 1171 * Disable APIC (implies clearing of registers 1172 * for 82489DX!). 1173 */ 1174 value = apic_read(APIC_SPIV); 1175 value &= ~APIC_SPIV_APIC_ENABLED; 1176 apic_write(APIC_SPIV, value); 1177 1178 #ifdef CONFIG_X86_32 1179 /* 1180 * When LAPIC was disabled by the BIOS and enabled by the kernel, 1181 * restore the disabled state. 1182 */ 1183 if (enabled_via_apicbase) { 1184 unsigned int l, h; 1185 1186 rdmsr(MSR_IA32_APICBASE, l, h); 1187 l &= ~MSR_IA32_APICBASE_ENABLE; 1188 wrmsr(MSR_IA32_APICBASE, l, h); 1189 } 1190 #endif 1191 } 1192 1193 /* 1194 * If Linux enabled the LAPIC against the BIOS default disable it down before 1195 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 1196 * not power-off. Additionally clear all LVT entries before disable_local_APIC 1197 * for the case where Linux didn't enable the LAPIC. 1198 */ 1199 void lapic_shutdown(void) 1200 { 1201 unsigned long flags; 1202 1203 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) 1204 return; 1205 1206 local_irq_save(flags); 1207 1208 #ifdef CONFIG_X86_32 1209 if (!enabled_via_apicbase) 1210 clear_local_APIC(); 1211 else 1212 #endif 1213 disable_local_APIC(); 1214 1215 1216 local_irq_restore(flags); 1217 } 1218 1219 /** 1220 * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1221 */ 1222 void __init sync_Arb_IDs(void) 1223 { 1224 /* 1225 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1226 * needed on AMD. 1227 */ 1228 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1229 return; 1230 1231 /* 1232 * Wait for idle. 1233 */ 1234 apic_wait_icr_idle(); 1235 1236 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1237 apic_write(APIC_ICR, APIC_DEST_ALLINC | 1238 APIC_INT_LEVELTRIG | APIC_DM_INIT); 1239 } 1240 1241 enum apic_intr_mode_id apic_intr_mode; 1242 1243 static int __init apic_intr_mode_select(void) 1244 { 1245 /* Check kernel option */ 1246 if (disable_apic) { 1247 pr_info("APIC disabled via kernel command line\n"); 1248 return APIC_PIC; 1249 } 1250 1251 /* Check BIOS */ 1252 #ifdef CONFIG_X86_64 1253 /* On 64-bit, the APIC must be integrated, Check local APIC only */ 1254 if (!boot_cpu_has(X86_FEATURE_APIC)) { 1255 disable_apic = 1; 1256 pr_info("APIC disabled by BIOS\n"); 1257 return APIC_PIC; 1258 } 1259 #else 1260 /* On 32-bit, the APIC may be integrated APIC or 82489DX */ 1261 1262 /* Neither 82489DX nor integrated APIC ? */ 1263 if (!boot_cpu_has(X86_FEATURE_APIC) && !smp_found_config) { 1264 disable_apic = 1; 1265 return APIC_PIC; 1266 } 1267 1268 /* If the BIOS pretends there is an integrated APIC ? */ 1269 if (!boot_cpu_has(X86_FEATURE_APIC) && 1270 APIC_INTEGRATED(boot_cpu_apic_version)) { 1271 disable_apic = 1; 1272 pr_err(FW_BUG "Local APIC %d not detected, force emulation\n", 1273 boot_cpu_physical_apicid); 1274 return APIC_PIC; 1275 } 1276 #endif 1277 1278 /* Check MP table or ACPI MADT configuration */ 1279 if (!smp_found_config) { 1280 disable_ioapic_support(); 1281 if (!acpi_lapic) { 1282 pr_info("APIC: ACPI MADT or MP tables are not detected\n"); 1283 return APIC_VIRTUAL_WIRE_NO_CONFIG; 1284 } 1285 return APIC_VIRTUAL_WIRE; 1286 } 1287 1288 #ifdef CONFIG_SMP 1289 /* If SMP should be disabled, then really disable it! */ 1290 if (!setup_max_cpus) { 1291 pr_info("APIC: SMP mode deactivated\n"); 1292 return APIC_SYMMETRIC_IO_NO_ROUTING; 1293 } 1294 1295 if (read_apic_id() != boot_cpu_physical_apicid) { 1296 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1297 read_apic_id(), boot_cpu_physical_apicid); 1298 /* Or can we switch back to PIC here? */ 1299 } 1300 #endif 1301 1302 return APIC_SYMMETRIC_IO; 1303 } 1304 1305 /* 1306 * An initial setup of the virtual wire mode. 1307 */ 1308 void __init init_bsp_APIC(void) 1309 { 1310 unsigned int value; 1311 1312 /* 1313 * Don't do the setup now if we have a SMP BIOS as the 1314 * through-I/O-APIC virtual wire mode might be active. 1315 */ 1316 if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC)) 1317 return; 1318 1319 /* 1320 * Do not trust the local APIC being empty at bootup. 1321 */ 1322 clear_local_APIC(); 1323 1324 /* 1325 * Enable APIC. 1326 */ 1327 value = apic_read(APIC_SPIV); 1328 value &= ~APIC_VECTOR_MASK; 1329 value |= APIC_SPIV_APIC_ENABLED; 1330 1331 #ifdef CONFIG_X86_32 1332 /* This bit is reserved on P4/Xeon and should be cleared */ 1333 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1334 (boot_cpu_data.x86 == 15)) 1335 value &= ~APIC_SPIV_FOCUS_DISABLED; 1336 else 1337 #endif 1338 value |= APIC_SPIV_FOCUS_DISABLED; 1339 value |= SPURIOUS_APIC_VECTOR; 1340 apic_write(APIC_SPIV, value); 1341 1342 /* 1343 * Set up the virtual wire mode. 1344 */ 1345 apic_write(APIC_LVT0, APIC_DM_EXTINT); 1346 value = APIC_DM_NMI; 1347 if (!lapic_is_integrated()) /* 82489DX */ 1348 value |= APIC_LVT_LEVEL_TRIGGER; 1349 if (apic_extnmi == APIC_EXTNMI_NONE) 1350 value |= APIC_LVT_MASKED; 1351 apic_write(APIC_LVT1, value); 1352 } 1353 1354 /* Init the interrupt delivery mode for the BSP */ 1355 void __init apic_intr_mode_init(void) 1356 { 1357 bool upmode = IS_ENABLED(CONFIG_UP_LATE_INIT); 1358 1359 apic_intr_mode = apic_intr_mode_select(); 1360 1361 switch (apic_intr_mode) { 1362 case APIC_PIC: 1363 pr_info("APIC: Keep in PIC mode(8259)\n"); 1364 return; 1365 case APIC_VIRTUAL_WIRE: 1366 pr_info("APIC: Switch to virtual wire mode setup\n"); 1367 default_setup_apic_routing(); 1368 break; 1369 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1370 pr_info("APIC: Switch to virtual wire mode setup with no configuration\n"); 1371 upmode = true; 1372 default_setup_apic_routing(); 1373 break; 1374 case APIC_SYMMETRIC_IO: 1375 pr_info("APIC: Switch to symmetric I/O mode setup\n"); 1376 default_setup_apic_routing(); 1377 break; 1378 case APIC_SYMMETRIC_IO_NO_ROUTING: 1379 pr_info("APIC: Switch to symmetric I/O mode setup in no SMP routine\n"); 1380 break; 1381 } 1382 1383 apic_bsp_setup(upmode); 1384 } 1385 1386 static void lapic_setup_esr(void) 1387 { 1388 unsigned int oldvalue, value, maxlvt; 1389 1390 if (!lapic_is_integrated()) { 1391 pr_info("No ESR for 82489DX.\n"); 1392 return; 1393 } 1394 1395 if (apic->disable_esr) { 1396 /* 1397 * Something untraceable is creating bad interrupts on 1398 * secondary quads ... for the moment, just leave the 1399 * ESR disabled - we can't do anything useful with the 1400 * errors anyway - mbligh 1401 */ 1402 pr_info("Leaving ESR disabled.\n"); 1403 return; 1404 } 1405 1406 maxlvt = lapic_get_maxlvt(); 1407 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1408 apic_write(APIC_ESR, 0); 1409 oldvalue = apic_read(APIC_ESR); 1410 1411 /* enables sending errors */ 1412 value = ERROR_APIC_VECTOR; 1413 apic_write(APIC_LVTERR, value); 1414 1415 /* 1416 * spec says clear errors after enabling vector. 1417 */ 1418 if (maxlvt > 3) 1419 apic_write(APIC_ESR, 0); 1420 value = apic_read(APIC_ESR); 1421 if (value != oldvalue) 1422 apic_printk(APIC_VERBOSE, "ESR value before enabling " 1423 "vector: 0x%08x after: 0x%08x\n", 1424 oldvalue, value); 1425 } 1426 1427 static void apic_pending_intr_clear(void) 1428 { 1429 long long max_loops = cpu_khz ? cpu_khz : 1000000; 1430 unsigned long long tsc = 0, ntsc; 1431 unsigned int queued; 1432 unsigned long value; 1433 int i, j, acked = 0; 1434 1435 if (boot_cpu_has(X86_FEATURE_TSC)) 1436 tsc = rdtsc(); 1437 /* 1438 * After a crash, we no longer service the interrupts and a pending 1439 * interrupt from previous kernel might still have ISR bit set. 1440 * 1441 * Most probably by now CPU has serviced that pending interrupt and 1442 * it might not have done the ack_APIC_irq() because it thought, 1443 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it 1444 * does not clear the ISR bit and cpu thinks it has already serivced 1445 * the interrupt. Hence a vector might get locked. It was noticed 1446 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. 1447 */ 1448 do { 1449 queued = 0; 1450 for (i = APIC_ISR_NR - 1; i >= 0; i--) 1451 queued |= apic_read(APIC_IRR + i*0x10); 1452 1453 for (i = APIC_ISR_NR - 1; i >= 0; i--) { 1454 value = apic_read(APIC_ISR + i*0x10); 1455 for_each_set_bit(j, &value, 32) { 1456 ack_APIC_irq(); 1457 acked++; 1458 } 1459 } 1460 if (acked > 256) { 1461 pr_err("LAPIC pending interrupts after %d EOI\n", acked); 1462 break; 1463 } 1464 if (queued) { 1465 if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) { 1466 ntsc = rdtsc(); 1467 max_loops = (cpu_khz << 10) - (ntsc - tsc); 1468 } else { 1469 max_loops--; 1470 } 1471 } 1472 } while (queued && max_loops > 0); 1473 WARN_ON(max_loops <= 0); 1474 } 1475 1476 /** 1477 * setup_local_APIC - setup the local APIC 1478 * 1479 * Used to setup local APIC while initializing BSP or bringing up APs. 1480 * Always called with preemption disabled. 1481 */ 1482 static void setup_local_APIC(void) 1483 { 1484 int cpu = smp_processor_id(); 1485 unsigned int value; 1486 #ifdef CONFIG_X86_32 1487 int logical_apicid, ldr_apicid; 1488 #endif 1489 1490 1491 if (disable_apic) { 1492 disable_ioapic_support(); 1493 return; 1494 } 1495 1496 #ifdef CONFIG_X86_32 1497 /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1498 if (lapic_is_integrated() && apic->disable_esr) { 1499 apic_write(APIC_ESR, 0); 1500 apic_write(APIC_ESR, 0); 1501 apic_write(APIC_ESR, 0); 1502 apic_write(APIC_ESR, 0); 1503 } 1504 #endif 1505 perf_events_lapic_init(); 1506 1507 /* 1508 * Double-check whether this APIC is really registered. 1509 * This is meaningless in clustered apic mode, so we skip it. 1510 */ 1511 BUG_ON(!apic->apic_id_registered()); 1512 1513 /* 1514 * Intel recommends to set DFR, LDR and TPR before enabling 1515 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1516 * document number 292116). So here it goes... 1517 */ 1518 apic->init_apic_ldr(); 1519 1520 #ifdef CONFIG_X86_32 1521 /* 1522 * APIC LDR is initialized. If logical_apicid mapping was 1523 * initialized during get_smp_config(), make sure it matches the 1524 * actual value. 1525 */ 1526 logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu); 1527 ldr_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 1528 WARN_ON(logical_apicid != BAD_APICID && logical_apicid != ldr_apicid); 1529 /* always use the value from LDR */ 1530 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = ldr_apicid; 1531 #endif 1532 1533 /* 1534 * Set Task Priority to 'accept all'. We never change this 1535 * later on. 1536 */ 1537 value = apic_read(APIC_TASKPRI); 1538 value &= ~APIC_TPRI_MASK; 1539 apic_write(APIC_TASKPRI, value); 1540 1541 apic_pending_intr_clear(); 1542 1543 /* 1544 * Now that we are all set up, enable the APIC 1545 */ 1546 value = apic_read(APIC_SPIV); 1547 value &= ~APIC_VECTOR_MASK; 1548 /* 1549 * Enable APIC 1550 */ 1551 value |= APIC_SPIV_APIC_ENABLED; 1552 1553 #ifdef CONFIG_X86_32 1554 /* 1555 * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1556 * certain networking cards. If high frequency interrupts are 1557 * happening on a particular IOAPIC pin, plus the IOAPIC routing 1558 * entry is masked/unmasked at a high rate as well then sooner or 1559 * later IOAPIC line gets 'stuck', no more interrupts are received 1560 * from the device. If focus CPU is disabled then the hang goes 1561 * away, oh well :-( 1562 * 1563 * [ This bug can be reproduced easily with a level-triggered 1564 * PCI Ne2000 networking cards and PII/PIII processors, dual 1565 * BX chipset. ] 1566 */ 1567 /* 1568 * Actually disabling the focus CPU check just makes the hang less 1569 * frequent as it makes the interrupt distributon model be more 1570 * like LRU than MRU (the short-term load is more even across CPUs). 1571 */ 1572 1573 /* 1574 * - enable focus processor (bit==0) 1575 * - 64bit mode always use processor focus 1576 * so no need to set it 1577 */ 1578 value &= ~APIC_SPIV_FOCUS_DISABLED; 1579 #endif 1580 1581 /* 1582 * Set spurious IRQ vector 1583 */ 1584 value |= SPURIOUS_APIC_VECTOR; 1585 apic_write(APIC_SPIV, value); 1586 1587 /* 1588 * Set up LVT0, LVT1: 1589 * 1590 * set up through-local-APIC on the boot CPU's LINT0. This is not 1591 * strictly necessary in pure symmetric-IO mode, but sometimes 1592 * we delegate interrupts to the 8259A. 1593 */ 1594 /* 1595 * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1596 */ 1597 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 1598 if (!cpu && (pic_mode || !value || skip_ioapic_setup)) { 1599 value = APIC_DM_EXTINT; 1600 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); 1601 } else { 1602 value = APIC_DM_EXTINT | APIC_LVT_MASKED; 1603 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); 1604 } 1605 apic_write(APIC_LVT0, value); 1606 1607 /* 1608 * Only the BSP sees the LINT1 NMI signal by default. This can be 1609 * modified by apic_extnmi= boot option. 1610 */ 1611 if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) || 1612 apic_extnmi == APIC_EXTNMI_ALL) 1613 value = APIC_DM_NMI; 1614 else 1615 value = APIC_DM_NMI | APIC_LVT_MASKED; 1616 1617 /* Is 82489DX ? */ 1618 if (!lapic_is_integrated()) 1619 value |= APIC_LVT_LEVEL_TRIGGER; 1620 apic_write(APIC_LVT1, value); 1621 1622 #ifdef CONFIG_X86_MCE_INTEL 1623 /* Recheck CMCI information after local APIC is up on CPU #0 */ 1624 if (!cpu) 1625 cmci_recheck(); 1626 #endif 1627 } 1628 1629 static void end_local_APIC_setup(void) 1630 { 1631 lapic_setup_esr(); 1632 1633 #ifdef CONFIG_X86_32 1634 { 1635 unsigned int value; 1636 /* Disable the local apic timer */ 1637 value = apic_read(APIC_LVTT); 1638 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1639 apic_write(APIC_LVTT, value); 1640 } 1641 #endif 1642 1643 apic_pm_activate(); 1644 } 1645 1646 /* 1647 * APIC setup function for application processors. Called from smpboot.c 1648 */ 1649 void apic_ap_setup(void) 1650 { 1651 setup_local_APIC(); 1652 end_local_APIC_setup(); 1653 } 1654 1655 #ifdef CONFIG_X86_X2APIC 1656 int x2apic_mode; 1657 1658 enum { 1659 X2APIC_OFF, 1660 X2APIC_ON, 1661 X2APIC_DISABLED, 1662 }; 1663 static int x2apic_state; 1664 1665 static void __x2apic_disable(void) 1666 { 1667 u64 msr; 1668 1669 if (!boot_cpu_has(X86_FEATURE_APIC)) 1670 return; 1671 1672 rdmsrl(MSR_IA32_APICBASE, msr); 1673 if (!(msr & X2APIC_ENABLE)) 1674 return; 1675 /* Disable xapic and x2apic first and then reenable xapic mode */ 1676 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); 1677 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); 1678 printk_once(KERN_INFO "x2apic disabled\n"); 1679 } 1680 1681 static void __x2apic_enable(void) 1682 { 1683 u64 msr; 1684 1685 rdmsrl(MSR_IA32_APICBASE, msr); 1686 if (msr & X2APIC_ENABLE) 1687 return; 1688 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); 1689 printk_once(KERN_INFO "x2apic enabled\n"); 1690 } 1691 1692 static int __init setup_nox2apic(char *str) 1693 { 1694 if (x2apic_enabled()) { 1695 int apicid = native_apic_msr_read(APIC_ID); 1696 1697 if (apicid >= 255) { 1698 pr_warning("Apicid: %08x, cannot enforce nox2apic\n", 1699 apicid); 1700 return 0; 1701 } 1702 pr_warning("x2apic already enabled.\n"); 1703 __x2apic_disable(); 1704 } 1705 setup_clear_cpu_cap(X86_FEATURE_X2APIC); 1706 x2apic_state = X2APIC_DISABLED; 1707 x2apic_mode = 0; 1708 return 0; 1709 } 1710 early_param("nox2apic", setup_nox2apic); 1711 1712 /* Called from cpu_init() to enable x2apic on (secondary) cpus */ 1713 void x2apic_setup(void) 1714 { 1715 /* 1716 * If x2apic is not in ON state, disable it if already enabled 1717 * from BIOS. 1718 */ 1719 if (x2apic_state != X2APIC_ON) { 1720 __x2apic_disable(); 1721 return; 1722 } 1723 __x2apic_enable(); 1724 } 1725 1726 static __init void x2apic_disable(void) 1727 { 1728 u32 x2apic_id, state = x2apic_state; 1729 1730 x2apic_mode = 0; 1731 x2apic_state = X2APIC_DISABLED; 1732 1733 if (state != X2APIC_ON) 1734 return; 1735 1736 x2apic_id = read_apic_id(); 1737 if (x2apic_id >= 255) 1738 panic("Cannot disable x2apic, id: %08x\n", x2apic_id); 1739 1740 __x2apic_disable(); 1741 register_lapic_address(mp_lapic_addr); 1742 } 1743 1744 static __init void x2apic_enable(void) 1745 { 1746 if (x2apic_state != X2APIC_OFF) 1747 return; 1748 1749 x2apic_mode = 1; 1750 x2apic_state = X2APIC_ON; 1751 __x2apic_enable(); 1752 } 1753 1754 static __init void try_to_enable_x2apic(int remap_mode) 1755 { 1756 if (x2apic_state == X2APIC_DISABLED) 1757 return; 1758 1759 if (remap_mode != IRQ_REMAP_X2APIC_MODE) { 1760 /* IR is required if there is APIC ID > 255 even when running 1761 * under KVM 1762 */ 1763 if (max_physical_apicid > 255 || 1764 !x86_init.hyper.x2apic_available()) { 1765 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n"); 1766 x2apic_disable(); 1767 return; 1768 } 1769 1770 /* 1771 * without IR all CPUs can be addressed by IOAPIC/MSI 1772 * only in physical mode 1773 */ 1774 x2apic_phys = 1; 1775 } 1776 x2apic_enable(); 1777 } 1778 1779 void __init check_x2apic(void) 1780 { 1781 if (x2apic_enabled()) { 1782 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n"); 1783 x2apic_mode = 1; 1784 x2apic_state = X2APIC_ON; 1785 } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) { 1786 x2apic_state = X2APIC_DISABLED; 1787 } 1788 } 1789 #else /* CONFIG_X86_X2APIC */ 1790 static int __init validate_x2apic(void) 1791 { 1792 if (!apic_is_x2apic_enabled()) 1793 return 0; 1794 /* 1795 * Checkme: Can we simply turn off x2apic here instead of panic? 1796 */ 1797 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n"); 1798 } 1799 early_initcall(validate_x2apic); 1800 1801 static inline void try_to_enable_x2apic(int remap_mode) { } 1802 static inline void __x2apic_enable(void) { } 1803 #endif /* !CONFIG_X86_X2APIC */ 1804 1805 void __init enable_IR_x2apic(void) 1806 { 1807 unsigned long flags; 1808 int ret, ir_stat; 1809 1810 if (skip_ioapic_setup) { 1811 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n"); 1812 return; 1813 } 1814 1815 ir_stat = irq_remapping_prepare(); 1816 if (ir_stat < 0 && !x2apic_supported()) 1817 return; 1818 1819 ret = save_ioapic_entries(); 1820 if (ret) { 1821 pr_info("Saving IO-APIC state failed: %d\n", ret); 1822 return; 1823 } 1824 1825 local_irq_save(flags); 1826 legacy_pic->mask_all(); 1827 mask_ioapic_entries(); 1828 1829 /* If irq_remapping_prepare() succeeded, try to enable it */ 1830 if (ir_stat >= 0) 1831 ir_stat = irq_remapping_enable(); 1832 /* ir_stat contains the remap mode or an error code */ 1833 try_to_enable_x2apic(ir_stat); 1834 1835 if (ir_stat < 0) 1836 restore_ioapic_entries(); 1837 legacy_pic->restore_mask(); 1838 local_irq_restore(flags); 1839 } 1840 1841 #ifdef CONFIG_X86_64 1842 /* 1843 * Detect and enable local APICs on non-SMP boards. 1844 * Original code written by Keir Fraser. 1845 * On AMD64 we trust the BIOS - if it says no APIC it is likely 1846 * not correctly set up (usually the APIC timer won't work etc.) 1847 */ 1848 static int __init detect_init_APIC(void) 1849 { 1850 if (!boot_cpu_has(X86_FEATURE_APIC)) { 1851 pr_info("No local APIC present\n"); 1852 return -1; 1853 } 1854 1855 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1856 return 0; 1857 } 1858 #else 1859 1860 static int __init apic_verify(void) 1861 { 1862 u32 features, h, l; 1863 1864 /* 1865 * The APIC feature bit should now be enabled 1866 * in `cpuid' 1867 */ 1868 features = cpuid_edx(1); 1869 if (!(features & (1 << X86_FEATURE_APIC))) { 1870 pr_warning("Could not enable APIC!\n"); 1871 return -1; 1872 } 1873 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 1874 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1875 1876 /* The BIOS may have set up the APIC at some other address */ 1877 if (boot_cpu_data.x86 >= 6) { 1878 rdmsr(MSR_IA32_APICBASE, l, h); 1879 if (l & MSR_IA32_APICBASE_ENABLE) 1880 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 1881 } 1882 1883 pr_info("Found and enabled local APIC!\n"); 1884 return 0; 1885 } 1886 1887 int __init apic_force_enable(unsigned long addr) 1888 { 1889 u32 h, l; 1890 1891 if (disable_apic) 1892 return -1; 1893 1894 /* 1895 * Some BIOSes disable the local APIC in the APIC_BASE 1896 * MSR. This can only be done in software for Intel P6 or later 1897 * and AMD K7 (Model > 1) or later. 1898 */ 1899 if (boot_cpu_data.x86 >= 6) { 1900 rdmsr(MSR_IA32_APICBASE, l, h); 1901 if (!(l & MSR_IA32_APICBASE_ENABLE)) { 1902 pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 1903 l &= ~MSR_IA32_APICBASE_BASE; 1904 l |= MSR_IA32_APICBASE_ENABLE | addr; 1905 wrmsr(MSR_IA32_APICBASE, l, h); 1906 enabled_via_apicbase = 1; 1907 } 1908 } 1909 return apic_verify(); 1910 } 1911 1912 /* 1913 * Detect and initialize APIC 1914 */ 1915 static int __init detect_init_APIC(void) 1916 { 1917 /* Disabled by kernel option? */ 1918 if (disable_apic) 1919 return -1; 1920 1921 switch (boot_cpu_data.x86_vendor) { 1922 case X86_VENDOR_AMD: 1923 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 1924 (boot_cpu_data.x86 >= 15)) 1925 break; 1926 goto no_apic; 1927 case X86_VENDOR_HYGON: 1928 break; 1929 case X86_VENDOR_INTEL: 1930 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 1931 (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC))) 1932 break; 1933 goto no_apic; 1934 default: 1935 goto no_apic; 1936 } 1937 1938 if (!boot_cpu_has(X86_FEATURE_APIC)) { 1939 /* 1940 * Over-ride BIOS and try to enable the local APIC only if 1941 * "lapic" specified. 1942 */ 1943 if (!force_enable_local_apic) { 1944 pr_info("Local APIC disabled by BIOS -- " 1945 "you can enable it with \"lapic\"\n"); 1946 return -1; 1947 } 1948 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) 1949 return -1; 1950 } else { 1951 if (apic_verify()) 1952 return -1; 1953 } 1954 1955 apic_pm_activate(); 1956 1957 return 0; 1958 1959 no_apic: 1960 pr_info("No local APIC present or hardware disabled\n"); 1961 return -1; 1962 } 1963 #endif 1964 1965 /** 1966 * init_apic_mappings - initialize APIC mappings 1967 */ 1968 void __init init_apic_mappings(void) 1969 { 1970 unsigned int new_apicid; 1971 1972 apic_check_deadline_errata(); 1973 1974 if (x2apic_mode) { 1975 boot_cpu_physical_apicid = read_apic_id(); 1976 return; 1977 } 1978 1979 /* If no local APIC can be found return early */ 1980 if (!smp_found_config && detect_init_APIC()) { 1981 /* lets NOP'ify apic operations */ 1982 pr_info("APIC: disable apic facility\n"); 1983 apic_disable(); 1984 } else { 1985 apic_phys = mp_lapic_addr; 1986 1987 /* 1988 * If the system has ACPI MADT tables or MP info, the LAPIC 1989 * address is already registered. 1990 */ 1991 if (!acpi_lapic && !smp_found_config) 1992 register_lapic_address(apic_phys); 1993 } 1994 1995 /* 1996 * Fetch the APIC ID of the BSP in case we have a 1997 * default configuration (or the MP table is broken). 1998 */ 1999 new_apicid = read_apic_id(); 2000 if (boot_cpu_physical_apicid != new_apicid) { 2001 boot_cpu_physical_apicid = new_apicid; 2002 /* 2003 * yeah -- we lie about apic_version 2004 * in case if apic was disabled via boot option 2005 * but it's not a problem for SMP compiled kernel 2006 * since apic_intr_mode_select is prepared for such 2007 * a case and disable smp mode 2008 */ 2009 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 2010 } 2011 } 2012 2013 void __init register_lapic_address(unsigned long address) 2014 { 2015 mp_lapic_addr = address; 2016 2017 if (!x2apic_mode) { 2018 set_fixmap_nocache(FIX_APIC_BASE, address); 2019 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 2020 APIC_BASE, address); 2021 } 2022 if (boot_cpu_physical_apicid == -1U) { 2023 boot_cpu_physical_apicid = read_apic_id(); 2024 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 2025 } 2026 } 2027 2028 /* 2029 * Local APIC interrupts 2030 */ 2031 2032 /* 2033 * This interrupt should _never_ happen with our APIC/SMP architecture 2034 */ 2035 __visible void __irq_entry smp_spurious_interrupt(struct pt_regs *regs) 2036 { 2037 u8 vector = ~regs->orig_ax; 2038 u32 v; 2039 2040 entering_irq(); 2041 trace_spurious_apic_entry(vector); 2042 2043 /* 2044 * Check if this really is a spurious interrupt and ACK it 2045 * if it is a vectored one. Just in case... 2046 * Spurious interrupts should not be ACKed. 2047 */ 2048 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1)); 2049 if (v & (1 << (vector & 0x1f))) 2050 ack_APIC_irq(); 2051 2052 inc_irq_stat(irq_spurious_count); 2053 2054 /* see sw-dev-man vol 3, chapter 7.4.13.5 */ 2055 pr_info("spurious APIC interrupt through vector %02x on CPU#%d, " 2056 "should never happen.\n", vector, smp_processor_id()); 2057 2058 trace_spurious_apic_exit(vector); 2059 exiting_irq(); 2060 } 2061 2062 /* 2063 * This interrupt should never happen with our APIC/SMP architecture 2064 */ 2065 __visible void __irq_entry smp_error_interrupt(struct pt_regs *regs) 2066 { 2067 static const char * const error_interrupt_reason[] = { 2068 "Send CS error", /* APIC Error Bit 0 */ 2069 "Receive CS error", /* APIC Error Bit 1 */ 2070 "Send accept error", /* APIC Error Bit 2 */ 2071 "Receive accept error", /* APIC Error Bit 3 */ 2072 "Redirectable IPI", /* APIC Error Bit 4 */ 2073 "Send illegal vector", /* APIC Error Bit 5 */ 2074 "Received illegal vector", /* APIC Error Bit 6 */ 2075 "Illegal register address", /* APIC Error Bit 7 */ 2076 }; 2077 u32 v, i = 0; 2078 2079 entering_irq(); 2080 trace_error_apic_entry(ERROR_APIC_VECTOR); 2081 2082 /* First tickle the hardware, only then report what went on. -- REW */ 2083 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */ 2084 apic_write(APIC_ESR, 0); 2085 v = apic_read(APIC_ESR); 2086 ack_APIC_irq(); 2087 atomic_inc(&irq_err_count); 2088 2089 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x", 2090 smp_processor_id(), v); 2091 2092 v &= 0xff; 2093 while (v) { 2094 if (v & 0x1) 2095 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); 2096 i++; 2097 v >>= 1; 2098 } 2099 2100 apic_printk(APIC_DEBUG, KERN_CONT "\n"); 2101 2102 trace_error_apic_exit(ERROR_APIC_VECTOR); 2103 exiting_irq(); 2104 } 2105 2106 /** 2107 * connect_bsp_APIC - attach the APIC to the interrupt system 2108 */ 2109 static void __init connect_bsp_APIC(void) 2110 { 2111 #ifdef CONFIG_X86_32 2112 if (pic_mode) { 2113 /* 2114 * Do not trust the local APIC being empty at bootup. 2115 */ 2116 clear_local_APIC(); 2117 /* 2118 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 2119 * local APIC to INT and NMI lines. 2120 */ 2121 apic_printk(APIC_VERBOSE, "leaving PIC mode, " 2122 "enabling APIC mode.\n"); 2123 imcr_pic_to_apic(); 2124 } 2125 #endif 2126 } 2127 2128 /** 2129 * disconnect_bsp_APIC - detach the APIC from the interrupt system 2130 * @virt_wire_setup: indicates, whether virtual wire mode is selected 2131 * 2132 * Virtual wire mode is necessary to deliver legacy interrupts even when the 2133 * APIC is disabled. 2134 */ 2135 void disconnect_bsp_APIC(int virt_wire_setup) 2136 { 2137 unsigned int value; 2138 2139 #ifdef CONFIG_X86_32 2140 if (pic_mode) { 2141 /* 2142 * Put the board back into PIC mode (has an effect only on 2143 * certain older boards). Note that APIC interrupts, including 2144 * IPIs, won't work beyond this point! The only exception are 2145 * INIT IPIs. 2146 */ 2147 apic_printk(APIC_VERBOSE, "disabling APIC mode, " 2148 "entering PIC mode.\n"); 2149 imcr_apic_to_pic(); 2150 return; 2151 } 2152 #endif 2153 2154 /* Go back to Virtual Wire compatibility mode */ 2155 2156 /* For the spurious interrupt use vector F, and enable it */ 2157 value = apic_read(APIC_SPIV); 2158 value &= ~APIC_VECTOR_MASK; 2159 value |= APIC_SPIV_APIC_ENABLED; 2160 value |= 0xf; 2161 apic_write(APIC_SPIV, value); 2162 2163 if (!virt_wire_setup) { 2164 /* 2165 * For LVT0 make it edge triggered, active high, 2166 * external and enabled 2167 */ 2168 value = apic_read(APIC_LVT0); 2169 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2170 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2171 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2172 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2173 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 2174 apic_write(APIC_LVT0, value); 2175 } else { 2176 /* Disable LVT0 */ 2177 apic_write(APIC_LVT0, APIC_LVT_MASKED); 2178 } 2179 2180 /* 2181 * For LVT1 make it edge triggered, active high, 2182 * nmi and enabled 2183 */ 2184 value = apic_read(APIC_LVT1); 2185 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2186 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2187 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2188 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2189 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 2190 apic_write(APIC_LVT1, value); 2191 } 2192 2193 /* 2194 * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated 2195 * contiguously, it equals to current allocated max logical CPU ID plus 1. 2196 * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range, 2197 * so the maximum of nr_logical_cpuids is nr_cpu_ids. 2198 * 2199 * NOTE: Reserve 0 for BSP. 2200 */ 2201 static int nr_logical_cpuids = 1; 2202 2203 /* 2204 * Used to store mapping between logical CPU IDs and APIC IDs. 2205 */ 2206 static int cpuid_to_apicid[] = { 2207 [0 ... NR_CPUS - 1] = -1, 2208 }; 2209 2210 #ifdef CONFIG_SMP 2211 /** 2212 * apic_id_is_primary_thread - Check whether APIC ID belongs to a primary thread 2213 * @id: APIC ID to check 2214 */ 2215 bool apic_id_is_primary_thread(unsigned int apicid) 2216 { 2217 u32 mask; 2218 2219 if (smp_num_siblings == 1) 2220 return true; 2221 /* Isolate the SMT bit(s) in the APICID and check for 0 */ 2222 mask = (1U << (fls(smp_num_siblings) - 1)) - 1; 2223 return !(apicid & mask); 2224 } 2225 #endif 2226 2227 /* 2228 * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids 2229 * and cpuid_to_apicid[] synchronized. 2230 */ 2231 static int allocate_logical_cpuid(int apicid) 2232 { 2233 int i; 2234 2235 /* 2236 * cpuid <-> apicid mapping is persistent, so when a cpu is up, 2237 * check if the kernel has allocated a cpuid for it. 2238 */ 2239 for (i = 0; i < nr_logical_cpuids; i++) { 2240 if (cpuid_to_apicid[i] == apicid) 2241 return i; 2242 } 2243 2244 /* Allocate a new cpuid. */ 2245 if (nr_logical_cpuids >= nr_cpu_ids) { 2246 WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. " 2247 "Processor %d/0x%x and the rest are ignored.\n", 2248 nr_cpu_ids, nr_logical_cpuids, apicid); 2249 return -EINVAL; 2250 } 2251 2252 cpuid_to_apicid[nr_logical_cpuids] = apicid; 2253 return nr_logical_cpuids++; 2254 } 2255 2256 int generic_processor_info(int apicid, int version) 2257 { 2258 int cpu, max = nr_cpu_ids; 2259 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, 2260 phys_cpu_present_map); 2261 2262 /* 2263 * boot_cpu_physical_apicid is designed to have the apicid 2264 * returned by read_apic_id(), i.e, the apicid of the 2265 * currently booting-up processor. However, on some platforms, 2266 * it is temporarily modified by the apicid reported as BSP 2267 * through MP table. Concretely: 2268 * 2269 * - arch/x86/kernel/mpparse.c: MP_processor_info() 2270 * - arch/x86/mm/amdtopology.c: amd_numa_init() 2271 * 2272 * This function is executed with the modified 2273 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel 2274 * parameter doesn't work to disable APs on kdump 2nd kernel. 2275 * 2276 * Since fixing handling of boot_cpu_physical_apicid requires 2277 * another discussion and tests on each platform, we leave it 2278 * for now and here we use read_apic_id() directly in this 2279 * function, generic_processor_info(). 2280 */ 2281 if (disabled_cpu_apicid != BAD_APICID && 2282 disabled_cpu_apicid != read_apic_id() && 2283 disabled_cpu_apicid == apicid) { 2284 int thiscpu = num_processors + disabled_cpus; 2285 2286 pr_warning("APIC: Disabling requested cpu." 2287 " Processor %d/0x%x ignored.\n", 2288 thiscpu, apicid); 2289 2290 disabled_cpus++; 2291 return -ENODEV; 2292 } 2293 2294 /* 2295 * If boot cpu has not been detected yet, then only allow upto 2296 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu 2297 */ 2298 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && 2299 apicid != boot_cpu_physical_apicid) { 2300 int thiscpu = max + disabled_cpus - 1; 2301 2302 pr_warning( 2303 "APIC: NR_CPUS/possible_cpus limit of %i almost" 2304 " reached. Keeping one slot for boot cpu." 2305 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 2306 2307 disabled_cpus++; 2308 return -ENODEV; 2309 } 2310 2311 if (num_processors >= nr_cpu_ids) { 2312 int thiscpu = max + disabled_cpus; 2313 2314 pr_warning("APIC: NR_CPUS/possible_cpus limit of %i " 2315 "reached. Processor %d/0x%x ignored.\n", 2316 max, thiscpu, apicid); 2317 2318 disabled_cpus++; 2319 return -EINVAL; 2320 } 2321 2322 if (apicid == boot_cpu_physical_apicid) { 2323 /* 2324 * x86_bios_cpu_apicid is required to have processors listed 2325 * in same order as logical cpu numbers. Hence the first 2326 * entry is BSP, and so on. 2327 * boot_cpu_init() already hold bit 0 in cpu_present_mask 2328 * for BSP. 2329 */ 2330 cpu = 0; 2331 2332 /* Logical cpuid 0 is reserved for BSP. */ 2333 cpuid_to_apicid[0] = apicid; 2334 } else { 2335 cpu = allocate_logical_cpuid(apicid); 2336 if (cpu < 0) { 2337 disabled_cpus++; 2338 return -EINVAL; 2339 } 2340 } 2341 2342 /* 2343 * Validate version 2344 */ 2345 if (version == 0x0) { 2346 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", 2347 cpu, apicid); 2348 version = 0x10; 2349 } 2350 2351 if (version != boot_cpu_apic_version) { 2352 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", 2353 boot_cpu_apic_version, cpu, version); 2354 } 2355 2356 if (apicid > max_physical_apicid) 2357 max_physical_apicid = apicid; 2358 2359 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 2360 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 2361 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 2362 #endif 2363 #ifdef CONFIG_X86_32 2364 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 2365 apic->x86_32_early_logical_apicid(cpu); 2366 #endif 2367 set_cpu_possible(cpu, true); 2368 physid_set(apicid, phys_cpu_present_map); 2369 set_cpu_present(cpu, true); 2370 num_processors++; 2371 2372 return cpu; 2373 } 2374 2375 int hard_smp_processor_id(void) 2376 { 2377 return read_apic_id(); 2378 } 2379 2380 /* 2381 * Override the generic EOI implementation with an optimized version. 2382 * Only called during early boot when only one CPU is active and with 2383 * interrupts disabled, so we know this does not race with actual APIC driver 2384 * use. 2385 */ 2386 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) 2387 { 2388 struct apic **drv; 2389 2390 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { 2391 /* Should happen once for each apic */ 2392 WARN_ON((*drv)->eoi_write == eoi_write); 2393 (*drv)->native_eoi_write = (*drv)->eoi_write; 2394 (*drv)->eoi_write = eoi_write; 2395 } 2396 } 2397 2398 static void __init apic_bsp_up_setup(void) 2399 { 2400 #ifdef CONFIG_X86_64 2401 apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid)); 2402 #else 2403 /* 2404 * Hack: In case of kdump, after a crash, kernel might be booting 2405 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 2406 * might be zero if read from MP tables. Get it from LAPIC. 2407 */ 2408 # ifdef CONFIG_CRASH_DUMP 2409 boot_cpu_physical_apicid = read_apic_id(); 2410 # endif 2411 #endif 2412 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 2413 } 2414 2415 /** 2416 * apic_bsp_setup - Setup function for local apic and io-apic 2417 * @upmode: Force UP mode (for APIC_init_uniprocessor) 2418 * 2419 * Returns: 2420 * apic_id of BSP APIC 2421 */ 2422 void __init apic_bsp_setup(bool upmode) 2423 { 2424 connect_bsp_APIC(); 2425 if (upmode) 2426 apic_bsp_up_setup(); 2427 setup_local_APIC(); 2428 2429 enable_IO_APIC(); 2430 end_local_APIC_setup(); 2431 irq_remap_enable_fault_handling(); 2432 setup_IO_APIC(); 2433 } 2434 2435 #ifdef CONFIG_UP_LATE_INIT 2436 void __init up_late_init(void) 2437 { 2438 if (apic_intr_mode == APIC_PIC) 2439 return; 2440 2441 /* Setup local timer */ 2442 x86_init.timers.setup_percpu_clockev(); 2443 } 2444 #endif 2445 2446 /* 2447 * Power management 2448 */ 2449 #ifdef CONFIG_PM 2450 2451 static struct { 2452 /* 2453 * 'active' is true if the local APIC was enabled by us and 2454 * not the BIOS; this signifies that we are also responsible 2455 * for disabling it before entering apm/acpi suspend 2456 */ 2457 int active; 2458 /* r/w apic fields */ 2459 unsigned int apic_id; 2460 unsigned int apic_taskpri; 2461 unsigned int apic_ldr; 2462 unsigned int apic_dfr; 2463 unsigned int apic_spiv; 2464 unsigned int apic_lvtt; 2465 unsigned int apic_lvtpc; 2466 unsigned int apic_lvt0; 2467 unsigned int apic_lvt1; 2468 unsigned int apic_lvterr; 2469 unsigned int apic_tmict; 2470 unsigned int apic_tdcr; 2471 unsigned int apic_thmr; 2472 unsigned int apic_cmci; 2473 } apic_pm_state; 2474 2475 static int lapic_suspend(void) 2476 { 2477 unsigned long flags; 2478 int maxlvt; 2479 2480 if (!apic_pm_state.active) 2481 return 0; 2482 2483 maxlvt = lapic_get_maxlvt(); 2484 2485 apic_pm_state.apic_id = apic_read(APIC_ID); 2486 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 2487 apic_pm_state.apic_ldr = apic_read(APIC_LDR); 2488 apic_pm_state.apic_dfr = apic_read(APIC_DFR); 2489 apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2490 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2491 if (maxlvt >= 4) 2492 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2493 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2494 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2495 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2496 apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2497 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 2498 #ifdef CONFIG_X86_THERMAL_VECTOR 2499 if (maxlvt >= 5) 2500 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2501 #endif 2502 #ifdef CONFIG_X86_MCE_INTEL 2503 if (maxlvt >= 6) 2504 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI); 2505 #endif 2506 2507 local_irq_save(flags); 2508 disable_local_APIC(); 2509 2510 irq_remapping_disable(); 2511 2512 local_irq_restore(flags); 2513 return 0; 2514 } 2515 2516 static void lapic_resume(void) 2517 { 2518 unsigned int l, h; 2519 unsigned long flags; 2520 int maxlvt; 2521 2522 if (!apic_pm_state.active) 2523 return; 2524 2525 local_irq_save(flags); 2526 2527 /* 2528 * IO-APIC and PIC have their own resume routines. 2529 * We just mask them here to make sure the interrupt 2530 * subsystem is completely quiet while we enable x2apic 2531 * and interrupt-remapping. 2532 */ 2533 mask_ioapic_entries(); 2534 legacy_pic->mask_all(); 2535 2536 if (x2apic_mode) { 2537 __x2apic_enable(); 2538 } else { 2539 /* 2540 * Make sure the APICBASE points to the right address 2541 * 2542 * FIXME! This will be wrong if we ever support suspend on 2543 * SMP! We'll need to do this as part of the CPU restore! 2544 */ 2545 if (boot_cpu_data.x86 >= 6) { 2546 rdmsr(MSR_IA32_APICBASE, l, h); 2547 l &= ~MSR_IA32_APICBASE_BASE; 2548 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2549 wrmsr(MSR_IA32_APICBASE, l, h); 2550 } 2551 } 2552 2553 maxlvt = lapic_get_maxlvt(); 2554 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2555 apic_write(APIC_ID, apic_pm_state.apic_id); 2556 apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2557 apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2558 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2559 apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2560 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2561 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 2562 #ifdef CONFIG_X86_THERMAL_VECTOR 2563 if (maxlvt >= 5) 2564 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2565 #endif 2566 #ifdef CONFIG_X86_MCE_INTEL 2567 if (maxlvt >= 6) 2568 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci); 2569 #endif 2570 if (maxlvt >= 4) 2571 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2572 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2573 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2574 apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2575 apic_write(APIC_ESR, 0); 2576 apic_read(APIC_ESR); 2577 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2578 apic_write(APIC_ESR, 0); 2579 apic_read(APIC_ESR); 2580 2581 irq_remapping_reenable(x2apic_mode); 2582 2583 local_irq_restore(flags); 2584 } 2585 2586 /* 2587 * This device has no shutdown method - fully functioning local APICs 2588 * are needed on every CPU up until machine_halt/restart/poweroff. 2589 */ 2590 2591 static struct syscore_ops lapic_syscore_ops = { 2592 .resume = lapic_resume, 2593 .suspend = lapic_suspend, 2594 }; 2595 2596 static void apic_pm_activate(void) 2597 { 2598 apic_pm_state.active = 1; 2599 } 2600 2601 static int __init init_lapic_sysfs(void) 2602 { 2603 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 2604 if (boot_cpu_has(X86_FEATURE_APIC)) 2605 register_syscore_ops(&lapic_syscore_ops); 2606 2607 return 0; 2608 } 2609 2610 /* local apic needs to resume before other devices access its registers. */ 2611 core_initcall(init_lapic_sysfs); 2612 2613 #else /* CONFIG_PM */ 2614 2615 static void apic_pm_activate(void) { } 2616 2617 #endif /* CONFIG_PM */ 2618 2619 #ifdef CONFIG_X86_64 2620 2621 static int multi_checked; 2622 static int multi; 2623 2624 static int set_multi(const struct dmi_system_id *d) 2625 { 2626 if (multi) 2627 return 0; 2628 pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2629 multi = 1; 2630 return 0; 2631 } 2632 2633 static const struct dmi_system_id multi_dmi_table[] = { 2634 { 2635 .callback = set_multi, 2636 .ident = "IBM System Summit2", 2637 .matches = { 2638 DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2639 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2640 }, 2641 }, 2642 {} 2643 }; 2644 2645 static void dmi_check_multi(void) 2646 { 2647 if (multi_checked) 2648 return; 2649 2650 dmi_check_system(multi_dmi_table); 2651 multi_checked = 1; 2652 } 2653 2654 /* 2655 * apic_is_clustered_box() -- Check if we can expect good TSC 2656 * 2657 * Thus far, the major user of this is IBM's Summit2 series: 2658 * Clustered boxes may have unsynced TSC problems if they are 2659 * multi-chassis. 2660 * Use DMI to check them 2661 */ 2662 int apic_is_clustered_box(void) 2663 { 2664 dmi_check_multi(); 2665 return multi; 2666 } 2667 #endif 2668 2669 /* 2670 * APIC command line parameters 2671 */ 2672 static int __init setup_disableapic(char *arg) 2673 { 2674 disable_apic = 1; 2675 setup_clear_cpu_cap(X86_FEATURE_APIC); 2676 return 0; 2677 } 2678 early_param("disableapic", setup_disableapic); 2679 2680 /* same as disableapic, for compatibility */ 2681 static int __init setup_nolapic(char *arg) 2682 { 2683 return setup_disableapic(arg); 2684 } 2685 early_param("nolapic", setup_nolapic); 2686 2687 static int __init parse_lapic_timer_c2_ok(char *arg) 2688 { 2689 local_apic_timer_c2_ok = 1; 2690 return 0; 2691 } 2692 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2693 2694 static int __init parse_disable_apic_timer(char *arg) 2695 { 2696 disable_apic_timer = 1; 2697 return 0; 2698 } 2699 early_param("noapictimer", parse_disable_apic_timer); 2700 2701 static int __init parse_nolapic_timer(char *arg) 2702 { 2703 disable_apic_timer = 1; 2704 return 0; 2705 } 2706 early_param("nolapic_timer", parse_nolapic_timer); 2707 2708 static int __init apic_set_verbosity(char *arg) 2709 { 2710 if (!arg) { 2711 #ifdef CONFIG_X86_64 2712 skip_ioapic_setup = 0; 2713 return 0; 2714 #endif 2715 return -EINVAL; 2716 } 2717 2718 if (strcmp("debug", arg) == 0) 2719 apic_verbosity = APIC_DEBUG; 2720 else if (strcmp("verbose", arg) == 0) 2721 apic_verbosity = APIC_VERBOSE; 2722 #ifdef CONFIG_X86_64 2723 else { 2724 pr_warning("APIC Verbosity level %s not recognised" 2725 " use apic=verbose or apic=debug\n", arg); 2726 return -EINVAL; 2727 } 2728 #endif 2729 2730 return 0; 2731 } 2732 early_param("apic", apic_set_verbosity); 2733 2734 static int __init lapic_insert_resource(void) 2735 { 2736 if (!apic_phys) 2737 return -1; 2738 2739 /* Put local APIC into the resource map. */ 2740 lapic_resource.start = apic_phys; 2741 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2742 insert_resource(&iomem_resource, &lapic_resource); 2743 2744 return 0; 2745 } 2746 2747 /* 2748 * need call insert after e820__reserve_resources() 2749 * that is using request_resource 2750 */ 2751 late_initcall(lapic_insert_resource); 2752 2753 static int __init apic_set_disabled_cpu_apicid(char *arg) 2754 { 2755 if (!arg || !get_option(&arg, &disabled_cpu_apicid)) 2756 return -EINVAL; 2757 2758 return 0; 2759 } 2760 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); 2761 2762 static int __init apic_set_extnmi(char *arg) 2763 { 2764 if (!arg) 2765 return -EINVAL; 2766 2767 if (!strncmp("all", arg, 3)) 2768 apic_extnmi = APIC_EXTNMI_ALL; 2769 else if (!strncmp("none", arg, 4)) 2770 apic_extnmi = APIC_EXTNMI_NONE; 2771 else if (!strncmp("bsp", arg, 3)) 2772 apic_extnmi = APIC_EXTNMI_BSP; 2773 else { 2774 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg); 2775 return -EINVAL; 2776 } 2777 2778 return 0; 2779 } 2780 early_param("apic_extnmi", apic_set_extnmi); 2781