1 /* 2 * Local APIC handling, local APIC timers 3 * 4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 5 * 6 * Fixes 7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 8 * thanks to Eric Gilmore 9 * and Rolf G. Tews 10 * for testing these extensively. 11 * Maciej W. Rozycki : Various updates and fixes. 12 * Mikael Pettersson : Power Management for UP-APIC. 13 * Pavel Machek and 14 * Mikael Pettersson : PM converted to driver model. 15 */ 16 17 #include <linux/perf_event.h> 18 #include <linux/kernel_stat.h> 19 #include <linux/mc146818rtc.h> 20 #include <linux/acpi_pmtmr.h> 21 #include <linux/clockchips.h> 22 #include <linux/interrupt.h> 23 #include <linux/bootmem.h> 24 #include <linux/ftrace.h> 25 #include <linux/ioport.h> 26 #include <linux/module.h> 27 #include <linux/sysdev.h> 28 #include <linux/delay.h> 29 #include <linux/timex.h> 30 #include <linux/dmar.h> 31 #include <linux/init.h> 32 #include <linux/cpu.h> 33 #include <linux/dmi.h> 34 #include <linux/smp.h> 35 #include <linux/mm.h> 36 37 #include <asm/perf_event.h> 38 #include <asm/x86_init.h> 39 #include <asm/pgalloc.h> 40 #include <asm/atomic.h> 41 #include <asm/mpspec.h> 42 #include <asm/i8253.h> 43 #include <asm/i8259.h> 44 #include <asm/proto.h> 45 #include <asm/apic.h> 46 #include <asm/io_apic.h> 47 #include <asm/desc.h> 48 #include <asm/hpet.h> 49 #include <asm/idle.h> 50 #include <asm/mtrr.h> 51 #include <asm/smp.h> 52 #include <asm/mce.h> 53 #include <asm/tsc.h> 54 #include <asm/hypervisor.h> 55 56 unsigned int num_processors; 57 58 unsigned disabled_cpus __cpuinitdata; 59 60 /* Processor that is doing the boot up */ 61 unsigned int boot_cpu_physical_apicid = -1U; 62 63 /* 64 * The highest APIC ID seen during enumeration. 65 */ 66 unsigned int max_physical_apicid; 67 68 /* 69 * Bitmask of physically existing CPUs: 70 */ 71 physid_mask_t phys_cpu_present_map; 72 73 /* 74 * Map cpu index to physical APIC ID 75 */ 76 DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID); 77 DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID); 78 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 79 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 80 81 #ifdef CONFIG_X86_32 82 /* 83 * Knob to control our willingness to enable the local APIC. 84 * 85 * +1=force-enable 86 */ 87 static int force_enable_local_apic; 88 /* 89 * APIC command line parameters 90 */ 91 static int __init parse_lapic(char *arg) 92 { 93 force_enable_local_apic = 1; 94 return 0; 95 } 96 early_param("lapic", parse_lapic); 97 /* Local APIC was disabled by the BIOS and enabled by the kernel */ 98 static int enabled_via_apicbase; 99 100 /* 101 * Handle interrupt mode configuration register (IMCR). 102 * This register controls whether the interrupt signals 103 * that reach the BSP come from the master PIC or from the 104 * local APIC. Before entering Symmetric I/O Mode, either 105 * the BIOS or the operating system must switch out of 106 * PIC Mode by changing the IMCR. 107 */ 108 static inline void imcr_pic_to_apic(void) 109 { 110 /* select IMCR register */ 111 outb(0x70, 0x22); 112 /* NMI and 8259 INTR go through APIC */ 113 outb(0x01, 0x23); 114 } 115 116 static inline void imcr_apic_to_pic(void) 117 { 118 /* select IMCR register */ 119 outb(0x70, 0x22); 120 /* NMI and 8259 INTR go directly to BSP */ 121 outb(0x00, 0x23); 122 } 123 #endif 124 125 #ifdef CONFIG_X86_64 126 static int apic_calibrate_pmtmr __initdata; 127 static __init int setup_apicpmtimer(char *s) 128 { 129 apic_calibrate_pmtmr = 1; 130 notsc_setup(NULL); 131 return 0; 132 } 133 __setup("apicpmtimer", setup_apicpmtimer); 134 #endif 135 136 int x2apic_mode; 137 #ifdef CONFIG_X86_X2APIC 138 /* x2apic enabled before OS handover */ 139 static int x2apic_preenabled; 140 static __init int setup_nox2apic(char *str) 141 { 142 if (x2apic_enabled()) { 143 pr_warning("Bios already enabled x2apic, " 144 "can't enforce nox2apic"); 145 return 0; 146 } 147 148 setup_clear_cpu_cap(X86_FEATURE_X2APIC); 149 return 0; 150 } 151 early_param("nox2apic", setup_nox2apic); 152 #endif 153 154 unsigned long mp_lapic_addr; 155 int disable_apic; 156 /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 157 static int disable_apic_timer __cpuinitdata; 158 /* Local APIC timer works in C2 */ 159 int local_apic_timer_c2_ok; 160 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 161 162 int first_system_vector = 0xfe; 163 164 /* 165 * Debug level, exported for io_apic.c 166 */ 167 unsigned int apic_verbosity; 168 169 int pic_mode; 170 171 /* Have we found an MP table */ 172 int smp_found_config; 173 174 static struct resource lapic_resource = { 175 .name = "Local APIC", 176 .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 177 }; 178 179 static unsigned int calibration_result; 180 181 static int lapic_next_event(unsigned long delta, 182 struct clock_event_device *evt); 183 static void lapic_timer_setup(enum clock_event_mode mode, 184 struct clock_event_device *evt); 185 static void lapic_timer_broadcast(const struct cpumask *mask); 186 static void apic_pm_activate(void); 187 188 /* 189 * The local apic timer can be used for any function which is CPU local. 190 */ 191 static struct clock_event_device lapic_clockevent = { 192 .name = "lapic", 193 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT 194 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, 195 .shift = 32, 196 .set_mode = lapic_timer_setup, 197 .set_next_event = lapic_next_event, 198 .broadcast = lapic_timer_broadcast, 199 .rating = 100, 200 .irq = -1, 201 }; 202 static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 203 204 static unsigned long apic_phys; 205 206 /* 207 * Get the LAPIC version 208 */ 209 static inline int lapic_get_version(void) 210 { 211 return GET_APIC_VERSION(apic_read(APIC_LVR)); 212 } 213 214 /* 215 * Check, if the APIC is integrated or a separate chip 216 */ 217 static inline int lapic_is_integrated(void) 218 { 219 #ifdef CONFIG_X86_64 220 return 1; 221 #else 222 return APIC_INTEGRATED(lapic_get_version()); 223 #endif 224 } 225 226 /* 227 * Check, whether this is a modern or a first generation APIC 228 */ 229 static int modern_apic(void) 230 { 231 /* AMD systems use old APIC versions, so check the CPU */ 232 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 233 boot_cpu_data.x86 >= 0xf) 234 return 1; 235 return lapic_get_version() >= 0x14; 236 } 237 238 /* 239 * right after this call apic become NOOP driven 240 * so apic->write/read doesn't do anything 241 */ 242 void apic_disable(void) 243 { 244 pr_info("APIC: switched to apic NOOP\n"); 245 apic = &apic_noop; 246 } 247 248 void native_apic_wait_icr_idle(void) 249 { 250 while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 251 cpu_relax(); 252 } 253 254 u32 native_safe_apic_wait_icr_idle(void) 255 { 256 u32 send_status; 257 int timeout; 258 259 timeout = 0; 260 do { 261 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 262 if (!send_status) 263 break; 264 udelay(100); 265 } while (timeout++ < 1000); 266 267 return send_status; 268 } 269 270 void native_apic_icr_write(u32 low, u32 id) 271 { 272 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 273 apic_write(APIC_ICR, low); 274 } 275 276 u64 native_apic_icr_read(void) 277 { 278 u32 icr1, icr2; 279 280 icr2 = apic_read(APIC_ICR2); 281 icr1 = apic_read(APIC_ICR); 282 283 return icr1 | ((u64)icr2 << 32); 284 } 285 286 /** 287 * enable_NMI_through_LVT0 - enable NMI through local vector table 0 288 */ 289 void __cpuinit enable_NMI_through_LVT0(void) 290 { 291 unsigned int v; 292 293 /* unmask and set to NMI */ 294 v = APIC_DM_NMI; 295 296 /* Level triggered for 82489DX (32bit mode) */ 297 if (!lapic_is_integrated()) 298 v |= APIC_LVT_LEVEL_TRIGGER; 299 300 apic_write(APIC_LVT0, v); 301 } 302 303 #ifdef CONFIG_X86_32 304 /** 305 * get_physical_broadcast - Get number of physical broadcast IDs 306 */ 307 int get_physical_broadcast(void) 308 { 309 return modern_apic() ? 0xff : 0xf; 310 } 311 #endif 312 313 /** 314 * lapic_get_maxlvt - get the maximum number of local vector table entries 315 */ 316 int lapic_get_maxlvt(void) 317 { 318 unsigned int v; 319 320 v = apic_read(APIC_LVR); 321 /* 322 * - we always have APIC integrated on 64bit mode 323 * - 82489DXs do not report # of LVT entries 324 */ 325 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; 326 } 327 328 /* 329 * Local APIC timer 330 */ 331 332 /* Clock divisor */ 333 #define APIC_DIVISOR 16 334 335 /* 336 * This function sets up the local APIC timer, with a timeout of 337 * 'clocks' APIC bus clock. During calibration we actually call 338 * this function twice on the boot CPU, once with a bogus timeout 339 * value, second time for real. The other (noncalibrating) CPUs 340 * call this function only once, with the real, calibrated value. 341 * 342 * We do reads before writes even if unnecessary, to get around the 343 * P5 APIC double write bug. 344 */ 345 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 346 { 347 unsigned int lvtt_value, tmp_value; 348 349 lvtt_value = LOCAL_TIMER_VECTOR; 350 if (!oneshot) 351 lvtt_value |= APIC_LVT_TIMER_PERIODIC; 352 if (!lapic_is_integrated()) 353 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 354 355 if (!irqen) 356 lvtt_value |= APIC_LVT_MASKED; 357 358 apic_write(APIC_LVTT, lvtt_value); 359 360 /* 361 * Divide PICLK by 16 362 */ 363 tmp_value = apic_read(APIC_TDCR); 364 apic_write(APIC_TDCR, 365 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 366 APIC_TDR_DIV_16); 367 368 if (!oneshot) 369 apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 370 } 371 372 /* 373 * Setup extended LVT, AMD specific 374 * 375 * Software should use the LVT offsets the BIOS provides. The offsets 376 * are determined by the subsystems using it like those for MCE 377 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts 378 * are supported. Beginning with family 10h at least 4 offsets are 379 * available. 380 * 381 * Since the offsets must be consistent for all cores, we keep track 382 * of the LVT offsets in software and reserve the offset for the same 383 * vector also to be used on other cores. An offset is freed by 384 * setting the entry to APIC_EILVT_MASKED. 385 * 386 * If the BIOS is right, there should be no conflicts. Otherwise a 387 * "[Firmware Bug]: ..." error message is generated. However, if 388 * software does not properly determines the offsets, it is not 389 * necessarily a BIOS bug. 390 */ 391 392 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; 393 394 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) 395 { 396 return (old & APIC_EILVT_MASKED) 397 || (new == APIC_EILVT_MASKED) 398 || ((new & ~APIC_EILVT_MASKED) == old); 399 } 400 401 static unsigned int reserve_eilvt_offset(int offset, unsigned int new) 402 { 403 unsigned int rsvd; /* 0: uninitialized */ 404 405 if (offset >= APIC_EILVT_NR_MAX) 406 return ~0; 407 408 rsvd = atomic_read(&eilvt_offsets[offset]) & ~APIC_EILVT_MASKED; 409 do { 410 if (rsvd && 411 !eilvt_entry_is_changeable(rsvd, new)) 412 /* may not change if vectors are different */ 413 return rsvd; 414 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); 415 } while (rsvd != new); 416 417 return new; 418 } 419 420 /* 421 * If mask=1, the LVT entry does not generate interrupts while mask=0 422 * enables the vector. See also the BKDGs. 423 */ 424 425 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) 426 { 427 unsigned long reg = APIC_EILVTn(offset); 428 unsigned int new, old, reserved; 429 430 new = (mask << 16) | (msg_type << 8) | vector; 431 old = apic_read(reg); 432 reserved = reserve_eilvt_offset(offset, new); 433 434 if (reserved != new) { 435 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 436 "vector 0x%x, but the register is already in use for " 437 "vector 0x%x on another cpu\n", 438 smp_processor_id(), reg, offset, new, reserved); 439 return -EINVAL; 440 } 441 442 if (!eilvt_entry_is_changeable(old, new)) { 443 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 444 "vector 0x%x, but the register is already in use for " 445 "vector 0x%x on this cpu\n", 446 smp_processor_id(), reg, offset, new, old); 447 return -EBUSY; 448 } 449 450 apic_write(reg, new); 451 452 return 0; 453 } 454 EXPORT_SYMBOL_GPL(setup_APIC_eilvt); 455 456 /* 457 * Program the next event, relative to now 458 */ 459 static int lapic_next_event(unsigned long delta, 460 struct clock_event_device *evt) 461 { 462 apic_write(APIC_TMICT, delta); 463 return 0; 464 } 465 466 /* 467 * Setup the lapic timer in periodic or oneshot mode 468 */ 469 static void lapic_timer_setup(enum clock_event_mode mode, 470 struct clock_event_device *evt) 471 { 472 unsigned long flags; 473 unsigned int v; 474 475 /* Lapic used as dummy for broadcast ? */ 476 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 477 return; 478 479 local_irq_save(flags); 480 481 switch (mode) { 482 case CLOCK_EVT_MODE_PERIODIC: 483 case CLOCK_EVT_MODE_ONESHOT: 484 __setup_APIC_LVTT(calibration_result, 485 mode != CLOCK_EVT_MODE_PERIODIC, 1); 486 break; 487 case CLOCK_EVT_MODE_UNUSED: 488 case CLOCK_EVT_MODE_SHUTDOWN: 489 v = apic_read(APIC_LVTT); 490 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 491 apic_write(APIC_LVTT, v); 492 apic_write(APIC_TMICT, 0); 493 break; 494 case CLOCK_EVT_MODE_RESUME: 495 /* Nothing to do here */ 496 break; 497 } 498 499 local_irq_restore(flags); 500 } 501 502 /* 503 * Local APIC timer broadcast function 504 */ 505 static void lapic_timer_broadcast(const struct cpumask *mask) 506 { 507 #ifdef CONFIG_SMP 508 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 509 #endif 510 } 511 512 /* 513 * Setup the local APIC timer for this CPU. Copy the initialized values 514 * of the boot CPU and register the clock event in the framework. 515 */ 516 static void __cpuinit setup_APIC_timer(void) 517 { 518 struct clock_event_device *levt = &__get_cpu_var(lapic_events); 519 520 if (cpu_has(__this_cpu_ptr(&cpu_info), X86_FEATURE_ARAT)) { 521 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 522 /* Make LAPIC timer preferrable over percpu HPET */ 523 lapic_clockevent.rating = 150; 524 } 525 526 memcpy(levt, &lapic_clockevent, sizeof(*levt)); 527 levt->cpumask = cpumask_of(smp_processor_id()); 528 529 clockevents_register_device(levt); 530 } 531 532 /* 533 * In this functions we calibrate APIC bus clocks to the external timer. 534 * 535 * We want to do the calibration only once since we want to have local timer 536 * irqs syncron. CPUs connected by the same APIC bus have the very same bus 537 * frequency. 538 * 539 * This was previously done by reading the PIT/HPET and waiting for a wrap 540 * around to find out, that a tick has elapsed. I have a box, where the PIT 541 * readout is broken, so it never gets out of the wait loop again. This was 542 * also reported by others. 543 * 544 * Monitoring the jiffies value is inaccurate and the clockevents 545 * infrastructure allows us to do a simple substitution of the interrupt 546 * handler. 547 * 548 * The calibration routine also uses the pm_timer when possible, as the PIT 549 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 550 * back to normal later in the boot process). 551 */ 552 553 #define LAPIC_CAL_LOOPS (HZ/10) 554 555 static __initdata int lapic_cal_loops = -1; 556 static __initdata long lapic_cal_t1, lapic_cal_t2; 557 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 558 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 559 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 560 561 /* 562 * Temporary interrupt handler. 563 */ 564 static void __init lapic_cal_handler(struct clock_event_device *dev) 565 { 566 unsigned long long tsc = 0; 567 long tapic = apic_read(APIC_TMCCT); 568 unsigned long pm = acpi_pm_read_early(); 569 570 if (cpu_has_tsc) 571 rdtscll(tsc); 572 573 switch (lapic_cal_loops++) { 574 case 0: 575 lapic_cal_t1 = tapic; 576 lapic_cal_tsc1 = tsc; 577 lapic_cal_pm1 = pm; 578 lapic_cal_j1 = jiffies; 579 break; 580 581 case LAPIC_CAL_LOOPS: 582 lapic_cal_t2 = tapic; 583 lapic_cal_tsc2 = tsc; 584 if (pm < lapic_cal_pm1) 585 pm += ACPI_PM_OVRRUN; 586 lapic_cal_pm2 = pm; 587 lapic_cal_j2 = jiffies; 588 break; 589 } 590 } 591 592 static int __init 593 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 594 { 595 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 596 const long pm_thresh = pm_100ms / 100; 597 unsigned long mult; 598 u64 res; 599 600 #ifndef CONFIG_X86_PM_TIMER 601 return -1; 602 #endif 603 604 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 605 606 /* Check, if the PM timer is available */ 607 if (!deltapm) 608 return -1; 609 610 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 611 612 if (deltapm > (pm_100ms - pm_thresh) && 613 deltapm < (pm_100ms + pm_thresh)) { 614 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 615 return 0; 616 } 617 618 res = (((u64)deltapm) * mult) >> 22; 619 do_div(res, 1000000); 620 pr_warning("APIC calibration not consistent " 621 "with PM-Timer: %ldms instead of 100ms\n",(long)res); 622 623 /* Correct the lapic counter value */ 624 res = (((u64)(*delta)) * pm_100ms); 625 do_div(res, deltapm); 626 pr_info("APIC delta adjusted to PM-Timer: " 627 "%lu (%ld)\n", (unsigned long)res, *delta); 628 *delta = (long)res; 629 630 /* Correct the tsc counter value */ 631 if (cpu_has_tsc) { 632 res = (((u64)(*deltatsc)) * pm_100ms); 633 do_div(res, deltapm); 634 apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 635 "PM-Timer: %lu (%ld)\n", 636 (unsigned long)res, *deltatsc); 637 *deltatsc = (long)res; 638 } 639 640 return 0; 641 } 642 643 static int __init calibrate_APIC_clock(void) 644 { 645 struct clock_event_device *levt = &__get_cpu_var(lapic_events); 646 void (*real_handler)(struct clock_event_device *dev); 647 unsigned long deltaj; 648 long delta, deltatsc; 649 int pm_referenced = 0; 650 651 local_irq_disable(); 652 653 /* Replace the global interrupt handler */ 654 real_handler = global_clock_event->event_handler; 655 global_clock_event->event_handler = lapic_cal_handler; 656 657 /* 658 * Setup the APIC counter to maximum. There is no way the lapic 659 * can underflow in the 100ms detection time frame 660 */ 661 __setup_APIC_LVTT(0xffffffff, 0, 0); 662 663 /* Let the interrupts run */ 664 local_irq_enable(); 665 666 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 667 cpu_relax(); 668 669 local_irq_disable(); 670 671 /* Restore the real event handler */ 672 global_clock_event->event_handler = real_handler; 673 674 /* Build delta t1-t2 as apic timer counts down */ 675 delta = lapic_cal_t1 - lapic_cal_t2; 676 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 677 678 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 679 680 /* we trust the PM based calibration if possible */ 681 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 682 &delta, &deltatsc); 683 684 /* Calculate the scaled math multiplication factor */ 685 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 686 lapic_clockevent.shift); 687 lapic_clockevent.max_delta_ns = 688 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); 689 lapic_clockevent.min_delta_ns = 690 clockevent_delta2ns(0xF, &lapic_clockevent); 691 692 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 693 694 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 695 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); 696 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 697 calibration_result); 698 699 if (cpu_has_tsc) { 700 apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 701 "%ld.%04ld MHz.\n", 702 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 703 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 704 } 705 706 apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 707 "%u.%04u MHz.\n", 708 calibration_result / (1000000 / HZ), 709 calibration_result % (1000000 / HZ)); 710 711 /* 712 * Do a sanity check on the APIC calibration result 713 */ 714 if (calibration_result < (1000000 / HZ)) { 715 local_irq_enable(); 716 pr_warning("APIC frequency too slow, disabling apic timer\n"); 717 return -1; 718 } 719 720 levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 721 722 /* 723 * PM timer calibration failed or not turned on 724 * so lets try APIC timer based calibration 725 */ 726 if (!pm_referenced) { 727 apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 728 729 /* 730 * Setup the apic timer manually 731 */ 732 levt->event_handler = lapic_cal_handler; 733 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); 734 lapic_cal_loops = -1; 735 736 /* Let the interrupts run */ 737 local_irq_enable(); 738 739 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 740 cpu_relax(); 741 742 /* Stop the lapic timer */ 743 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); 744 745 /* Jiffies delta */ 746 deltaj = lapic_cal_j2 - lapic_cal_j1; 747 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 748 749 /* Check, if the jiffies result is consistent */ 750 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 751 apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 752 else 753 levt->features |= CLOCK_EVT_FEAT_DUMMY; 754 } else 755 local_irq_enable(); 756 757 if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 758 pr_warning("APIC timer disabled due to verification failure\n"); 759 return -1; 760 } 761 762 return 0; 763 } 764 765 /* 766 * Setup the boot APIC 767 * 768 * Calibrate and verify the result. 769 */ 770 void __init setup_boot_APIC_clock(void) 771 { 772 /* 773 * The local apic timer can be disabled via the kernel 774 * commandline or from the CPU detection code. Register the lapic 775 * timer as a dummy clock event source on SMP systems, so the 776 * broadcast mechanism is used. On UP systems simply ignore it. 777 */ 778 if (disable_apic_timer) { 779 pr_info("Disabling APIC timer\n"); 780 /* No broadcast on UP ! */ 781 if (num_possible_cpus() > 1) { 782 lapic_clockevent.mult = 1; 783 setup_APIC_timer(); 784 } 785 return; 786 } 787 788 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 789 "calibrating APIC timer ...\n"); 790 791 if (calibrate_APIC_clock()) { 792 /* No broadcast on UP ! */ 793 if (num_possible_cpus() > 1) 794 setup_APIC_timer(); 795 return; 796 } 797 798 /* 799 * If nmi_watchdog is set to IO_APIC, we need the 800 * PIT/HPET going. Otherwise register lapic as a dummy 801 * device. 802 */ 803 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 804 805 /* Setup the lapic or request the broadcast */ 806 setup_APIC_timer(); 807 } 808 809 void __cpuinit setup_secondary_APIC_clock(void) 810 { 811 setup_APIC_timer(); 812 } 813 814 /* 815 * The guts of the apic timer interrupt 816 */ 817 static void local_apic_timer_interrupt(void) 818 { 819 int cpu = smp_processor_id(); 820 struct clock_event_device *evt = &per_cpu(lapic_events, cpu); 821 822 /* 823 * Normally we should not be here till LAPIC has been initialized but 824 * in some cases like kdump, its possible that there is a pending LAPIC 825 * timer interrupt from previous kernel's context and is delivered in 826 * new kernel the moment interrupts are enabled. 827 * 828 * Interrupts are enabled early and LAPIC is setup much later, hence 829 * its possible that when we get here evt->event_handler is NULL. 830 * Check for event_handler being NULL and discard the interrupt as 831 * spurious. 832 */ 833 if (!evt->event_handler) { 834 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); 835 /* Switch it off */ 836 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); 837 return; 838 } 839 840 /* 841 * the NMI deadlock-detector uses this. 842 */ 843 inc_irq_stat(apic_timer_irqs); 844 845 evt->event_handler(evt); 846 } 847 848 /* 849 * Local APIC timer interrupt. This is the most natural way for doing 850 * local interrupts, but local timer interrupts can be emulated by 851 * broadcast interrupts too. [in case the hw doesn't support APIC timers] 852 * 853 * [ if a single-CPU system runs an SMP kernel then we call the local 854 * interrupt as well. Thus we cannot inline the local irq ... ] 855 */ 856 void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) 857 { 858 struct pt_regs *old_regs = set_irq_regs(regs); 859 860 /* 861 * NOTE! We'd better ACK the irq immediately, 862 * because timer handling can be slow. 863 */ 864 ack_APIC_irq(); 865 /* 866 * update_process_times() expects us to have done irq_enter(). 867 * Besides, if we don't timer interrupts ignore the global 868 * interrupt lock, which is the WrongThing (tm) to do. 869 */ 870 exit_idle(); 871 irq_enter(); 872 local_apic_timer_interrupt(); 873 irq_exit(); 874 875 set_irq_regs(old_regs); 876 } 877 878 int setup_profiling_timer(unsigned int multiplier) 879 { 880 return -EINVAL; 881 } 882 883 /* 884 * Local APIC start and shutdown 885 */ 886 887 /** 888 * clear_local_APIC - shutdown the local APIC 889 * 890 * This is called, when a CPU is disabled and before rebooting, so the state of 891 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 892 * leftovers during boot. 893 */ 894 void clear_local_APIC(void) 895 { 896 int maxlvt; 897 u32 v; 898 899 /* APIC hasn't been mapped yet */ 900 if (!x2apic_mode && !apic_phys) 901 return; 902 903 maxlvt = lapic_get_maxlvt(); 904 /* 905 * Masking an LVT entry can trigger a local APIC error 906 * if the vector is zero. Mask LVTERR first to prevent this. 907 */ 908 if (maxlvt >= 3) { 909 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 910 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 911 } 912 /* 913 * Careful: we have to set masks only first to deassert 914 * any level-triggered sources. 915 */ 916 v = apic_read(APIC_LVTT); 917 apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 918 v = apic_read(APIC_LVT0); 919 apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 920 v = apic_read(APIC_LVT1); 921 apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 922 if (maxlvt >= 4) { 923 v = apic_read(APIC_LVTPC); 924 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 925 } 926 927 /* lets not touch this if we didn't frob it */ 928 #ifdef CONFIG_X86_THERMAL_VECTOR 929 if (maxlvt >= 5) { 930 v = apic_read(APIC_LVTTHMR); 931 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 932 } 933 #endif 934 #ifdef CONFIG_X86_MCE_INTEL 935 if (maxlvt >= 6) { 936 v = apic_read(APIC_LVTCMCI); 937 if (!(v & APIC_LVT_MASKED)) 938 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 939 } 940 #endif 941 942 /* 943 * Clean APIC state for other OSs: 944 */ 945 apic_write(APIC_LVTT, APIC_LVT_MASKED); 946 apic_write(APIC_LVT0, APIC_LVT_MASKED); 947 apic_write(APIC_LVT1, APIC_LVT_MASKED); 948 if (maxlvt >= 3) 949 apic_write(APIC_LVTERR, APIC_LVT_MASKED); 950 if (maxlvt >= 4) 951 apic_write(APIC_LVTPC, APIC_LVT_MASKED); 952 953 /* Integrated APIC (!82489DX) ? */ 954 if (lapic_is_integrated()) { 955 if (maxlvt > 3) 956 /* Clear ESR due to Pentium errata 3AP and 11AP */ 957 apic_write(APIC_ESR, 0); 958 apic_read(APIC_ESR); 959 } 960 } 961 962 /** 963 * disable_local_APIC - clear and disable the local APIC 964 */ 965 void disable_local_APIC(void) 966 { 967 unsigned int value; 968 969 /* APIC hasn't been mapped yet */ 970 if (!x2apic_mode && !apic_phys) 971 return; 972 973 clear_local_APIC(); 974 975 /* 976 * Disable APIC (implies clearing of registers 977 * for 82489DX!). 978 */ 979 value = apic_read(APIC_SPIV); 980 value &= ~APIC_SPIV_APIC_ENABLED; 981 apic_write(APIC_SPIV, value); 982 983 #ifdef CONFIG_X86_32 984 /* 985 * When LAPIC was disabled by the BIOS and enabled by the kernel, 986 * restore the disabled state. 987 */ 988 if (enabled_via_apicbase) { 989 unsigned int l, h; 990 991 rdmsr(MSR_IA32_APICBASE, l, h); 992 l &= ~MSR_IA32_APICBASE_ENABLE; 993 wrmsr(MSR_IA32_APICBASE, l, h); 994 } 995 #endif 996 } 997 998 /* 999 * If Linux enabled the LAPIC against the BIOS default disable it down before 1000 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 1001 * not power-off. Additionally clear all LVT entries before disable_local_APIC 1002 * for the case where Linux didn't enable the LAPIC. 1003 */ 1004 void lapic_shutdown(void) 1005 { 1006 unsigned long flags; 1007 1008 if (!cpu_has_apic && !apic_from_smp_config()) 1009 return; 1010 1011 local_irq_save(flags); 1012 1013 #ifdef CONFIG_X86_32 1014 if (!enabled_via_apicbase) 1015 clear_local_APIC(); 1016 else 1017 #endif 1018 disable_local_APIC(); 1019 1020 1021 local_irq_restore(flags); 1022 } 1023 1024 /* 1025 * This is to verify that we're looking at a real local APIC. 1026 * Check these against your board if the CPUs aren't getting 1027 * started for no apparent reason. 1028 */ 1029 int __init verify_local_APIC(void) 1030 { 1031 unsigned int reg0, reg1; 1032 1033 /* 1034 * The version register is read-only in a real APIC. 1035 */ 1036 reg0 = apic_read(APIC_LVR); 1037 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); 1038 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); 1039 reg1 = apic_read(APIC_LVR); 1040 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); 1041 1042 /* 1043 * The two version reads above should print the same 1044 * numbers. If the second one is different, then we 1045 * poke at a non-APIC. 1046 */ 1047 if (reg1 != reg0) 1048 return 0; 1049 1050 /* 1051 * Check if the version looks reasonably. 1052 */ 1053 reg1 = GET_APIC_VERSION(reg0); 1054 if (reg1 == 0x00 || reg1 == 0xff) 1055 return 0; 1056 reg1 = lapic_get_maxlvt(); 1057 if (reg1 < 0x02 || reg1 == 0xff) 1058 return 0; 1059 1060 /* 1061 * The ID register is read/write in a real APIC. 1062 */ 1063 reg0 = apic_read(APIC_ID); 1064 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); 1065 apic_write(APIC_ID, reg0 ^ apic->apic_id_mask); 1066 reg1 = apic_read(APIC_ID); 1067 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); 1068 apic_write(APIC_ID, reg0); 1069 if (reg1 != (reg0 ^ apic->apic_id_mask)) 1070 return 0; 1071 1072 /* 1073 * The next two are just to see if we have sane values. 1074 * They're only really relevant if we're in Virtual Wire 1075 * compatibility mode, but most boxes are anymore. 1076 */ 1077 reg0 = apic_read(APIC_LVT0); 1078 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); 1079 reg1 = apic_read(APIC_LVT1); 1080 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); 1081 1082 return 1; 1083 } 1084 1085 /** 1086 * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1087 */ 1088 void __init sync_Arb_IDs(void) 1089 { 1090 /* 1091 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1092 * needed on AMD. 1093 */ 1094 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1095 return; 1096 1097 /* 1098 * Wait for idle. 1099 */ 1100 apic_wait_icr_idle(); 1101 1102 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1103 apic_write(APIC_ICR, APIC_DEST_ALLINC | 1104 APIC_INT_LEVELTRIG | APIC_DM_INIT); 1105 } 1106 1107 /* 1108 * An initial setup of the virtual wire mode. 1109 */ 1110 void __init init_bsp_APIC(void) 1111 { 1112 unsigned int value; 1113 1114 /* 1115 * Don't do the setup now if we have a SMP BIOS as the 1116 * through-I/O-APIC virtual wire mode might be active. 1117 */ 1118 if (smp_found_config || !cpu_has_apic) 1119 return; 1120 1121 /* 1122 * Do not trust the local APIC being empty at bootup. 1123 */ 1124 clear_local_APIC(); 1125 1126 /* 1127 * Enable APIC. 1128 */ 1129 value = apic_read(APIC_SPIV); 1130 value &= ~APIC_VECTOR_MASK; 1131 value |= APIC_SPIV_APIC_ENABLED; 1132 1133 #ifdef CONFIG_X86_32 1134 /* This bit is reserved on P4/Xeon and should be cleared */ 1135 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1136 (boot_cpu_data.x86 == 15)) 1137 value &= ~APIC_SPIV_FOCUS_DISABLED; 1138 else 1139 #endif 1140 value |= APIC_SPIV_FOCUS_DISABLED; 1141 value |= SPURIOUS_APIC_VECTOR; 1142 apic_write(APIC_SPIV, value); 1143 1144 /* 1145 * Set up the virtual wire mode. 1146 */ 1147 apic_write(APIC_LVT0, APIC_DM_EXTINT); 1148 value = APIC_DM_NMI; 1149 if (!lapic_is_integrated()) /* 82489DX */ 1150 value |= APIC_LVT_LEVEL_TRIGGER; 1151 apic_write(APIC_LVT1, value); 1152 } 1153 1154 static void __cpuinit lapic_setup_esr(void) 1155 { 1156 unsigned int oldvalue, value, maxlvt; 1157 1158 if (!lapic_is_integrated()) { 1159 pr_info("No ESR for 82489DX.\n"); 1160 return; 1161 } 1162 1163 if (apic->disable_esr) { 1164 /* 1165 * Something untraceable is creating bad interrupts on 1166 * secondary quads ... for the moment, just leave the 1167 * ESR disabled - we can't do anything useful with the 1168 * errors anyway - mbligh 1169 */ 1170 pr_info("Leaving ESR disabled.\n"); 1171 return; 1172 } 1173 1174 maxlvt = lapic_get_maxlvt(); 1175 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1176 apic_write(APIC_ESR, 0); 1177 oldvalue = apic_read(APIC_ESR); 1178 1179 /* enables sending errors */ 1180 value = ERROR_APIC_VECTOR; 1181 apic_write(APIC_LVTERR, value); 1182 1183 /* 1184 * spec says clear errors after enabling vector. 1185 */ 1186 if (maxlvt > 3) 1187 apic_write(APIC_ESR, 0); 1188 value = apic_read(APIC_ESR); 1189 if (value != oldvalue) 1190 apic_printk(APIC_VERBOSE, "ESR value before enabling " 1191 "vector: 0x%08x after: 0x%08x\n", 1192 oldvalue, value); 1193 } 1194 1195 /** 1196 * setup_local_APIC - setup the local APIC 1197 * 1198 * Used to setup local APIC while initializing BSP or bringin up APs. 1199 * Always called with preemption disabled. 1200 */ 1201 void __cpuinit setup_local_APIC(void) 1202 { 1203 int cpu = smp_processor_id(); 1204 unsigned int value, queued; 1205 int i, j, acked = 0; 1206 unsigned long long tsc = 0, ntsc; 1207 long long max_loops = cpu_khz; 1208 1209 if (cpu_has_tsc) 1210 rdtscll(tsc); 1211 1212 if (disable_apic) { 1213 disable_ioapic_support(); 1214 return; 1215 } 1216 1217 #ifdef CONFIG_X86_32 1218 /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1219 if (lapic_is_integrated() && apic->disable_esr) { 1220 apic_write(APIC_ESR, 0); 1221 apic_write(APIC_ESR, 0); 1222 apic_write(APIC_ESR, 0); 1223 apic_write(APIC_ESR, 0); 1224 } 1225 #endif 1226 perf_events_lapic_init(); 1227 1228 /* 1229 * Double-check whether this APIC is really registered. 1230 * This is meaningless in clustered apic mode, so we skip it. 1231 */ 1232 BUG_ON(!apic->apic_id_registered()); 1233 1234 /* 1235 * Intel recommends to set DFR, LDR and TPR before enabling 1236 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1237 * document number 292116). So here it goes... 1238 */ 1239 apic->init_apic_ldr(); 1240 1241 /* 1242 * Set Task Priority to 'accept all'. We never change this 1243 * later on. 1244 */ 1245 value = apic_read(APIC_TASKPRI); 1246 value &= ~APIC_TPRI_MASK; 1247 apic_write(APIC_TASKPRI, value); 1248 1249 /* 1250 * After a crash, we no longer service the interrupts and a pending 1251 * interrupt from previous kernel might still have ISR bit set. 1252 * 1253 * Most probably by now CPU has serviced that pending interrupt and 1254 * it might not have done the ack_APIC_irq() because it thought, 1255 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it 1256 * does not clear the ISR bit and cpu thinks it has already serivced 1257 * the interrupt. Hence a vector might get locked. It was noticed 1258 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. 1259 */ 1260 do { 1261 queued = 0; 1262 for (i = APIC_ISR_NR - 1; i >= 0; i--) 1263 queued |= apic_read(APIC_IRR + i*0x10); 1264 1265 for (i = APIC_ISR_NR - 1; i >= 0; i--) { 1266 value = apic_read(APIC_ISR + i*0x10); 1267 for (j = 31; j >= 0; j--) { 1268 if (value & (1<<j)) { 1269 ack_APIC_irq(); 1270 acked++; 1271 } 1272 } 1273 } 1274 if (acked > 256) { 1275 printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n", 1276 acked); 1277 break; 1278 } 1279 if (cpu_has_tsc) { 1280 rdtscll(ntsc); 1281 max_loops = (cpu_khz << 10) - (ntsc - tsc); 1282 } else 1283 max_loops--; 1284 } while (queued && max_loops > 0); 1285 WARN_ON(max_loops <= 0); 1286 1287 /* 1288 * Now that we are all set up, enable the APIC 1289 */ 1290 value = apic_read(APIC_SPIV); 1291 value &= ~APIC_VECTOR_MASK; 1292 /* 1293 * Enable APIC 1294 */ 1295 value |= APIC_SPIV_APIC_ENABLED; 1296 1297 #ifdef CONFIG_X86_32 1298 /* 1299 * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1300 * certain networking cards. If high frequency interrupts are 1301 * happening on a particular IOAPIC pin, plus the IOAPIC routing 1302 * entry is masked/unmasked at a high rate as well then sooner or 1303 * later IOAPIC line gets 'stuck', no more interrupts are received 1304 * from the device. If focus CPU is disabled then the hang goes 1305 * away, oh well :-( 1306 * 1307 * [ This bug can be reproduced easily with a level-triggered 1308 * PCI Ne2000 networking cards and PII/PIII processors, dual 1309 * BX chipset. ] 1310 */ 1311 /* 1312 * Actually disabling the focus CPU check just makes the hang less 1313 * frequent as it makes the interrupt distributon model be more 1314 * like LRU than MRU (the short-term load is more even across CPUs). 1315 * See also the comment in end_level_ioapic_irq(). --macro 1316 */ 1317 1318 /* 1319 * - enable focus processor (bit==0) 1320 * - 64bit mode always use processor focus 1321 * so no need to set it 1322 */ 1323 value &= ~APIC_SPIV_FOCUS_DISABLED; 1324 #endif 1325 1326 /* 1327 * Set spurious IRQ vector 1328 */ 1329 value |= SPURIOUS_APIC_VECTOR; 1330 apic_write(APIC_SPIV, value); 1331 1332 /* 1333 * Set up LVT0, LVT1: 1334 * 1335 * set up through-local-APIC on the BP's LINT0. This is not 1336 * strictly necessary in pure symmetric-IO mode, but sometimes 1337 * we delegate interrupts to the 8259A. 1338 */ 1339 /* 1340 * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1341 */ 1342 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 1343 if (!cpu && (pic_mode || !value)) { 1344 value = APIC_DM_EXTINT; 1345 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); 1346 } else { 1347 value = APIC_DM_EXTINT | APIC_LVT_MASKED; 1348 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); 1349 } 1350 apic_write(APIC_LVT0, value); 1351 1352 /* 1353 * only the BP should see the LINT1 NMI signal, obviously. 1354 */ 1355 if (!cpu) 1356 value = APIC_DM_NMI; 1357 else 1358 value = APIC_DM_NMI | APIC_LVT_MASKED; 1359 if (!lapic_is_integrated()) /* 82489DX */ 1360 value |= APIC_LVT_LEVEL_TRIGGER; 1361 apic_write(APIC_LVT1, value); 1362 1363 #ifdef CONFIG_X86_MCE_INTEL 1364 /* Recheck CMCI information after local APIC is up on CPU #0 */ 1365 if (!cpu) 1366 cmci_recheck(); 1367 #endif 1368 } 1369 1370 void __cpuinit end_local_APIC_setup(void) 1371 { 1372 lapic_setup_esr(); 1373 1374 #ifdef CONFIG_X86_32 1375 { 1376 unsigned int value; 1377 /* Disable the local apic timer */ 1378 value = apic_read(APIC_LVTT); 1379 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1380 apic_write(APIC_LVTT, value); 1381 } 1382 #endif 1383 1384 apic_pm_activate(); 1385 } 1386 1387 void __init bsp_end_local_APIC_setup(void) 1388 { 1389 end_local_APIC_setup(); 1390 1391 /* 1392 * Now that local APIC setup is completed for BP, configure the fault 1393 * handling for interrupt remapping. 1394 */ 1395 if (intr_remapping_enabled) 1396 enable_drhd_fault_handling(); 1397 1398 } 1399 1400 #ifdef CONFIG_X86_X2APIC 1401 void check_x2apic(void) 1402 { 1403 if (x2apic_enabled()) { 1404 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n"); 1405 x2apic_preenabled = x2apic_mode = 1; 1406 } 1407 } 1408 1409 void enable_x2apic(void) 1410 { 1411 int msr, msr2; 1412 1413 if (!x2apic_mode) 1414 return; 1415 1416 rdmsr(MSR_IA32_APICBASE, msr, msr2); 1417 if (!(msr & X2APIC_ENABLE)) { 1418 printk_once(KERN_INFO "Enabling x2apic\n"); 1419 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); 1420 } 1421 } 1422 #endif /* CONFIG_X86_X2APIC */ 1423 1424 int __init enable_IR(void) 1425 { 1426 #ifdef CONFIG_INTR_REMAP 1427 if (!intr_remapping_supported()) { 1428 pr_debug("intr-remapping not supported\n"); 1429 return 0; 1430 } 1431 1432 if (!x2apic_preenabled && skip_ioapic_setup) { 1433 pr_info("Skipped enabling intr-remap because of skipping " 1434 "io-apic setup\n"); 1435 return 0; 1436 } 1437 1438 if (enable_intr_remapping(x2apic_supported())) 1439 return 0; 1440 1441 pr_info("Enabled Interrupt-remapping\n"); 1442 1443 return 1; 1444 1445 #endif 1446 return 0; 1447 } 1448 1449 void __init enable_IR_x2apic(void) 1450 { 1451 unsigned long flags; 1452 struct IO_APIC_route_entry **ioapic_entries; 1453 int ret, x2apic_enabled = 0; 1454 int dmar_table_init_ret; 1455 1456 dmar_table_init_ret = dmar_table_init(); 1457 if (dmar_table_init_ret && !x2apic_supported()) 1458 return; 1459 1460 ioapic_entries = alloc_ioapic_entries(); 1461 if (!ioapic_entries) { 1462 pr_err("Allocate ioapic_entries failed\n"); 1463 goto out; 1464 } 1465 1466 ret = save_IO_APIC_setup(ioapic_entries); 1467 if (ret) { 1468 pr_info("Saving IO-APIC state failed: %d\n", ret); 1469 goto out; 1470 } 1471 1472 local_irq_save(flags); 1473 legacy_pic->mask_all(); 1474 mask_IO_APIC_setup(ioapic_entries); 1475 1476 if (dmar_table_init_ret) 1477 ret = 0; 1478 else 1479 ret = enable_IR(); 1480 1481 if (!ret) { 1482 /* IR is required if there is APIC ID > 255 even when running 1483 * under KVM 1484 */ 1485 if (max_physical_apicid > 255 || 1486 !hypervisor_x2apic_available()) 1487 goto nox2apic; 1488 /* 1489 * without IR all CPUs can be addressed by IOAPIC/MSI 1490 * only in physical mode 1491 */ 1492 x2apic_force_phys(); 1493 } 1494 1495 x2apic_enabled = 1; 1496 1497 if (x2apic_supported() && !x2apic_mode) { 1498 x2apic_mode = 1; 1499 enable_x2apic(); 1500 pr_info("Enabled x2apic\n"); 1501 } 1502 1503 nox2apic: 1504 if (!ret) /* IR enabling failed */ 1505 restore_IO_APIC_setup(ioapic_entries); 1506 legacy_pic->restore_mask(); 1507 local_irq_restore(flags); 1508 1509 out: 1510 if (ioapic_entries) 1511 free_ioapic_entries(ioapic_entries); 1512 1513 if (x2apic_enabled) 1514 return; 1515 1516 if (x2apic_preenabled) 1517 panic("x2apic: enabled by BIOS but kernel init failed."); 1518 else if (cpu_has_x2apic) 1519 pr_info("Not enabling x2apic, Intr-remapping init failed.\n"); 1520 } 1521 1522 #ifdef CONFIG_X86_64 1523 /* 1524 * Detect and enable local APICs on non-SMP boards. 1525 * Original code written by Keir Fraser. 1526 * On AMD64 we trust the BIOS - if it says no APIC it is likely 1527 * not correctly set up (usually the APIC timer won't work etc.) 1528 */ 1529 static int __init detect_init_APIC(void) 1530 { 1531 if (!cpu_has_apic) { 1532 pr_info("No local APIC present\n"); 1533 return -1; 1534 } 1535 1536 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1537 return 0; 1538 } 1539 #else 1540 1541 static int apic_verify(void) 1542 { 1543 u32 features, h, l; 1544 1545 /* 1546 * The APIC feature bit should now be enabled 1547 * in `cpuid' 1548 */ 1549 features = cpuid_edx(1); 1550 if (!(features & (1 << X86_FEATURE_APIC))) { 1551 pr_warning("Could not enable APIC!\n"); 1552 return -1; 1553 } 1554 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 1555 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1556 1557 /* The BIOS may have set up the APIC at some other address */ 1558 rdmsr(MSR_IA32_APICBASE, l, h); 1559 if (l & MSR_IA32_APICBASE_ENABLE) 1560 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 1561 1562 pr_info("Found and enabled local APIC!\n"); 1563 return 0; 1564 } 1565 1566 int apic_force_enable(void) 1567 { 1568 u32 h, l; 1569 1570 if (disable_apic) 1571 return -1; 1572 1573 /* 1574 * Some BIOSes disable the local APIC in the APIC_BASE 1575 * MSR. This can only be done in software for Intel P6 or later 1576 * and AMD K7 (Model > 1) or later. 1577 */ 1578 rdmsr(MSR_IA32_APICBASE, l, h); 1579 if (!(l & MSR_IA32_APICBASE_ENABLE)) { 1580 pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 1581 l &= ~MSR_IA32_APICBASE_BASE; 1582 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; 1583 wrmsr(MSR_IA32_APICBASE, l, h); 1584 enabled_via_apicbase = 1; 1585 } 1586 return apic_verify(); 1587 } 1588 1589 /* 1590 * Detect and initialize APIC 1591 */ 1592 static int __init detect_init_APIC(void) 1593 { 1594 /* Disabled by kernel option? */ 1595 if (disable_apic) 1596 return -1; 1597 1598 switch (boot_cpu_data.x86_vendor) { 1599 case X86_VENDOR_AMD: 1600 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 1601 (boot_cpu_data.x86 >= 15)) 1602 break; 1603 goto no_apic; 1604 case X86_VENDOR_INTEL: 1605 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 1606 (boot_cpu_data.x86 == 5 && cpu_has_apic)) 1607 break; 1608 goto no_apic; 1609 default: 1610 goto no_apic; 1611 } 1612 1613 if (!cpu_has_apic) { 1614 /* 1615 * Over-ride BIOS and try to enable the local APIC only if 1616 * "lapic" specified. 1617 */ 1618 if (!force_enable_local_apic) { 1619 pr_info("Local APIC disabled by BIOS -- " 1620 "you can enable it with \"lapic\"\n"); 1621 return -1; 1622 } 1623 if (apic_force_enable()) 1624 return -1; 1625 } else { 1626 if (apic_verify()) 1627 return -1; 1628 } 1629 1630 apic_pm_activate(); 1631 1632 return 0; 1633 1634 no_apic: 1635 pr_info("No local APIC present or hardware disabled\n"); 1636 return -1; 1637 } 1638 #endif 1639 1640 /** 1641 * init_apic_mappings - initialize APIC mappings 1642 */ 1643 void __init init_apic_mappings(void) 1644 { 1645 unsigned int new_apicid; 1646 1647 if (x2apic_mode) { 1648 boot_cpu_physical_apicid = read_apic_id(); 1649 return; 1650 } 1651 1652 /* If no local APIC can be found return early */ 1653 if (!smp_found_config && detect_init_APIC()) { 1654 /* lets NOP'ify apic operations */ 1655 pr_info("APIC: disable apic facility\n"); 1656 apic_disable(); 1657 } else { 1658 apic_phys = mp_lapic_addr; 1659 1660 /* 1661 * acpi lapic path already maps that address in 1662 * acpi_register_lapic_address() 1663 */ 1664 if (!acpi_lapic && !smp_found_config) 1665 register_lapic_address(apic_phys); 1666 } 1667 1668 /* 1669 * Fetch the APIC ID of the BSP in case we have a 1670 * default configuration (or the MP table is broken). 1671 */ 1672 new_apicid = read_apic_id(); 1673 if (boot_cpu_physical_apicid != new_apicid) { 1674 boot_cpu_physical_apicid = new_apicid; 1675 /* 1676 * yeah -- we lie about apic_version 1677 * in case if apic was disabled via boot option 1678 * but it's not a problem for SMP compiled kernel 1679 * since smp_sanity_check is prepared for such a case 1680 * and disable smp mode 1681 */ 1682 apic_version[new_apicid] = 1683 GET_APIC_VERSION(apic_read(APIC_LVR)); 1684 } 1685 } 1686 1687 void __init register_lapic_address(unsigned long address) 1688 { 1689 mp_lapic_addr = address; 1690 1691 if (!x2apic_mode) { 1692 set_fixmap_nocache(FIX_APIC_BASE, address); 1693 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 1694 APIC_BASE, mp_lapic_addr); 1695 } 1696 if (boot_cpu_physical_apicid == -1U) { 1697 boot_cpu_physical_apicid = read_apic_id(); 1698 apic_version[boot_cpu_physical_apicid] = 1699 GET_APIC_VERSION(apic_read(APIC_LVR)); 1700 } 1701 } 1702 1703 /* 1704 * This initializes the IO-APIC and APIC hardware if this is 1705 * a UP kernel. 1706 */ 1707 int apic_version[MAX_LOCAL_APIC]; 1708 1709 int __init APIC_init_uniprocessor(void) 1710 { 1711 if (disable_apic) { 1712 pr_info("Apic disabled\n"); 1713 return -1; 1714 } 1715 #ifdef CONFIG_X86_64 1716 if (!cpu_has_apic) { 1717 disable_apic = 1; 1718 pr_info("Apic disabled by BIOS\n"); 1719 return -1; 1720 } 1721 #else 1722 if (!smp_found_config && !cpu_has_apic) 1723 return -1; 1724 1725 /* 1726 * Complain if the BIOS pretends there is one. 1727 */ 1728 if (!cpu_has_apic && 1729 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 1730 pr_err("BIOS bug, local APIC 0x%x not detected!...\n", 1731 boot_cpu_physical_apicid); 1732 return -1; 1733 } 1734 #endif 1735 1736 default_setup_apic_routing(); 1737 1738 verify_local_APIC(); 1739 connect_bsp_APIC(); 1740 1741 #ifdef CONFIG_X86_64 1742 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); 1743 #else 1744 /* 1745 * Hack: In case of kdump, after a crash, kernel might be booting 1746 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 1747 * might be zero if read from MP tables. Get it from LAPIC. 1748 */ 1749 # ifdef CONFIG_CRASH_DUMP 1750 boot_cpu_physical_apicid = read_apic_id(); 1751 # endif 1752 #endif 1753 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1754 setup_local_APIC(); 1755 1756 #ifdef CONFIG_X86_IO_APIC 1757 /* 1758 * Now enable IO-APICs, actually call clear_IO_APIC 1759 * We need clear_IO_APIC before enabling error vector 1760 */ 1761 if (!skip_ioapic_setup && nr_ioapics) 1762 enable_IO_APIC(); 1763 #endif 1764 1765 bsp_end_local_APIC_setup(); 1766 1767 #ifdef CONFIG_X86_IO_APIC 1768 if (smp_found_config && !skip_ioapic_setup && nr_ioapics) 1769 setup_IO_APIC(); 1770 else { 1771 nr_ioapics = 0; 1772 } 1773 #endif 1774 1775 x86_init.timers.setup_percpu_clockev(); 1776 return 0; 1777 } 1778 1779 /* 1780 * Local APIC interrupts 1781 */ 1782 1783 /* 1784 * This interrupt should _never_ happen with our APIC/SMP architecture 1785 */ 1786 void smp_spurious_interrupt(struct pt_regs *regs) 1787 { 1788 u32 v; 1789 1790 exit_idle(); 1791 irq_enter(); 1792 /* 1793 * Check if this really is a spurious interrupt and ACK it 1794 * if it is a vectored one. Just in case... 1795 * Spurious interrupts should not be ACKed. 1796 */ 1797 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); 1798 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) 1799 ack_APIC_irq(); 1800 1801 inc_irq_stat(irq_spurious_count); 1802 1803 /* see sw-dev-man vol 3, chapter 7.4.13.5 */ 1804 pr_info("spurious APIC interrupt on CPU#%d, " 1805 "should never happen.\n", smp_processor_id()); 1806 irq_exit(); 1807 } 1808 1809 /* 1810 * This interrupt should never happen with our APIC/SMP architecture 1811 */ 1812 void smp_error_interrupt(struct pt_regs *regs) 1813 { 1814 u32 v, v1; 1815 1816 exit_idle(); 1817 irq_enter(); 1818 /* First tickle the hardware, only then report what went on. -- REW */ 1819 v = apic_read(APIC_ESR); 1820 apic_write(APIC_ESR, 0); 1821 v1 = apic_read(APIC_ESR); 1822 ack_APIC_irq(); 1823 atomic_inc(&irq_err_count); 1824 1825 /* 1826 * Here is what the APIC error bits mean: 1827 * 0: Send CS error 1828 * 1: Receive CS error 1829 * 2: Send accept error 1830 * 3: Receive accept error 1831 * 4: Reserved 1832 * 5: Send illegal vector 1833 * 6: Received illegal vector 1834 * 7: Illegal register address 1835 */ 1836 pr_debug("APIC error on CPU%d: %02x(%02x)\n", 1837 smp_processor_id(), v , v1); 1838 irq_exit(); 1839 } 1840 1841 /** 1842 * connect_bsp_APIC - attach the APIC to the interrupt system 1843 */ 1844 void __init connect_bsp_APIC(void) 1845 { 1846 #ifdef CONFIG_X86_32 1847 if (pic_mode) { 1848 /* 1849 * Do not trust the local APIC being empty at bootup. 1850 */ 1851 clear_local_APIC(); 1852 /* 1853 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 1854 * local APIC to INT and NMI lines. 1855 */ 1856 apic_printk(APIC_VERBOSE, "leaving PIC mode, " 1857 "enabling APIC mode.\n"); 1858 imcr_pic_to_apic(); 1859 } 1860 #endif 1861 if (apic->enable_apic_mode) 1862 apic->enable_apic_mode(); 1863 } 1864 1865 /** 1866 * disconnect_bsp_APIC - detach the APIC from the interrupt system 1867 * @virt_wire_setup: indicates, whether virtual wire mode is selected 1868 * 1869 * Virtual wire mode is necessary to deliver legacy interrupts even when the 1870 * APIC is disabled. 1871 */ 1872 void disconnect_bsp_APIC(int virt_wire_setup) 1873 { 1874 unsigned int value; 1875 1876 #ifdef CONFIG_X86_32 1877 if (pic_mode) { 1878 /* 1879 * Put the board back into PIC mode (has an effect only on 1880 * certain older boards). Note that APIC interrupts, including 1881 * IPIs, won't work beyond this point! The only exception are 1882 * INIT IPIs. 1883 */ 1884 apic_printk(APIC_VERBOSE, "disabling APIC mode, " 1885 "entering PIC mode.\n"); 1886 imcr_apic_to_pic(); 1887 return; 1888 } 1889 #endif 1890 1891 /* Go back to Virtual Wire compatibility mode */ 1892 1893 /* For the spurious interrupt use vector F, and enable it */ 1894 value = apic_read(APIC_SPIV); 1895 value &= ~APIC_VECTOR_MASK; 1896 value |= APIC_SPIV_APIC_ENABLED; 1897 value |= 0xf; 1898 apic_write(APIC_SPIV, value); 1899 1900 if (!virt_wire_setup) { 1901 /* 1902 * For LVT0 make it edge triggered, active high, 1903 * external and enabled 1904 */ 1905 value = apic_read(APIC_LVT0); 1906 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 1907 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 1908 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 1909 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 1910 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 1911 apic_write(APIC_LVT0, value); 1912 } else { 1913 /* Disable LVT0 */ 1914 apic_write(APIC_LVT0, APIC_LVT_MASKED); 1915 } 1916 1917 /* 1918 * For LVT1 make it edge triggered, active high, 1919 * nmi and enabled 1920 */ 1921 value = apic_read(APIC_LVT1); 1922 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 1923 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 1924 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 1925 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 1926 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 1927 apic_write(APIC_LVT1, value); 1928 } 1929 1930 void __cpuinit generic_processor_info(int apicid, int version) 1931 { 1932 int cpu; 1933 1934 /* 1935 * Validate version 1936 */ 1937 if (version == 0x0) { 1938 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! " 1939 "fixing up to 0x10. (tell your hw vendor)\n", 1940 version); 1941 version = 0x10; 1942 } 1943 apic_version[apicid] = version; 1944 1945 if (num_processors >= nr_cpu_ids) { 1946 int max = nr_cpu_ids; 1947 int thiscpu = max + disabled_cpus; 1948 1949 pr_warning( 1950 "ACPI: NR_CPUS/possible_cpus limit of %i reached." 1951 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 1952 1953 disabled_cpus++; 1954 return; 1955 } 1956 1957 num_processors++; 1958 cpu = cpumask_next_zero(-1, cpu_present_mask); 1959 1960 if (version != apic_version[boot_cpu_physical_apicid]) 1961 WARN_ONCE(1, 1962 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n", 1963 apic_version[boot_cpu_physical_apicid], cpu, version); 1964 1965 physid_set(apicid, phys_cpu_present_map); 1966 if (apicid == boot_cpu_physical_apicid) { 1967 /* 1968 * x86_bios_cpu_apicid is required to have processors listed 1969 * in same order as logical cpu numbers. Hence the first 1970 * entry is BSP, and so on. 1971 */ 1972 cpu = 0; 1973 } 1974 if (apicid > max_physical_apicid) 1975 max_physical_apicid = apicid; 1976 1977 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 1978 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 1979 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 1980 #endif 1981 1982 set_cpu_possible(cpu, true); 1983 set_cpu_present(cpu, true); 1984 } 1985 1986 int hard_smp_processor_id(void) 1987 { 1988 return read_apic_id(); 1989 } 1990 1991 void default_init_apic_ldr(void) 1992 { 1993 unsigned long val; 1994 1995 apic_write(APIC_DFR, APIC_DFR_VALUE); 1996 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; 1997 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); 1998 apic_write(APIC_LDR, val); 1999 } 2000 2001 #ifdef CONFIG_X86_32 2002 int default_apicid_to_node(int logical_apicid) 2003 { 2004 #ifdef CONFIG_SMP 2005 return apicid_2_node[hard_smp_processor_id()]; 2006 #else 2007 return 0; 2008 #endif 2009 } 2010 #endif 2011 2012 /* 2013 * Power management 2014 */ 2015 #ifdef CONFIG_PM 2016 2017 static struct { 2018 /* 2019 * 'active' is true if the local APIC was enabled by us and 2020 * not the BIOS; this signifies that we are also responsible 2021 * for disabling it before entering apm/acpi suspend 2022 */ 2023 int active; 2024 /* r/w apic fields */ 2025 unsigned int apic_id; 2026 unsigned int apic_taskpri; 2027 unsigned int apic_ldr; 2028 unsigned int apic_dfr; 2029 unsigned int apic_spiv; 2030 unsigned int apic_lvtt; 2031 unsigned int apic_lvtpc; 2032 unsigned int apic_lvt0; 2033 unsigned int apic_lvt1; 2034 unsigned int apic_lvterr; 2035 unsigned int apic_tmict; 2036 unsigned int apic_tdcr; 2037 unsigned int apic_thmr; 2038 } apic_pm_state; 2039 2040 static int lapic_suspend(struct sys_device *dev, pm_message_t state) 2041 { 2042 unsigned long flags; 2043 int maxlvt; 2044 2045 if (!apic_pm_state.active) 2046 return 0; 2047 2048 maxlvt = lapic_get_maxlvt(); 2049 2050 apic_pm_state.apic_id = apic_read(APIC_ID); 2051 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 2052 apic_pm_state.apic_ldr = apic_read(APIC_LDR); 2053 apic_pm_state.apic_dfr = apic_read(APIC_DFR); 2054 apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2055 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2056 if (maxlvt >= 4) 2057 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2058 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2059 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2060 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2061 apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2062 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 2063 #ifdef CONFIG_X86_THERMAL_VECTOR 2064 if (maxlvt >= 5) 2065 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2066 #endif 2067 2068 local_irq_save(flags); 2069 disable_local_APIC(); 2070 2071 if (intr_remapping_enabled) 2072 disable_intr_remapping(); 2073 2074 local_irq_restore(flags); 2075 return 0; 2076 } 2077 2078 static int lapic_resume(struct sys_device *dev) 2079 { 2080 unsigned int l, h; 2081 unsigned long flags; 2082 int maxlvt; 2083 int ret = 0; 2084 struct IO_APIC_route_entry **ioapic_entries = NULL; 2085 2086 if (!apic_pm_state.active) 2087 return 0; 2088 2089 local_irq_save(flags); 2090 if (intr_remapping_enabled) { 2091 ioapic_entries = alloc_ioapic_entries(); 2092 if (!ioapic_entries) { 2093 WARN(1, "Alloc ioapic_entries in lapic resume failed."); 2094 ret = -ENOMEM; 2095 goto restore; 2096 } 2097 2098 ret = save_IO_APIC_setup(ioapic_entries); 2099 if (ret) { 2100 WARN(1, "Saving IO-APIC state failed: %d\n", ret); 2101 free_ioapic_entries(ioapic_entries); 2102 goto restore; 2103 } 2104 2105 mask_IO_APIC_setup(ioapic_entries); 2106 legacy_pic->mask_all(); 2107 } 2108 2109 if (x2apic_mode) 2110 enable_x2apic(); 2111 else { 2112 /* 2113 * Make sure the APICBASE points to the right address 2114 * 2115 * FIXME! This will be wrong if we ever support suspend on 2116 * SMP! We'll need to do this as part of the CPU restore! 2117 */ 2118 rdmsr(MSR_IA32_APICBASE, l, h); 2119 l &= ~MSR_IA32_APICBASE_BASE; 2120 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2121 wrmsr(MSR_IA32_APICBASE, l, h); 2122 } 2123 2124 maxlvt = lapic_get_maxlvt(); 2125 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2126 apic_write(APIC_ID, apic_pm_state.apic_id); 2127 apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2128 apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2129 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2130 apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2131 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2132 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 2133 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) 2134 if (maxlvt >= 5) 2135 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2136 #endif 2137 if (maxlvt >= 4) 2138 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2139 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2140 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2141 apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2142 apic_write(APIC_ESR, 0); 2143 apic_read(APIC_ESR); 2144 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2145 apic_write(APIC_ESR, 0); 2146 apic_read(APIC_ESR); 2147 2148 if (intr_remapping_enabled) { 2149 reenable_intr_remapping(x2apic_mode); 2150 legacy_pic->restore_mask(); 2151 restore_IO_APIC_setup(ioapic_entries); 2152 free_ioapic_entries(ioapic_entries); 2153 } 2154 restore: 2155 local_irq_restore(flags); 2156 2157 return ret; 2158 } 2159 2160 /* 2161 * This device has no shutdown method - fully functioning local APICs 2162 * are needed on every CPU up until machine_halt/restart/poweroff. 2163 */ 2164 2165 static struct sysdev_class lapic_sysclass = { 2166 .name = "lapic", 2167 .resume = lapic_resume, 2168 .suspend = lapic_suspend, 2169 }; 2170 2171 static struct sys_device device_lapic = { 2172 .id = 0, 2173 .cls = &lapic_sysclass, 2174 }; 2175 2176 static void __cpuinit apic_pm_activate(void) 2177 { 2178 apic_pm_state.active = 1; 2179 } 2180 2181 static int __init init_lapic_sysfs(void) 2182 { 2183 int error; 2184 2185 if (!cpu_has_apic) 2186 return 0; 2187 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 2188 2189 error = sysdev_class_register(&lapic_sysclass); 2190 if (!error) 2191 error = sysdev_register(&device_lapic); 2192 return error; 2193 } 2194 2195 /* local apic needs to resume before other devices access its registers. */ 2196 core_initcall(init_lapic_sysfs); 2197 2198 #else /* CONFIG_PM */ 2199 2200 static void apic_pm_activate(void) { } 2201 2202 #endif /* CONFIG_PM */ 2203 2204 #ifdef CONFIG_X86_64 2205 2206 static int __cpuinit apic_cluster_num(void) 2207 { 2208 int i, clusters, zeros; 2209 unsigned id; 2210 u16 *bios_cpu_apicid; 2211 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); 2212 2213 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); 2214 bitmap_zero(clustermap, NUM_APIC_CLUSTERS); 2215 2216 for (i = 0; i < nr_cpu_ids; i++) { 2217 /* are we being called early in kernel startup? */ 2218 if (bios_cpu_apicid) { 2219 id = bios_cpu_apicid[i]; 2220 } else if (i < nr_cpu_ids) { 2221 if (cpu_present(i)) 2222 id = per_cpu(x86_bios_cpu_apicid, i); 2223 else 2224 continue; 2225 } else 2226 break; 2227 2228 if (id != BAD_APICID) 2229 __set_bit(APIC_CLUSTERID(id), clustermap); 2230 } 2231 2232 /* Problem: Partially populated chassis may not have CPUs in some of 2233 * the APIC clusters they have been allocated. Only present CPUs have 2234 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. 2235 * Since clusters are allocated sequentially, count zeros only if 2236 * they are bounded by ones. 2237 */ 2238 clusters = 0; 2239 zeros = 0; 2240 for (i = 0; i < NUM_APIC_CLUSTERS; i++) { 2241 if (test_bit(i, clustermap)) { 2242 clusters += 1 + zeros; 2243 zeros = 0; 2244 } else 2245 ++zeros; 2246 } 2247 2248 return clusters; 2249 } 2250 2251 static int __cpuinitdata multi_checked; 2252 static int __cpuinitdata multi; 2253 2254 static int __cpuinit set_multi(const struct dmi_system_id *d) 2255 { 2256 if (multi) 2257 return 0; 2258 pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2259 multi = 1; 2260 return 0; 2261 } 2262 2263 static const __cpuinitconst struct dmi_system_id multi_dmi_table[] = { 2264 { 2265 .callback = set_multi, 2266 .ident = "IBM System Summit2", 2267 .matches = { 2268 DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2269 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2270 }, 2271 }, 2272 {} 2273 }; 2274 2275 static void __cpuinit dmi_check_multi(void) 2276 { 2277 if (multi_checked) 2278 return; 2279 2280 dmi_check_system(multi_dmi_table); 2281 multi_checked = 1; 2282 } 2283 2284 /* 2285 * apic_is_clustered_box() -- Check if we can expect good TSC 2286 * 2287 * Thus far, the major user of this is IBM's Summit2 series: 2288 * Clustered boxes may have unsynced TSC problems if they are 2289 * multi-chassis. 2290 * Use DMI to check them 2291 */ 2292 __cpuinit int apic_is_clustered_box(void) 2293 { 2294 dmi_check_multi(); 2295 if (multi) 2296 return 1; 2297 2298 if (!is_vsmp_box()) 2299 return 0; 2300 2301 /* 2302 * ScaleMP vSMPowered boxes have one cluster per board and TSCs are 2303 * not guaranteed to be synced between boards 2304 */ 2305 if (apic_cluster_num() > 1) 2306 return 1; 2307 2308 return 0; 2309 } 2310 #endif 2311 2312 /* 2313 * APIC command line parameters 2314 */ 2315 static int __init setup_disableapic(char *arg) 2316 { 2317 disable_apic = 1; 2318 setup_clear_cpu_cap(X86_FEATURE_APIC); 2319 return 0; 2320 } 2321 early_param("disableapic", setup_disableapic); 2322 2323 /* same as disableapic, for compatibility */ 2324 static int __init setup_nolapic(char *arg) 2325 { 2326 return setup_disableapic(arg); 2327 } 2328 early_param("nolapic", setup_nolapic); 2329 2330 static int __init parse_lapic_timer_c2_ok(char *arg) 2331 { 2332 local_apic_timer_c2_ok = 1; 2333 return 0; 2334 } 2335 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2336 2337 static int __init parse_disable_apic_timer(char *arg) 2338 { 2339 disable_apic_timer = 1; 2340 return 0; 2341 } 2342 early_param("noapictimer", parse_disable_apic_timer); 2343 2344 static int __init parse_nolapic_timer(char *arg) 2345 { 2346 disable_apic_timer = 1; 2347 return 0; 2348 } 2349 early_param("nolapic_timer", parse_nolapic_timer); 2350 2351 static int __init apic_set_verbosity(char *arg) 2352 { 2353 if (!arg) { 2354 #ifdef CONFIG_X86_64 2355 skip_ioapic_setup = 0; 2356 return 0; 2357 #endif 2358 return -EINVAL; 2359 } 2360 2361 if (strcmp("debug", arg) == 0) 2362 apic_verbosity = APIC_DEBUG; 2363 else if (strcmp("verbose", arg) == 0) 2364 apic_verbosity = APIC_VERBOSE; 2365 else { 2366 pr_warning("APIC Verbosity level %s not recognised" 2367 " use apic=verbose or apic=debug\n", arg); 2368 return -EINVAL; 2369 } 2370 2371 return 0; 2372 } 2373 early_param("apic", apic_set_verbosity); 2374 2375 static int __init lapic_insert_resource(void) 2376 { 2377 if (!apic_phys) 2378 return -1; 2379 2380 /* Put local APIC into the resource map. */ 2381 lapic_resource.start = apic_phys; 2382 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2383 insert_resource(&iomem_resource, &lapic_resource); 2384 2385 return 0; 2386 } 2387 2388 /* 2389 * need call insert after e820_reserve_resources() 2390 * that is using request_resource 2391 */ 2392 late_initcall(lapic_insert_resource); 2393