1 /* 2 * Local APIC handling, local APIC timers 3 * 4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 5 * 6 * Fixes 7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 8 * thanks to Eric Gilmore 9 * and Rolf G. Tews 10 * for testing these extensively. 11 * Maciej W. Rozycki : Various updates and fixes. 12 * Mikael Pettersson : Power Management for UP-APIC. 13 * Pavel Machek and 14 * Mikael Pettersson : PM converted to driver model. 15 */ 16 17 #include <linux/perf_event.h> 18 #include <linux/kernel_stat.h> 19 #include <linux/mc146818rtc.h> 20 #include <linux/acpi_pmtmr.h> 21 #include <linux/clockchips.h> 22 #include <linux/interrupt.h> 23 #include <linux/bootmem.h> 24 #include <linux/ftrace.h> 25 #include <linux/ioport.h> 26 #include <linux/module.h> 27 #include <linux/syscore_ops.h> 28 #include <linux/delay.h> 29 #include <linux/timex.h> 30 #include <linux/i8253.h> 31 #include <linux/dmar.h> 32 #include <linux/init.h> 33 #include <linux/cpu.h> 34 #include <linux/dmi.h> 35 #include <linux/smp.h> 36 #include <linux/mm.h> 37 38 #include <asm/trace/irq_vectors.h> 39 #include <asm/irq_remapping.h> 40 #include <asm/perf_event.h> 41 #include <asm/x86_init.h> 42 #include <asm/pgalloc.h> 43 #include <linux/atomic.h> 44 #include <asm/mpspec.h> 45 #include <asm/i8259.h> 46 #include <asm/proto.h> 47 #include <asm/apic.h> 48 #include <asm/io_apic.h> 49 #include <asm/desc.h> 50 #include <asm/hpet.h> 51 #include <asm/idle.h> 52 #include <asm/mtrr.h> 53 #include <asm/time.h> 54 #include <asm/smp.h> 55 #include <asm/mce.h> 56 #include <asm/tsc.h> 57 #include <asm/hypervisor.h> 58 59 unsigned int num_processors; 60 61 unsigned disabled_cpus; 62 63 /* Processor that is doing the boot up */ 64 unsigned int boot_cpu_physical_apicid = -1U; 65 66 /* 67 * The highest APIC ID seen during enumeration. 68 */ 69 unsigned int max_physical_apicid; 70 71 /* 72 * Bitmask of physically existing CPUs: 73 */ 74 physid_mask_t phys_cpu_present_map; 75 76 /* 77 * Map cpu index to physical APIC ID 78 */ 79 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); 80 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID); 81 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 82 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 83 84 #ifdef CONFIG_X86_32 85 86 /* 87 * On x86_32, the mapping between cpu and logical apicid may vary 88 * depending on apic in use. The following early percpu variable is 89 * used for the mapping. This is where the behaviors of x86_64 and 32 90 * actually diverge. Let's keep it ugly for now. 91 */ 92 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID); 93 94 /* Local APIC was disabled by the BIOS and enabled by the kernel */ 95 static int enabled_via_apicbase; 96 97 /* 98 * Handle interrupt mode configuration register (IMCR). 99 * This register controls whether the interrupt signals 100 * that reach the BSP come from the master PIC or from the 101 * local APIC. Before entering Symmetric I/O Mode, either 102 * the BIOS or the operating system must switch out of 103 * PIC Mode by changing the IMCR. 104 */ 105 static inline void imcr_pic_to_apic(void) 106 { 107 /* select IMCR register */ 108 outb(0x70, 0x22); 109 /* NMI and 8259 INTR go through APIC */ 110 outb(0x01, 0x23); 111 } 112 113 static inline void imcr_apic_to_pic(void) 114 { 115 /* select IMCR register */ 116 outb(0x70, 0x22); 117 /* NMI and 8259 INTR go directly to BSP */ 118 outb(0x00, 0x23); 119 } 120 #endif 121 122 /* 123 * Knob to control our willingness to enable the local APIC. 124 * 125 * +1=force-enable 126 */ 127 static int force_enable_local_apic __initdata; 128 /* 129 * APIC command line parameters 130 */ 131 static int __init parse_lapic(char *arg) 132 { 133 if (config_enabled(CONFIG_X86_32) && !arg) 134 force_enable_local_apic = 1; 135 else if (arg && !strncmp(arg, "notscdeadline", 13)) 136 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 137 return 0; 138 } 139 early_param("lapic", parse_lapic); 140 141 #ifdef CONFIG_X86_64 142 static int apic_calibrate_pmtmr __initdata; 143 static __init int setup_apicpmtimer(char *s) 144 { 145 apic_calibrate_pmtmr = 1; 146 notsc_setup(NULL); 147 return 0; 148 } 149 __setup("apicpmtimer", setup_apicpmtimer); 150 #endif 151 152 int x2apic_mode; 153 #ifdef CONFIG_X86_X2APIC 154 /* x2apic enabled before OS handover */ 155 int x2apic_preenabled; 156 static int x2apic_disabled; 157 static int nox2apic; 158 static __init int setup_nox2apic(char *str) 159 { 160 if (x2apic_enabled()) { 161 int apicid = native_apic_msr_read(APIC_ID); 162 163 if (apicid >= 255) { 164 pr_warning("Apicid: %08x, cannot enforce nox2apic\n", 165 apicid); 166 return 0; 167 } 168 169 pr_warning("x2apic already enabled. will disable it\n"); 170 } else 171 setup_clear_cpu_cap(X86_FEATURE_X2APIC); 172 173 nox2apic = 1; 174 175 return 0; 176 } 177 early_param("nox2apic", setup_nox2apic); 178 #endif 179 180 unsigned long mp_lapic_addr; 181 int disable_apic; 182 /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 183 static int disable_apic_timer __initdata; 184 /* Local APIC timer works in C2 */ 185 int local_apic_timer_c2_ok; 186 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 187 188 int first_system_vector = 0xfe; 189 190 /* 191 * Debug level, exported for io_apic.c 192 */ 193 unsigned int apic_verbosity; 194 195 int pic_mode; 196 197 /* Have we found an MP table */ 198 int smp_found_config; 199 200 static struct resource lapic_resource = { 201 .name = "Local APIC", 202 .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 203 }; 204 205 unsigned int lapic_timer_frequency = 0; 206 207 static void apic_pm_activate(void); 208 209 static unsigned long apic_phys; 210 211 /* 212 * Get the LAPIC version 213 */ 214 static inline int lapic_get_version(void) 215 { 216 return GET_APIC_VERSION(apic_read(APIC_LVR)); 217 } 218 219 /* 220 * Check, if the APIC is integrated or a separate chip 221 */ 222 static inline int lapic_is_integrated(void) 223 { 224 #ifdef CONFIG_X86_64 225 return 1; 226 #else 227 return APIC_INTEGRATED(lapic_get_version()); 228 #endif 229 } 230 231 /* 232 * Check, whether this is a modern or a first generation APIC 233 */ 234 static int modern_apic(void) 235 { 236 /* AMD systems use old APIC versions, so check the CPU */ 237 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 238 boot_cpu_data.x86 >= 0xf) 239 return 1; 240 return lapic_get_version() >= 0x14; 241 } 242 243 /* 244 * right after this call apic become NOOP driven 245 * so apic->write/read doesn't do anything 246 */ 247 static void __init apic_disable(void) 248 { 249 pr_info("APIC: switched to apic NOOP\n"); 250 apic = &apic_noop; 251 } 252 253 void native_apic_wait_icr_idle(void) 254 { 255 while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 256 cpu_relax(); 257 } 258 259 u32 native_safe_apic_wait_icr_idle(void) 260 { 261 u32 send_status; 262 int timeout; 263 264 timeout = 0; 265 do { 266 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 267 if (!send_status) 268 break; 269 inc_irq_stat(icr_read_retry_count); 270 udelay(100); 271 } while (timeout++ < 1000); 272 273 return send_status; 274 } 275 276 void native_apic_icr_write(u32 low, u32 id) 277 { 278 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 279 apic_write(APIC_ICR, low); 280 } 281 282 u64 native_apic_icr_read(void) 283 { 284 u32 icr1, icr2; 285 286 icr2 = apic_read(APIC_ICR2); 287 icr1 = apic_read(APIC_ICR); 288 289 return icr1 | ((u64)icr2 << 32); 290 } 291 292 #ifdef CONFIG_X86_32 293 /** 294 * get_physical_broadcast - Get number of physical broadcast IDs 295 */ 296 int get_physical_broadcast(void) 297 { 298 return modern_apic() ? 0xff : 0xf; 299 } 300 #endif 301 302 /** 303 * lapic_get_maxlvt - get the maximum number of local vector table entries 304 */ 305 int lapic_get_maxlvt(void) 306 { 307 unsigned int v; 308 309 v = apic_read(APIC_LVR); 310 /* 311 * - we always have APIC integrated on 64bit mode 312 * - 82489DXs do not report # of LVT entries 313 */ 314 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; 315 } 316 317 /* 318 * Local APIC timer 319 */ 320 321 /* Clock divisor */ 322 #define APIC_DIVISOR 16 323 #define TSC_DIVISOR 32 324 325 /* 326 * This function sets up the local APIC timer, with a timeout of 327 * 'clocks' APIC bus clock. During calibration we actually call 328 * this function twice on the boot CPU, once with a bogus timeout 329 * value, second time for real. The other (noncalibrating) CPUs 330 * call this function only once, with the real, calibrated value. 331 * 332 * We do reads before writes even if unnecessary, to get around the 333 * P5 APIC double write bug. 334 */ 335 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 336 { 337 unsigned int lvtt_value, tmp_value; 338 339 lvtt_value = LOCAL_TIMER_VECTOR; 340 if (!oneshot) 341 lvtt_value |= APIC_LVT_TIMER_PERIODIC; 342 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 343 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE; 344 345 if (!lapic_is_integrated()) 346 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 347 348 if (!irqen) 349 lvtt_value |= APIC_LVT_MASKED; 350 351 apic_write(APIC_LVTT, lvtt_value); 352 353 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { 354 printk_once(KERN_DEBUG "TSC deadline timer enabled\n"); 355 return; 356 } 357 358 /* 359 * Divide PICLK by 16 360 */ 361 tmp_value = apic_read(APIC_TDCR); 362 apic_write(APIC_TDCR, 363 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 364 APIC_TDR_DIV_16); 365 366 if (!oneshot) 367 apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 368 } 369 370 /* 371 * Setup extended LVT, AMD specific 372 * 373 * Software should use the LVT offsets the BIOS provides. The offsets 374 * are determined by the subsystems using it like those for MCE 375 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts 376 * are supported. Beginning with family 10h at least 4 offsets are 377 * available. 378 * 379 * Since the offsets must be consistent for all cores, we keep track 380 * of the LVT offsets in software and reserve the offset for the same 381 * vector also to be used on other cores. An offset is freed by 382 * setting the entry to APIC_EILVT_MASKED. 383 * 384 * If the BIOS is right, there should be no conflicts. Otherwise a 385 * "[Firmware Bug]: ..." error message is generated. However, if 386 * software does not properly determines the offsets, it is not 387 * necessarily a BIOS bug. 388 */ 389 390 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; 391 392 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) 393 { 394 return (old & APIC_EILVT_MASKED) 395 || (new == APIC_EILVT_MASKED) 396 || ((new & ~APIC_EILVT_MASKED) == old); 397 } 398 399 static unsigned int reserve_eilvt_offset(int offset, unsigned int new) 400 { 401 unsigned int rsvd, vector; 402 403 if (offset >= APIC_EILVT_NR_MAX) 404 return ~0; 405 406 rsvd = atomic_read(&eilvt_offsets[offset]); 407 do { 408 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ 409 if (vector && !eilvt_entry_is_changeable(vector, new)) 410 /* may not change if vectors are different */ 411 return rsvd; 412 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); 413 } while (rsvd != new); 414 415 rsvd &= ~APIC_EILVT_MASKED; 416 if (rsvd && rsvd != vector) 417 pr_info("LVT offset %d assigned for vector 0x%02x\n", 418 offset, rsvd); 419 420 return new; 421 } 422 423 /* 424 * If mask=1, the LVT entry does not generate interrupts while mask=0 425 * enables the vector. See also the BKDGs. Must be called with 426 * preemption disabled. 427 */ 428 429 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) 430 { 431 unsigned long reg = APIC_EILVTn(offset); 432 unsigned int new, old, reserved; 433 434 new = (mask << 16) | (msg_type << 8) | vector; 435 old = apic_read(reg); 436 reserved = reserve_eilvt_offset(offset, new); 437 438 if (reserved != new) { 439 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 440 "vector 0x%x, but the register is already in use for " 441 "vector 0x%x on another cpu\n", 442 smp_processor_id(), reg, offset, new, reserved); 443 return -EINVAL; 444 } 445 446 if (!eilvt_entry_is_changeable(old, new)) { 447 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 448 "vector 0x%x, but the register is already in use for " 449 "vector 0x%x on this cpu\n", 450 smp_processor_id(), reg, offset, new, old); 451 return -EBUSY; 452 } 453 454 apic_write(reg, new); 455 456 return 0; 457 } 458 EXPORT_SYMBOL_GPL(setup_APIC_eilvt); 459 460 /* 461 * Program the next event, relative to now 462 */ 463 static int lapic_next_event(unsigned long delta, 464 struct clock_event_device *evt) 465 { 466 apic_write(APIC_TMICT, delta); 467 return 0; 468 } 469 470 static int lapic_next_deadline(unsigned long delta, 471 struct clock_event_device *evt) 472 { 473 u64 tsc; 474 475 rdtscll(tsc); 476 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); 477 return 0; 478 } 479 480 /* 481 * Setup the lapic timer in periodic or oneshot mode 482 */ 483 static void lapic_timer_setup(enum clock_event_mode mode, 484 struct clock_event_device *evt) 485 { 486 unsigned long flags; 487 unsigned int v; 488 489 /* Lapic used as dummy for broadcast ? */ 490 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 491 return; 492 493 local_irq_save(flags); 494 495 switch (mode) { 496 case CLOCK_EVT_MODE_PERIODIC: 497 case CLOCK_EVT_MODE_ONESHOT: 498 __setup_APIC_LVTT(lapic_timer_frequency, 499 mode != CLOCK_EVT_MODE_PERIODIC, 1); 500 break; 501 case CLOCK_EVT_MODE_UNUSED: 502 case CLOCK_EVT_MODE_SHUTDOWN: 503 v = apic_read(APIC_LVTT); 504 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 505 apic_write(APIC_LVTT, v); 506 apic_write(APIC_TMICT, 0); 507 break; 508 case CLOCK_EVT_MODE_RESUME: 509 /* Nothing to do here */ 510 break; 511 } 512 513 local_irq_restore(flags); 514 } 515 516 /* 517 * Local APIC timer broadcast function 518 */ 519 static void lapic_timer_broadcast(const struct cpumask *mask) 520 { 521 #ifdef CONFIG_SMP 522 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 523 #endif 524 } 525 526 527 /* 528 * The local apic timer can be used for any function which is CPU local. 529 */ 530 static struct clock_event_device lapic_clockevent = { 531 .name = "lapic", 532 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT 533 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, 534 .shift = 32, 535 .set_mode = lapic_timer_setup, 536 .set_next_event = lapic_next_event, 537 .broadcast = lapic_timer_broadcast, 538 .rating = 100, 539 .irq = -1, 540 }; 541 static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 542 543 /* 544 * Setup the local APIC timer for this CPU. Copy the initialized values 545 * of the boot CPU and register the clock event in the framework. 546 */ 547 static void setup_APIC_timer(void) 548 { 549 struct clock_event_device *levt = &__get_cpu_var(lapic_events); 550 551 if (this_cpu_has(X86_FEATURE_ARAT)) { 552 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 553 /* Make LAPIC timer preferrable over percpu HPET */ 554 lapic_clockevent.rating = 150; 555 } 556 557 memcpy(levt, &lapic_clockevent, sizeof(*levt)); 558 levt->cpumask = cpumask_of(smp_processor_id()); 559 560 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 561 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | 562 CLOCK_EVT_FEAT_DUMMY); 563 levt->set_next_event = lapic_next_deadline; 564 clockevents_config_and_register(levt, 565 (tsc_khz / TSC_DIVISOR) * 1000, 566 0xF, ~0UL); 567 } else 568 clockevents_register_device(levt); 569 } 570 571 /* 572 * In this functions we calibrate APIC bus clocks to the external timer. 573 * 574 * We want to do the calibration only once since we want to have local timer 575 * irqs syncron. CPUs connected by the same APIC bus have the very same bus 576 * frequency. 577 * 578 * This was previously done by reading the PIT/HPET and waiting for a wrap 579 * around to find out, that a tick has elapsed. I have a box, where the PIT 580 * readout is broken, so it never gets out of the wait loop again. This was 581 * also reported by others. 582 * 583 * Monitoring the jiffies value is inaccurate and the clockevents 584 * infrastructure allows us to do a simple substitution of the interrupt 585 * handler. 586 * 587 * The calibration routine also uses the pm_timer when possible, as the PIT 588 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 589 * back to normal later in the boot process). 590 */ 591 592 #define LAPIC_CAL_LOOPS (HZ/10) 593 594 static __initdata int lapic_cal_loops = -1; 595 static __initdata long lapic_cal_t1, lapic_cal_t2; 596 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 597 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 598 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 599 600 /* 601 * Temporary interrupt handler. 602 */ 603 static void __init lapic_cal_handler(struct clock_event_device *dev) 604 { 605 unsigned long long tsc = 0; 606 long tapic = apic_read(APIC_TMCCT); 607 unsigned long pm = acpi_pm_read_early(); 608 609 if (cpu_has_tsc) 610 rdtscll(tsc); 611 612 switch (lapic_cal_loops++) { 613 case 0: 614 lapic_cal_t1 = tapic; 615 lapic_cal_tsc1 = tsc; 616 lapic_cal_pm1 = pm; 617 lapic_cal_j1 = jiffies; 618 break; 619 620 case LAPIC_CAL_LOOPS: 621 lapic_cal_t2 = tapic; 622 lapic_cal_tsc2 = tsc; 623 if (pm < lapic_cal_pm1) 624 pm += ACPI_PM_OVRRUN; 625 lapic_cal_pm2 = pm; 626 lapic_cal_j2 = jiffies; 627 break; 628 } 629 } 630 631 static int __init 632 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 633 { 634 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 635 const long pm_thresh = pm_100ms / 100; 636 unsigned long mult; 637 u64 res; 638 639 #ifndef CONFIG_X86_PM_TIMER 640 return -1; 641 #endif 642 643 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 644 645 /* Check, if the PM timer is available */ 646 if (!deltapm) 647 return -1; 648 649 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 650 651 if (deltapm > (pm_100ms - pm_thresh) && 652 deltapm < (pm_100ms + pm_thresh)) { 653 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 654 return 0; 655 } 656 657 res = (((u64)deltapm) * mult) >> 22; 658 do_div(res, 1000000); 659 pr_warning("APIC calibration not consistent " 660 "with PM-Timer: %ldms instead of 100ms\n",(long)res); 661 662 /* Correct the lapic counter value */ 663 res = (((u64)(*delta)) * pm_100ms); 664 do_div(res, deltapm); 665 pr_info("APIC delta adjusted to PM-Timer: " 666 "%lu (%ld)\n", (unsigned long)res, *delta); 667 *delta = (long)res; 668 669 /* Correct the tsc counter value */ 670 if (cpu_has_tsc) { 671 res = (((u64)(*deltatsc)) * pm_100ms); 672 do_div(res, deltapm); 673 apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 674 "PM-Timer: %lu (%ld)\n", 675 (unsigned long)res, *deltatsc); 676 *deltatsc = (long)res; 677 } 678 679 return 0; 680 } 681 682 static int __init calibrate_APIC_clock(void) 683 { 684 struct clock_event_device *levt = &__get_cpu_var(lapic_events); 685 void (*real_handler)(struct clock_event_device *dev); 686 unsigned long deltaj; 687 long delta, deltatsc; 688 int pm_referenced = 0; 689 690 /** 691 * check if lapic timer has already been calibrated by platform 692 * specific routine, such as tsc calibration code. if so, we just fill 693 * in the clockevent structure and return. 694 */ 695 696 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 697 return 0; 698 } else if (lapic_timer_frequency) { 699 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", 700 lapic_timer_frequency); 701 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR, 702 TICK_NSEC, lapic_clockevent.shift); 703 lapic_clockevent.max_delta_ns = 704 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); 705 lapic_clockevent.min_delta_ns = 706 clockevent_delta2ns(0xF, &lapic_clockevent); 707 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 708 return 0; 709 } 710 711 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 712 "calibrating APIC timer ...\n"); 713 714 local_irq_disable(); 715 716 /* Replace the global interrupt handler */ 717 real_handler = global_clock_event->event_handler; 718 global_clock_event->event_handler = lapic_cal_handler; 719 720 /* 721 * Setup the APIC counter to maximum. There is no way the lapic 722 * can underflow in the 100ms detection time frame 723 */ 724 __setup_APIC_LVTT(0xffffffff, 0, 0); 725 726 /* Let the interrupts run */ 727 local_irq_enable(); 728 729 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 730 cpu_relax(); 731 732 local_irq_disable(); 733 734 /* Restore the real event handler */ 735 global_clock_event->event_handler = real_handler; 736 737 /* Build delta t1-t2 as apic timer counts down */ 738 delta = lapic_cal_t1 - lapic_cal_t2; 739 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 740 741 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 742 743 /* we trust the PM based calibration if possible */ 744 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 745 &delta, &deltatsc); 746 747 /* Calculate the scaled math multiplication factor */ 748 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 749 lapic_clockevent.shift); 750 lapic_clockevent.max_delta_ns = 751 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); 752 lapic_clockevent.min_delta_ns = 753 clockevent_delta2ns(0xF, &lapic_clockevent); 754 755 lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 756 757 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 758 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); 759 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 760 lapic_timer_frequency); 761 762 if (cpu_has_tsc) { 763 apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 764 "%ld.%04ld MHz.\n", 765 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 766 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 767 } 768 769 apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 770 "%u.%04u MHz.\n", 771 lapic_timer_frequency / (1000000 / HZ), 772 lapic_timer_frequency % (1000000 / HZ)); 773 774 /* 775 * Do a sanity check on the APIC calibration result 776 */ 777 if (lapic_timer_frequency < (1000000 / HZ)) { 778 local_irq_enable(); 779 pr_warning("APIC frequency too slow, disabling apic timer\n"); 780 return -1; 781 } 782 783 levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 784 785 /* 786 * PM timer calibration failed or not turned on 787 * so lets try APIC timer based calibration 788 */ 789 if (!pm_referenced) { 790 apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 791 792 /* 793 * Setup the apic timer manually 794 */ 795 levt->event_handler = lapic_cal_handler; 796 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); 797 lapic_cal_loops = -1; 798 799 /* Let the interrupts run */ 800 local_irq_enable(); 801 802 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 803 cpu_relax(); 804 805 /* Stop the lapic timer */ 806 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); 807 808 /* Jiffies delta */ 809 deltaj = lapic_cal_j2 - lapic_cal_j1; 810 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 811 812 /* Check, if the jiffies result is consistent */ 813 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 814 apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 815 else 816 levt->features |= CLOCK_EVT_FEAT_DUMMY; 817 } else 818 local_irq_enable(); 819 820 if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 821 pr_warning("APIC timer disabled due to verification failure\n"); 822 return -1; 823 } 824 825 return 0; 826 } 827 828 /* 829 * Setup the boot APIC 830 * 831 * Calibrate and verify the result. 832 */ 833 void __init setup_boot_APIC_clock(void) 834 { 835 /* 836 * The local apic timer can be disabled via the kernel 837 * commandline or from the CPU detection code. Register the lapic 838 * timer as a dummy clock event source on SMP systems, so the 839 * broadcast mechanism is used. On UP systems simply ignore it. 840 */ 841 if (disable_apic_timer) { 842 pr_info("Disabling APIC timer\n"); 843 /* No broadcast on UP ! */ 844 if (num_possible_cpus() > 1) { 845 lapic_clockevent.mult = 1; 846 setup_APIC_timer(); 847 } 848 return; 849 } 850 851 if (calibrate_APIC_clock()) { 852 /* No broadcast on UP ! */ 853 if (num_possible_cpus() > 1) 854 setup_APIC_timer(); 855 return; 856 } 857 858 /* 859 * If nmi_watchdog is set to IO_APIC, we need the 860 * PIT/HPET going. Otherwise register lapic as a dummy 861 * device. 862 */ 863 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 864 865 /* Setup the lapic or request the broadcast */ 866 setup_APIC_timer(); 867 } 868 869 void setup_secondary_APIC_clock(void) 870 { 871 setup_APIC_timer(); 872 } 873 874 /* 875 * The guts of the apic timer interrupt 876 */ 877 static void local_apic_timer_interrupt(void) 878 { 879 int cpu = smp_processor_id(); 880 struct clock_event_device *evt = &per_cpu(lapic_events, cpu); 881 882 /* 883 * Normally we should not be here till LAPIC has been initialized but 884 * in some cases like kdump, its possible that there is a pending LAPIC 885 * timer interrupt from previous kernel's context and is delivered in 886 * new kernel the moment interrupts are enabled. 887 * 888 * Interrupts are enabled early and LAPIC is setup much later, hence 889 * its possible that when we get here evt->event_handler is NULL. 890 * Check for event_handler being NULL and discard the interrupt as 891 * spurious. 892 */ 893 if (!evt->event_handler) { 894 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); 895 /* Switch it off */ 896 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); 897 return; 898 } 899 900 /* 901 * the NMI deadlock-detector uses this. 902 */ 903 inc_irq_stat(apic_timer_irqs); 904 905 evt->event_handler(evt); 906 } 907 908 /* 909 * Local APIC timer interrupt. This is the most natural way for doing 910 * local interrupts, but local timer interrupts can be emulated by 911 * broadcast interrupts too. [in case the hw doesn't support APIC timers] 912 * 913 * [ if a single-CPU system runs an SMP kernel then we call the local 914 * interrupt as well. Thus we cannot inline the local irq ... ] 915 */ 916 void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) 917 { 918 struct pt_regs *old_regs = set_irq_regs(regs); 919 920 /* 921 * NOTE! We'd better ACK the irq immediately, 922 * because timer handling can be slow. 923 * 924 * update_process_times() expects us to have done irq_enter(). 925 * Besides, if we don't timer interrupts ignore the global 926 * interrupt lock, which is the WrongThing (tm) to do. 927 */ 928 entering_ack_irq(); 929 local_apic_timer_interrupt(); 930 exiting_irq(); 931 932 set_irq_regs(old_regs); 933 } 934 935 void __irq_entry smp_trace_apic_timer_interrupt(struct pt_regs *regs) 936 { 937 struct pt_regs *old_regs = set_irq_regs(regs); 938 939 /* 940 * NOTE! We'd better ACK the irq immediately, 941 * because timer handling can be slow. 942 * 943 * update_process_times() expects us to have done irq_enter(). 944 * Besides, if we don't timer interrupts ignore the global 945 * interrupt lock, which is the WrongThing (tm) to do. 946 */ 947 entering_ack_irq(); 948 trace_local_timer_entry(LOCAL_TIMER_VECTOR); 949 local_apic_timer_interrupt(); 950 trace_local_timer_exit(LOCAL_TIMER_VECTOR); 951 exiting_irq(); 952 953 set_irq_regs(old_regs); 954 } 955 956 int setup_profiling_timer(unsigned int multiplier) 957 { 958 return -EINVAL; 959 } 960 961 /* 962 * Local APIC start and shutdown 963 */ 964 965 /** 966 * clear_local_APIC - shutdown the local APIC 967 * 968 * This is called, when a CPU is disabled and before rebooting, so the state of 969 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 970 * leftovers during boot. 971 */ 972 void clear_local_APIC(void) 973 { 974 int maxlvt; 975 u32 v; 976 977 /* APIC hasn't been mapped yet */ 978 if (!x2apic_mode && !apic_phys) 979 return; 980 981 maxlvt = lapic_get_maxlvt(); 982 /* 983 * Masking an LVT entry can trigger a local APIC error 984 * if the vector is zero. Mask LVTERR first to prevent this. 985 */ 986 if (maxlvt >= 3) { 987 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 988 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 989 } 990 /* 991 * Careful: we have to set masks only first to deassert 992 * any level-triggered sources. 993 */ 994 v = apic_read(APIC_LVTT); 995 apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 996 v = apic_read(APIC_LVT0); 997 apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 998 v = apic_read(APIC_LVT1); 999 apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 1000 if (maxlvt >= 4) { 1001 v = apic_read(APIC_LVTPC); 1002 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 1003 } 1004 1005 /* lets not touch this if we didn't frob it */ 1006 #ifdef CONFIG_X86_THERMAL_VECTOR 1007 if (maxlvt >= 5) { 1008 v = apic_read(APIC_LVTTHMR); 1009 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 1010 } 1011 #endif 1012 #ifdef CONFIG_X86_MCE_INTEL 1013 if (maxlvt >= 6) { 1014 v = apic_read(APIC_LVTCMCI); 1015 if (!(v & APIC_LVT_MASKED)) 1016 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 1017 } 1018 #endif 1019 1020 /* 1021 * Clean APIC state for other OSs: 1022 */ 1023 apic_write(APIC_LVTT, APIC_LVT_MASKED); 1024 apic_write(APIC_LVT0, APIC_LVT_MASKED); 1025 apic_write(APIC_LVT1, APIC_LVT_MASKED); 1026 if (maxlvt >= 3) 1027 apic_write(APIC_LVTERR, APIC_LVT_MASKED); 1028 if (maxlvt >= 4) 1029 apic_write(APIC_LVTPC, APIC_LVT_MASKED); 1030 1031 /* Integrated APIC (!82489DX) ? */ 1032 if (lapic_is_integrated()) { 1033 if (maxlvt > 3) 1034 /* Clear ESR due to Pentium errata 3AP and 11AP */ 1035 apic_write(APIC_ESR, 0); 1036 apic_read(APIC_ESR); 1037 } 1038 } 1039 1040 /** 1041 * disable_local_APIC - clear and disable the local APIC 1042 */ 1043 void disable_local_APIC(void) 1044 { 1045 unsigned int value; 1046 1047 /* APIC hasn't been mapped yet */ 1048 if (!x2apic_mode && !apic_phys) 1049 return; 1050 1051 clear_local_APIC(); 1052 1053 /* 1054 * Disable APIC (implies clearing of registers 1055 * for 82489DX!). 1056 */ 1057 value = apic_read(APIC_SPIV); 1058 value &= ~APIC_SPIV_APIC_ENABLED; 1059 apic_write(APIC_SPIV, value); 1060 1061 #ifdef CONFIG_X86_32 1062 /* 1063 * When LAPIC was disabled by the BIOS and enabled by the kernel, 1064 * restore the disabled state. 1065 */ 1066 if (enabled_via_apicbase) { 1067 unsigned int l, h; 1068 1069 rdmsr(MSR_IA32_APICBASE, l, h); 1070 l &= ~MSR_IA32_APICBASE_ENABLE; 1071 wrmsr(MSR_IA32_APICBASE, l, h); 1072 } 1073 #endif 1074 } 1075 1076 /* 1077 * If Linux enabled the LAPIC against the BIOS default disable it down before 1078 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 1079 * not power-off. Additionally clear all LVT entries before disable_local_APIC 1080 * for the case where Linux didn't enable the LAPIC. 1081 */ 1082 void lapic_shutdown(void) 1083 { 1084 unsigned long flags; 1085 1086 if (!cpu_has_apic && !apic_from_smp_config()) 1087 return; 1088 1089 local_irq_save(flags); 1090 1091 #ifdef CONFIG_X86_32 1092 if (!enabled_via_apicbase) 1093 clear_local_APIC(); 1094 else 1095 #endif 1096 disable_local_APIC(); 1097 1098 1099 local_irq_restore(flags); 1100 } 1101 1102 /* 1103 * This is to verify that we're looking at a real local APIC. 1104 * Check these against your board if the CPUs aren't getting 1105 * started for no apparent reason. 1106 */ 1107 int __init verify_local_APIC(void) 1108 { 1109 unsigned int reg0, reg1; 1110 1111 /* 1112 * The version register is read-only in a real APIC. 1113 */ 1114 reg0 = apic_read(APIC_LVR); 1115 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); 1116 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); 1117 reg1 = apic_read(APIC_LVR); 1118 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); 1119 1120 /* 1121 * The two version reads above should print the same 1122 * numbers. If the second one is different, then we 1123 * poke at a non-APIC. 1124 */ 1125 if (reg1 != reg0) 1126 return 0; 1127 1128 /* 1129 * Check if the version looks reasonably. 1130 */ 1131 reg1 = GET_APIC_VERSION(reg0); 1132 if (reg1 == 0x00 || reg1 == 0xff) 1133 return 0; 1134 reg1 = lapic_get_maxlvt(); 1135 if (reg1 < 0x02 || reg1 == 0xff) 1136 return 0; 1137 1138 /* 1139 * The ID register is read/write in a real APIC. 1140 */ 1141 reg0 = apic_read(APIC_ID); 1142 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); 1143 apic_write(APIC_ID, reg0 ^ apic->apic_id_mask); 1144 reg1 = apic_read(APIC_ID); 1145 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); 1146 apic_write(APIC_ID, reg0); 1147 if (reg1 != (reg0 ^ apic->apic_id_mask)) 1148 return 0; 1149 1150 /* 1151 * The next two are just to see if we have sane values. 1152 * They're only really relevant if we're in Virtual Wire 1153 * compatibility mode, but most boxes are anymore. 1154 */ 1155 reg0 = apic_read(APIC_LVT0); 1156 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); 1157 reg1 = apic_read(APIC_LVT1); 1158 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); 1159 1160 return 1; 1161 } 1162 1163 /** 1164 * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1165 */ 1166 void __init sync_Arb_IDs(void) 1167 { 1168 /* 1169 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1170 * needed on AMD. 1171 */ 1172 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1173 return; 1174 1175 /* 1176 * Wait for idle. 1177 */ 1178 apic_wait_icr_idle(); 1179 1180 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1181 apic_write(APIC_ICR, APIC_DEST_ALLINC | 1182 APIC_INT_LEVELTRIG | APIC_DM_INIT); 1183 } 1184 1185 /* 1186 * An initial setup of the virtual wire mode. 1187 */ 1188 void __init init_bsp_APIC(void) 1189 { 1190 unsigned int value; 1191 1192 /* 1193 * Don't do the setup now if we have a SMP BIOS as the 1194 * through-I/O-APIC virtual wire mode might be active. 1195 */ 1196 if (smp_found_config || !cpu_has_apic) 1197 return; 1198 1199 /* 1200 * Do not trust the local APIC being empty at bootup. 1201 */ 1202 clear_local_APIC(); 1203 1204 /* 1205 * Enable APIC. 1206 */ 1207 value = apic_read(APIC_SPIV); 1208 value &= ~APIC_VECTOR_MASK; 1209 value |= APIC_SPIV_APIC_ENABLED; 1210 1211 #ifdef CONFIG_X86_32 1212 /* This bit is reserved on P4/Xeon and should be cleared */ 1213 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1214 (boot_cpu_data.x86 == 15)) 1215 value &= ~APIC_SPIV_FOCUS_DISABLED; 1216 else 1217 #endif 1218 value |= APIC_SPIV_FOCUS_DISABLED; 1219 value |= SPURIOUS_APIC_VECTOR; 1220 apic_write(APIC_SPIV, value); 1221 1222 /* 1223 * Set up the virtual wire mode. 1224 */ 1225 apic_write(APIC_LVT0, APIC_DM_EXTINT); 1226 value = APIC_DM_NMI; 1227 if (!lapic_is_integrated()) /* 82489DX */ 1228 value |= APIC_LVT_LEVEL_TRIGGER; 1229 apic_write(APIC_LVT1, value); 1230 } 1231 1232 static void lapic_setup_esr(void) 1233 { 1234 unsigned int oldvalue, value, maxlvt; 1235 1236 if (!lapic_is_integrated()) { 1237 pr_info("No ESR for 82489DX.\n"); 1238 return; 1239 } 1240 1241 if (apic->disable_esr) { 1242 /* 1243 * Something untraceable is creating bad interrupts on 1244 * secondary quads ... for the moment, just leave the 1245 * ESR disabled - we can't do anything useful with the 1246 * errors anyway - mbligh 1247 */ 1248 pr_info("Leaving ESR disabled.\n"); 1249 return; 1250 } 1251 1252 maxlvt = lapic_get_maxlvt(); 1253 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1254 apic_write(APIC_ESR, 0); 1255 oldvalue = apic_read(APIC_ESR); 1256 1257 /* enables sending errors */ 1258 value = ERROR_APIC_VECTOR; 1259 apic_write(APIC_LVTERR, value); 1260 1261 /* 1262 * spec says clear errors after enabling vector. 1263 */ 1264 if (maxlvt > 3) 1265 apic_write(APIC_ESR, 0); 1266 value = apic_read(APIC_ESR); 1267 if (value != oldvalue) 1268 apic_printk(APIC_VERBOSE, "ESR value before enabling " 1269 "vector: 0x%08x after: 0x%08x\n", 1270 oldvalue, value); 1271 } 1272 1273 /** 1274 * setup_local_APIC - setup the local APIC 1275 * 1276 * Used to setup local APIC while initializing BSP or bringin up APs. 1277 * Always called with preemption disabled. 1278 */ 1279 void setup_local_APIC(void) 1280 { 1281 int cpu = smp_processor_id(); 1282 unsigned int value, queued; 1283 int i, j, acked = 0; 1284 unsigned long long tsc = 0, ntsc; 1285 long long max_loops = cpu_khz; 1286 1287 if (cpu_has_tsc) 1288 rdtscll(tsc); 1289 1290 if (disable_apic) { 1291 disable_ioapic_support(); 1292 return; 1293 } 1294 1295 #ifdef CONFIG_X86_32 1296 /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1297 if (lapic_is_integrated() && apic->disable_esr) { 1298 apic_write(APIC_ESR, 0); 1299 apic_write(APIC_ESR, 0); 1300 apic_write(APIC_ESR, 0); 1301 apic_write(APIC_ESR, 0); 1302 } 1303 #endif 1304 perf_events_lapic_init(); 1305 1306 /* 1307 * Double-check whether this APIC is really registered. 1308 * This is meaningless in clustered apic mode, so we skip it. 1309 */ 1310 BUG_ON(!apic->apic_id_registered()); 1311 1312 /* 1313 * Intel recommends to set DFR, LDR and TPR before enabling 1314 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1315 * document number 292116). So here it goes... 1316 */ 1317 apic->init_apic_ldr(); 1318 1319 #ifdef CONFIG_X86_32 1320 /* 1321 * APIC LDR is initialized. If logical_apicid mapping was 1322 * initialized during get_smp_config(), make sure it matches the 1323 * actual value. 1324 */ 1325 i = early_per_cpu(x86_cpu_to_logical_apicid, cpu); 1326 WARN_ON(i != BAD_APICID && i != logical_smp_processor_id()); 1327 /* always use the value from LDR */ 1328 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 1329 logical_smp_processor_id(); 1330 1331 /* 1332 * Some NUMA implementations (NUMAQ) don't initialize apicid to 1333 * node mapping during NUMA init. Now that logical apicid is 1334 * guaranteed to be known, give it another chance. This is already 1335 * a bit too late - percpu allocation has already happened without 1336 * proper NUMA affinity. 1337 */ 1338 if (apic->x86_32_numa_cpu_node) 1339 set_apicid_to_node(early_per_cpu(x86_cpu_to_apicid, cpu), 1340 apic->x86_32_numa_cpu_node(cpu)); 1341 #endif 1342 1343 /* 1344 * Set Task Priority to 'accept all'. We never change this 1345 * later on. 1346 */ 1347 value = apic_read(APIC_TASKPRI); 1348 value &= ~APIC_TPRI_MASK; 1349 apic_write(APIC_TASKPRI, value); 1350 1351 /* 1352 * After a crash, we no longer service the interrupts and a pending 1353 * interrupt from previous kernel might still have ISR bit set. 1354 * 1355 * Most probably by now CPU has serviced that pending interrupt and 1356 * it might not have done the ack_APIC_irq() because it thought, 1357 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it 1358 * does not clear the ISR bit and cpu thinks it has already serivced 1359 * the interrupt. Hence a vector might get locked. It was noticed 1360 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. 1361 */ 1362 do { 1363 queued = 0; 1364 for (i = APIC_ISR_NR - 1; i >= 0; i--) 1365 queued |= apic_read(APIC_IRR + i*0x10); 1366 1367 for (i = APIC_ISR_NR - 1; i >= 0; i--) { 1368 value = apic_read(APIC_ISR + i*0x10); 1369 for (j = 31; j >= 0; j--) { 1370 if (value & (1<<j)) { 1371 ack_APIC_irq(); 1372 acked++; 1373 } 1374 } 1375 } 1376 if (acked > 256) { 1377 printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n", 1378 acked); 1379 break; 1380 } 1381 if (queued) { 1382 if (cpu_has_tsc) { 1383 rdtscll(ntsc); 1384 max_loops = (cpu_khz << 10) - (ntsc - tsc); 1385 } else 1386 max_loops--; 1387 } 1388 } while (queued && max_loops > 0); 1389 WARN_ON(max_loops <= 0); 1390 1391 /* 1392 * Now that we are all set up, enable the APIC 1393 */ 1394 value = apic_read(APIC_SPIV); 1395 value &= ~APIC_VECTOR_MASK; 1396 /* 1397 * Enable APIC 1398 */ 1399 value |= APIC_SPIV_APIC_ENABLED; 1400 1401 #ifdef CONFIG_X86_32 1402 /* 1403 * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1404 * certain networking cards. If high frequency interrupts are 1405 * happening on a particular IOAPIC pin, plus the IOAPIC routing 1406 * entry is masked/unmasked at a high rate as well then sooner or 1407 * later IOAPIC line gets 'stuck', no more interrupts are received 1408 * from the device. If focus CPU is disabled then the hang goes 1409 * away, oh well :-( 1410 * 1411 * [ This bug can be reproduced easily with a level-triggered 1412 * PCI Ne2000 networking cards and PII/PIII processors, dual 1413 * BX chipset. ] 1414 */ 1415 /* 1416 * Actually disabling the focus CPU check just makes the hang less 1417 * frequent as it makes the interrupt distributon model be more 1418 * like LRU than MRU (the short-term load is more even across CPUs). 1419 * See also the comment in end_level_ioapic_irq(). --macro 1420 */ 1421 1422 /* 1423 * - enable focus processor (bit==0) 1424 * - 64bit mode always use processor focus 1425 * so no need to set it 1426 */ 1427 value &= ~APIC_SPIV_FOCUS_DISABLED; 1428 #endif 1429 1430 /* 1431 * Set spurious IRQ vector 1432 */ 1433 value |= SPURIOUS_APIC_VECTOR; 1434 apic_write(APIC_SPIV, value); 1435 1436 /* 1437 * Set up LVT0, LVT1: 1438 * 1439 * set up through-local-APIC on the BP's LINT0. This is not 1440 * strictly necessary in pure symmetric-IO mode, but sometimes 1441 * we delegate interrupts to the 8259A. 1442 */ 1443 /* 1444 * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1445 */ 1446 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 1447 if (!cpu && (pic_mode || !value)) { 1448 value = APIC_DM_EXTINT; 1449 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); 1450 } else { 1451 value = APIC_DM_EXTINT | APIC_LVT_MASKED; 1452 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); 1453 } 1454 apic_write(APIC_LVT0, value); 1455 1456 /* 1457 * only the BP should see the LINT1 NMI signal, obviously. 1458 */ 1459 if (!cpu) 1460 value = APIC_DM_NMI; 1461 else 1462 value = APIC_DM_NMI | APIC_LVT_MASKED; 1463 if (!lapic_is_integrated()) /* 82489DX */ 1464 value |= APIC_LVT_LEVEL_TRIGGER; 1465 apic_write(APIC_LVT1, value); 1466 1467 #ifdef CONFIG_X86_MCE_INTEL 1468 /* Recheck CMCI information after local APIC is up on CPU #0 */ 1469 if (!cpu) 1470 cmci_recheck(); 1471 #endif 1472 } 1473 1474 void end_local_APIC_setup(void) 1475 { 1476 lapic_setup_esr(); 1477 1478 #ifdef CONFIG_X86_32 1479 { 1480 unsigned int value; 1481 /* Disable the local apic timer */ 1482 value = apic_read(APIC_LVTT); 1483 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1484 apic_write(APIC_LVTT, value); 1485 } 1486 #endif 1487 1488 apic_pm_activate(); 1489 } 1490 1491 void __init bsp_end_local_APIC_setup(void) 1492 { 1493 end_local_APIC_setup(); 1494 1495 /* 1496 * Now that local APIC setup is completed for BP, configure the fault 1497 * handling for interrupt remapping. 1498 */ 1499 irq_remap_enable_fault_handling(); 1500 1501 } 1502 1503 #ifdef CONFIG_X86_X2APIC 1504 /* 1505 * Need to disable xapic and x2apic at the same time and then enable xapic mode 1506 */ 1507 static inline void __disable_x2apic(u64 msr) 1508 { 1509 wrmsrl(MSR_IA32_APICBASE, 1510 msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); 1511 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); 1512 } 1513 1514 static __init void disable_x2apic(void) 1515 { 1516 u64 msr; 1517 1518 if (!cpu_has_x2apic) 1519 return; 1520 1521 rdmsrl(MSR_IA32_APICBASE, msr); 1522 if (msr & X2APIC_ENABLE) { 1523 u32 x2apic_id = read_apic_id(); 1524 1525 if (x2apic_id >= 255) 1526 panic("Cannot disable x2apic, id: %08x\n", x2apic_id); 1527 1528 pr_info("Disabling x2apic\n"); 1529 __disable_x2apic(msr); 1530 1531 if (nox2apic) { 1532 clear_cpu_cap(&cpu_data(0), X86_FEATURE_X2APIC); 1533 setup_clear_cpu_cap(X86_FEATURE_X2APIC); 1534 } 1535 1536 x2apic_disabled = 1; 1537 x2apic_mode = 0; 1538 1539 register_lapic_address(mp_lapic_addr); 1540 } 1541 } 1542 1543 void check_x2apic(void) 1544 { 1545 if (x2apic_enabled()) { 1546 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n"); 1547 x2apic_preenabled = x2apic_mode = 1; 1548 } 1549 } 1550 1551 void enable_x2apic(void) 1552 { 1553 u64 msr; 1554 1555 rdmsrl(MSR_IA32_APICBASE, msr); 1556 if (x2apic_disabled) { 1557 __disable_x2apic(msr); 1558 return; 1559 } 1560 1561 if (!x2apic_mode) 1562 return; 1563 1564 if (!(msr & X2APIC_ENABLE)) { 1565 printk_once(KERN_INFO "Enabling x2apic\n"); 1566 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); 1567 } 1568 } 1569 #endif /* CONFIG_X86_X2APIC */ 1570 1571 int __init enable_IR(void) 1572 { 1573 #ifdef CONFIG_IRQ_REMAP 1574 if (!irq_remapping_supported()) { 1575 pr_debug("intr-remapping not supported\n"); 1576 return -1; 1577 } 1578 1579 if (!x2apic_preenabled && skip_ioapic_setup) { 1580 pr_info("Skipped enabling intr-remap because of skipping " 1581 "io-apic setup\n"); 1582 return -1; 1583 } 1584 1585 return irq_remapping_enable(); 1586 #endif 1587 return -1; 1588 } 1589 1590 void __init enable_IR_x2apic(void) 1591 { 1592 unsigned long flags; 1593 int ret, x2apic_enabled = 0; 1594 int hardware_init_ret; 1595 1596 /* Make sure irq_remap_ops are initialized */ 1597 setup_irq_remapping_ops(); 1598 1599 hardware_init_ret = irq_remapping_prepare(); 1600 if (hardware_init_ret && !x2apic_supported()) 1601 return; 1602 1603 ret = save_ioapic_entries(); 1604 if (ret) { 1605 pr_info("Saving IO-APIC state failed: %d\n", ret); 1606 return; 1607 } 1608 1609 local_irq_save(flags); 1610 legacy_pic->mask_all(); 1611 mask_ioapic_entries(); 1612 1613 if (x2apic_preenabled && nox2apic) 1614 disable_x2apic(); 1615 1616 if (hardware_init_ret) 1617 ret = -1; 1618 else 1619 ret = enable_IR(); 1620 1621 if (!x2apic_supported()) 1622 goto skip_x2apic; 1623 1624 if (ret < 0) { 1625 /* IR is required if there is APIC ID > 255 even when running 1626 * under KVM 1627 */ 1628 if (max_physical_apicid > 255 || 1629 !hypervisor_x2apic_available()) { 1630 if (x2apic_preenabled) 1631 disable_x2apic(); 1632 goto skip_x2apic; 1633 } 1634 /* 1635 * without IR all CPUs can be addressed by IOAPIC/MSI 1636 * only in physical mode 1637 */ 1638 x2apic_force_phys(); 1639 } 1640 1641 if (ret == IRQ_REMAP_XAPIC_MODE) { 1642 pr_info("x2apic not enabled, IRQ remapping is in xapic mode\n"); 1643 goto skip_x2apic; 1644 } 1645 1646 x2apic_enabled = 1; 1647 1648 if (x2apic_supported() && !x2apic_mode) { 1649 x2apic_mode = 1; 1650 enable_x2apic(); 1651 pr_info("Enabled x2apic\n"); 1652 } 1653 1654 skip_x2apic: 1655 if (ret < 0) /* IR enabling failed */ 1656 restore_ioapic_entries(); 1657 legacy_pic->restore_mask(); 1658 local_irq_restore(flags); 1659 } 1660 1661 #ifdef CONFIG_X86_64 1662 /* 1663 * Detect and enable local APICs on non-SMP boards. 1664 * Original code written by Keir Fraser. 1665 * On AMD64 we trust the BIOS - if it says no APIC it is likely 1666 * not correctly set up (usually the APIC timer won't work etc.) 1667 */ 1668 static int __init detect_init_APIC(void) 1669 { 1670 if (!cpu_has_apic) { 1671 pr_info("No local APIC present\n"); 1672 return -1; 1673 } 1674 1675 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1676 return 0; 1677 } 1678 #else 1679 1680 static int __init apic_verify(void) 1681 { 1682 u32 features, h, l; 1683 1684 /* 1685 * The APIC feature bit should now be enabled 1686 * in `cpuid' 1687 */ 1688 features = cpuid_edx(1); 1689 if (!(features & (1 << X86_FEATURE_APIC))) { 1690 pr_warning("Could not enable APIC!\n"); 1691 return -1; 1692 } 1693 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 1694 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1695 1696 /* The BIOS may have set up the APIC at some other address */ 1697 if (boot_cpu_data.x86 >= 6) { 1698 rdmsr(MSR_IA32_APICBASE, l, h); 1699 if (l & MSR_IA32_APICBASE_ENABLE) 1700 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 1701 } 1702 1703 pr_info("Found and enabled local APIC!\n"); 1704 return 0; 1705 } 1706 1707 int __init apic_force_enable(unsigned long addr) 1708 { 1709 u32 h, l; 1710 1711 if (disable_apic) 1712 return -1; 1713 1714 /* 1715 * Some BIOSes disable the local APIC in the APIC_BASE 1716 * MSR. This can only be done in software for Intel P6 or later 1717 * and AMD K7 (Model > 1) or later. 1718 */ 1719 if (boot_cpu_data.x86 >= 6) { 1720 rdmsr(MSR_IA32_APICBASE, l, h); 1721 if (!(l & MSR_IA32_APICBASE_ENABLE)) { 1722 pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 1723 l &= ~MSR_IA32_APICBASE_BASE; 1724 l |= MSR_IA32_APICBASE_ENABLE | addr; 1725 wrmsr(MSR_IA32_APICBASE, l, h); 1726 enabled_via_apicbase = 1; 1727 } 1728 } 1729 return apic_verify(); 1730 } 1731 1732 /* 1733 * Detect and initialize APIC 1734 */ 1735 static int __init detect_init_APIC(void) 1736 { 1737 /* Disabled by kernel option? */ 1738 if (disable_apic) 1739 return -1; 1740 1741 switch (boot_cpu_data.x86_vendor) { 1742 case X86_VENDOR_AMD: 1743 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 1744 (boot_cpu_data.x86 >= 15)) 1745 break; 1746 goto no_apic; 1747 case X86_VENDOR_INTEL: 1748 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 1749 (boot_cpu_data.x86 == 5 && cpu_has_apic)) 1750 break; 1751 goto no_apic; 1752 default: 1753 goto no_apic; 1754 } 1755 1756 if (!cpu_has_apic) { 1757 /* 1758 * Over-ride BIOS and try to enable the local APIC only if 1759 * "lapic" specified. 1760 */ 1761 if (!force_enable_local_apic) { 1762 pr_info("Local APIC disabled by BIOS -- " 1763 "you can enable it with \"lapic\"\n"); 1764 return -1; 1765 } 1766 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) 1767 return -1; 1768 } else { 1769 if (apic_verify()) 1770 return -1; 1771 } 1772 1773 apic_pm_activate(); 1774 1775 return 0; 1776 1777 no_apic: 1778 pr_info("No local APIC present or hardware disabled\n"); 1779 return -1; 1780 } 1781 #endif 1782 1783 /** 1784 * init_apic_mappings - initialize APIC mappings 1785 */ 1786 void __init init_apic_mappings(void) 1787 { 1788 unsigned int new_apicid; 1789 1790 if (x2apic_mode) { 1791 boot_cpu_physical_apicid = read_apic_id(); 1792 return; 1793 } 1794 1795 /* If no local APIC can be found return early */ 1796 if (!smp_found_config && detect_init_APIC()) { 1797 /* lets NOP'ify apic operations */ 1798 pr_info("APIC: disable apic facility\n"); 1799 apic_disable(); 1800 } else { 1801 apic_phys = mp_lapic_addr; 1802 1803 /* 1804 * acpi lapic path already maps that address in 1805 * acpi_register_lapic_address() 1806 */ 1807 if (!acpi_lapic && !smp_found_config) 1808 register_lapic_address(apic_phys); 1809 } 1810 1811 /* 1812 * Fetch the APIC ID of the BSP in case we have a 1813 * default configuration (or the MP table is broken). 1814 */ 1815 new_apicid = read_apic_id(); 1816 if (boot_cpu_physical_apicid != new_apicid) { 1817 boot_cpu_physical_apicid = new_apicid; 1818 /* 1819 * yeah -- we lie about apic_version 1820 * in case if apic was disabled via boot option 1821 * but it's not a problem for SMP compiled kernel 1822 * since smp_sanity_check is prepared for such a case 1823 * and disable smp mode 1824 */ 1825 apic_version[new_apicid] = 1826 GET_APIC_VERSION(apic_read(APIC_LVR)); 1827 } 1828 } 1829 1830 void __init register_lapic_address(unsigned long address) 1831 { 1832 mp_lapic_addr = address; 1833 1834 if (!x2apic_mode) { 1835 set_fixmap_nocache(FIX_APIC_BASE, address); 1836 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 1837 APIC_BASE, mp_lapic_addr); 1838 } 1839 if (boot_cpu_physical_apicid == -1U) { 1840 boot_cpu_physical_apicid = read_apic_id(); 1841 apic_version[boot_cpu_physical_apicid] = 1842 GET_APIC_VERSION(apic_read(APIC_LVR)); 1843 } 1844 } 1845 1846 /* 1847 * This initializes the IO-APIC and APIC hardware if this is 1848 * a UP kernel. 1849 */ 1850 int apic_version[MAX_LOCAL_APIC]; 1851 1852 int __init APIC_init_uniprocessor(void) 1853 { 1854 if (disable_apic) { 1855 pr_info("Apic disabled\n"); 1856 return -1; 1857 } 1858 #ifdef CONFIG_X86_64 1859 if (!cpu_has_apic) { 1860 disable_apic = 1; 1861 pr_info("Apic disabled by BIOS\n"); 1862 return -1; 1863 } 1864 #else 1865 if (!smp_found_config && !cpu_has_apic) 1866 return -1; 1867 1868 /* 1869 * Complain if the BIOS pretends there is one. 1870 */ 1871 if (!cpu_has_apic && 1872 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 1873 pr_err("BIOS bug, local APIC 0x%x not detected!...\n", 1874 boot_cpu_physical_apicid); 1875 return -1; 1876 } 1877 #endif 1878 1879 default_setup_apic_routing(); 1880 1881 verify_local_APIC(); 1882 connect_bsp_APIC(); 1883 1884 #ifdef CONFIG_X86_64 1885 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); 1886 #else 1887 /* 1888 * Hack: In case of kdump, after a crash, kernel might be booting 1889 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 1890 * might be zero if read from MP tables. Get it from LAPIC. 1891 */ 1892 # ifdef CONFIG_CRASH_DUMP 1893 boot_cpu_physical_apicid = read_apic_id(); 1894 # endif 1895 #endif 1896 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1897 setup_local_APIC(); 1898 1899 #ifdef CONFIG_X86_IO_APIC 1900 /* 1901 * Now enable IO-APICs, actually call clear_IO_APIC 1902 * We need clear_IO_APIC before enabling error vector 1903 */ 1904 if (!skip_ioapic_setup && nr_ioapics) 1905 enable_IO_APIC(); 1906 #endif 1907 1908 bsp_end_local_APIC_setup(); 1909 1910 #ifdef CONFIG_X86_IO_APIC 1911 if (smp_found_config && !skip_ioapic_setup && nr_ioapics) 1912 setup_IO_APIC(); 1913 else { 1914 nr_ioapics = 0; 1915 } 1916 #endif 1917 1918 x86_init.timers.setup_percpu_clockev(); 1919 return 0; 1920 } 1921 1922 /* 1923 * Local APIC interrupts 1924 */ 1925 1926 /* 1927 * This interrupt should _never_ happen with our APIC/SMP architecture 1928 */ 1929 static inline void __smp_spurious_interrupt(void) 1930 { 1931 u32 v; 1932 1933 /* 1934 * Check if this really is a spurious interrupt and ACK it 1935 * if it is a vectored one. Just in case... 1936 * Spurious interrupts should not be ACKed. 1937 */ 1938 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); 1939 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) 1940 ack_APIC_irq(); 1941 1942 inc_irq_stat(irq_spurious_count); 1943 1944 /* see sw-dev-man vol 3, chapter 7.4.13.5 */ 1945 pr_info("spurious APIC interrupt on CPU#%d, " 1946 "should never happen.\n", smp_processor_id()); 1947 } 1948 1949 void smp_spurious_interrupt(struct pt_regs *regs) 1950 { 1951 entering_irq(); 1952 __smp_spurious_interrupt(); 1953 exiting_irq(); 1954 } 1955 1956 void smp_trace_spurious_interrupt(struct pt_regs *regs) 1957 { 1958 entering_irq(); 1959 trace_spurious_apic_entry(SPURIOUS_APIC_VECTOR); 1960 __smp_spurious_interrupt(); 1961 trace_spurious_apic_exit(SPURIOUS_APIC_VECTOR); 1962 exiting_irq(); 1963 } 1964 1965 /* 1966 * This interrupt should never happen with our APIC/SMP architecture 1967 */ 1968 static inline void __smp_error_interrupt(struct pt_regs *regs) 1969 { 1970 u32 v0, v1; 1971 u32 i = 0; 1972 static const char * const error_interrupt_reason[] = { 1973 "Send CS error", /* APIC Error Bit 0 */ 1974 "Receive CS error", /* APIC Error Bit 1 */ 1975 "Send accept error", /* APIC Error Bit 2 */ 1976 "Receive accept error", /* APIC Error Bit 3 */ 1977 "Redirectable IPI", /* APIC Error Bit 4 */ 1978 "Send illegal vector", /* APIC Error Bit 5 */ 1979 "Received illegal vector", /* APIC Error Bit 6 */ 1980 "Illegal register address", /* APIC Error Bit 7 */ 1981 }; 1982 1983 /* First tickle the hardware, only then report what went on. -- REW */ 1984 v0 = apic_read(APIC_ESR); 1985 apic_write(APIC_ESR, 0); 1986 v1 = apic_read(APIC_ESR); 1987 ack_APIC_irq(); 1988 atomic_inc(&irq_err_count); 1989 1990 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x(%02x)", 1991 smp_processor_id(), v0 , v1); 1992 1993 v1 = v1 & 0xff; 1994 while (v1) { 1995 if (v1 & 0x1) 1996 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); 1997 i++; 1998 v1 >>= 1; 1999 } 2000 2001 apic_printk(APIC_DEBUG, KERN_CONT "\n"); 2002 2003 } 2004 2005 void smp_error_interrupt(struct pt_regs *regs) 2006 { 2007 entering_irq(); 2008 __smp_error_interrupt(regs); 2009 exiting_irq(); 2010 } 2011 2012 void smp_trace_error_interrupt(struct pt_regs *regs) 2013 { 2014 entering_irq(); 2015 trace_error_apic_entry(ERROR_APIC_VECTOR); 2016 __smp_error_interrupt(regs); 2017 trace_error_apic_exit(ERROR_APIC_VECTOR); 2018 exiting_irq(); 2019 } 2020 2021 /** 2022 * connect_bsp_APIC - attach the APIC to the interrupt system 2023 */ 2024 void __init connect_bsp_APIC(void) 2025 { 2026 #ifdef CONFIG_X86_32 2027 if (pic_mode) { 2028 /* 2029 * Do not trust the local APIC being empty at bootup. 2030 */ 2031 clear_local_APIC(); 2032 /* 2033 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 2034 * local APIC to INT and NMI lines. 2035 */ 2036 apic_printk(APIC_VERBOSE, "leaving PIC mode, " 2037 "enabling APIC mode.\n"); 2038 imcr_pic_to_apic(); 2039 } 2040 #endif 2041 if (apic->enable_apic_mode) 2042 apic->enable_apic_mode(); 2043 } 2044 2045 /** 2046 * disconnect_bsp_APIC - detach the APIC from the interrupt system 2047 * @virt_wire_setup: indicates, whether virtual wire mode is selected 2048 * 2049 * Virtual wire mode is necessary to deliver legacy interrupts even when the 2050 * APIC is disabled. 2051 */ 2052 void disconnect_bsp_APIC(int virt_wire_setup) 2053 { 2054 unsigned int value; 2055 2056 #ifdef CONFIG_X86_32 2057 if (pic_mode) { 2058 /* 2059 * Put the board back into PIC mode (has an effect only on 2060 * certain older boards). Note that APIC interrupts, including 2061 * IPIs, won't work beyond this point! The only exception are 2062 * INIT IPIs. 2063 */ 2064 apic_printk(APIC_VERBOSE, "disabling APIC mode, " 2065 "entering PIC mode.\n"); 2066 imcr_apic_to_pic(); 2067 return; 2068 } 2069 #endif 2070 2071 /* Go back to Virtual Wire compatibility mode */ 2072 2073 /* For the spurious interrupt use vector F, and enable it */ 2074 value = apic_read(APIC_SPIV); 2075 value &= ~APIC_VECTOR_MASK; 2076 value |= APIC_SPIV_APIC_ENABLED; 2077 value |= 0xf; 2078 apic_write(APIC_SPIV, value); 2079 2080 if (!virt_wire_setup) { 2081 /* 2082 * For LVT0 make it edge triggered, active high, 2083 * external and enabled 2084 */ 2085 value = apic_read(APIC_LVT0); 2086 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2087 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2088 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2089 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2090 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 2091 apic_write(APIC_LVT0, value); 2092 } else { 2093 /* Disable LVT0 */ 2094 apic_write(APIC_LVT0, APIC_LVT_MASKED); 2095 } 2096 2097 /* 2098 * For LVT1 make it edge triggered, active high, 2099 * nmi and enabled 2100 */ 2101 value = apic_read(APIC_LVT1); 2102 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2103 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2104 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2105 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2106 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 2107 apic_write(APIC_LVT1, value); 2108 } 2109 2110 void generic_processor_info(int apicid, int version) 2111 { 2112 int cpu, max = nr_cpu_ids; 2113 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, 2114 phys_cpu_present_map); 2115 2116 /* 2117 * If boot cpu has not been detected yet, then only allow upto 2118 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu 2119 */ 2120 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && 2121 apicid != boot_cpu_physical_apicid) { 2122 int thiscpu = max + disabled_cpus - 1; 2123 2124 pr_warning( 2125 "ACPI: NR_CPUS/possible_cpus limit of %i almost" 2126 " reached. Keeping one slot for boot cpu." 2127 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 2128 2129 disabled_cpus++; 2130 return; 2131 } 2132 2133 if (num_processors >= nr_cpu_ids) { 2134 int thiscpu = max + disabled_cpus; 2135 2136 pr_warning( 2137 "ACPI: NR_CPUS/possible_cpus limit of %i reached." 2138 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 2139 2140 disabled_cpus++; 2141 return; 2142 } 2143 2144 num_processors++; 2145 if (apicid == boot_cpu_physical_apicid) { 2146 /* 2147 * x86_bios_cpu_apicid is required to have processors listed 2148 * in same order as logical cpu numbers. Hence the first 2149 * entry is BSP, and so on. 2150 * boot_cpu_init() already hold bit 0 in cpu_present_mask 2151 * for BSP. 2152 */ 2153 cpu = 0; 2154 } else 2155 cpu = cpumask_next_zero(-1, cpu_present_mask); 2156 2157 /* 2158 * Validate version 2159 */ 2160 if (version == 0x0) { 2161 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", 2162 cpu, apicid); 2163 version = 0x10; 2164 } 2165 apic_version[apicid] = version; 2166 2167 if (version != apic_version[boot_cpu_physical_apicid]) { 2168 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", 2169 apic_version[boot_cpu_physical_apicid], cpu, version); 2170 } 2171 2172 physid_set(apicid, phys_cpu_present_map); 2173 if (apicid > max_physical_apicid) 2174 max_physical_apicid = apicid; 2175 2176 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 2177 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 2178 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 2179 #endif 2180 #ifdef CONFIG_X86_32 2181 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 2182 apic->x86_32_early_logical_apicid(cpu); 2183 #endif 2184 set_cpu_possible(cpu, true); 2185 set_cpu_present(cpu, true); 2186 } 2187 2188 int hard_smp_processor_id(void) 2189 { 2190 return read_apic_id(); 2191 } 2192 2193 void default_init_apic_ldr(void) 2194 { 2195 unsigned long val; 2196 2197 apic_write(APIC_DFR, APIC_DFR_VALUE); 2198 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; 2199 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); 2200 apic_write(APIC_LDR, val); 2201 } 2202 2203 int default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 2204 const struct cpumask *andmask, 2205 unsigned int *apicid) 2206 { 2207 unsigned int cpu; 2208 2209 for_each_cpu_and(cpu, cpumask, andmask) { 2210 if (cpumask_test_cpu(cpu, cpu_online_mask)) 2211 break; 2212 } 2213 2214 if (likely(cpu < nr_cpu_ids)) { 2215 *apicid = per_cpu(x86_cpu_to_apicid, cpu); 2216 return 0; 2217 } 2218 2219 return -EINVAL; 2220 } 2221 2222 /* 2223 * Override the generic EOI implementation with an optimized version. 2224 * Only called during early boot when only one CPU is active and with 2225 * interrupts disabled, so we know this does not race with actual APIC driver 2226 * use. 2227 */ 2228 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) 2229 { 2230 struct apic **drv; 2231 2232 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { 2233 /* Should happen once for each apic */ 2234 WARN_ON((*drv)->eoi_write == eoi_write); 2235 (*drv)->eoi_write = eoi_write; 2236 } 2237 } 2238 2239 /* 2240 * Power management 2241 */ 2242 #ifdef CONFIG_PM 2243 2244 static struct { 2245 /* 2246 * 'active' is true if the local APIC was enabled by us and 2247 * not the BIOS; this signifies that we are also responsible 2248 * for disabling it before entering apm/acpi suspend 2249 */ 2250 int active; 2251 /* r/w apic fields */ 2252 unsigned int apic_id; 2253 unsigned int apic_taskpri; 2254 unsigned int apic_ldr; 2255 unsigned int apic_dfr; 2256 unsigned int apic_spiv; 2257 unsigned int apic_lvtt; 2258 unsigned int apic_lvtpc; 2259 unsigned int apic_lvt0; 2260 unsigned int apic_lvt1; 2261 unsigned int apic_lvterr; 2262 unsigned int apic_tmict; 2263 unsigned int apic_tdcr; 2264 unsigned int apic_thmr; 2265 } apic_pm_state; 2266 2267 static int lapic_suspend(void) 2268 { 2269 unsigned long flags; 2270 int maxlvt; 2271 2272 if (!apic_pm_state.active) 2273 return 0; 2274 2275 maxlvt = lapic_get_maxlvt(); 2276 2277 apic_pm_state.apic_id = apic_read(APIC_ID); 2278 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 2279 apic_pm_state.apic_ldr = apic_read(APIC_LDR); 2280 apic_pm_state.apic_dfr = apic_read(APIC_DFR); 2281 apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2282 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2283 if (maxlvt >= 4) 2284 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2285 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2286 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2287 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2288 apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2289 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 2290 #ifdef CONFIG_X86_THERMAL_VECTOR 2291 if (maxlvt >= 5) 2292 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2293 #endif 2294 2295 local_irq_save(flags); 2296 disable_local_APIC(); 2297 2298 irq_remapping_disable(); 2299 2300 local_irq_restore(flags); 2301 return 0; 2302 } 2303 2304 static void lapic_resume(void) 2305 { 2306 unsigned int l, h; 2307 unsigned long flags; 2308 int maxlvt; 2309 2310 if (!apic_pm_state.active) 2311 return; 2312 2313 local_irq_save(flags); 2314 2315 /* 2316 * IO-APIC and PIC have their own resume routines. 2317 * We just mask them here to make sure the interrupt 2318 * subsystem is completely quiet while we enable x2apic 2319 * and interrupt-remapping. 2320 */ 2321 mask_ioapic_entries(); 2322 legacy_pic->mask_all(); 2323 2324 if (x2apic_mode) 2325 enable_x2apic(); 2326 else { 2327 /* 2328 * Make sure the APICBASE points to the right address 2329 * 2330 * FIXME! This will be wrong if we ever support suspend on 2331 * SMP! We'll need to do this as part of the CPU restore! 2332 */ 2333 if (boot_cpu_data.x86 >= 6) { 2334 rdmsr(MSR_IA32_APICBASE, l, h); 2335 l &= ~MSR_IA32_APICBASE_BASE; 2336 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2337 wrmsr(MSR_IA32_APICBASE, l, h); 2338 } 2339 } 2340 2341 maxlvt = lapic_get_maxlvt(); 2342 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2343 apic_write(APIC_ID, apic_pm_state.apic_id); 2344 apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2345 apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2346 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2347 apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2348 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2349 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 2350 #if defined(CONFIG_X86_MCE_INTEL) 2351 if (maxlvt >= 5) 2352 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2353 #endif 2354 if (maxlvt >= 4) 2355 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2356 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2357 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2358 apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2359 apic_write(APIC_ESR, 0); 2360 apic_read(APIC_ESR); 2361 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2362 apic_write(APIC_ESR, 0); 2363 apic_read(APIC_ESR); 2364 2365 irq_remapping_reenable(x2apic_mode); 2366 2367 local_irq_restore(flags); 2368 } 2369 2370 /* 2371 * This device has no shutdown method - fully functioning local APICs 2372 * are needed on every CPU up until machine_halt/restart/poweroff. 2373 */ 2374 2375 static struct syscore_ops lapic_syscore_ops = { 2376 .resume = lapic_resume, 2377 .suspend = lapic_suspend, 2378 }; 2379 2380 static void apic_pm_activate(void) 2381 { 2382 apic_pm_state.active = 1; 2383 } 2384 2385 static int __init init_lapic_sysfs(void) 2386 { 2387 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 2388 if (cpu_has_apic) 2389 register_syscore_ops(&lapic_syscore_ops); 2390 2391 return 0; 2392 } 2393 2394 /* local apic needs to resume before other devices access its registers. */ 2395 core_initcall(init_lapic_sysfs); 2396 2397 #else /* CONFIG_PM */ 2398 2399 static void apic_pm_activate(void) { } 2400 2401 #endif /* CONFIG_PM */ 2402 2403 #ifdef CONFIG_X86_64 2404 2405 static int apic_cluster_num(void) 2406 { 2407 int i, clusters, zeros; 2408 unsigned id; 2409 u16 *bios_cpu_apicid; 2410 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); 2411 2412 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); 2413 bitmap_zero(clustermap, NUM_APIC_CLUSTERS); 2414 2415 for (i = 0; i < nr_cpu_ids; i++) { 2416 /* are we being called early in kernel startup? */ 2417 if (bios_cpu_apicid) { 2418 id = bios_cpu_apicid[i]; 2419 } else if (i < nr_cpu_ids) { 2420 if (cpu_present(i)) 2421 id = per_cpu(x86_bios_cpu_apicid, i); 2422 else 2423 continue; 2424 } else 2425 break; 2426 2427 if (id != BAD_APICID) 2428 __set_bit(APIC_CLUSTERID(id), clustermap); 2429 } 2430 2431 /* Problem: Partially populated chassis may not have CPUs in some of 2432 * the APIC clusters they have been allocated. Only present CPUs have 2433 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. 2434 * Since clusters are allocated sequentially, count zeros only if 2435 * they are bounded by ones. 2436 */ 2437 clusters = 0; 2438 zeros = 0; 2439 for (i = 0; i < NUM_APIC_CLUSTERS; i++) { 2440 if (test_bit(i, clustermap)) { 2441 clusters += 1 + zeros; 2442 zeros = 0; 2443 } else 2444 ++zeros; 2445 } 2446 2447 return clusters; 2448 } 2449 2450 static int multi_checked; 2451 static int multi; 2452 2453 static int set_multi(const struct dmi_system_id *d) 2454 { 2455 if (multi) 2456 return 0; 2457 pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2458 multi = 1; 2459 return 0; 2460 } 2461 2462 static const struct dmi_system_id multi_dmi_table[] = { 2463 { 2464 .callback = set_multi, 2465 .ident = "IBM System Summit2", 2466 .matches = { 2467 DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2468 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2469 }, 2470 }, 2471 {} 2472 }; 2473 2474 static void dmi_check_multi(void) 2475 { 2476 if (multi_checked) 2477 return; 2478 2479 dmi_check_system(multi_dmi_table); 2480 multi_checked = 1; 2481 } 2482 2483 /* 2484 * apic_is_clustered_box() -- Check if we can expect good TSC 2485 * 2486 * Thus far, the major user of this is IBM's Summit2 series: 2487 * Clustered boxes may have unsynced TSC problems if they are 2488 * multi-chassis. 2489 * Use DMI to check them 2490 */ 2491 int apic_is_clustered_box(void) 2492 { 2493 dmi_check_multi(); 2494 if (multi) 2495 return 1; 2496 2497 if (!is_vsmp_box()) 2498 return 0; 2499 2500 /* 2501 * ScaleMP vSMPowered boxes have one cluster per board and TSCs are 2502 * not guaranteed to be synced between boards 2503 */ 2504 if (apic_cluster_num() > 1) 2505 return 1; 2506 2507 return 0; 2508 } 2509 #endif 2510 2511 /* 2512 * APIC command line parameters 2513 */ 2514 static int __init setup_disableapic(char *arg) 2515 { 2516 disable_apic = 1; 2517 setup_clear_cpu_cap(X86_FEATURE_APIC); 2518 return 0; 2519 } 2520 early_param("disableapic", setup_disableapic); 2521 2522 /* same as disableapic, for compatibility */ 2523 static int __init setup_nolapic(char *arg) 2524 { 2525 return setup_disableapic(arg); 2526 } 2527 early_param("nolapic", setup_nolapic); 2528 2529 static int __init parse_lapic_timer_c2_ok(char *arg) 2530 { 2531 local_apic_timer_c2_ok = 1; 2532 return 0; 2533 } 2534 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2535 2536 static int __init parse_disable_apic_timer(char *arg) 2537 { 2538 disable_apic_timer = 1; 2539 return 0; 2540 } 2541 early_param("noapictimer", parse_disable_apic_timer); 2542 2543 static int __init parse_nolapic_timer(char *arg) 2544 { 2545 disable_apic_timer = 1; 2546 return 0; 2547 } 2548 early_param("nolapic_timer", parse_nolapic_timer); 2549 2550 static int __init apic_set_verbosity(char *arg) 2551 { 2552 if (!arg) { 2553 #ifdef CONFIG_X86_64 2554 skip_ioapic_setup = 0; 2555 return 0; 2556 #endif 2557 return -EINVAL; 2558 } 2559 2560 if (strcmp("debug", arg) == 0) 2561 apic_verbosity = APIC_DEBUG; 2562 else if (strcmp("verbose", arg) == 0) 2563 apic_verbosity = APIC_VERBOSE; 2564 else { 2565 pr_warning("APIC Verbosity level %s not recognised" 2566 " use apic=verbose or apic=debug\n", arg); 2567 return -EINVAL; 2568 } 2569 2570 return 0; 2571 } 2572 early_param("apic", apic_set_verbosity); 2573 2574 static int __init lapic_insert_resource(void) 2575 { 2576 if (!apic_phys) 2577 return -1; 2578 2579 /* Put local APIC into the resource map. */ 2580 lapic_resource.start = apic_phys; 2581 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2582 insert_resource(&iomem_resource, &lapic_resource); 2583 2584 return 0; 2585 } 2586 2587 /* 2588 * need call insert after e820_reserve_resources() 2589 * that is using request_resource 2590 */ 2591 late_initcall(lapic_insert_resource); 2592