1 /* 2 * Local APIC handling, local APIC timers 3 * 4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 5 * 6 * Fixes 7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 8 * thanks to Eric Gilmore 9 * and Rolf G. Tews 10 * for testing these extensively. 11 * Maciej W. Rozycki : Various updates and fixes. 12 * Mikael Pettersson : Power Management for UP-APIC. 13 * Pavel Machek and 14 * Mikael Pettersson : PM converted to driver model. 15 */ 16 17 #include <linux/perf_event.h> 18 #include <linux/kernel_stat.h> 19 #include <linux/mc146818rtc.h> 20 #include <linux/acpi_pmtmr.h> 21 #include <linux/clockchips.h> 22 #include <linux/interrupt.h> 23 #include <linux/bootmem.h> 24 #include <linux/ftrace.h> 25 #include <linux/ioport.h> 26 #include <linux/export.h> 27 #include <linux/syscore_ops.h> 28 #include <linux/delay.h> 29 #include <linux/timex.h> 30 #include <linux/i8253.h> 31 #include <linux/dmar.h> 32 #include <linux/init.h> 33 #include <linux/cpu.h> 34 #include <linux/dmi.h> 35 #include <linux/smp.h> 36 #include <linux/mm.h> 37 38 #include <asm/trace/irq_vectors.h> 39 #include <asm/irq_remapping.h> 40 #include <asm/perf_event.h> 41 #include <asm/x86_init.h> 42 #include <asm/pgalloc.h> 43 #include <linux/atomic.h> 44 #include <asm/mpspec.h> 45 #include <asm/i8259.h> 46 #include <asm/proto.h> 47 #include <asm/apic.h> 48 #include <asm/io_apic.h> 49 #include <asm/desc.h> 50 #include <asm/hpet.h> 51 #include <asm/mtrr.h> 52 #include <asm/time.h> 53 #include <asm/smp.h> 54 #include <asm/mce.h> 55 #include <asm/tsc.h> 56 #include <asm/hypervisor.h> 57 #include <asm/cpu_device_id.h> 58 #include <asm/intel-family.h> 59 60 unsigned int num_processors; 61 62 unsigned disabled_cpus; 63 64 /* Processor that is doing the boot up */ 65 unsigned int boot_cpu_physical_apicid = -1U; 66 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); 67 68 u8 boot_cpu_apic_version; 69 70 /* 71 * The highest APIC ID seen during enumeration. 72 */ 73 static unsigned int max_physical_apicid; 74 75 /* 76 * Bitmask of physically existing CPUs: 77 */ 78 physid_mask_t phys_cpu_present_map; 79 80 /* 81 * Processor to be disabled specified by kernel parameter 82 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to 83 * avoid undefined behaviour caused by sending INIT from AP to BSP. 84 */ 85 static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID; 86 87 /* 88 * This variable controls which CPUs receive external NMIs. By default, 89 * external NMIs are delivered only to the BSP. 90 */ 91 static int apic_extnmi = APIC_EXTNMI_BSP; 92 93 /* 94 * Map cpu index to physical APIC ID 95 */ 96 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); 97 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID); 98 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX); 99 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 100 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 101 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid); 102 103 #ifdef CONFIG_X86_32 104 105 /* 106 * On x86_32, the mapping between cpu and logical apicid may vary 107 * depending on apic in use. The following early percpu variable is 108 * used for the mapping. This is where the behaviors of x86_64 and 32 109 * actually diverge. Let's keep it ugly for now. 110 */ 111 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID); 112 113 /* Local APIC was disabled by the BIOS and enabled by the kernel */ 114 static int enabled_via_apicbase; 115 116 /* 117 * Handle interrupt mode configuration register (IMCR). 118 * This register controls whether the interrupt signals 119 * that reach the BSP come from the master PIC or from the 120 * local APIC. Before entering Symmetric I/O Mode, either 121 * the BIOS or the operating system must switch out of 122 * PIC Mode by changing the IMCR. 123 */ 124 static inline void imcr_pic_to_apic(void) 125 { 126 /* select IMCR register */ 127 outb(0x70, 0x22); 128 /* NMI and 8259 INTR go through APIC */ 129 outb(0x01, 0x23); 130 } 131 132 static inline void imcr_apic_to_pic(void) 133 { 134 /* select IMCR register */ 135 outb(0x70, 0x22); 136 /* NMI and 8259 INTR go directly to BSP */ 137 outb(0x00, 0x23); 138 } 139 #endif 140 141 /* 142 * Knob to control our willingness to enable the local APIC. 143 * 144 * +1=force-enable 145 */ 146 static int force_enable_local_apic __initdata; 147 148 /* 149 * APIC command line parameters 150 */ 151 static int __init parse_lapic(char *arg) 152 { 153 if (IS_ENABLED(CONFIG_X86_32) && !arg) 154 force_enable_local_apic = 1; 155 else if (arg && !strncmp(arg, "notscdeadline", 13)) 156 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 157 return 0; 158 } 159 early_param("lapic", parse_lapic); 160 161 #ifdef CONFIG_X86_64 162 static int apic_calibrate_pmtmr __initdata; 163 static __init int setup_apicpmtimer(char *s) 164 { 165 apic_calibrate_pmtmr = 1; 166 notsc_setup(NULL); 167 return 0; 168 } 169 __setup("apicpmtimer", setup_apicpmtimer); 170 #endif 171 172 unsigned long mp_lapic_addr; 173 int disable_apic; 174 /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 175 static int disable_apic_timer __initdata; 176 /* Local APIC timer works in C2 */ 177 int local_apic_timer_c2_ok; 178 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 179 180 /* 181 * Debug level, exported for io_apic.c 182 */ 183 unsigned int apic_verbosity; 184 185 int pic_mode; 186 187 /* Have we found an MP table */ 188 int smp_found_config; 189 190 static struct resource lapic_resource = { 191 .name = "Local APIC", 192 .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 193 }; 194 195 unsigned int lapic_timer_frequency = 0; 196 197 static void apic_pm_activate(void); 198 199 static unsigned long apic_phys; 200 201 /* 202 * Get the LAPIC version 203 */ 204 static inline int lapic_get_version(void) 205 { 206 return GET_APIC_VERSION(apic_read(APIC_LVR)); 207 } 208 209 /* 210 * Check, if the APIC is integrated or a separate chip 211 */ 212 static inline int lapic_is_integrated(void) 213 { 214 return APIC_INTEGRATED(lapic_get_version()); 215 } 216 217 /* 218 * Check, whether this is a modern or a first generation APIC 219 */ 220 static int modern_apic(void) 221 { 222 /* AMD systems use old APIC versions, so check the CPU */ 223 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 224 boot_cpu_data.x86 >= 0xf) 225 return 1; 226 return lapic_get_version() >= 0x14; 227 } 228 229 /* 230 * right after this call apic become NOOP driven 231 * so apic->write/read doesn't do anything 232 */ 233 static void __init apic_disable(void) 234 { 235 pr_info("APIC: switched to apic NOOP\n"); 236 apic = &apic_noop; 237 } 238 239 void native_apic_wait_icr_idle(void) 240 { 241 while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 242 cpu_relax(); 243 } 244 245 u32 native_safe_apic_wait_icr_idle(void) 246 { 247 u32 send_status; 248 int timeout; 249 250 timeout = 0; 251 do { 252 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 253 if (!send_status) 254 break; 255 inc_irq_stat(icr_read_retry_count); 256 udelay(100); 257 } while (timeout++ < 1000); 258 259 return send_status; 260 } 261 262 void native_apic_icr_write(u32 low, u32 id) 263 { 264 unsigned long flags; 265 266 local_irq_save(flags); 267 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 268 apic_write(APIC_ICR, low); 269 local_irq_restore(flags); 270 } 271 272 u64 native_apic_icr_read(void) 273 { 274 u32 icr1, icr2; 275 276 icr2 = apic_read(APIC_ICR2); 277 icr1 = apic_read(APIC_ICR); 278 279 return icr1 | ((u64)icr2 << 32); 280 } 281 282 #ifdef CONFIG_X86_32 283 /** 284 * get_physical_broadcast - Get number of physical broadcast IDs 285 */ 286 int get_physical_broadcast(void) 287 { 288 return modern_apic() ? 0xff : 0xf; 289 } 290 #endif 291 292 /** 293 * lapic_get_maxlvt - get the maximum number of local vector table entries 294 */ 295 int lapic_get_maxlvt(void) 296 { 297 /* 298 * - we always have APIC integrated on 64bit mode 299 * - 82489DXs do not report # of LVT entries 300 */ 301 return lapic_is_integrated() ? GET_APIC_MAXLVT(apic_read(APIC_LVR)) : 2; 302 } 303 304 /* 305 * Local APIC timer 306 */ 307 308 /* Clock divisor */ 309 #define APIC_DIVISOR 16 310 #define TSC_DIVISOR 8 311 312 /* 313 * This function sets up the local APIC timer, with a timeout of 314 * 'clocks' APIC bus clock. During calibration we actually call 315 * this function twice on the boot CPU, once with a bogus timeout 316 * value, second time for real. The other (noncalibrating) CPUs 317 * call this function only once, with the real, calibrated value. 318 * 319 * We do reads before writes even if unnecessary, to get around the 320 * P5 APIC double write bug. 321 */ 322 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 323 { 324 unsigned int lvtt_value, tmp_value; 325 326 lvtt_value = LOCAL_TIMER_VECTOR; 327 if (!oneshot) 328 lvtt_value |= APIC_LVT_TIMER_PERIODIC; 329 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 330 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE; 331 332 if (!lapic_is_integrated()) 333 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 334 335 if (!irqen) 336 lvtt_value |= APIC_LVT_MASKED; 337 338 apic_write(APIC_LVTT, lvtt_value); 339 340 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { 341 /* 342 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, 343 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized. 344 * According to Intel, MFENCE can do the serialization here. 345 */ 346 asm volatile("mfence" : : : "memory"); 347 348 printk_once(KERN_DEBUG "TSC deadline timer enabled\n"); 349 return; 350 } 351 352 /* 353 * Divide PICLK by 16 354 */ 355 tmp_value = apic_read(APIC_TDCR); 356 apic_write(APIC_TDCR, 357 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 358 APIC_TDR_DIV_16); 359 360 if (!oneshot) 361 apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 362 } 363 364 /* 365 * Setup extended LVT, AMD specific 366 * 367 * Software should use the LVT offsets the BIOS provides. The offsets 368 * are determined by the subsystems using it like those for MCE 369 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts 370 * are supported. Beginning with family 10h at least 4 offsets are 371 * available. 372 * 373 * Since the offsets must be consistent for all cores, we keep track 374 * of the LVT offsets in software and reserve the offset for the same 375 * vector also to be used on other cores. An offset is freed by 376 * setting the entry to APIC_EILVT_MASKED. 377 * 378 * If the BIOS is right, there should be no conflicts. Otherwise a 379 * "[Firmware Bug]: ..." error message is generated. However, if 380 * software does not properly determines the offsets, it is not 381 * necessarily a BIOS bug. 382 */ 383 384 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; 385 386 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) 387 { 388 return (old & APIC_EILVT_MASKED) 389 || (new == APIC_EILVT_MASKED) 390 || ((new & ~APIC_EILVT_MASKED) == old); 391 } 392 393 static unsigned int reserve_eilvt_offset(int offset, unsigned int new) 394 { 395 unsigned int rsvd, vector; 396 397 if (offset >= APIC_EILVT_NR_MAX) 398 return ~0; 399 400 rsvd = atomic_read(&eilvt_offsets[offset]); 401 do { 402 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ 403 if (vector && !eilvt_entry_is_changeable(vector, new)) 404 /* may not change if vectors are different */ 405 return rsvd; 406 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); 407 } while (rsvd != new); 408 409 rsvd &= ~APIC_EILVT_MASKED; 410 if (rsvd && rsvd != vector) 411 pr_info("LVT offset %d assigned for vector 0x%02x\n", 412 offset, rsvd); 413 414 return new; 415 } 416 417 /* 418 * If mask=1, the LVT entry does not generate interrupts while mask=0 419 * enables the vector. See also the BKDGs. Must be called with 420 * preemption disabled. 421 */ 422 423 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) 424 { 425 unsigned long reg = APIC_EILVTn(offset); 426 unsigned int new, old, reserved; 427 428 new = (mask << 16) | (msg_type << 8) | vector; 429 old = apic_read(reg); 430 reserved = reserve_eilvt_offset(offset, new); 431 432 if (reserved != new) { 433 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 434 "vector 0x%x, but the register is already in use for " 435 "vector 0x%x on another cpu\n", 436 smp_processor_id(), reg, offset, new, reserved); 437 return -EINVAL; 438 } 439 440 if (!eilvt_entry_is_changeable(old, new)) { 441 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 442 "vector 0x%x, but the register is already in use for " 443 "vector 0x%x on this cpu\n", 444 smp_processor_id(), reg, offset, new, old); 445 return -EBUSY; 446 } 447 448 apic_write(reg, new); 449 450 return 0; 451 } 452 EXPORT_SYMBOL_GPL(setup_APIC_eilvt); 453 454 /* 455 * Program the next event, relative to now 456 */ 457 static int lapic_next_event(unsigned long delta, 458 struct clock_event_device *evt) 459 { 460 apic_write(APIC_TMICT, delta); 461 return 0; 462 } 463 464 static int lapic_next_deadline(unsigned long delta, 465 struct clock_event_device *evt) 466 { 467 u64 tsc; 468 469 tsc = rdtsc(); 470 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); 471 return 0; 472 } 473 474 static int lapic_timer_shutdown(struct clock_event_device *evt) 475 { 476 unsigned int v; 477 478 /* Lapic used as dummy for broadcast ? */ 479 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 480 return 0; 481 482 v = apic_read(APIC_LVTT); 483 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 484 apic_write(APIC_LVTT, v); 485 apic_write(APIC_TMICT, 0); 486 return 0; 487 } 488 489 static inline int 490 lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot) 491 { 492 /* Lapic used as dummy for broadcast ? */ 493 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 494 return 0; 495 496 __setup_APIC_LVTT(lapic_timer_frequency, oneshot, 1); 497 return 0; 498 } 499 500 static int lapic_timer_set_periodic(struct clock_event_device *evt) 501 { 502 return lapic_timer_set_periodic_oneshot(evt, false); 503 } 504 505 static int lapic_timer_set_oneshot(struct clock_event_device *evt) 506 { 507 return lapic_timer_set_periodic_oneshot(evt, true); 508 } 509 510 /* 511 * Local APIC timer broadcast function 512 */ 513 static void lapic_timer_broadcast(const struct cpumask *mask) 514 { 515 #ifdef CONFIG_SMP 516 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 517 #endif 518 } 519 520 521 /* 522 * The local apic timer can be used for any function which is CPU local. 523 */ 524 static struct clock_event_device lapic_clockevent = { 525 .name = "lapic", 526 .features = CLOCK_EVT_FEAT_PERIODIC | 527 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP 528 | CLOCK_EVT_FEAT_DUMMY, 529 .shift = 32, 530 .set_state_shutdown = lapic_timer_shutdown, 531 .set_state_periodic = lapic_timer_set_periodic, 532 .set_state_oneshot = lapic_timer_set_oneshot, 533 .set_state_oneshot_stopped = lapic_timer_shutdown, 534 .set_next_event = lapic_next_event, 535 .broadcast = lapic_timer_broadcast, 536 .rating = 100, 537 .irq = -1, 538 }; 539 static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 540 541 #define DEADLINE_MODEL_MATCH_FUNC(model, func) \ 542 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&func } 543 544 #define DEADLINE_MODEL_MATCH_REV(model, rev) \ 545 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)rev } 546 547 static u32 hsx_deadline_rev(void) 548 { 549 switch (boot_cpu_data.x86_stepping) { 550 case 0x02: return 0x3a; /* EP */ 551 case 0x04: return 0x0f; /* EX */ 552 } 553 554 return ~0U; 555 } 556 557 static u32 bdx_deadline_rev(void) 558 { 559 switch (boot_cpu_data.x86_stepping) { 560 case 0x02: return 0x00000011; 561 case 0x03: return 0x0700000e; 562 case 0x04: return 0x0f00000c; 563 case 0x05: return 0x0e000003; 564 } 565 566 return ~0U; 567 } 568 569 static u32 skx_deadline_rev(void) 570 { 571 switch (boot_cpu_data.x86_stepping) { 572 case 0x03: return 0x01000136; 573 case 0x04: return 0x02000014; 574 } 575 576 if (boot_cpu_data.x86_stepping > 4) 577 return 0; 578 579 return ~0U; 580 } 581 582 static const struct x86_cpu_id deadline_match[] = { 583 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_HASWELL_X, hsx_deadline_rev), 584 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_X, 0x0b000020), 585 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_BROADWELL_XEON_D, bdx_deadline_rev), 586 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_SKYLAKE_X, skx_deadline_rev), 587 588 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_CORE, 0x22), 589 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_ULT, 0x20), 590 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_GT3E, 0x17), 591 592 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_CORE, 0x25), 593 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_GT3E, 0x17), 594 595 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_MOBILE, 0xb2), 596 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_DESKTOP, 0xb2), 597 598 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_MOBILE, 0x52), 599 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_DESKTOP, 0x52), 600 601 {}, 602 }; 603 604 static void apic_check_deadline_errata(void) 605 { 606 const struct x86_cpu_id *m; 607 u32 rev; 608 609 if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER) || 610 boot_cpu_has(X86_FEATURE_HYPERVISOR)) 611 return; 612 613 m = x86_match_cpu(deadline_match); 614 if (!m) 615 return; 616 617 /* 618 * Function pointers will have the MSB set due to address layout, 619 * immediate revisions will not. 620 */ 621 if ((long)m->driver_data < 0) 622 rev = ((u32 (*)(void))(m->driver_data))(); 623 else 624 rev = (u32)m->driver_data; 625 626 if (boot_cpu_data.microcode >= rev) 627 return; 628 629 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 630 pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; " 631 "please update microcode to version: 0x%x (or later)\n", rev); 632 } 633 634 /* 635 * Setup the local APIC timer for this CPU. Copy the initialized values 636 * of the boot CPU and register the clock event in the framework. 637 */ 638 static void setup_APIC_timer(void) 639 { 640 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 641 642 if (this_cpu_has(X86_FEATURE_ARAT)) { 643 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 644 /* Make LAPIC timer preferrable over percpu HPET */ 645 lapic_clockevent.rating = 150; 646 } 647 648 memcpy(levt, &lapic_clockevent, sizeof(*levt)); 649 levt->cpumask = cpumask_of(smp_processor_id()); 650 651 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 652 levt->name = "lapic-deadline"; 653 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | 654 CLOCK_EVT_FEAT_DUMMY); 655 levt->set_next_event = lapic_next_deadline; 656 clockevents_config_and_register(levt, 657 tsc_khz * (1000 / TSC_DIVISOR), 658 0xF, ~0UL); 659 } else 660 clockevents_register_device(levt); 661 } 662 663 /* 664 * Install the updated TSC frequency from recalibration at the TSC 665 * deadline clockevent devices. 666 */ 667 static void __lapic_update_tsc_freq(void *info) 668 { 669 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 670 671 if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 672 return; 673 674 clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR)); 675 } 676 677 void lapic_update_tsc_freq(void) 678 { 679 /* 680 * The clockevent device's ->mult and ->shift can both be 681 * changed. In order to avoid races, schedule the frequency 682 * update code on each CPU. 683 */ 684 on_each_cpu(__lapic_update_tsc_freq, NULL, 0); 685 } 686 687 /* 688 * In this functions we calibrate APIC bus clocks to the external timer. 689 * 690 * We want to do the calibration only once since we want to have local timer 691 * irqs syncron. CPUs connected by the same APIC bus have the very same bus 692 * frequency. 693 * 694 * This was previously done by reading the PIT/HPET and waiting for a wrap 695 * around to find out, that a tick has elapsed. I have a box, where the PIT 696 * readout is broken, so it never gets out of the wait loop again. This was 697 * also reported by others. 698 * 699 * Monitoring the jiffies value is inaccurate and the clockevents 700 * infrastructure allows us to do a simple substitution of the interrupt 701 * handler. 702 * 703 * The calibration routine also uses the pm_timer when possible, as the PIT 704 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 705 * back to normal later in the boot process). 706 */ 707 708 #define LAPIC_CAL_LOOPS (HZ/10) 709 710 static __initdata int lapic_cal_loops = -1; 711 static __initdata long lapic_cal_t1, lapic_cal_t2; 712 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 713 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 714 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 715 716 /* 717 * Temporary interrupt handler. 718 */ 719 static void __init lapic_cal_handler(struct clock_event_device *dev) 720 { 721 unsigned long long tsc = 0; 722 long tapic = apic_read(APIC_TMCCT); 723 unsigned long pm = acpi_pm_read_early(); 724 725 if (boot_cpu_has(X86_FEATURE_TSC)) 726 tsc = rdtsc(); 727 728 switch (lapic_cal_loops++) { 729 case 0: 730 lapic_cal_t1 = tapic; 731 lapic_cal_tsc1 = tsc; 732 lapic_cal_pm1 = pm; 733 lapic_cal_j1 = jiffies; 734 break; 735 736 case LAPIC_CAL_LOOPS: 737 lapic_cal_t2 = tapic; 738 lapic_cal_tsc2 = tsc; 739 if (pm < lapic_cal_pm1) 740 pm += ACPI_PM_OVRRUN; 741 lapic_cal_pm2 = pm; 742 lapic_cal_j2 = jiffies; 743 break; 744 } 745 } 746 747 static int __init 748 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 749 { 750 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 751 const long pm_thresh = pm_100ms / 100; 752 unsigned long mult; 753 u64 res; 754 755 #ifndef CONFIG_X86_PM_TIMER 756 return -1; 757 #endif 758 759 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 760 761 /* Check, if the PM timer is available */ 762 if (!deltapm) 763 return -1; 764 765 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 766 767 if (deltapm > (pm_100ms - pm_thresh) && 768 deltapm < (pm_100ms + pm_thresh)) { 769 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 770 return 0; 771 } 772 773 res = (((u64)deltapm) * mult) >> 22; 774 do_div(res, 1000000); 775 pr_warning("APIC calibration not consistent " 776 "with PM-Timer: %ldms instead of 100ms\n",(long)res); 777 778 /* Correct the lapic counter value */ 779 res = (((u64)(*delta)) * pm_100ms); 780 do_div(res, deltapm); 781 pr_info("APIC delta adjusted to PM-Timer: " 782 "%lu (%ld)\n", (unsigned long)res, *delta); 783 *delta = (long)res; 784 785 /* Correct the tsc counter value */ 786 if (boot_cpu_has(X86_FEATURE_TSC)) { 787 res = (((u64)(*deltatsc)) * pm_100ms); 788 do_div(res, deltapm); 789 apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 790 "PM-Timer: %lu (%ld)\n", 791 (unsigned long)res, *deltatsc); 792 *deltatsc = (long)res; 793 } 794 795 return 0; 796 } 797 798 static int __init calibrate_APIC_clock(void) 799 { 800 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 801 void (*real_handler)(struct clock_event_device *dev); 802 unsigned long deltaj; 803 long delta, deltatsc; 804 int pm_referenced = 0; 805 806 /** 807 * check if lapic timer has already been calibrated by platform 808 * specific routine, such as tsc calibration code. if so, we just fill 809 * in the clockevent structure and return. 810 */ 811 812 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 813 return 0; 814 } else if (lapic_timer_frequency) { 815 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", 816 lapic_timer_frequency); 817 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR, 818 TICK_NSEC, lapic_clockevent.shift); 819 lapic_clockevent.max_delta_ns = 820 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); 821 lapic_clockevent.max_delta_ticks = 0x7FFFFF; 822 lapic_clockevent.min_delta_ns = 823 clockevent_delta2ns(0xF, &lapic_clockevent); 824 lapic_clockevent.min_delta_ticks = 0xF; 825 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 826 return 0; 827 } 828 829 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 830 "calibrating APIC timer ...\n"); 831 832 local_irq_disable(); 833 834 /* Replace the global interrupt handler */ 835 real_handler = global_clock_event->event_handler; 836 global_clock_event->event_handler = lapic_cal_handler; 837 838 /* 839 * Setup the APIC counter to maximum. There is no way the lapic 840 * can underflow in the 100ms detection time frame 841 */ 842 __setup_APIC_LVTT(0xffffffff, 0, 0); 843 844 /* Let the interrupts run */ 845 local_irq_enable(); 846 847 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 848 cpu_relax(); 849 850 local_irq_disable(); 851 852 /* Restore the real event handler */ 853 global_clock_event->event_handler = real_handler; 854 855 /* Build delta t1-t2 as apic timer counts down */ 856 delta = lapic_cal_t1 - lapic_cal_t2; 857 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 858 859 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 860 861 /* we trust the PM based calibration if possible */ 862 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 863 &delta, &deltatsc); 864 865 /* Calculate the scaled math multiplication factor */ 866 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 867 lapic_clockevent.shift); 868 lapic_clockevent.max_delta_ns = 869 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); 870 lapic_clockevent.max_delta_ticks = 0x7FFFFFFF; 871 lapic_clockevent.min_delta_ns = 872 clockevent_delta2ns(0xF, &lapic_clockevent); 873 lapic_clockevent.min_delta_ticks = 0xF; 874 875 lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 876 877 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 878 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); 879 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 880 lapic_timer_frequency); 881 882 if (boot_cpu_has(X86_FEATURE_TSC)) { 883 apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 884 "%ld.%04ld MHz.\n", 885 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 886 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 887 } 888 889 apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 890 "%u.%04u MHz.\n", 891 lapic_timer_frequency / (1000000 / HZ), 892 lapic_timer_frequency % (1000000 / HZ)); 893 894 /* 895 * Do a sanity check on the APIC calibration result 896 */ 897 if (lapic_timer_frequency < (1000000 / HZ)) { 898 local_irq_enable(); 899 pr_warning("APIC frequency too slow, disabling apic timer\n"); 900 return -1; 901 } 902 903 levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 904 905 /* 906 * PM timer calibration failed or not turned on 907 * so lets try APIC timer based calibration 908 */ 909 if (!pm_referenced) { 910 apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 911 912 /* 913 * Setup the apic timer manually 914 */ 915 levt->event_handler = lapic_cal_handler; 916 lapic_timer_set_periodic(levt); 917 lapic_cal_loops = -1; 918 919 /* Let the interrupts run */ 920 local_irq_enable(); 921 922 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 923 cpu_relax(); 924 925 /* Stop the lapic timer */ 926 local_irq_disable(); 927 lapic_timer_shutdown(levt); 928 929 /* Jiffies delta */ 930 deltaj = lapic_cal_j2 - lapic_cal_j1; 931 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 932 933 /* Check, if the jiffies result is consistent */ 934 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 935 apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 936 else 937 levt->features |= CLOCK_EVT_FEAT_DUMMY; 938 } 939 local_irq_enable(); 940 941 if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 942 pr_warning("APIC timer disabled due to verification failure\n"); 943 return -1; 944 } 945 946 return 0; 947 } 948 949 /* 950 * Setup the boot APIC 951 * 952 * Calibrate and verify the result. 953 */ 954 void __init setup_boot_APIC_clock(void) 955 { 956 /* 957 * The local apic timer can be disabled via the kernel 958 * commandline or from the CPU detection code. Register the lapic 959 * timer as a dummy clock event source on SMP systems, so the 960 * broadcast mechanism is used. On UP systems simply ignore it. 961 */ 962 if (disable_apic_timer) { 963 pr_info("Disabling APIC timer\n"); 964 /* No broadcast on UP ! */ 965 if (num_possible_cpus() > 1) { 966 lapic_clockevent.mult = 1; 967 setup_APIC_timer(); 968 } 969 return; 970 } 971 972 if (calibrate_APIC_clock()) { 973 /* No broadcast on UP ! */ 974 if (num_possible_cpus() > 1) 975 setup_APIC_timer(); 976 return; 977 } 978 979 /* 980 * If nmi_watchdog is set to IO_APIC, we need the 981 * PIT/HPET going. Otherwise register lapic as a dummy 982 * device. 983 */ 984 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 985 986 /* Setup the lapic or request the broadcast */ 987 setup_APIC_timer(); 988 amd_e400_c1e_apic_setup(); 989 } 990 991 void setup_secondary_APIC_clock(void) 992 { 993 setup_APIC_timer(); 994 amd_e400_c1e_apic_setup(); 995 } 996 997 /* 998 * The guts of the apic timer interrupt 999 */ 1000 static void local_apic_timer_interrupt(void) 1001 { 1002 struct clock_event_device *evt = this_cpu_ptr(&lapic_events); 1003 1004 /* 1005 * Normally we should not be here till LAPIC has been initialized but 1006 * in some cases like kdump, its possible that there is a pending LAPIC 1007 * timer interrupt from previous kernel's context and is delivered in 1008 * new kernel the moment interrupts are enabled. 1009 * 1010 * Interrupts are enabled early and LAPIC is setup much later, hence 1011 * its possible that when we get here evt->event_handler is NULL. 1012 * Check for event_handler being NULL and discard the interrupt as 1013 * spurious. 1014 */ 1015 if (!evt->event_handler) { 1016 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", 1017 smp_processor_id()); 1018 /* Switch it off */ 1019 lapic_timer_shutdown(evt); 1020 return; 1021 } 1022 1023 /* 1024 * the NMI deadlock-detector uses this. 1025 */ 1026 inc_irq_stat(apic_timer_irqs); 1027 1028 evt->event_handler(evt); 1029 } 1030 1031 /* 1032 * Local APIC timer interrupt. This is the most natural way for doing 1033 * local interrupts, but local timer interrupts can be emulated by 1034 * broadcast interrupts too. [in case the hw doesn't support APIC timers] 1035 * 1036 * [ if a single-CPU system runs an SMP kernel then we call the local 1037 * interrupt as well. Thus we cannot inline the local irq ... ] 1038 */ 1039 __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) 1040 { 1041 struct pt_regs *old_regs = set_irq_regs(regs); 1042 1043 /* 1044 * NOTE! We'd better ACK the irq immediately, 1045 * because timer handling can be slow. 1046 * 1047 * update_process_times() expects us to have done irq_enter(). 1048 * Besides, if we don't timer interrupts ignore the global 1049 * interrupt lock, which is the WrongThing (tm) to do. 1050 */ 1051 entering_ack_irq(); 1052 trace_local_timer_entry(LOCAL_TIMER_VECTOR); 1053 local_apic_timer_interrupt(); 1054 trace_local_timer_exit(LOCAL_TIMER_VECTOR); 1055 exiting_irq(); 1056 1057 set_irq_regs(old_regs); 1058 } 1059 1060 int setup_profiling_timer(unsigned int multiplier) 1061 { 1062 return -EINVAL; 1063 } 1064 1065 /* 1066 * Local APIC start and shutdown 1067 */ 1068 1069 /** 1070 * clear_local_APIC - shutdown the local APIC 1071 * 1072 * This is called, when a CPU is disabled and before rebooting, so the state of 1073 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 1074 * leftovers during boot. 1075 */ 1076 void clear_local_APIC(void) 1077 { 1078 int maxlvt; 1079 u32 v; 1080 1081 /* APIC hasn't been mapped yet */ 1082 if (!x2apic_mode && !apic_phys) 1083 return; 1084 1085 maxlvt = lapic_get_maxlvt(); 1086 /* 1087 * Masking an LVT entry can trigger a local APIC error 1088 * if the vector is zero. Mask LVTERR first to prevent this. 1089 */ 1090 if (maxlvt >= 3) { 1091 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 1092 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 1093 } 1094 /* 1095 * Careful: we have to set masks only first to deassert 1096 * any level-triggered sources. 1097 */ 1098 v = apic_read(APIC_LVTT); 1099 apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 1100 v = apic_read(APIC_LVT0); 1101 apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 1102 v = apic_read(APIC_LVT1); 1103 apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 1104 if (maxlvt >= 4) { 1105 v = apic_read(APIC_LVTPC); 1106 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 1107 } 1108 1109 /* lets not touch this if we didn't frob it */ 1110 #ifdef CONFIG_X86_THERMAL_VECTOR 1111 if (maxlvt >= 5) { 1112 v = apic_read(APIC_LVTTHMR); 1113 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 1114 } 1115 #endif 1116 #ifdef CONFIG_X86_MCE_INTEL 1117 if (maxlvt >= 6) { 1118 v = apic_read(APIC_LVTCMCI); 1119 if (!(v & APIC_LVT_MASKED)) 1120 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 1121 } 1122 #endif 1123 1124 /* 1125 * Clean APIC state for other OSs: 1126 */ 1127 apic_write(APIC_LVTT, APIC_LVT_MASKED); 1128 apic_write(APIC_LVT0, APIC_LVT_MASKED); 1129 apic_write(APIC_LVT1, APIC_LVT_MASKED); 1130 if (maxlvt >= 3) 1131 apic_write(APIC_LVTERR, APIC_LVT_MASKED); 1132 if (maxlvt >= 4) 1133 apic_write(APIC_LVTPC, APIC_LVT_MASKED); 1134 1135 /* Integrated APIC (!82489DX) ? */ 1136 if (lapic_is_integrated()) { 1137 if (maxlvt > 3) 1138 /* Clear ESR due to Pentium errata 3AP and 11AP */ 1139 apic_write(APIC_ESR, 0); 1140 apic_read(APIC_ESR); 1141 } 1142 } 1143 1144 /** 1145 * disable_local_APIC - clear and disable the local APIC 1146 */ 1147 void disable_local_APIC(void) 1148 { 1149 unsigned int value; 1150 1151 /* APIC hasn't been mapped yet */ 1152 if (!x2apic_mode && !apic_phys) 1153 return; 1154 1155 clear_local_APIC(); 1156 1157 /* 1158 * Disable APIC (implies clearing of registers 1159 * for 82489DX!). 1160 */ 1161 value = apic_read(APIC_SPIV); 1162 value &= ~APIC_SPIV_APIC_ENABLED; 1163 apic_write(APIC_SPIV, value); 1164 1165 #ifdef CONFIG_X86_32 1166 /* 1167 * When LAPIC was disabled by the BIOS and enabled by the kernel, 1168 * restore the disabled state. 1169 */ 1170 if (enabled_via_apicbase) { 1171 unsigned int l, h; 1172 1173 rdmsr(MSR_IA32_APICBASE, l, h); 1174 l &= ~MSR_IA32_APICBASE_ENABLE; 1175 wrmsr(MSR_IA32_APICBASE, l, h); 1176 } 1177 #endif 1178 } 1179 1180 /* 1181 * If Linux enabled the LAPIC against the BIOS default disable it down before 1182 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 1183 * not power-off. Additionally clear all LVT entries before disable_local_APIC 1184 * for the case where Linux didn't enable the LAPIC. 1185 */ 1186 void lapic_shutdown(void) 1187 { 1188 unsigned long flags; 1189 1190 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) 1191 return; 1192 1193 local_irq_save(flags); 1194 1195 #ifdef CONFIG_X86_32 1196 if (!enabled_via_apicbase) 1197 clear_local_APIC(); 1198 else 1199 #endif 1200 disable_local_APIC(); 1201 1202 1203 local_irq_restore(flags); 1204 } 1205 1206 /** 1207 * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1208 */ 1209 void __init sync_Arb_IDs(void) 1210 { 1211 /* 1212 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1213 * needed on AMD. 1214 */ 1215 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1216 return; 1217 1218 /* 1219 * Wait for idle. 1220 */ 1221 apic_wait_icr_idle(); 1222 1223 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1224 apic_write(APIC_ICR, APIC_DEST_ALLINC | 1225 APIC_INT_LEVELTRIG | APIC_DM_INIT); 1226 } 1227 1228 enum apic_intr_mode_id apic_intr_mode; 1229 1230 static int __init apic_intr_mode_select(void) 1231 { 1232 /* Check kernel option */ 1233 if (disable_apic) { 1234 pr_info("APIC disabled via kernel command line\n"); 1235 return APIC_PIC; 1236 } 1237 1238 /* Check BIOS */ 1239 #ifdef CONFIG_X86_64 1240 /* On 64-bit, the APIC must be integrated, Check local APIC only */ 1241 if (!boot_cpu_has(X86_FEATURE_APIC)) { 1242 disable_apic = 1; 1243 pr_info("APIC disabled by BIOS\n"); 1244 return APIC_PIC; 1245 } 1246 #else 1247 /* On 32-bit, the APIC may be integrated APIC or 82489DX */ 1248 1249 /* Neither 82489DX nor integrated APIC ? */ 1250 if (!boot_cpu_has(X86_FEATURE_APIC) && !smp_found_config) { 1251 disable_apic = 1; 1252 return APIC_PIC; 1253 } 1254 1255 /* If the BIOS pretends there is an integrated APIC ? */ 1256 if (!boot_cpu_has(X86_FEATURE_APIC) && 1257 APIC_INTEGRATED(boot_cpu_apic_version)) { 1258 disable_apic = 1; 1259 pr_err(FW_BUG "Local APIC %d not detected, force emulation\n", 1260 boot_cpu_physical_apicid); 1261 return APIC_PIC; 1262 } 1263 #endif 1264 1265 /* Check MP table or ACPI MADT configuration */ 1266 if (!smp_found_config) { 1267 disable_ioapic_support(); 1268 if (!acpi_lapic) { 1269 pr_info("APIC: ACPI MADT or MP tables are not detected\n"); 1270 return APIC_VIRTUAL_WIRE_NO_CONFIG; 1271 } 1272 return APIC_VIRTUAL_WIRE; 1273 } 1274 1275 #ifdef CONFIG_SMP 1276 /* If SMP should be disabled, then really disable it! */ 1277 if (!setup_max_cpus) { 1278 pr_info("APIC: SMP mode deactivated\n"); 1279 return APIC_SYMMETRIC_IO_NO_ROUTING; 1280 } 1281 1282 if (read_apic_id() != boot_cpu_physical_apicid) { 1283 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1284 read_apic_id(), boot_cpu_physical_apicid); 1285 /* Or can we switch back to PIC here? */ 1286 } 1287 #endif 1288 1289 return APIC_SYMMETRIC_IO; 1290 } 1291 1292 /* 1293 * An initial setup of the virtual wire mode. 1294 */ 1295 void __init init_bsp_APIC(void) 1296 { 1297 unsigned int value; 1298 1299 /* 1300 * Don't do the setup now if we have a SMP BIOS as the 1301 * through-I/O-APIC virtual wire mode might be active. 1302 */ 1303 if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC)) 1304 return; 1305 1306 /* 1307 * Do not trust the local APIC being empty at bootup. 1308 */ 1309 clear_local_APIC(); 1310 1311 /* 1312 * Enable APIC. 1313 */ 1314 value = apic_read(APIC_SPIV); 1315 value &= ~APIC_VECTOR_MASK; 1316 value |= APIC_SPIV_APIC_ENABLED; 1317 1318 #ifdef CONFIG_X86_32 1319 /* This bit is reserved on P4/Xeon and should be cleared */ 1320 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1321 (boot_cpu_data.x86 == 15)) 1322 value &= ~APIC_SPIV_FOCUS_DISABLED; 1323 else 1324 #endif 1325 value |= APIC_SPIV_FOCUS_DISABLED; 1326 value |= SPURIOUS_APIC_VECTOR; 1327 apic_write(APIC_SPIV, value); 1328 1329 /* 1330 * Set up the virtual wire mode. 1331 */ 1332 apic_write(APIC_LVT0, APIC_DM_EXTINT); 1333 value = APIC_DM_NMI; 1334 if (!lapic_is_integrated()) /* 82489DX */ 1335 value |= APIC_LVT_LEVEL_TRIGGER; 1336 if (apic_extnmi == APIC_EXTNMI_NONE) 1337 value |= APIC_LVT_MASKED; 1338 apic_write(APIC_LVT1, value); 1339 } 1340 1341 /* Init the interrupt delivery mode for the BSP */ 1342 void __init apic_intr_mode_init(void) 1343 { 1344 bool upmode = IS_ENABLED(CONFIG_UP_LATE_INIT); 1345 1346 apic_intr_mode = apic_intr_mode_select(); 1347 1348 switch (apic_intr_mode) { 1349 case APIC_PIC: 1350 pr_info("APIC: Keep in PIC mode(8259)\n"); 1351 return; 1352 case APIC_VIRTUAL_WIRE: 1353 pr_info("APIC: Switch to virtual wire mode setup\n"); 1354 default_setup_apic_routing(); 1355 break; 1356 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1357 pr_info("APIC: Switch to virtual wire mode setup with no configuration\n"); 1358 upmode = true; 1359 default_setup_apic_routing(); 1360 break; 1361 case APIC_SYMMETRIC_IO: 1362 pr_info("APIC: Switch to symmetric I/O mode setup\n"); 1363 default_setup_apic_routing(); 1364 break; 1365 case APIC_SYMMETRIC_IO_NO_ROUTING: 1366 pr_info("APIC: Switch to symmetric I/O mode setup in no SMP routine\n"); 1367 break; 1368 } 1369 1370 apic_bsp_setup(upmode); 1371 } 1372 1373 static void lapic_setup_esr(void) 1374 { 1375 unsigned int oldvalue, value, maxlvt; 1376 1377 if (!lapic_is_integrated()) { 1378 pr_info("No ESR for 82489DX.\n"); 1379 return; 1380 } 1381 1382 if (apic->disable_esr) { 1383 /* 1384 * Something untraceable is creating bad interrupts on 1385 * secondary quads ... for the moment, just leave the 1386 * ESR disabled - we can't do anything useful with the 1387 * errors anyway - mbligh 1388 */ 1389 pr_info("Leaving ESR disabled.\n"); 1390 return; 1391 } 1392 1393 maxlvt = lapic_get_maxlvt(); 1394 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1395 apic_write(APIC_ESR, 0); 1396 oldvalue = apic_read(APIC_ESR); 1397 1398 /* enables sending errors */ 1399 value = ERROR_APIC_VECTOR; 1400 apic_write(APIC_LVTERR, value); 1401 1402 /* 1403 * spec says clear errors after enabling vector. 1404 */ 1405 if (maxlvt > 3) 1406 apic_write(APIC_ESR, 0); 1407 value = apic_read(APIC_ESR); 1408 if (value != oldvalue) 1409 apic_printk(APIC_VERBOSE, "ESR value before enabling " 1410 "vector: 0x%08x after: 0x%08x\n", 1411 oldvalue, value); 1412 } 1413 1414 static void apic_pending_intr_clear(void) 1415 { 1416 long long max_loops = cpu_khz ? cpu_khz : 1000000; 1417 unsigned long long tsc = 0, ntsc; 1418 unsigned int queued; 1419 unsigned long value; 1420 int i, j, acked = 0; 1421 1422 if (boot_cpu_has(X86_FEATURE_TSC)) 1423 tsc = rdtsc(); 1424 /* 1425 * After a crash, we no longer service the interrupts and a pending 1426 * interrupt from previous kernel might still have ISR bit set. 1427 * 1428 * Most probably by now CPU has serviced that pending interrupt and 1429 * it might not have done the ack_APIC_irq() because it thought, 1430 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it 1431 * does not clear the ISR bit and cpu thinks it has already serivced 1432 * the interrupt. Hence a vector might get locked. It was noticed 1433 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. 1434 */ 1435 do { 1436 queued = 0; 1437 for (i = APIC_ISR_NR - 1; i >= 0; i--) 1438 queued |= apic_read(APIC_IRR + i*0x10); 1439 1440 for (i = APIC_ISR_NR - 1; i >= 0; i--) { 1441 value = apic_read(APIC_ISR + i*0x10); 1442 for_each_set_bit(j, &value, 32) { 1443 ack_APIC_irq(); 1444 acked++; 1445 } 1446 } 1447 if (acked > 256) { 1448 pr_err("LAPIC pending interrupts after %d EOI\n", acked); 1449 break; 1450 } 1451 if (queued) { 1452 if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) { 1453 ntsc = rdtsc(); 1454 max_loops = (cpu_khz << 10) - (ntsc - tsc); 1455 } else { 1456 max_loops--; 1457 } 1458 } 1459 } while (queued && max_loops > 0); 1460 WARN_ON(max_loops <= 0); 1461 } 1462 1463 /** 1464 * setup_local_APIC - setup the local APIC 1465 * 1466 * Used to setup local APIC while initializing BSP or bringing up APs. 1467 * Always called with preemption disabled. 1468 */ 1469 static void setup_local_APIC(void) 1470 { 1471 int cpu = smp_processor_id(); 1472 unsigned int value; 1473 #ifdef CONFIG_X86_32 1474 int logical_apicid, ldr_apicid; 1475 #endif 1476 1477 1478 if (disable_apic) { 1479 disable_ioapic_support(); 1480 return; 1481 } 1482 1483 #ifdef CONFIG_X86_32 1484 /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1485 if (lapic_is_integrated() && apic->disable_esr) { 1486 apic_write(APIC_ESR, 0); 1487 apic_write(APIC_ESR, 0); 1488 apic_write(APIC_ESR, 0); 1489 apic_write(APIC_ESR, 0); 1490 } 1491 #endif 1492 perf_events_lapic_init(); 1493 1494 /* 1495 * Double-check whether this APIC is really registered. 1496 * This is meaningless in clustered apic mode, so we skip it. 1497 */ 1498 BUG_ON(!apic->apic_id_registered()); 1499 1500 /* 1501 * Intel recommends to set DFR, LDR and TPR before enabling 1502 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1503 * document number 292116). So here it goes... 1504 */ 1505 apic->init_apic_ldr(); 1506 1507 #ifdef CONFIG_X86_32 1508 /* 1509 * APIC LDR is initialized. If logical_apicid mapping was 1510 * initialized during get_smp_config(), make sure it matches the 1511 * actual value. 1512 */ 1513 logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu); 1514 ldr_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 1515 WARN_ON(logical_apicid != BAD_APICID && logical_apicid != ldr_apicid); 1516 /* always use the value from LDR */ 1517 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = ldr_apicid; 1518 #endif 1519 1520 /* 1521 * Set Task Priority to 'accept all'. We never change this 1522 * later on. 1523 */ 1524 value = apic_read(APIC_TASKPRI); 1525 value &= ~APIC_TPRI_MASK; 1526 apic_write(APIC_TASKPRI, value); 1527 1528 apic_pending_intr_clear(); 1529 1530 /* 1531 * Now that we are all set up, enable the APIC 1532 */ 1533 value = apic_read(APIC_SPIV); 1534 value &= ~APIC_VECTOR_MASK; 1535 /* 1536 * Enable APIC 1537 */ 1538 value |= APIC_SPIV_APIC_ENABLED; 1539 1540 #ifdef CONFIG_X86_32 1541 /* 1542 * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1543 * certain networking cards. If high frequency interrupts are 1544 * happening on a particular IOAPIC pin, plus the IOAPIC routing 1545 * entry is masked/unmasked at a high rate as well then sooner or 1546 * later IOAPIC line gets 'stuck', no more interrupts are received 1547 * from the device. If focus CPU is disabled then the hang goes 1548 * away, oh well :-( 1549 * 1550 * [ This bug can be reproduced easily with a level-triggered 1551 * PCI Ne2000 networking cards and PII/PIII processors, dual 1552 * BX chipset. ] 1553 */ 1554 /* 1555 * Actually disabling the focus CPU check just makes the hang less 1556 * frequent as it makes the interrupt distributon model be more 1557 * like LRU than MRU (the short-term load is more even across CPUs). 1558 */ 1559 1560 /* 1561 * - enable focus processor (bit==0) 1562 * - 64bit mode always use processor focus 1563 * so no need to set it 1564 */ 1565 value &= ~APIC_SPIV_FOCUS_DISABLED; 1566 #endif 1567 1568 /* 1569 * Set spurious IRQ vector 1570 */ 1571 value |= SPURIOUS_APIC_VECTOR; 1572 apic_write(APIC_SPIV, value); 1573 1574 /* 1575 * Set up LVT0, LVT1: 1576 * 1577 * set up through-local-APIC on the boot CPU's LINT0. This is not 1578 * strictly necessary in pure symmetric-IO mode, but sometimes 1579 * we delegate interrupts to the 8259A. 1580 */ 1581 /* 1582 * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1583 */ 1584 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 1585 if (!cpu && (pic_mode || !value || skip_ioapic_setup)) { 1586 value = APIC_DM_EXTINT; 1587 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); 1588 } else { 1589 value = APIC_DM_EXTINT | APIC_LVT_MASKED; 1590 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); 1591 } 1592 apic_write(APIC_LVT0, value); 1593 1594 /* 1595 * Only the BSP sees the LINT1 NMI signal by default. This can be 1596 * modified by apic_extnmi= boot option. 1597 */ 1598 if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) || 1599 apic_extnmi == APIC_EXTNMI_ALL) 1600 value = APIC_DM_NMI; 1601 else 1602 value = APIC_DM_NMI | APIC_LVT_MASKED; 1603 1604 /* Is 82489DX ? */ 1605 if (!lapic_is_integrated()) 1606 value |= APIC_LVT_LEVEL_TRIGGER; 1607 apic_write(APIC_LVT1, value); 1608 1609 #ifdef CONFIG_X86_MCE_INTEL 1610 /* Recheck CMCI information after local APIC is up on CPU #0 */ 1611 if (!cpu) 1612 cmci_recheck(); 1613 #endif 1614 } 1615 1616 static void end_local_APIC_setup(void) 1617 { 1618 lapic_setup_esr(); 1619 1620 #ifdef CONFIG_X86_32 1621 { 1622 unsigned int value; 1623 /* Disable the local apic timer */ 1624 value = apic_read(APIC_LVTT); 1625 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1626 apic_write(APIC_LVTT, value); 1627 } 1628 #endif 1629 1630 apic_pm_activate(); 1631 } 1632 1633 /* 1634 * APIC setup function for application processors. Called from smpboot.c 1635 */ 1636 void apic_ap_setup(void) 1637 { 1638 setup_local_APIC(); 1639 end_local_APIC_setup(); 1640 } 1641 1642 #ifdef CONFIG_X86_X2APIC 1643 int x2apic_mode; 1644 1645 enum { 1646 X2APIC_OFF, 1647 X2APIC_ON, 1648 X2APIC_DISABLED, 1649 }; 1650 static int x2apic_state; 1651 1652 static void __x2apic_disable(void) 1653 { 1654 u64 msr; 1655 1656 if (!boot_cpu_has(X86_FEATURE_APIC)) 1657 return; 1658 1659 rdmsrl(MSR_IA32_APICBASE, msr); 1660 if (!(msr & X2APIC_ENABLE)) 1661 return; 1662 /* Disable xapic and x2apic first and then reenable xapic mode */ 1663 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); 1664 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); 1665 printk_once(KERN_INFO "x2apic disabled\n"); 1666 } 1667 1668 static void __x2apic_enable(void) 1669 { 1670 u64 msr; 1671 1672 rdmsrl(MSR_IA32_APICBASE, msr); 1673 if (msr & X2APIC_ENABLE) 1674 return; 1675 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); 1676 printk_once(KERN_INFO "x2apic enabled\n"); 1677 } 1678 1679 static int __init setup_nox2apic(char *str) 1680 { 1681 if (x2apic_enabled()) { 1682 int apicid = native_apic_msr_read(APIC_ID); 1683 1684 if (apicid >= 255) { 1685 pr_warning("Apicid: %08x, cannot enforce nox2apic\n", 1686 apicid); 1687 return 0; 1688 } 1689 pr_warning("x2apic already enabled.\n"); 1690 __x2apic_disable(); 1691 } 1692 setup_clear_cpu_cap(X86_FEATURE_X2APIC); 1693 x2apic_state = X2APIC_DISABLED; 1694 x2apic_mode = 0; 1695 return 0; 1696 } 1697 early_param("nox2apic", setup_nox2apic); 1698 1699 /* Called from cpu_init() to enable x2apic on (secondary) cpus */ 1700 void x2apic_setup(void) 1701 { 1702 /* 1703 * If x2apic is not in ON state, disable it if already enabled 1704 * from BIOS. 1705 */ 1706 if (x2apic_state != X2APIC_ON) { 1707 __x2apic_disable(); 1708 return; 1709 } 1710 __x2apic_enable(); 1711 } 1712 1713 static __init void x2apic_disable(void) 1714 { 1715 u32 x2apic_id, state = x2apic_state; 1716 1717 x2apic_mode = 0; 1718 x2apic_state = X2APIC_DISABLED; 1719 1720 if (state != X2APIC_ON) 1721 return; 1722 1723 x2apic_id = read_apic_id(); 1724 if (x2apic_id >= 255) 1725 panic("Cannot disable x2apic, id: %08x\n", x2apic_id); 1726 1727 __x2apic_disable(); 1728 register_lapic_address(mp_lapic_addr); 1729 } 1730 1731 static __init void x2apic_enable(void) 1732 { 1733 if (x2apic_state != X2APIC_OFF) 1734 return; 1735 1736 x2apic_mode = 1; 1737 x2apic_state = X2APIC_ON; 1738 __x2apic_enable(); 1739 } 1740 1741 static __init void try_to_enable_x2apic(int remap_mode) 1742 { 1743 if (x2apic_state == X2APIC_DISABLED) 1744 return; 1745 1746 if (remap_mode != IRQ_REMAP_X2APIC_MODE) { 1747 /* IR is required if there is APIC ID > 255 even when running 1748 * under KVM 1749 */ 1750 if (max_physical_apicid > 255 || 1751 !x86_init.hyper.x2apic_available()) { 1752 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n"); 1753 x2apic_disable(); 1754 return; 1755 } 1756 1757 /* 1758 * without IR all CPUs can be addressed by IOAPIC/MSI 1759 * only in physical mode 1760 */ 1761 x2apic_phys = 1; 1762 } 1763 x2apic_enable(); 1764 } 1765 1766 void __init check_x2apic(void) 1767 { 1768 if (x2apic_enabled()) { 1769 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n"); 1770 x2apic_mode = 1; 1771 x2apic_state = X2APIC_ON; 1772 } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) { 1773 x2apic_state = X2APIC_DISABLED; 1774 } 1775 } 1776 #else /* CONFIG_X86_X2APIC */ 1777 static int __init validate_x2apic(void) 1778 { 1779 if (!apic_is_x2apic_enabled()) 1780 return 0; 1781 /* 1782 * Checkme: Can we simply turn off x2apic here instead of panic? 1783 */ 1784 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n"); 1785 } 1786 early_initcall(validate_x2apic); 1787 1788 static inline void try_to_enable_x2apic(int remap_mode) { } 1789 static inline void __x2apic_enable(void) { } 1790 #endif /* !CONFIG_X86_X2APIC */ 1791 1792 void __init enable_IR_x2apic(void) 1793 { 1794 unsigned long flags; 1795 int ret, ir_stat; 1796 1797 if (skip_ioapic_setup) { 1798 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n"); 1799 return; 1800 } 1801 1802 ir_stat = irq_remapping_prepare(); 1803 if (ir_stat < 0 && !x2apic_supported()) 1804 return; 1805 1806 ret = save_ioapic_entries(); 1807 if (ret) { 1808 pr_info("Saving IO-APIC state failed: %d\n", ret); 1809 return; 1810 } 1811 1812 local_irq_save(flags); 1813 legacy_pic->mask_all(); 1814 mask_ioapic_entries(); 1815 1816 /* If irq_remapping_prepare() succeeded, try to enable it */ 1817 if (ir_stat >= 0) 1818 ir_stat = irq_remapping_enable(); 1819 /* ir_stat contains the remap mode or an error code */ 1820 try_to_enable_x2apic(ir_stat); 1821 1822 if (ir_stat < 0) 1823 restore_ioapic_entries(); 1824 legacy_pic->restore_mask(); 1825 local_irq_restore(flags); 1826 } 1827 1828 #ifdef CONFIG_X86_64 1829 /* 1830 * Detect and enable local APICs on non-SMP boards. 1831 * Original code written by Keir Fraser. 1832 * On AMD64 we trust the BIOS - if it says no APIC it is likely 1833 * not correctly set up (usually the APIC timer won't work etc.) 1834 */ 1835 static int __init detect_init_APIC(void) 1836 { 1837 if (!boot_cpu_has(X86_FEATURE_APIC)) { 1838 pr_info("No local APIC present\n"); 1839 return -1; 1840 } 1841 1842 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1843 return 0; 1844 } 1845 #else 1846 1847 static int __init apic_verify(void) 1848 { 1849 u32 features, h, l; 1850 1851 /* 1852 * The APIC feature bit should now be enabled 1853 * in `cpuid' 1854 */ 1855 features = cpuid_edx(1); 1856 if (!(features & (1 << X86_FEATURE_APIC))) { 1857 pr_warning("Could not enable APIC!\n"); 1858 return -1; 1859 } 1860 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 1861 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1862 1863 /* The BIOS may have set up the APIC at some other address */ 1864 if (boot_cpu_data.x86 >= 6) { 1865 rdmsr(MSR_IA32_APICBASE, l, h); 1866 if (l & MSR_IA32_APICBASE_ENABLE) 1867 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 1868 } 1869 1870 pr_info("Found and enabled local APIC!\n"); 1871 return 0; 1872 } 1873 1874 int __init apic_force_enable(unsigned long addr) 1875 { 1876 u32 h, l; 1877 1878 if (disable_apic) 1879 return -1; 1880 1881 /* 1882 * Some BIOSes disable the local APIC in the APIC_BASE 1883 * MSR. This can only be done in software for Intel P6 or later 1884 * and AMD K7 (Model > 1) or later. 1885 */ 1886 if (boot_cpu_data.x86 >= 6) { 1887 rdmsr(MSR_IA32_APICBASE, l, h); 1888 if (!(l & MSR_IA32_APICBASE_ENABLE)) { 1889 pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 1890 l &= ~MSR_IA32_APICBASE_BASE; 1891 l |= MSR_IA32_APICBASE_ENABLE | addr; 1892 wrmsr(MSR_IA32_APICBASE, l, h); 1893 enabled_via_apicbase = 1; 1894 } 1895 } 1896 return apic_verify(); 1897 } 1898 1899 /* 1900 * Detect and initialize APIC 1901 */ 1902 static int __init detect_init_APIC(void) 1903 { 1904 /* Disabled by kernel option? */ 1905 if (disable_apic) 1906 return -1; 1907 1908 switch (boot_cpu_data.x86_vendor) { 1909 case X86_VENDOR_AMD: 1910 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 1911 (boot_cpu_data.x86 >= 15)) 1912 break; 1913 goto no_apic; 1914 case X86_VENDOR_INTEL: 1915 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 1916 (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC))) 1917 break; 1918 goto no_apic; 1919 default: 1920 goto no_apic; 1921 } 1922 1923 if (!boot_cpu_has(X86_FEATURE_APIC)) { 1924 /* 1925 * Over-ride BIOS and try to enable the local APIC only if 1926 * "lapic" specified. 1927 */ 1928 if (!force_enable_local_apic) { 1929 pr_info("Local APIC disabled by BIOS -- " 1930 "you can enable it with \"lapic\"\n"); 1931 return -1; 1932 } 1933 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) 1934 return -1; 1935 } else { 1936 if (apic_verify()) 1937 return -1; 1938 } 1939 1940 apic_pm_activate(); 1941 1942 return 0; 1943 1944 no_apic: 1945 pr_info("No local APIC present or hardware disabled\n"); 1946 return -1; 1947 } 1948 #endif 1949 1950 /** 1951 * init_apic_mappings - initialize APIC mappings 1952 */ 1953 void __init init_apic_mappings(void) 1954 { 1955 unsigned int new_apicid; 1956 1957 apic_check_deadline_errata(); 1958 1959 if (x2apic_mode) { 1960 boot_cpu_physical_apicid = read_apic_id(); 1961 return; 1962 } 1963 1964 /* If no local APIC can be found return early */ 1965 if (!smp_found_config && detect_init_APIC()) { 1966 /* lets NOP'ify apic operations */ 1967 pr_info("APIC: disable apic facility\n"); 1968 apic_disable(); 1969 } else { 1970 apic_phys = mp_lapic_addr; 1971 1972 /* 1973 * If the system has ACPI MADT tables or MP info, the LAPIC 1974 * address is already registered. 1975 */ 1976 if (!acpi_lapic && !smp_found_config) 1977 register_lapic_address(apic_phys); 1978 } 1979 1980 /* 1981 * Fetch the APIC ID of the BSP in case we have a 1982 * default configuration (or the MP table is broken). 1983 */ 1984 new_apicid = read_apic_id(); 1985 if (boot_cpu_physical_apicid != new_apicid) { 1986 boot_cpu_physical_apicid = new_apicid; 1987 /* 1988 * yeah -- we lie about apic_version 1989 * in case if apic was disabled via boot option 1990 * but it's not a problem for SMP compiled kernel 1991 * since apic_intr_mode_select is prepared for such 1992 * a case and disable smp mode 1993 */ 1994 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 1995 } 1996 } 1997 1998 void __init register_lapic_address(unsigned long address) 1999 { 2000 mp_lapic_addr = address; 2001 2002 if (!x2apic_mode) { 2003 set_fixmap_nocache(FIX_APIC_BASE, address); 2004 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 2005 APIC_BASE, address); 2006 } 2007 if (boot_cpu_physical_apicid == -1U) { 2008 boot_cpu_physical_apicid = read_apic_id(); 2009 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 2010 } 2011 } 2012 2013 /* 2014 * Local APIC interrupts 2015 */ 2016 2017 /* 2018 * This interrupt should _never_ happen with our APIC/SMP architecture 2019 */ 2020 __visible void __irq_entry smp_spurious_interrupt(struct pt_regs *regs) 2021 { 2022 u8 vector = ~regs->orig_ax; 2023 u32 v; 2024 2025 entering_irq(); 2026 trace_spurious_apic_entry(vector); 2027 2028 /* 2029 * Check if this really is a spurious interrupt and ACK it 2030 * if it is a vectored one. Just in case... 2031 * Spurious interrupts should not be ACKed. 2032 */ 2033 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1)); 2034 if (v & (1 << (vector & 0x1f))) 2035 ack_APIC_irq(); 2036 2037 inc_irq_stat(irq_spurious_count); 2038 2039 /* see sw-dev-man vol 3, chapter 7.4.13.5 */ 2040 pr_info("spurious APIC interrupt through vector %02x on CPU#%d, " 2041 "should never happen.\n", vector, smp_processor_id()); 2042 2043 trace_spurious_apic_exit(vector); 2044 exiting_irq(); 2045 } 2046 2047 /* 2048 * This interrupt should never happen with our APIC/SMP architecture 2049 */ 2050 __visible void __irq_entry smp_error_interrupt(struct pt_regs *regs) 2051 { 2052 static const char * const error_interrupt_reason[] = { 2053 "Send CS error", /* APIC Error Bit 0 */ 2054 "Receive CS error", /* APIC Error Bit 1 */ 2055 "Send accept error", /* APIC Error Bit 2 */ 2056 "Receive accept error", /* APIC Error Bit 3 */ 2057 "Redirectable IPI", /* APIC Error Bit 4 */ 2058 "Send illegal vector", /* APIC Error Bit 5 */ 2059 "Received illegal vector", /* APIC Error Bit 6 */ 2060 "Illegal register address", /* APIC Error Bit 7 */ 2061 }; 2062 u32 v, i = 0; 2063 2064 entering_irq(); 2065 trace_error_apic_entry(ERROR_APIC_VECTOR); 2066 2067 /* First tickle the hardware, only then report what went on. -- REW */ 2068 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */ 2069 apic_write(APIC_ESR, 0); 2070 v = apic_read(APIC_ESR); 2071 ack_APIC_irq(); 2072 atomic_inc(&irq_err_count); 2073 2074 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x", 2075 smp_processor_id(), v); 2076 2077 v &= 0xff; 2078 while (v) { 2079 if (v & 0x1) 2080 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); 2081 i++; 2082 v >>= 1; 2083 } 2084 2085 apic_printk(APIC_DEBUG, KERN_CONT "\n"); 2086 2087 trace_error_apic_exit(ERROR_APIC_VECTOR); 2088 exiting_irq(); 2089 } 2090 2091 /** 2092 * connect_bsp_APIC - attach the APIC to the interrupt system 2093 */ 2094 static void __init connect_bsp_APIC(void) 2095 { 2096 #ifdef CONFIG_X86_32 2097 if (pic_mode) { 2098 /* 2099 * Do not trust the local APIC being empty at bootup. 2100 */ 2101 clear_local_APIC(); 2102 /* 2103 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 2104 * local APIC to INT and NMI lines. 2105 */ 2106 apic_printk(APIC_VERBOSE, "leaving PIC mode, " 2107 "enabling APIC mode.\n"); 2108 imcr_pic_to_apic(); 2109 } 2110 #endif 2111 } 2112 2113 /** 2114 * disconnect_bsp_APIC - detach the APIC from the interrupt system 2115 * @virt_wire_setup: indicates, whether virtual wire mode is selected 2116 * 2117 * Virtual wire mode is necessary to deliver legacy interrupts even when the 2118 * APIC is disabled. 2119 */ 2120 void disconnect_bsp_APIC(int virt_wire_setup) 2121 { 2122 unsigned int value; 2123 2124 #ifdef CONFIG_X86_32 2125 if (pic_mode) { 2126 /* 2127 * Put the board back into PIC mode (has an effect only on 2128 * certain older boards). Note that APIC interrupts, including 2129 * IPIs, won't work beyond this point! The only exception are 2130 * INIT IPIs. 2131 */ 2132 apic_printk(APIC_VERBOSE, "disabling APIC mode, " 2133 "entering PIC mode.\n"); 2134 imcr_apic_to_pic(); 2135 return; 2136 } 2137 #endif 2138 2139 /* Go back to Virtual Wire compatibility mode */ 2140 2141 /* For the spurious interrupt use vector F, and enable it */ 2142 value = apic_read(APIC_SPIV); 2143 value &= ~APIC_VECTOR_MASK; 2144 value |= APIC_SPIV_APIC_ENABLED; 2145 value |= 0xf; 2146 apic_write(APIC_SPIV, value); 2147 2148 if (!virt_wire_setup) { 2149 /* 2150 * For LVT0 make it edge triggered, active high, 2151 * external and enabled 2152 */ 2153 value = apic_read(APIC_LVT0); 2154 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2155 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2156 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2157 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2158 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 2159 apic_write(APIC_LVT0, value); 2160 } else { 2161 /* Disable LVT0 */ 2162 apic_write(APIC_LVT0, APIC_LVT_MASKED); 2163 } 2164 2165 /* 2166 * For LVT1 make it edge triggered, active high, 2167 * nmi and enabled 2168 */ 2169 value = apic_read(APIC_LVT1); 2170 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2171 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2172 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2173 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2174 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 2175 apic_write(APIC_LVT1, value); 2176 } 2177 2178 /* 2179 * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated 2180 * contiguously, it equals to current allocated max logical CPU ID plus 1. 2181 * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range, 2182 * so the maximum of nr_logical_cpuids is nr_cpu_ids. 2183 * 2184 * NOTE: Reserve 0 for BSP. 2185 */ 2186 static int nr_logical_cpuids = 1; 2187 2188 /* 2189 * Used to store mapping between logical CPU IDs and APIC IDs. 2190 */ 2191 static int cpuid_to_apicid[] = { 2192 [0 ... NR_CPUS - 1] = -1, 2193 }; 2194 2195 /* 2196 * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids 2197 * and cpuid_to_apicid[] synchronized. 2198 */ 2199 static int allocate_logical_cpuid(int apicid) 2200 { 2201 int i; 2202 2203 /* 2204 * cpuid <-> apicid mapping is persistent, so when a cpu is up, 2205 * check if the kernel has allocated a cpuid for it. 2206 */ 2207 for (i = 0; i < nr_logical_cpuids; i++) { 2208 if (cpuid_to_apicid[i] == apicid) 2209 return i; 2210 } 2211 2212 /* Allocate a new cpuid. */ 2213 if (nr_logical_cpuids >= nr_cpu_ids) { 2214 WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. " 2215 "Processor %d/0x%x and the rest are ignored.\n", 2216 nr_cpu_ids, nr_logical_cpuids, apicid); 2217 return -EINVAL; 2218 } 2219 2220 cpuid_to_apicid[nr_logical_cpuids] = apicid; 2221 return nr_logical_cpuids++; 2222 } 2223 2224 int generic_processor_info(int apicid, int version) 2225 { 2226 int cpu, max = nr_cpu_ids; 2227 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, 2228 phys_cpu_present_map); 2229 2230 /* 2231 * boot_cpu_physical_apicid is designed to have the apicid 2232 * returned by read_apic_id(), i.e, the apicid of the 2233 * currently booting-up processor. However, on some platforms, 2234 * it is temporarily modified by the apicid reported as BSP 2235 * through MP table. Concretely: 2236 * 2237 * - arch/x86/kernel/mpparse.c: MP_processor_info() 2238 * - arch/x86/mm/amdtopology.c: amd_numa_init() 2239 * 2240 * This function is executed with the modified 2241 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel 2242 * parameter doesn't work to disable APs on kdump 2nd kernel. 2243 * 2244 * Since fixing handling of boot_cpu_physical_apicid requires 2245 * another discussion and tests on each platform, we leave it 2246 * for now and here we use read_apic_id() directly in this 2247 * function, generic_processor_info(). 2248 */ 2249 if (disabled_cpu_apicid != BAD_APICID && 2250 disabled_cpu_apicid != read_apic_id() && 2251 disabled_cpu_apicid == apicid) { 2252 int thiscpu = num_processors + disabled_cpus; 2253 2254 pr_warning("APIC: Disabling requested cpu." 2255 " Processor %d/0x%x ignored.\n", 2256 thiscpu, apicid); 2257 2258 disabled_cpus++; 2259 return -ENODEV; 2260 } 2261 2262 /* 2263 * If boot cpu has not been detected yet, then only allow upto 2264 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu 2265 */ 2266 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && 2267 apicid != boot_cpu_physical_apicid) { 2268 int thiscpu = max + disabled_cpus - 1; 2269 2270 pr_warning( 2271 "APIC: NR_CPUS/possible_cpus limit of %i almost" 2272 " reached. Keeping one slot for boot cpu." 2273 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 2274 2275 disabled_cpus++; 2276 return -ENODEV; 2277 } 2278 2279 if (num_processors >= nr_cpu_ids) { 2280 int thiscpu = max + disabled_cpus; 2281 2282 pr_warning("APIC: NR_CPUS/possible_cpus limit of %i " 2283 "reached. Processor %d/0x%x ignored.\n", 2284 max, thiscpu, apicid); 2285 2286 disabled_cpus++; 2287 return -EINVAL; 2288 } 2289 2290 if (apicid == boot_cpu_physical_apicid) { 2291 /* 2292 * x86_bios_cpu_apicid is required to have processors listed 2293 * in same order as logical cpu numbers. Hence the first 2294 * entry is BSP, and so on. 2295 * boot_cpu_init() already hold bit 0 in cpu_present_mask 2296 * for BSP. 2297 */ 2298 cpu = 0; 2299 2300 /* Logical cpuid 0 is reserved for BSP. */ 2301 cpuid_to_apicid[0] = apicid; 2302 } else { 2303 cpu = allocate_logical_cpuid(apicid); 2304 if (cpu < 0) { 2305 disabled_cpus++; 2306 return -EINVAL; 2307 } 2308 } 2309 2310 /* 2311 * Validate version 2312 */ 2313 if (version == 0x0) { 2314 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", 2315 cpu, apicid); 2316 version = 0x10; 2317 } 2318 2319 if (version != boot_cpu_apic_version) { 2320 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", 2321 boot_cpu_apic_version, cpu, version); 2322 } 2323 2324 if (apicid > max_physical_apicid) 2325 max_physical_apicid = apicid; 2326 2327 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 2328 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 2329 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 2330 #endif 2331 #ifdef CONFIG_X86_32 2332 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 2333 apic->x86_32_early_logical_apicid(cpu); 2334 #endif 2335 set_cpu_possible(cpu, true); 2336 physid_set(apicid, phys_cpu_present_map); 2337 set_cpu_present(cpu, true); 2338 num_processors++; 2339 2340 return cpu; 2341 } 2342 2343 int hard_smp_processor_id(void) 2344 { 2345 return read_apic_id(); 2346 } 2347 2348 /* 2349 * Override the generic EOI implementation with an optimized version. 2350 * Only called during early boot when only one CPU is active and with 2351 * interrupts disabled, so we know this does not race with actual APIC driver 2352 * use. 2353 */ 2354 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) 2355 { 2356 struct apic **drv; 2357 2358 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { 2359 /* Should happen once for each apic */ 2360 WARN_ON((*drv)->eoi_write == eoi_write); 2361 (*drv)->native_eoi_write = (*drv)->eoi_write; 2362 (*drv)->eoi_write = eoi_write; 2363 } 2364 } 2365 2366 static void __init apic_bsp_up_setup(void) 2367 { 2368 #ifdef CONFIG_X86_64 2369 apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid)); 2370 #else 2371 /* 2372 * Hack: In case of kdump, after a crash, kernel might be booting 2373 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 2374 * might be zero if read from MP tables. Get it from LAPIC. 2375 */ 2376 # ifdef CONFIG_CRASH_DUMP 2377 boot_cpu_physical_apicid = read_apic_id(); 2378 # endif 2379 #endif 2380 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 2381 } 2382 2383 /** 2384 * apic_bsp_setup - Setup function for local apic and io-apic 2385 * @upmode: Force UP mode (for APIC_init_uniprocessor) 2386 * 2387 * Returns: 2388 * apic_id of BSP APIC 2389 */ 2390 void __init apic_bsp_setup(bool upmode) 2391 { 2392 connect_bsp_APIC(); 2393 if (upmode) 2394 apic_bsp_up_setup(); 2395 setup_local_APIC(); 2396 2397 enable_IO_APIC(); 2398 end_local_APIC_setup(); 2399 irq_remap_enable_fault_handling(); 2400 setup_IO_APIC(); 2401 } 2402 2403 #ifdef CONFIG_UP_LATE_INIT 2404 void __init up_late_init(void) 2405 { 2406 if (apic_intr_mode == APIC_PIC) 2407 return; 2408 2409 /* Setup local timer */ 2410 x86_init.timers.setup_percpu_clockev(); 2411 } 2412 #endif 2413 2414 /* 2415 * Power management 2416 */ 2417 #ifdef CONFIG_PM 2418 2419 static struct { 2420 /* 2421 * 'active' is true if the local APIC was enabled by us and 2422 * not the BIOS; this signifies that we are also responsible 2423 * for disabling it before entering apm/acpi suspend 2424 */ 2425 int active; 2426 /* r/w apic fields */ 2427 unsigned int apic_id; 2428 unsigned int apic_taskpri; 2429 unsigned int apic_ldr; 2430 unsigned int apic_dfr; 2431 unsigned int apic_spiv; 2432 unsigned int apic_lvtt; 2433 unsigned int apic_lvtpc; 2434 unsigned int apic_lvt0; 2435 unsigned int apic_lvt1; 2436 unsigned int apic_lvterr; 2437 unsigned int apic_tmict; 2438 unsigned int apic_tdcr; 2439 unsigned int apic_thmr; 2440 unsigned int apic_cmci; 2441 } apic_pm_state; 2442 2443 static int lapic_suspend(void) 2444 { 2445 unsigned long flags; 2446 int maxlvt; 2447 2448 if (!apic_pm_state.active) 2449 return 0; 2450 2451 maxlvt = lapic_get_maxlvt(); 2452 2453 apic_pm_state.apic_id = apic_read(APIC_ID); 2454 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 2455 apic_pm_state.apic_ldr = apic_read(APIC_LDR); 2456 apic_pm_state.apic_dfr = apic_read(APIC_DFR); 2457 apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2458 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2459 if (maxlvt >= 4) 2460 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2461 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2462 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2463 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2464 apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2465 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 2466 #ifdef CONFIG_X86_THERMAL_VECTOR 2467 if (maxlvt >= 5) 2468 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2469 #endif 2470 #ifdef CONFIG_X86_MCE_INTEL 2471 if (maxlvt >= 6) 2472 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI); 2473 #endif 2474 2475 local_irq_save(flags); 2476 disable_local_APIC(); 2477 2478 irq_remapping_disable(); 2479 2480 local_irq_restore(flags); 2481 return 0; 2482 } 2483 2484 static void lapic_resume(void) 2485 { 2486 unsigned int l, h; 2487 unsigned long flags; 2488 int maxlvt; 2489 2490 if (!apic_pm_state.active) 2491 return; 2492 2493 local_irq_save(flags); 2494 2495 /* 2496 * IO-APIC and PIC have their own resume routines. 2497 * We just mask them here to make sure the interrupt 2498 * subsystem is completely quiet while we enable x2apic 2499 * and interrupt-remapping. 2500 */ 2501 mask_ioapic_entries(); 2502 legacy_pic->mask_all(); 2503 2504 if (x2apic_mode) { 2505 __x2apic_enable(); 2506 } else { 2507 /* 2508 * Make sure the APICBASE points to the right address 2509 * 2510 * FIXME! This will be wrong if we ever support suspend on 2511 * SMP! We'll need to do this as part of the CPU restore! 2512 */ 2513 if (boot_cpu_data.x86 >= 6) { 2514 rdmsr(MSR_IA32_APICBASE, l, h); 2515 l &= ~MSR_IA32_APICBASE_BASE; 2516 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2517 wrmsr(MSR_IA32_APICBASE, l, h); 2518 } 2519 } 2520 2521 maxlvt = lapic_get_maxlvt(); 2522 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2523 apic_write(APIC_ID, apic_pm_state.apic_id); 2524 apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2525 apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2526 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2527 apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2528 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2529 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 2530 #ifdef CONFIG_X86_THERMAL_VECTOR 2531 if (maxlvt >= 5) 2532 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2533 #endif 2534 #ifdef CONFIG_X86_MCE_INTEL 2535 if (maxlvt >= 6) 2536 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci); 2537 #endif 2538 if (maxlvt >= 4) 2539 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2540 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2541 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2542 apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2543 apic_write(APIC_ESR, 0); 2544 apic_read(APIC_ESR); 2545 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2546 apic_write(APIC_ESR, 0); 2547 apic_read(APIC_ESR); 2548 2549 irq_remapping_reenable(x2apic_mode); 2550 2551 local_irq_restore(flags); 2552 } 2553 2554 /* 2555 * This device has no shutdown method - fully functioning local APICs 2556 * are needed on every CPU up until machine_halt/restart/poweroff. 2557 */ 2558 2559 static struct syscore_ops lapic_syscore_ops = { 2560 .resume = lapic_resume, 2561 .suspend = lapic_suspend, 2562 }; 2563 2564 static void apic_pm_activate(void) 2565 { 2566 apic_pm_state.active = 1; 2567 } 2568 2569 static int __init init_lapic_sysfs(void) 2570 { 2571 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 2572 if (boot_cpu_has(X86_FEATURE_APIC)) 2573 register_syscore_ops(&lapic_syscore_ops); 2574 2575 return 0; 2576 } 2577 2578 /* local apic needs to resume before other devices access its registers. */ 2579 core_initcall(init_lapic_sysfs); 2580 2581 #else /* CONFIG_PM */ 2582 2583 static void apic_pm_activate(void) { } 2584 2585 #endif /* CONFIG_PM */ 2586 2587 #ifdef CONFIG_X86_64 2588 2589 static int multi_checked; 2590 static int multi; 2591 2592 static int set_multi(const struct dmi_system_id *d) 2593 { 2594 if (multi) 2595 return 0; 2596 pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2597 multi = 1; 2598 return 0; 2599 } 2600 2601 static const struct dmi_system_id multi_dmi_table[] = { 2602 { 2603 .callback = set_multi, 2604 .ident = "IBM System Summit2", 2605 .matches = { 2606 DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2607 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2608 }, 2609 }, 2610 {} 2611 }; 2612 2613 static void dmi_check_multi(void) 2614 { 2615 if (multi_checked) 2616 return; 2617 2618 dmi_check_system(multi_dmi_table); 2619 multi_checked = 1; 2620 } 2621 2622 /* 2623 * apic_is_clustered_box() -- Check if we can expect good TSC 2624 * 2625 * Thus far, the major user of this is IBM's Summit2 series: 2626 * Clustered boxes may have unsynced TSC problems if they are 2627 * multi-chassis. 2628 * Use DMI to check them 2629 */ 2630 int apic_is_clustered_box(void) 2631 { 2632 dmi_check_multi(); 2633 return multi; 2634 } 2635 #endif 2636 2637 /* 2638 * APIC command line parameters 2639 */ 2640 static int __init setup_disableapic(char *arg) 2641 { 2642 disable_apic = 1; 2643 setup_clear_cpu_cap(X86_FEATURE_APIC); 2644 return 0; 2645 } 2646 early_param("disableapic", setup_disableapic); 2647 2648 /* same as disableapic, for compatibility */ 2649 static int __init setup_nolapic(char *arg) 2650 { 2651 return setup_disableapic(arg); 2652 } 2653 early_param("nolapic", setup_nolapic); 2654 2655 static int __init parse_lapic_timer_c2_ok(char *arg) 2656 { 2657 local_apic_timer_c2_ok = 1; 2658 return 0; 2659 } 2660 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2661 2662 static int __init parse_disable_apic_timer(char *arg) 2663 { 2664 disable_apic_timer = 1; 2665 return 0; 2666 } 2667 early_param("noapictimer", parse_disable_apic_timer); 2668 2669 static int __init parse_nolapic_timer(char *arg) 2670 { 2671 disable_apic_timer = 1; 2672 return 0; 2673 } 2674 early_param("nolapic_timer", parse_nolapic_timer); 2675 2676 static int __init apic_set_verbosity(char *arg) 2677 { 2678 if (!arg) { 2679 #ifdef CONFIG_X86_64 2680 skip_ioapic_setup = 0; 2681 return 0; 2682 #endif 2683 return -EINVAL; 2684 } 2685 2686 if (strcmp("debug", arg) == 0) 2687 apic_verbosity = APIC_DEBUG; 2688 else if (strcmp("verbose", arg) == 0) 2689 apic_verbosity = APIC_VERBOSE; 2690 #ifdef CONFIG_X86_64 2691 else { 2692 pr_warning("APIC Verbosity level %s not recognised" 2693 " use apic=verbose or apic=debug\n", arg); 2694 return -EINVAL; 2695 } 2696 #endif 2697 2698 return 0; 2699 } 2700 early_param("apic", apic_set_verbosity); 2701 2702 static int __init lapic_insert_resource(void) 2703 { 2704 if (!apic_phys) 2705 return -1; 2706 2707 /* Put local APIC into the resource map. */ 2708 lapic_resource.start = apic_phys; 2709 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2710 insert_resource(&iomem_resource, &lapic_resource); 2711 2712 return 0; 2713 } 2714 2715 /* 2716 * need call insert after e820__reserve_resources() 2717 * that is using request_resource 2718 */ 2719 late_initcall(lapic_insert_resource); 2720 2721 static int __init apic_set_disabled_cpu_apicid(char *arg) 2722 { 2723 if (!arg || !get_option(&arg, &disabled_cpu_apicid)) 2724 return -EINVAL; 2725 2726 return 0; 2727 } 2728 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); 2729 2730 static int __init apic_set_extnmi(char *arg) 2731 { 2732 if (!arg) 2733 return -EINVAL; 2734 2735 if (!strncmp("all", arg, 3)) 2736 apic_extnmi = APIC_EXTNMI_ALL; 2737 else if (!strncmp("none", arg, 4)) 2738 apic_extnmi = APIC_EXTNMI_NONE; 2739 else if (!strncmp("bsp", arg, 3)) 2740 apic_extnmi = APIC_EXTNMI_BSP; 2741 else { 2742 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg); 2743 return -EINVAL; 2744 } 2745 2746 return 0; 2747 } 2748 early_param("apic_extnmi", apic_set_extnmi); 2749