1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Local APIC handling, local APIC timers 4 * 5 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * 7 * Fixes 8 * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 9 * thanks to Eric Gilmore 10 * and Rolf G. Tews 11 * for testing these extensively. 12 * Maciej W. Rozycki : Various updates and fixes. 13 * Mikael Pettersson : Power Management for UP-APIC. 14 * Pavel Machek and 15 * Mikael Pettersson : PM converted to driver model. 16 */ 17 18 #include <linux/perf_event.h> 19 #include <linux/kernel_stat.h> 20 #include <linux/mc146818rtc.h> 21 #include <linux/acpi_pmtmr.h> 22 #include <linux/clockchips.h> 23 #include <linux/interrupt.h> 24 #include <linux/memblock.h> 25 #include <linux/ftrace.h> 26 #include <linux/ioport.h> 27 #include <linux/export.h> 28 #include <linux/syscore_ops.h> 29 #include <linux/delay.h> 30 #include <linux/timex.h> 31 #include <linux/i8253.h> 32 #include <linux/dmar.h> 33 #include <linux/init.h> 34 #include <linux/cpu.h> 35 #include <linux/dmi.h> 36 #include <linux/smp.h> 37 #include <linux/mm.h> 38 39 #include <asm/trace/irq_vectors.h> 40 #include <asm/irq_remapping.h> 41 #include <asm/perf_event.h> 42 #include <asm/x86_init.h> 43 #include <asm/pgalloc.h> 44 #include <linux/atomic.h> 45 #include <asm/mpspec.h> 46 #include <asm/i8259.h> 47 #include <asm/proto.h> 48 #include <asm/traps.h> 49 #include <asm/apic.h> 50 #include <asm/io_apic.h> 51 #include <asm/desc.h> 52 #include <asm/hpet.h> 53 #include <asm/mtrr.h> 54 #include <asm/time.h> 55 #include <asm/smp.h> 56 #include <asm/mce.h> 57 #include <asm/tsc.h> 58 #include <asm/hypervisor.h> 59 #include <asm/cpu_device_id.h> 60 #include <asm/intel-family.h> 61 #include <asm/irq_regs.h> 62 63 unsigned int num_processors; 64 65 unsigned disabled_cpus; 66 67 /* Processor that is doing the boot up */ 68 unsigned int boot_cpu_physical_apicid = -1U; 69 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); 70 71 u8 boot_cpu_apic_version; 72 73 /* 74 * The highest APIC ID seen during enumeration. 75 */ 76 static unsigned int max_physical_apicid; 77 78 /* 79 * Bitmask of physically existing CPUs: 80 */ 81 physid_mask_t phys_cpu_present_map; 82 83 /* 84 * Processor to be disabled specified by kernel parameter 85 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to 86 * avoid undefined behaviour caused by sending INIT from AP to BSP. 87 */ 88 static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID; 89 90 /* 91 * This variable controls which CPUs receive external NMIs. By default, 92 * external NMIs are delivered only to the BSP. 93 */ 94 static int apic_extnmi = APIC_EXTNMI_BSP; 95 96 /* 97 * Map cpu index to physical APIC ID 98 */ 99 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); 100 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID); 101 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX); 102 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 103 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 104 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid); 105 106 #ifdef CONFIG_X86_32 107 108 /* 109 * On x86_32, the mapping between cpu and logical apicid may vary 110 * depending on apic in use. The following early percpu variable is 111 * used for the mapping. This is where the behaviors of x86_64 and 32 112 * actually diverge. Let's keep it ugly for now. 113 */ 114 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID); 115 116 /* Local APIC was disabled by the BIOS and enabled by the kernel */ 117 static int enabled_via_apicbase; 118 119 /* 120 * Handle interrupt mode configuration register (IMCR). 121 * This register controls whether the interrupt signals 122 * that reach the BSP come from the master PIC or from the 123 * local APIC. Before entering Symmetric I/O Mode, either 124 * the BIOS or the operating system must switch out of 125 * PIC Mode by changing the IMCR. 126 */ 127 static inline void imcr_pic_to_apic(void) 128 { 129 /* select IMCR register */ 130 outb(0x70, 0x22); 131 /* NMI and 8259 INTR go through APIC */ 132 outb(0x01, 0x23); 133 } 134 135 static inline void imcr_apic_to_pic(void) 136 { 137 /* select IMCR register */ 138 outb(0x70, 0x22); 139 /* NMI and 8259 INTR go directly to BSP */ 140 outb(0x00, 0x23); 141 } 142 #endif 143 144 /* 145 * Knob to control our willingness to enable the local APIC. 146 * 147 * +1=force-enable 148 */ 149 static int force_enable_local_apic __initdata; 150 151 /* 152 * APIC command line parameters 153 */ 154 static int __init parse_lapic(char *arg) 155 { 156 if (IS_ENABLED(CONFIG_X86_32) && !arg) 157 force_enable_local_apic = 1; 158 else if (arg && !strncmp(arg, "notscdeadline", 13)) 159 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 160 return 0; 161 } 162 early_param("lapic", parse_lapic); 163 164 #ifdef CONFIG_X86_64 165 static int apic_calibrate_pmtmr __initdata; 166 static __init int setup_apicpmtimer(char *s) 167 { 168 apic_calibrate_pmtmr = 1; 169 notsc_setup(NULL); 170 return 0; 171 } 172 __setup("apicpmtimer", setup_apicpmtimer); 173 #endif 174 175 unsigned long mp_lapic_addr; 176 int disable_apic; 177 /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 178 static int disable_apic_timer __initdata; 179 /* Local APIC timer works in C2 */ 180 int local_apic_timer_c2_ok; 181 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 182 183 /* 184 * Debug level, exported for io_apic.c 185 */ 186 int apic_verbosity; 187 188 int pic_mode; 189 190 /* Have we found an MP table */ 191 int smp_found_config; 192 193 static struct resource lapic_resource = { 194 .name = "Local APIC", 195 .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 196 }; 197 198 unsigned int lapic_timer_period = 0; 199 200 static void apic_pm_activate(void); 201 202 static unsigned long apic_phys; 203 204 /* 205 * Get the LAPIC version 206 */ 207 static inline int lapic_get_version(void) 208 { 209 return GET_APIC_VERSION(apic_read(APIC_LVR)); 210 } 211 212 /* 213 * Check, if the APIC is integrated or a separate chip 214 */ 215 static inline int lapic_is_integrated(void) 216 { 217 return APIC_INTEGRATED(lapic_get_version()); 218 } 219 220 /* 221 * Check, whether this is a modern or a first generation APIC 222 */ 223 static int modern_apic(void) 224 { 225 /* AMD systems use old APIC versions, so check the CPU */ 226 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 227 boot_cpu_data.x86 >= 0xf) 228 return 1; 229 230 /* Hygon systems use modern APIC */ 231 if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 232 return 1; 233 234 return lapic_get_version() >= 0x14; 235 } 236 237 /* 238 * right after this call apic become NOOP driven 239 * so apic->write/read doesn't do anything 240 */ 241 static void __init apic_disable(void) 242 { 243 pr_info("APIC: switched to apic NOOP\n"); 244 apic = &apic_noop; 245 } 246 247 void native_apic_wait_icr_idle(void) 248 { 249 while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 250 cpu_relax(); 251 } 252 253 u32 native_safe_apic_wait_icr_idle(void) 254 { 255 u32 send_status; 256 int timeout; 257 258 timeout = 0; 259 do { 260 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 261 if (!send_status) 262 break; 263 inc_irq_stat(icr_read_retry_count); 264 udelay(100); 265 } while (timeout++ < 1000); 266 267 return send_status; 268 } 269 270 void native_apic_icr_write(u32 low, u32 id) 271 { 272 unsigned long flags; 273 274 local_irq_save(flags); 275 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 276 apic_write(APIC_ICR, low); 277 local_irq_restore(flags); 278 } 279 280 u64 native_apic_icr_read(void) 281 { 282 u32 icr1, icr2; 283 284 icr2 = apic_read(APIC_ICR2); 285 icr1 = apic_read(APIC_ICR); 286 287 return icr1 | ((u64)icr2 << 32); 288 } 289 290 #ifdef CONFIG_X86_32 291 /** 292 * get_physical_broadcast - Get number of physical broadcast IDs 293 */ 294 int get_physical_broadcast(void) 295 { 296 return modern_apic() ? 0xff : 0xf; 297 } 298 #endif 299 300 /** 301 * lapic_get_maxlvt - get the maximum number of local vector table entries 302 */ 303 int lapic_get_maxlvt(void) 304 { 305 /* 306 * - we always have APIC integrated on 64bit mode 307 * - 82489DXs do not report # of LVT entries 308 */ 309 return lapic_is_integrated() ? GET_APIC_MAXLVT(apic_read(APIC_LVR)) : 2; 310 } 311 312 /* 313 * Local APIC timer 314 */ 315 316 /* Clock divisor */ 317 #define APIC_DIVISOR 16 318 #define TSC_DIVISOR 8 319 320 /* 321 * This function sets up the local APIC timer, with a timeout of 322 * 'clocks' APIC bus clock. During calibration we actually call 323 * this function twice on the boot CPU, once with a bogus timeout 324 * value, second time for real. The other (noncalibrating) CPUs 325 * call this function only once, with the real, calibrated value. 326 * 327 * We do reads before writes even if unnecessary, to get around the 328 * P5 APIC double write bug. 329 */ 330 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 331 { 332 unsigned int lvtt_value, tmp_value; 333 334 lvtt_value = LOCAL_TIMER_VECTOR; 335 if (!oneshot) 336 lvtt_value |= APIC_LVT_TIMER_PERIODIC; 337 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 338 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE; 339 340 if (!lapic_is_integrated()) 341 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 342 343 if (!irqen) 344 lvtt_value |= APIC_LVT_MASKED; 345 346 apic_write(APIC_LVTT, lvtt_value); 347 348 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { 349 /* 350 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, 351 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized. 352 * According to Intel, MFENCE can do the serialization here. 353 */ 354 asm volatile("mfence" : : : "memory"); 355 356 printk_once(KERN_DEBUG "TSC deadline timer enabled\n"); 357 return; 358 } 359 360 /* 361 * Divide PICLK by 16 362 */ 363 tmp_value = apic_read(APIC_TDCR); 364 apic_write(APIC_TDCR, 365 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 366 APIC_TDR_DIV_16); 367 368 if (!oneshot) 369 apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 370 } 371 372 /* 373 * Setup extended LVT, AMD specific 374 * 375 * Software should use the LVT offsets the BIOS provides. The offsets 376 * are determined by the subsystems using it like those for MCE 377 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts 378 * are supported. Beginning with family 10h at least 4 offsets are 379 * available. 380 * 381 * Since the offsets must be consistent for all cores, we keep track 382 * of the LVT offsets in software and reserve the offset for the same 383 * vector also to be used on other cores. An offset is freed by 384 * setting the entry to APIC_EILVT_MASKED. 385 * 386 * If the BIOS is right, there should be no conflicts. Otherwise a 387 * "[Firmware Bug]: ..." error message is generated. However, if 388 * software does not properly determines the offsets, it is not 389 * necessarily a BIOS bug. 390 */ 391 392 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; 393 394 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) 395 { 396 return (old & APIC_EILVT_MASKED) 397 || (new == APIC_EILVT_MASKED) 398 || ((new & ~APIC_EILVT_MASKED) == old); 399 } 400 401 static unsigned int reserve_eilvt_offset(int offset, unsigned int new) 402 { 403 unsigned int rsvd, vector; 404 405 if (offset >= APIC_EILVT_NR_MAX) 406 return ~0; 407 408 rsvd = atomic_read(&eilvt_offsets[offset]); 409 do { 410 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ 411 if (vector && !eilvt_entry_is_changeable(vector, new)) 412 /* may not change if vectors are different */ 413 return rsvd; 414 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); 415 } while (rsvd != new); 416 417 rsvd &= ~APIC_EILVT_MASKED; 418 if (rsvd && rsvd != vector) 419 pr_info("LVT offset %d assigned for vector 0x%02x\n", 420 offset, rsvd); 421 422 return new; 423 } 424 425 /* 426 * If mask=1, the LVT entry does not generate interrupts while mask=0 427 * enables the vector. See also the BKDGs. Must be called with 428 * preemption disabled. 429 */ 430 431 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) 432 { 433 unsigned long reg = APIC_EILVTn(offset); 434 unsigned int new, old, reserved; 435 436 new = (mask << 16) | (msg_type << 8) | vector; 437 old = apic_read(reg); 438 reserved = reserve_eilvt_offset(offset, new); 439 440 if (reserved != new) { 441 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 442 "vector 0x%x, but the register is already in use for " 443 "vector 0x%x on another cpu\n", 444 smp_processor_id(), reg, offset, new, reserved); 445 return -EINVAL; 446 } 447 448 if (!eilvt_entry_is_changeable(old, new)) { 449 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 450 "vector 0x%x, but the register is already in use for " 451 "vector 0x%x on this cpu\n", 452 smp_processor_id(), reg, offset, new, old); 453 return -EBUSY; 454 } 455 456 apic_write(reg, new); 457 458 return 0; 459 } 460 EXPORT_SYMBOL_GPL(setup_APIC_eilvt); 461 462 /* 463 * Program the next event, relative to now 464 */ 465 static int lapic_next_event(unsigned long delta, 466 struct clock_event_device *evt) 467 { 468 apic_write(APIC_TMICT, delta); 469 return 0; 470 } 471 472 static int lapic_next_deadline(unsigned long delta, 473 struct clock_event_device *evt) 474 { 475 u64 tsc; 476 477 tsc = rdtsc(); 478 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); 479 return 0; 480 } 481 482 static int lapic_timer_shutdown(struct clock_event_device *evt) 483 { 484 unsigned int v; 485 486 /* Lapic used as dummy for broadcast ? */ 487 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 488 return 0; 489 490 v = apic_read(APIC_LVTT); 491 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 492 apic_write(APIC_LVTT, v); 493 apic_write(APIC_TMICT, 0); 494 return 0; 495 } 496 497 static inline int 498 lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot) 499 { 500 /* Lapic used as dummy for broadcast ? */ 501 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 502 return 0; 503 504 __setup_APIC_LVTT(lapic_timer_period, oneshot, 1); 505 return 0; 506 } 507 508 static int lapic_timer_set_periodic(struct clock_event_device *evt) 509 { 510 return lapic_timer_set_periodic_oneshot(evt, false); 511 } 512 513 static int lapic_timer_set_oneshot(struct clock_event_device *evt) 514 { 515 return lapic_timer_set_periodic_oneshot(evt, true); 516 } 517 518 /* 519 * Local APIC timer broadcast function 520 */ 521 static void lapic_timer_broadcast(const struct cpumask *mask) 522 { 523 #ifdef CONFIG_SMP 524 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 525 #endif 526 } 527 528 529 /* 530 * The local apic timer can be used for any function which is CPU local. 531 */ 532 static struct clock_event_device lapic_clockevent = { 533 .name = "lapic", 534 .features = CLOCK_EVT_FEAT_PERIODIC | 535 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP 536 | CLOCK_EVT_FEAT_DUMMY, 537 .shift = 32, 538 .set_state_shutdown = lapic_timer_shutdown, 539 .set_state_periodic = lapic_timer_set_periodic, 540 .set_state_oneshot = lapic_timer_set_oneshot, 541 .set_state_oneshot_stopped = lapic_timer_shutdown, 542 .set_next_event = lapic_next_event, 543 .broadcast = lapic_timer_broadcast, 544 .rating = 100, 545 .irq = -1, 546 }; 547 static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 548 549 #define DEADLINE_MODEL_MATCH_FUNC(model, func) \ 550 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&func } 551 552 #define DEADLINE_MODEL_MATCH_REV(model, rev) \ 553 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)rev } 554 555 static u32 hsx_deadline_rev(void) 556 { 557 switch (boot_cpu_data.x86_stepping) { 558 case 0x02: return 0x3a; /* EP */ 559 case 0x04: return 0x0f; /* EX */ 560 } 561 562 return ~0U; 563 } 564 565 static u32 bdx_deadline_rev(void) 566 { 567 switch (boot_cpu_data.x86_stepping) { 568 case 0x02: return 0x00000011; 569 case 0x03: return 0x0700000e; 570 case 0x04: return 0x0f00000c; 571 case 0x05: return 0x0e000003; 572 } 573 574 return ~0U; 575 } 576 577 static u32 skx_deadline_rev(void) 578 { 579 switch (boot_cpu_data.x86_stepping) { 580 case 0x03: return 0x01000136; 581 case 0x04: return 0x02000014; 582 } 583 584 if (boot_cpu_data.x86_stepping > 4) 585 return 0; 586 587 return ~0U; 588 } 589 590 static const struct x86_cpu_id deadline_match[] = { 591 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_HASWELL_X, hsx_deadline_rev), 592 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_X, 0x0b000020), 593 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_BROADWELL_XEON_D, bdx_deadline_rev), 594 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_SKYLAKE_X, skx_deadline_rev), 595 596 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_CORE, 0x22), 597 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_ULT, 0x20), 598 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_GT3E, 0x17), 599 600 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_CORE, 0x25), 601 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_GT3E, 0x17), 602 603 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_MOBILE, 0xb2), 604 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_DESKTOP, 0xb2), 605 606 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_MOBILE, 0x52), 607 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_DESKTOP, 0x52), 608 609 {}, 610 }; 611 612 static void apic_check_deadline_errata(void) 613 { 614 const struct x86_cpu_id *m; 615 u32 rev; 616 617 if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER) || 618 boot_cpu_has(X86_FEATURE_HYPERVISOR)) 619 return; 620 621 m = x86_match_cpu(deadline_match); 622 if (!m) 623 return; 624 625 /* 626 * Function pointers will have the MSB set due to address layout, 627 * immediate revisions will not. 628 */ 629 if ((long)m->driver_data < 0) 630 rev = ((u32 (*)(void))(m->driver_data))(); 631 else 632 rev = (u32)m->driver_data; 633 634 if (boot_cpu_data.microcode >= rev) 635 return; 636 637 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 638 pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; " 639 "please update microcode to version: 0x%x (or later)\n", rev); 640 } 641 642 /* 643 * Setup the local APIC timer for this CPU. Copy the initialized values 644 * of the boot CPU and register the clock event in the framework. 645 */ 646 static void setup_APIC_timer(void) 647 { 648 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 649 650 if (this_cpu_has(X86_FEATURE_ARAT)) { 651 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 652 /* Make LAPIC timer preferrable over percpu HPET */ 653 lapic_clockevent.rating = 150; 654 } 655 656 memcpy(levt, &lapic_clockevent, sizeof(*levt)); 657 levt->cpumask = cpumask_of(smp_processor_id()); 658 659 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 660 levt->name = "lapic-deadline"; 661 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | 662 CLOCK_EVT_FEAT_DUMMY); 663 levt->set_next_event = lapic_next_deadline; 664 clockevents_config_and_register(levt, 665 tsc_khz * (1000 / TSC_DIVISOR), 666 0xF, ~0UL); 667 } else 668 clockevents_register_device(levt); 669 } 670 671 /* 672 * Install the updated TSC frequency from recalibration at the TSC 673 * deadline clockevent devices. 674 */ 675 static void __lapic_update_tsc_freq(void *info) 676 { 677 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 678 679 if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 680 return; 681 682 clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR)); 683 } 684 685 void lapic_update_tsc_freq(void) 686 { 687 /* 688 * The clockevent device's ->mult and ->shift can both be 689 * changed. In order to avoid races, schedule the frequency 690 * update code on each CPU. 691 */ 692 on_each_cpu(__lapic_update_tsc_freq, NULL, 0); 693 } 694 695 /* 696 * In this functions we calibrate APIC bus clocks to the external timer. 697 * 698 * We want to do the calibration only once since we want to have local timer 699 * irqs syncron. CPUs connected by the same APIC bus have the very same bus 700 * frequency. 701 * 702 * This was previously done by reading the PIT/HPET and waiting for a wrap 703 * around to find out, that a tick has elapsed. I have a box, where the PIT 704 * readout is broken, so it never gets out of the wait loop again. This was 705 * also reported by others. 706 * 707 * Monitoring the jiffies value is inaccurate and the clockevents 708 * infrastructure allows us to do a simple substitution of the interrupt 709 * handler. 710 * 711 * The calibration routine also uses the pm_timer when possible, as the PIT 712 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 713 * back to normal later in the boot process). 714 */ 715 716 #define LAPIC_CAL_LOOPS (HZ/10) 717 718 static __initdata int lapic_cal_loops = -1; 719 static __initdata long lapic_cal_t1, lapic_cal_t2; 720 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 721 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 722 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 723 724 /* 725 * Temporary interrupt handler. 726 */ 727 static void __init lapic_cal_handler(struct clock_event_device *dev) 728 { 729 unsigned long long tsc = 0; 730 long tapic = apic_read(APIC_TMCCT); 731 unsigned long pm = acpi_pm_read_early(); 732 733 if (boot_cpu_has(X86_FEATURE_TSC)) 734 tsc = rdtsc(); 735 736 switch (lapic_cal_loops++) { 737 case 0: 738 lapic_cal_t1 = tapic; 739 lapic_cal_tsc1 = tsc; 740 lapic_cal_pm1 = pm; 741 lapic_cal_j1 = jiffies; 742 break; 743 744 case LAPIC_CAL_LOOPS: 745 lapic_cal_t2 = tapic; 746 lapic_cal_tsc2 = tsc; 747 if (pm < lapic_cal_pm1) 748 pm += ACPI_PM_OVRRUN; 749 lapic_cal_pm2 = pm; 750 lapic_cal_j2 = jiffies; 751 break; 752 } 753 } 754 755 static int __init 756 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 757 { 758 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 759 const long pm_thresh = pm_100ms / 100; 760 unsigned long mult; 761 u64 res; 762 763 #ifndef CONFIG_X86_PM_TIMER 764 return -1; 765 #endif 766 767 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 768 769 /* Check, if the PM timer is available */ 770 if (!deltapm) 771 return -1; 772 773 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 774 775 if (deltapm > (pm_100ms - pm_thresh) && 776 deltapm < (pm_100ms + pm_thresh)) { 777 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 778 return 0; 779 } 780 781 res = (((u64)deltapm) * mult) >> 22; 782 do_div(res, 1000000); 783 pr_warning("APIC calibration not consistent " 784 "with PM-Timer: %ldms instead of 100ms\n",(long)res); 785 786 /* Correct the lapic counter value */ 787 res = (((u64)(*delta)) * pm_100ms); 788 do_div(res, deltapm); 789 pr_info("APIC delta adjusted to PM-Timer: " 790 "%lu (%ld)\n", (unsigned long)res, *delta); 791 *delta = (long)res; 792 793 /* Correct the tsc counter value */ 794 if (boot_cpu_has(X86_FEATURE_TSC)) { 795 res = (((u64)(*deltatsc)) * pm_100ms); 796 do_div(res, deltapm); 797 apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 798 "PM-Timer: %lu (%ld)\n", 799 (unsigned long)res, *deltatsc); 800 *deltatsc = (long)res; 801 } 802 803 return 0; 804 } 805 806 static int __init lapic_init_clockevent(void) 807 { 808 if (!lapic_timer_period) 809 return -1; 810 811 /* Calculate the scaled math multiplication factor */ 812 lapic_clockevent.mult = div_sc(lapic_timer_period/APIC_DIVISOR, 813 TICK_NSEC, lapic_clockevent.shift); 814 lapic_clockevent.max_delta_ns = 815 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); 816 lapic_clockevent.max_delta_ticks = 0x7FFFFFFF; 817 lapic_clockevent.min_delta_ns = 818 clockevent_delta2ns(0xF, &lapic_clockevent); 819 lapic_clockevent.min_delta_ticks = 0xF; 820 821 return 0; 822 } 823 824 bool __init apic_needs_pit(void) 825 { 826 /* 827 * If the frequencies are not known, PIT is required for both TSC 828 * and apic timer calibration. 829 */ 830 if (!tsc_khz || !cpu_khz) 831 return true; 832 833 /* Is there an APIC at all? */ 834 if (!boot_cpu_has(X86_FEATURE_APIC)) 835 return true; 836 837 /* Deadline timer is based on TSC so no further PIT action required */ 838 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 839 return false; 840 841 /* APIC timer disabled? */ 842 if (disable_apic_timer) 843 return true; 844 /* 845 * The APIC timer frequency is known already, no PIT calibration 846 * required. If unknown, let the PIT be initialized. 847 */ 848 return lapic_timer_period == 0; 849 } 850 851 static int __init calibrate_APIC_clock(void) 852 { 853 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 854 void (*real_handler)(struct clock_event_device *dev); 855 unsigned long deltaj; 856 long delta, deltatsc; 857 int pm_referenced = 0; 858 859 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 860 return 0; 861 862 /* 863 * Check if lapic timer has already been calibrated by platform 864 * specific routine, such as tsc calibration code. If so just fill 865 * in the clockevent structure and return. 866 */ 867 if (!lapic_init_clockevent()) { 868 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", 869 lapic_timer_period); 870 /* 871 * Direct calibration methods must have an always running 872 * local APIC timer, no need for broadcast timer. 873 */ 874 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 875 return 0; 876 } 877 878 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 879 "calibrating APIC timer ...\n"); 880 881 local_irq_disable(); 882 883 /* Replace the global interrupt handler */ 884 real_handler = global_clock_event->event_handler; 885 global_clock_event->event_handler = lapic_cal_handler; 886 887 /* 888 * Setup the APIC counter to maximum. There is no way the lapic 889 * can underflow in the 100ms detection time frame 890 */ 891 __setup_APIC_LVTT(0xffffffff, 0, 0); 892 893 /* Let the interrupts run */ 894 local_irq_enable(); 895 896 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 897 cpu_relax(); 898 899 local_irq_disable(); 900 901 /* Restore the real event handler */ 902 global_clock_event->event_handler = real_handler; 903 904 /* Build delta t1-t2 as apic timer counts down */ 905 delta = lapic_cal_t1 - lapic_cal_t2; 906 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 907 908 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 909 910 /* we trust the PM based calibration if possible */ 911 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 912 &delta, &deltatsc); 913 914 lapic_timer_period = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 915 lapic_init_clockevent(); 916 917 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 918 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); 919 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 920 lapic_timer_period); 921 922 if (boot_cpu_has(X86_FEATURE_TSC)) { 923 apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 924 "%ld.%04ld MHz.\n", 925 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 926 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 927 } 928 929 apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 930 "%u.%04u MHz.\n", 931 lapic_timer_period / (1000000 / HZ), 932 lapic_timer_period % (1000000 / HZ)); 933 934 /* 935 * Do a sanity check on the APIC calibration result 936 */ 937 if (lapic_timer_period < (1000000 / HZ)) { 938 local_irq_enable(); 939 pr_warning("APIC frequency too slow, disabling apic timer\n"); 940 return -1; 941 } 942 943 levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 944 945 /* 946 * PM timer calibration failed or not turned on 947 * so lets try APIC timer based calibration 948 */ 949 if (!pm_referenced) { 950 apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 951 952 /* 953 * Setup the apic timer manually 954 */ 955 levt->event_handler = lapic_cal_handler; 956 lapic_timer_set_periodic(levt); 957 lapic_cal_loops = -1; 958 959 /* Let the interrupts run */ 960 local_irq_enable(); 961 962 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 963 cpu_relax(); 964 965 /* Stop the lapic timer */ 966 local_irq_disable(); 967 lapic_timer_shutdown(levt); 968 969 /* Jiffies delta */ 970 deltaj = lapic_cal_j2 - lapic_cal_j1; 971 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 972 973 /* Check, if the jiffies result is consistent */ 974 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 975 apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 976 else 977 levt->features |= CLOCK_EVT_FEAT_DUMMY; 978 } 979 local_irq_enable(); 980 981 if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 982 pr_warning("APIC timer disabled due to verification failure\n"); 983 return -1; 984 } 985 986 return 0; 987 } 988 989 /* 990 * Setup the boot APIC 991 * 992 * Calibrate and verify the result. 993 */ 994 void __init setup_boot_APIC_clock(void) 995 { 996 /* 997 * The local apic timer can be disabled via the kernel 998 * commandline or from the CPU detection code. Register the lapic 999 * timer as a dummy clock event source on SMP systems, so the 1000 * broadcast mechanism is used. On UP systems simply ignore it. 1001 */ 1002 if (disable_apic_timer) { 1003 pr_info("Disabling APIC timer\n"); 1004 /* No broadcast on UP ! */ 1005 if (num_possible_cpus() > 1) { 1006 lapic_clockevent.mult = 1; 1007 setup_APIC_timer(); 1008 } 1009 return; 1010 } 1011 1012 if (calibrate_APIC_clock()) { 1013 /* No broadcast on UP ! */ 1014 if (num_possible_cpus() > 1) 1015 setup_APIC_timer(); 1016 return; 1017 } 1018 1019 /* 1020 * If nmi_watchdog is set to IO_APIC, we need the 1021 * PIT/HPET going. Otherwise register lapic as a dummy 1022 * device. 1023 */ 1024 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 1025 1026 /* Setup the lapic or request the broadcast */ 1027 setup_APIC_timer(); 1028 amd_e400_c1e_apic_setup(); 1029 } 1030 1031 void setup_secondary_APIC_clock(void) 1032 { 1033 setup_APIC_timer(); 1034 amd_e400_c1e_apic_setup(); 1035 } 1036 1037 /* 1038 * The guts of the apic timer interrupt 1039 */ 1040 static void local_apic_timer_interrupt(void) 1041 { 1042 struct clock_event_device *evt = this_cpu_ptr(&lapic_events); 1043 1044 /* 1045 * Normally we should not be here till LAPIC has been initialized but 1046 * in some cases like kdump, its possible that there is a pending LAPIC 1047 * timer interrupt from previous kernel's context and is delivered in 1048 * new kernel the moment interrupts are enabled. 1049 * 1050 * Interrupts are enabled early and LAPIC is setup much later, hence 1051 * its possible that when we get here evt->event_handler is NULL. 1052 * Check for event_handler being NULL and discard the interrupt as 1053 * spurious. 1054 */ 1055 if (!evt->event_handler) { 1056 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", 1057 smp_processor_id()); 1058 /* Switch it off */ 1059 lapic_timer_shutdown(evt); 1060 return; 1061 } 1062 1063 /* 1064 * the NMI deadlock-detector uses this. 1065 */ 1066 inc_irq_stat(apic_timer_irqs); 1067 1068 evt->event_handler(evt); 1069 } 1070 1071 /* 1072 * Local APIC timer interrupt. This is the most natural way for doing 1073 * local interrupts, but local timer interrupts can be emulated by 1074 * broadcast interrupts too. [in case the hw doesn't support APIC timers] 1075 * 1076 * [ if a single-CPU system runs an SMP kernel then we call the local 1077 * interrupt as well. Thus we cannot inline the local irq ... ] 1078 */ 1079 __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) 1080 { 1081 struct pt_regs *old_regs = set_irq_regs(regs); 1082 1083 /* 1084 * NOTE! We'd better ACK the irq immediately, 1085 * because timer handling can be slow. 1086 * 1087 * update_process_times() expects us to have done irq_enter(). 1088 * Besides, if we don't timer interrupts ignore the global 1089 * interrupt lock, which is the WrongThing (tm) to do. 1090 */ 1091 entering_ack_irq(); 1092 trace_local_timer_entry(LOCAL_TIMER_VECTOR); 1093 local_apic_timer_interrupt(); 1094 trace_local_timer_exit(LOCAL_TIMER_VECTOR); 1095 exiting_irq(); 1096 1097 set_irq_regs(old_regs); 1098 } 1099 1100 int setup_profiling_timer(unsigned int multiplier) 1101 { 1102 return -EINVAL; 1103 } 1104 1105 /* 1106 * Local APIC start and shutdown 1107 */ 1108 1109 /** 1110 * clear_local_APIC - shutdown the local APIC 1111 * 1112 * This is called, when a CPU is disabled and before rebooting, so the state of 1113 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 1114 * leftovers during boot. 1115 */ 1116 void clear_local_APIC(void) 1117 { 1118 int maxlvt; 1119 u32 v; 1120 1121 /* APIC hasn't been mapped yet */ 1122 if (!x2apic_mode && !apic_phys) 1123 return; 1124 1125 maxlvt = lapic_get_maxlvt(); 1126 /* 1127 * Masking an LVT entry can trigger a local APIC error 1128 * if the vector is zero. Mask LVTERR first to prevent this. 1129 */ 1130 if (maxlvt >= 3) { 1131 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 1132 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 1133 } 1134 /* 1135 * Careful: we have to set masks only first to deassert 1136 * any level-triggered sources. 1137 */ 1138 v = apic_read(APIC_LVTT); 1139 apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 1140 v = apic_read(APIC_LVT0); 1141 apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 1142 v = apic_read(APIC_LVT1); 1143 apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 1144 if (maxlvt >= 4) { 1145 v = apic_read(APIC_LVTPC); 1146 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 1147 } 1148 1149 /* lets not touch this if we didn't frob it */ 1150 #ifdef CONFIG_X86_THERMAL_VECTOR 1151 if (maxlvt >= 5) { 1152 v = apic_read(APIC_LVTTHMR); 1153 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 1154 } 1155 #endif 1156 #ifdef CONFIG_X86_MCE_INTEL 1157 if (maxlvt >= 6) { 1158 v = apic_read(APIC_LVTCMCI); 1159 if (!(v & APIC_LVT_MASKED)) 1160 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 1161 } 1162 #endif 1163 1164 /* 1165 * Clean APIC state for other OSs: 1166 */ 1167 apic_write(APIC_LVTT, APIC_LVT_MASKED); 1168 apic_write(APIC_LVT0, APIC_LVT_MASKED); 1169 apic_write(APIC_LVT1, APIC_LVT_MASKED); 1170 if (maxlvt >= 3) 1171 apic_write(APIC_LVTERR, APIC_LVT_MASKED); 1172 if (maxlvt >= 4) 1173 apic_write(APIC_LVTPC, APIC_LVT_MASKED); 1174 1175 /* Integrated APIC (!82489DX) ? */ 1176 if (lapic_is_integrated()) { 1177 if (maxlvt > 3) 1178 /* Clear ESR due to Pentium errata 3AP and 11AP */ 1179 apic_write(APIC_ESR, 0); 1180 apic_read(APIC_ESR); 1181 } 1182 } 1183 1184 /** 1185 * disable_local_APIC - clear and disable the local APIC 1186 */ 1187 void disable_local_APIC(void) 1188 { 1189 unsigned int value; 1190 1191 /* APIC hasn't been mapped yet */ 1192 if (!x2apic_mode && !apic_phys) 1193 return; 1194 1195 clear_local_APIC(); 1196 1197 /* 1198 * Disable APIC (implies clearing of registers 1199 * for 82489DX!). 1200 */ 1201 value = apic_read(APIC_SPIV); 1202 value &= ~APIC_SPIV_APIC_ENABLED; 1203 apic_write(APIC_SPIV, value); 1204 1205 #ifdef CONFIG_X86_32 1206 /* 1207 * When LAPIC was disabled by the BIOS and enabled by the kernel, 1208 * restore the disabled state. 1209 */ 1210 if (enabled_via_apicbase) { 1211 unsigned int l, h; 1212 1213 rdmsr(MSR_IA32_APICBASE, l, h); 1214 l &= ~MSR_IA32_APICBASE_ENABLE; 1215 wrmsr(MSR_IA32_APICBASE, l, h); 1216 } 1217 #endif 1218 } 1219 1220 /* 1221 * If Linux enabled the LAPIC against the BIOS default disable it down before 1222 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 1223 * not power-off. Additionally clear all LVT entries before disable_local_APIC 1224 * for the case where Linux didn't enable the LAPIC. 1225 */ 1226 void lapic_shutdown(void) 1227 { 1228 unsigned long flags; 1229 1230 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) 1231 return; 1232 1233 local_irq_save(flags); 1234 1235 #ifdef CONFIG_X86_32 1236 if (!enabled_via_apicbase) 1237 clear_local_APIC(); 1238 else 1239 #endif 1240 disable_local_APIC(); 1241 1242 1243 local_irq_restore(flags); 1244 } 1245 1246 /** 1247 * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1248 */ 1249 void __init sync_Arb_IDs(void) 1250 { 1251 /* 1252 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1253 * needed on AMD. 1254 */ 1255 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1256 return; 1257 1258 /* 1259 * Wait for idle. 1260 */ 1261 apic_wait_icr_idle(); 1262 1263 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1264 apic_write(APIC_ICR, APIC_DEST_ALLINC | 1265 APIC_INT_LEVELTRIG | APIC_DM_INIT); 1266 } 1267 1268 enum apic_intr_mode_id apic_intr_mode; 1269 1270 static int __init apic_intr_mode_select(void) 1271 { 1272 /* Check kernel option */ 1273 if (disable_apic) { 1274 pr_info("APIC disabled via kernel command line\n"); 1275 return APIC_PIC; 1276 } 1277 1278 /* Check BIOS */ 1279 #ifdef CONFIG_X86_64 1280 /* On 64-bit, the APIC must be integrated, Check local APIC only */ 1281 if (!boot_cpu_has(X86_FEATURE_APIC)) { 1282 disable_apic = 1; 1283 pr_info("APIC disabled by BIOS\n"); 1284 return APIC_PIC; 1285 } 1286 #else 1287 /* On 32-bit, the APIC may be integrated APIC or 82489DX */ 1288 1289 /* Neither 82489DX nor integrated APIC ? */ 1290 if (!boot_cpu_has(X86_FEATURE_APIC) && !smp_found_config) { 1291 disable_apic = 1; 1292 return APIC_PIC; 1293 } 1294 1295 /* If the BIOS pretends there is an integrated APIC ? */ 1296 if (!boot_cpu_has(X86_FEATURE_APIC) && 1297 APIC_INTEGRATED(boot_cpu_apic_version)) { 1298 disable_apic = 1; 1299 pr_err(FW_BUG "Local APIC %d not detected, force emulation\n", 1300 boot_cpu_physical_apicid); 1301 return APIC_PIC; 1302 } 1303 #endif 1304 1305 /* Check MP table or ACPI MADT configuration */ 1306 if (!smp_found_config) { 1307 disable_ioapic_support(); 1308 if (!acpi_lapic) { 1309 pr_info("APIC: ACPI MADT or MP tables are not detected\n"); 1310 return APIC_VIRTUAL_WIRE_NO_CONFIG; 1311 } 1312 return APIC_VIRTUAL_WIRE; 1313 } 1314 1315 #ifdef CONFIG_SMP 1316 /* If SMP should be disabled, then really disable it! */ 1317 if (!setup_max_cpus) { 1318 pr_info("APIC: SMP mode deactivated\n"); 1319 return APIC_SYMMETRIC_IO_NO_ROUTING; 1320 } 1321 1322 if (read_apic_id() != boot_cpu_physical_apicid) { 1323 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1324 read_apic_id(), boot_cpu_physical_apicid); 1325 /* Or can we switch back to PIC here? */ 1326 } 1327 #endif 1328 1329 return APIC_SYMMETRIC_IO; 1330 } 1331 1332 /* 1333 * An initial setup of the virtual wire mode. 1334 */ 1335 void __init init_bsp_APIC(void) 1336 { 1337 unsigned int value; 1338 1339 /* 1340 * Don't do the setup now if we have a SMP BIOS as the 1341 * through-I/O-APIC virtual wire mode might be active. 1342 */ 1343 if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC)) 1344 return; 1345 1346 /* 1347 * Do not trust the local APIC being empty at bootup. 1348 */ 1349 clear_local_APIC(); 1350 1351 /* 1352 * Enable APIC. 1353 */ 1354 value = apic_read(APIC_SPIV); 1355 value &= ~APIC_VECTOR_MASK; 1356 value |= APIC_SPIV_APIC_ENABLED; 1357 1358 #ifdef CONFIG_X86_32 1359 /* This bit is reserved on P4/Xeon and should be cleared */ 1360 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1361 (boot_cpu_data.x86 == 15)) 1362 value &= ~APIC_SPIV_FOCUS_DISABLED; 1363 else 1364 #endif 1365 value |= APIC_SPIV_FOCUS_DISABLED; 1366 value |= SPURIOUS_APIC_VECTOR; 1367 apic_write(APIC_SPIV, value); 1368 1369 /* 1370 * Set up the virtual wire mode. 1371 */ 1372 apic_write(APIC_LVT0, APIC_DM_EXTINT); 1373 value = APIC_DM_NMI; 1374 if (!lapic_is_integrated()) /* 82489DX */ 1375 value |= APIC_LVT_LEVEL_TRIGGER; 1376 if (apic_extnmi == APIC_EXTNMI_NONE) 1377 value |= APIC_LVT_MASKED; 1378 apic_write(APIC_LVT1, value); 1379 } 1380 1381 static void __init apic_bsp_setup(bool upmode); 1382 1383 /* Init the interrupt delivery mode for the BSP */ 1384 void __init apic_intr_mode_init(void) 1385 { 1386 bool upmode = IS_ENABLED(CONFIG_UP_LATE_INIT); 1387 1388 apic_intr_mode = apic_intr_mode_select(); 1389 1390 switch (apic_intr_mode) { 1391 case APIC_PIC: 1392 pr_info("APIC: Keep in PIC mode(8259)\n"); 1393 return; 1394 case APIC_VIRTUAL_WIRE: 1395 pr_info("APIC: Switch to virtual wire mode setup\n"); 1396 default_setup_apic_routing(); 1397 break; 1398 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1399 pr_info("APIC: Switch to virtual wire mode setup with no configuration\n"); 1400 upmode = true; 1401 default_setup_apic_routing(); 1402 break; 1403 case APIC_SYMMETRIC_IO: 1404 pr_info("APIC: Switch to symmetric I/O mode setup\n"); 1405 default_setup_apic_routing(); 1406 break; 1407 case APIC_SYMMETRIC_IO_NO_ROUTING: 1408 pr_info("APIC: Switch to symmetric I/O mode setup in no SMP routine\n"); 1409 break; 1410 } 1411 1412 apic_bsp_setup(upmode); 1413 } 1414 1415 static void lapic_setup_esr(void) 1416 { 1417 unsigned int oldvalue, value, maxlvt; 1418 1419 if (!lapic_is_integrated()) { 1420 pr_info("No ESR for 82489DX.\n"); 1421 return; 1422 } 1423 1424 if (apic->disable_esr) { 1425 /* 1426 * Something untraceable is creating bad interrupts on 1427 * secondary quads ... for the moment, just leave the 1428 * ESR disabled - we can't do anything useful with the 1429 * errors anyway - mbligh 1430 */ 1431 pr_info("Leaving ESR disabled.\n"); 1432 return; 1433 } 1434 1435 maxlvt = lapic_get_maxlvt(); 1436 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1437 apic_write(APIC_ESR, 0); 1438 oldvalue = apic_read(APIC_ESR); 1439 1440 /* enables sending errors */ 1441 value = ERROR_APIC_VECTOR; 1442 apic_write(APIC_LVTERR, value); 1443 1444 /* 1445 * spec says clear errors after enabling vector. 1446 */ 1447 if (maxlvt > 3) 1448 apic_write(APIC_ESR, 0); 1449 value = apic_read(APIC_ESR); 1450 if (value != oldvalue) 1451 apic_printk(APIC_VERBOSE, "ESR value before enabling " 1452 "vector: 0x%08x after: 0x%08x\n", 1453 oldvalue, value); 1454 } 1455 1456 static void apic_pending_intr_clear(void) 1457 { 1458 long long max_loops = cpu_khz ? cpu_khz : 1000000; 1459 unsigned long long tsc = 0, ntsc; 1460 unsigned int queued; 1461 unsigned long value; 1462 int i, j, acked = 0; 1463 1464 if (boot_cpu_has(X86_FEATURE_TSC)) 1465 tsc = rdtsc(); 1466 /* 1467 * After a crash, we no longer service the interrupts and a pending 1468 * interrupt from previous kernel might still have ISR bit set. 1469 * 1470 * Most probably by now CPU has serviced that pending interrupt and 1471 * it might not have done the ack_APIC_irq() because it thought, 1472 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it 1473 * does not clear the ISR bit and cpu thinks it has already serivced 1474 * the interrupt. Hence a vector might get locked. It was noticed 1475 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. 1476 */ 1477 do { 1478 queued = 0; 1479 for (i = APIC_ISR_NR - 1; i >= 0; i--) 1480 queued |= apic_read(APIC_IRR + i*0x10); 1481 1482 for (i = APIC_ISR_NR - 1; i >= 0; i--) { 1483 value = apic_read(APIC_ISR + i*0x10); 1484 for_each_set_bit(j, &value, 32) { 1485 ack_APIC_irq(); 1486 acked++; 1487 } 1488 } 1489 if (acked > 256) { 1490 pr_err("LAPIC pending interrupts after %d EOI\n", acked); 1491 break; 1492 } 1493 if (queued) { 1494 if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) { 1495 ntsc = rdtsc(); 1496 max_loops = (long long)cpu_khz << 10; 1497 max_loops -= ntsc - tsc; 1498 } else { 1499 max_loops--; 1500 } 1501 } 1502 } while (queued && max_loops > 0); 1503 WARN_ON(max_loops <= 0); 1504 } 1505 1506 /** 1507 * setup_local_APIC - setup the local APIC 1508 * 1509 * Used to setup local APIC while initializing BSP or bringing up APs. 1510 * Always called with preemption disabled. 1511 */ 1512 static void setup_local_APIC(void) 1513 { 1514 int cpu = smp_processor_id(); 1515 unsigned int value; 1516 #ifdef CONFIG_X86_32 1517 int logical_apicid, ldr_apicid; 1518 #endif 1519 1520 1521 if (disable_apic) { 1522 disable_ioapic_support(); 1523 return; 1524 } 1525 1526 #ifdef CONFIG_X86_32 1527 /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1528 if (lapic_is_integrated() && apic->disable_esr) { 1529 apic_write(APIC_ESR, 0); 1530 apic_write(APIC_ESR, 0); 1531 apic_write(APIC_ESR, 0); 1532 apic_write(APIC_ESR, 0); 1533 } 1534 #endif 1535 perf_events_lapic_init(); 1536 1537 /* 1538 * Double-check whether this APIC is really registered. 1539 * This is meaningless in clustered apic mode, so we skip it. 1540 */ 1541 BUG_ON(!apic->apic_id_registered()); 1542 1543 /* 1544 * Intel recommends to set DFR, LDR and TPR before enabling 1545 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1546 * document number 292116). So here it goes... 1547 */ 1548 apic->init_apic_ldr(); 1549 1550 #ifdef CONFIG_X86_32 1551 /* 1552 * APIC LDR is initialized. If logical_apicid mapping was 1553 * initialized during get_smp_config(), make sure it matches the 1554 * actual value. 1555 */ 1556 logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu); 1557 ldr_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 1558 WARN_ON(logical_apicid != BAD_APICID && logical_apicid != ldr_apicid); 1559 /* always use the value from LDR */ 1560 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = ldr_apicid; 1561 #endif 1562 1563 /* 1564 * Set Task Priority to 'accept all'. We never change this 1565 * later on. 1566 */ 1567 value = apic_read(APIC_TASKPRI); 1568 value &= ~APIC_TPRI_MASK; 1569 apic_write(APIC_TASKPRI, value); 1570 1571 apic_pending_intr_clear(); 1572 1573 /* 1574 * Now that we are all set up, enable the APIC 1575 */ 1576 value = apic_read(APIC_SPIV); 1577 value &= ~APIC_VECTOR_MASK; 1578 /* 1579 * Enable APIC 1580 */ 1581 value |= APIC_SPIV_APIC_ENABLED; 1582 1583 #ifdef CONFIG_X86_32 1584 /* 1585 * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1586 * certain networking cards. If high frequency interrupts are 1587 * happening on a particular IOAPIC pin, plus the IOAPIC routing 1588 * entry is masked/unmasked at a high rate as well then sooner or 1589 * later IOAPIC line gets 'stuck', no more interrupts are received 1590 * from the device. If focus CPU is disabled then the hang goes 1591 * away, oh well :-( 1592 * 1593 * [ This bug can be reproduced easily with a level-triggered 1594 * PCI Ne2000 networking cards and PII/PIII processors, dual 1595 * BX chipset. ] 1596 */ 1597 /* 1598 * Actually disabling the focus CPU check just makes the hang less 1599 * frequent as it makes the interrupt distributon model be more 1600 * like LRU than MRU (the short-term load is more even across CPUs). 1601 */ 1602 1603 /* 1604 * - enable focus processor (bit==0) 1605 * - 64bit mode always use processor focus 1606 * so no need to set it 1607 */ 1608 value &= ~APIC_SPIV_FOCUS_DISABLED; 1609 #endif 1610 1611 /* 1612 * Set spurious IRQ vector 1613 */ 1614 value |= SPURIOUS_APIC_VECTOR; 1615 apic_write(APIC_SPIV, value); 1616 1617 /* 1618 * Set up LVT0, LVT1: 1619 * 1620 * set up through-local-APIC on the boot CPU's LINT0. This is not 1621 * strictly necessary in pure symmetric-IO mode, but sometimes 1622 * we delegate interrupts to the 8259A. 1623 */ 1624 /* 1625 * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1626 */ 1627 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 1628 if (!cpu && (pic_mode || !value || skip_ioapic_setup)) { 1629 value = APIC_DM_EXTINT; 1630 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); 1631 } else { 1632 value = APIC_DM_EXTINT | APIC_LVT_MASKED; 1633 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); 1634 } 1635 apic_write(APIC_LVT0, value); 1636 1637 /* 1638 * Only the BSP sees the LINT1 NMI signal by default. This can be 1639 * modified by apic_extnmi= boot option. 1640 */ 1641 if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) || 1642 apic_extnmi == APIC_EXTNMI_ALL) 1643 value = APIC_DM_NMI; 1644 else 1645 value = APIC_DM_NMI | APIC_LVT_MASKED; 1646 1647 /* Is 82489DX ? */ 1648 if (!lapic_is_integrated()) 1649 value |= APIC_LVT_LEVEL_TRIGGER; 1650 apic_write(APIC_LVT1, value); 1651 1652 #ifdef CONFIG_X86_MCE_INTEL 1653 /* Recheck CMCI information after local APIC is up on CPU #0 */ 1654 if (!cpu) 1655 cmci_recheck(); 1656 #endif 1657 } 1658 1659 static void end_local_APIC_setup(void) 1660 { 1661 lapic_setup_esr(); 1662 1663 #ifdef CONFIG_X86_32 1664 { 1665 unsigned int value; 1666 /* Disable the local apic timer */ 1667 value = apic_read(APIC_LVTT); 1668 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1669 apic_write(APIC_LVTT, value); 1670 } 1671 #endif 1672 1673 apic_pm_activate(); 1674 } 1675 1676 /* 1677 * APIC setup function for application processors. Called from smpboot.c 1678 */ 1679 void apic_ap_setup(void) 1680 { 1681 setup_local_APIC(); 1682 end_local_APIC_setup(); 1683 } 1684 1685 #ifdef CONFIG_X86_X2APIC 1686 int x2apic_mode; 1687 1688 enum { 1689 X2APIC_OFF, 1690 X2APIC_ON, 1691 X2APIC_DISABLED, 1692 }; 1693 static int x2apic_state; 1694 1695 static void __x2apic_disable(void) 1696 { 1697 u64 msr; 1698 1699 if (!boot_cpu_has(X86_FEATURE_APIC)) 1700 return; 1701 1702 rdmsrl(MSR_IA32_APICBASE, msr); 1703 if (!(msr & X2APIC_ENABLE)) 1704 return; 1705 /* Disable xapic and x2apic first and then reenable xapic mode */ 1706 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); 1707 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); 1708 printk_once(KERN_INFO "x2apic disabled\n"); 1709 } 1710 1711 static void __x2apic_enable(void) 1712 { 1713 u64 msr; 1714 1715 rdmsrl(MSR_IA32_APICBASE, msr); 1716 if (msr & X2APIC_ENABLE) 1717 return; 1718 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); 1719 printk_once(KERN_INFO "x2apic enabled\n"); 1720 } 1721 1722 static int __init setup_nox2apic(char *str) 1723 { 1724 if (x2apic_enabled()) { 1725 int apicid = native_apic_msr_read(APIC_ID); 1726 1727 if (apicid >= 255) { 1728 pr_warning("Apicid: %08x, cannot enforce nox2apic\n", 1729 apicid); 1730 return 0; 1731 } 1732 pr_warning("x2apic already enabled.\n"); 1733 __x2apic_disable(); 1734 } 1735 setup_clear_cpu_cap(X86_FEATURE_X2APIC); 1736 x2apic_state = X2APIC_DISABLED; 1737 x2apic_mode = 0; 1738 return 0; 1739 } 1740 early_param("nox2apic", setup_nox2apic); 1741 1742 /* Called from cpu_init() to enable x2apic on (secondary) cpus */ 1743 void x2apic_setup(void) 1744 { 1745 /* 1746 * If x2apic is not in ON state, disable it if already enabled 1747 * from BIOS. 1748 */ 1749 if (x2apic_state != X2APIC_ON) { 1750 __x2apic_disable(); 1751 return; 1752 } 1753 __x2apic_enable(); 1754 } 1755 1756 static __init void x2apic_disable(void) 1757 { 1758 u32 x2apic_id, state = x2apic_state; 1759 1760 x2apic_mode = 0; 1761 x2apic_state = X2APIC_DISABLED; 1762 1763 if (state != X2APIC_ON) 1764 return; 1765 1766 x2apic_id = read_apic_id(); 1767 if (x2apic_id >= 255) 1768 panic("Cannot disable x2apic, id: %08x\n", x2apic_id); 1769 1770 __x2apic_disable(); 1771 register_lapic_address(mp_lapic_addr); 1772 } 1773 1774 static __init void x2apic_enable(void) 1775 { 1776 if (x2apic_state != X2APIC_OFF) 1777 return; 1778 1779 x2apic_mode = 1; 1780 x2apic_state = X2APIC_ON; 1781 __x2apic_enable(); 1782 } 1783 1784 static __init void try_to_enable_x2apic(int remap_mode) 1785 { 1786 if (x2apic_state == X2APIC_DISABLED) 1787 return; 1788 1789 if (remap_mode != IRQ_REMAP_X2APIC_MODE) { 1790 /* IR is required if there is APIC ID > 255 even when running 1791 * under KVM 1792 */ 1793 if (max_physical_apicid > 255 || 1794 !x86_init.hyper.x2apic_available()) { 1795 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n"); 1796 x2apic_disable(); 1797 return; 1798 } 1799 1800 /* 1801 * without IR all CPUs can be addressed by IOAPIC/MSI 1802 * only in physical mode 1803 */ 1804 x2apic_phys = 1; 1805 } 1806 x2apic_enable(); 1807 } 1808 1809 void __init check_x2apic(void) 1810 { 1811 if (x2apic_enabled()) { 1812 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n"); 1813 x2apic_mode = 1; 1814 x2apic_state = X2APIC_ON; 1815 } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) { 1816 x2apic_state = X2APIC_DISABLED; 1817 } 1818 } 1819 #else /* CONFIG_X86_X2APIC */ 1820 static int __init validate_x2apic(void) 1821 { 1822 if (!apic_is_x2apic_enabled()) 1823 return 0; 1824 /* 1825 * Checkme: Can we simply turn off x2apic here instead of panic? 1826 */ 1827 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n"); 1828 } 1829 early_initcall(validate_x2apic); 1830 1831 static inline void try_to_enable_x2apic(int remap_mode) { } 1832 static inline void __x2apic_enable(void) { } 1833 #endif /* !CONFIG_X86_X2APIC */ 1834 1835 void __init enable_IR_x2apic(void) 1836 { 1837 unsigned long flags; 1838 int ret, ir_stat; 1839 1840 if (skip_ioapic_setup) { 1841 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n"); 1842 return; 1843 } 1844 1845 ir_stat = irq_remapping_prepare(); 1846 if (ir_stat < 0 && !x2apic_supported()) 1847 return; 1848 1849 ret = save_ioapic_entries(); 1850 if (ret) { 1851 pr_info("Saving IO-APIC state failed: %d\n", ret); 1852 return; 1853 } 1854 1855 local_irq_save(flags); 1856 legacy_pic->mask_all(); 1857 mask_ioapic_entries(); 1858 1859 /* If irq_remapping_prepare() succeeded, try to enable it */ 1860 if (ir_stat >= 0) 1861 ir_stat = irq_remapping_enable(); 1862 /* ir_stat contains the remap mode or an error code */ 1863 try_to_enable_x2apic(ir_stat); 1864 1865 if (ir_stat < 0) 1866 restore_ioapic_entries(); 1867 legacy_pic->restore_mask(); 1868 local_irq_restore(flags); 1869 } 1870 1871 #ifdef CONFIG_X86_64 1872 /* 1873 * Detect and enable local APICs on non-SMP boards. 1874 * Original code written by Keir Fraser. 1875 * On AMD64 we trust the BIOS - if it says no APIC it is likely 1876 * not correctly set up (usually the APIC timer won't work etc.) 1877 */ 1878 static int __init detect_init_APIC(void) 1879 { 1880 if (!boot_cpu_has(X86_FEATURE_APIC)) { 1881 pr_info("No local APIC present\n"); 1882 return -1; 1883 } 1884 1885 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1886 return 0; 1887 } 1888 #else 1889 1890 static int __init apic_verify(void) 1891 { 1892 u32 features, h, l; 1893 1894 /* 1895 * The APIC feature bit should now be enabled 1896 * in `cpuid' 1897 */ 1898 features = cpuid_edx(1); 1899 if (!(features & (1 << X86_FEATURE_APIC))) { 1900 pr_warning("Could not enable APIC!\n"); 1901 return -1; 1902 } 1903 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 1904 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1905 1906 /* The BIOS may have set up the APIC at some other address */ 1907 if (boot_cpu_data.x86 >= 6) { 1908 rdmsr(MSR_IA32_APICBASE, l, h); 1909 if (l & MSR_IA32_APICBASE_ENABLE) 1910 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 1911 } 1912 1913 pr_info("Found and enabled local APIC!\n"); 1914 return 0; 1915 } 1916 1917 int __init apic_force_enable(unsigned long addr) 1918 { 1919 u32 h, l; 1920 1921 if (disable_apic) 1922 return -1; 1923 1924 /* 1925 * Some BIOSes disable the local APIC in the APIC_BASE 1926 * MSR. This can only be done in software for Intel P6 or later 1927 * and AMD K7 (Model > 1) or later. 1928 */ 1929 if (boot_cpu_data.x86 >= 6) { 1930 rdmsr(MSR_IA32_APICBASE, l, h); 1931 if (!(l & MSR_IA32_APICBASE_ENABLE)) { 1932 pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 1933 l &= ~MSR_IA32_APICBASE_BASE; 1934 l |= MSR_IA32_APICBASE_ENABLE | addr; 1935 wrmsr(MSR_IA32_APICBASE, l, h); 1936 enabled_via_apicbase = 1; 1937 } 1938 } 1939 return apic_verify(); 1940 } 1941 1942 /* 1943 * Detect and initialize APIC 1944 */ 1945 static int __init detect_init_APIC(void) 1946 { 1947 /* Disabled by kernel option? */ 1948 if (disable_apic) 1949 return -1; 1950 1951 switch (boot_cpu_data.x86_vendor) { 1952 case X86_VENDOR_AMD: 1953 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 1954 (boot_cpu_data.x86 >= 15)) 1955 break; 1956 goto no_apic; 1957 case X86_VENDOR_HYGON: 1958 break; 1959 case X86_VENDOR_INTEL: 1960 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 1961 (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC))) 1962 break; 1963 goto no_apic; 1964 default: 1965 goto no_apic; 1966 } 1967 1968 if (!boot_cpu_has(X86_FEATURE_APIC)) { 1969 /* 1970 * Over-ride BIOS and try to enable the local APIC only if 1971 * "lapic" specified. 1972 */ 1973 if (!force_enable_local_apic) { 1974 pr_info("Local APIC disabled by BIOS -- " 1975 "you can enable it with \"lapic\"\n"); 1976 return -1; 1977 } 1978 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) 1979 return -1; 1980 } else { 1981 if (apic_verify()) 1982 return -1; 1983 } 1984 1985 apic_pm_activate(); 1986 1987 return 0; 1988 1989 no_apic: 1990 pr_info("No local APIC present or hardware disabled\n"); 1991 return -1; 1992 } 1993 #endif 1994 1995 /** 1996 * init_apic_mappings - initialize APIC mappings 1997 */ 1998 void __init init_apic_mappings(void) 1999 { 2000 unsigned int new_apicid; 2001 2002 apic_check_deadline_errata(); 2003 2004 if (x2apic_mode) { 2005 boot_cpu_physical_apicid = read_apic_id(); 2006 return; 2007 } 2008 2009 /* If no local APIC can be found return early */ 2010 if (!smp_found_config && detect_init_APIC()) { 2011 /* lets NOP'ify apic operations */ 2012 pr_info("APIC: disable apic facility\n"); 2013 apic_disable(); 2014 } else { 2015 apic_phys = mp_lapic_addr; 2016 2017 /* 2018 * If the system has ACPI MADT tables or MP info, the LAPIC 2019 * address is already registered. 2020 */ 2021 if (!acpi_lapic && !smp_found_config) 2022 register_lapic_address(apic_phys); 2023 } 2024 2025 /* 2026 * Fetch the APIC ID of the BSP in case we have a 2027 * default configuration (or the MP table is broken). 2028 */ 2029 new_apicid = read_apic_id(); 2030 if (boot_cpu_physical_apicid != new_apicid) { 2031 boot_cpu_physical_apicid = new_apicid; 2032 /* 2033 * yeah -- we lie about apic_version 2034 * in case if apic was disabled via boot option 2035 * but it's not a problem for SMP compiled kernel 2036 * since apic_intr_mode_select is prepared for such 2037 * a case and disable smp mode 2038 */ 2039 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 2040 } 2041 } 2042 2043 void __init register_lapic_address(unsigned long address) 2044 { 2045 mp_lapic_addr = address; 2046 2047 if (!x2apic_mode) { 2048 set_fixmap_nocache(FIX_APIC_BASE, address); 2049 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 2050 APIC_BASE, address); 2051 } 2052 if (boot_cpu_physical_apicid == -1U) { 2053 boot_cpu_physical_apicid = read_apic_id(); 2054 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 2055 } 2056 } 2057 2058 /* 2059 * Local APIC interrupts 2060 */ 2061 2062 /* 2063 * This interrupt should _never_ happen with our APIC/SMP architecture 2064 */ 2065 __visible void __irq_entry smp_spurious_interrupt(struct pt_regs *regs) 2066 { 2067 u8 vector = ~regs->orig_ax; 2068 u32 v; 2069 2070 entering_irq(); 2071 trace_spurious_apic_entry(vector); 2072 2073 inc_irq_stat(irq_spurious_count); 2074 2075 /* 2076 * If this is a spurious interrupt then do not acknowledge 2077 */ 2078 if (vector == SPURIOUS_APIC_VECTOR) { 2079 /* See SDM vol 3 */ 2080 pr_info("Spurious APIC interrupt (vector 0xFF) on CPU#%d, should never happen.\n", 2081 smp_processor_id()); 2082 goto out; 2083 } 2084 2085 /* 2086 * If it is a vectored one, verify it's set in the ISR. If set, 2087 * acknowledge it. 2088 */ 2089 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1)); 2090 if (v & (1 << (vector & 0x1f))) { 2091 pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Acked\n", 2092 vector, smp_processor_id()); 2093 ack_APIC_irq(); 2094 } else { 2095 pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Not pending!\n", 2096 vector, smp_processor_id()); 2097 } 2098 out: 2099 trace_spurious_apic_exit(vector); 2100 exiting_irq(); 2101 } 2102 2103 /* 2104 * This interrupt should never happen with our APIC/SMP architecture 2105 */ 2106 __visible void __irq_entry smp_error_interrupt(struct pt_regs *regs) 2107 { 2108 static const char * const error_interrupt_reason[] = { 2109 "Send CS error", /* APIC Error Bit 0 */ 2110 "Receive CS error", /* APIC Error Bit 1 */ 2111 "Send accept error", /* APIC Error Bit 2 */ 2112 "Receive accept error", /* APIC Error Bit 3 */ 2113 "Redirectable IPI", /* APIC Error Bit 4 */ 2114 "Send illegal vector", /* APIC Error Bit 5 */ 2115 "Received illegal vector", /* APIC Error Bit 6 */ 2116 "Illegal register address", /* APIC Error Bit 7 */ 2117 }; 2118 u32 v, i = 0; 2119 2120 entering_irq(); 2121 trace_error_apic_entry(ERROR_APIC_VECTOR); 2122 2123 /* First tickle the hardware, only then report what went on. -- REW */ 2124 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */ 2125 apic_write(APIC_ESR, 0); 2126 v = apic_read(APIC_ESR); 2127 ack_APIC_irq(); 2128 atomic_inc(&irq_err_count); 2129 2130 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x", 2131 smp_processor_id(), v); 2132 2133 v &= 0xff; 2134 while (v) { 2135 if (v & 0x1) 2136 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); 2137 i++; 2138 v >>= 1; 2139 } 2140 2141 apic_printk(APIC_DEBUG, KERN_CONT "\n"); 2142 2143 trace_error_apic_exit(ERROR_APIC_VECTOR); 2144 exiting_irq(); 2145 } 2146 2147 /** 2148 * connect_bsp_APIC - attach the APIC to the interrupt system 2149 */ 2150 static void __init connect_bsp_APIC(void) 2151 { 2152 #ifdef CONFIG_X86_32 2153 if (pic_mode) { 2154 /* 2155 * Do not trust the local APIC being empty at bootup. 2156 */ 2157 clear_local_APIC(); 2158 /* 2159 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 2160 * local APIC to INT and NMI lines. 2161 */ 2162 apic_printk(APIC_VERBOSE, "leaving PIC mode, " 2163 "enabling APIC mode.\n"); 2164 imcr_pic_to_apic(); 2165 } 2166 #endif 2167 } 2168 2169 /** 2170 * disconnect_bsp_APIC - detach the APIC from the interrupt system 2171 * @virt_wire_setup: indicates, whether virtual wire mode is selected 2172 * 2173 * Virtual wire mode is necessary to deliver legacy interrupts even when the 2174 * APIC is disabled. 2175 */ 2176 void disconnect_bsp_APIC(int virt_wire_setup) 2177 { 2178 unsigned int value; 2179 2180 #ifdef CONFIG_X86_32 2181 if (pic_mode) { 2182 /* 2183 * Put the board back into PIC mode (has an effect only on 2184 * certain older boards). Note that APIC interrupts, including 2185 * IPIs, won't work beyond this point! The only exception are 2186 * INIT IPIs. 2187 */ 2188 apic_printk(APIC_VERBOSE, "disabling APIC mode, " 2189 "entering PIC mode.\n"); 2190 imcr_apic_to_pic(); 2191 return; 2192 } 2193 #endif 2194 2195 /* Go back to Virtual Wire compatibility mode */ 2196 2197 /* For the spurious interrupt use vector F, and enable it */ 2198 value = apic_read(APIC_SPIV); 2199 value &= ~APIC_VECTOR_MASK; 2200 value |= APIC_SPIV_APIC_ENABLED; 2201 value |= 0xf; 2202 apic_write(APIC_SPIV, value); 2203 2204 if (!virt_wire_setup) { 2205 /* 2206 * For LVT0 make it edge triggered, active high, 2207 * external and enabled 2208 */ 2209 value = apic_read(APIC_LVT0); 2210 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2211 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2212 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2213 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2214 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 2215 apic_write(APIC_LVT0, value); 2216 } else { 2217 /* Disable LVT0 */ 2218 apic_write(APIC_LVT0, APIC_LVT_MASKED); 2219 } 2220 2221 /* 2222 * For LVT1 make it edge triggered, active high, 2223 * nmi and enabled 2224 */ 2225 value = apic_read(APIC_LVT1); 2226 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2227 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2228 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2229 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2230 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 2231 apic_write(APIC_LVT1, value); 2232 } 2233 2234 /* 2235 * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated 2236 * contiguously, it equals to current allocated max logical CPU ID plus 1. 2237 * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range, 2238 * so the maximum of nr_logical_cpuids is nr_cpu_ids. 2239 * 2240 * NOTE: Reserve 0 for BSP. 2241 */ 2242 static int nr_logical_cpuids = 1; 2243 2244 /* 2245 * Used to store mapping between logical CPU IDs and APIC IDs. 2246 */ 2247 static int cpuid_to_apicid[] = { 2248 [0 ... NR_CPUS - 1] = -1, 2249 }; 2250 2251 #ifdef CONFIG_SMP 2252 /** 2253 * apic_id_is_primary_thread - Check whether APIC ID belongs to a primary thread 2254 * @id: APIC ID to check 2255 */ 2256 bool apic_id_is_primary_thread(unsigned int apicid) 2257 { 2258 u32 mask; 2259 2260 if (smp_num_siblings == 1) 2261 return true; 2262 /* Isolate the SMT bit(s) in the APICID and check for 0 */ 2263 mask = (1U << (fls(smp_num_siblings) - 1)) - 1; 2264 return !(apicid & mask); 2265 } 2266 #endif 2267 2268 /* 2269 * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids 2270 * and cpuid_to_apicid[] synchronized. 2271 */ 2272 static int allocate_logical_cpuid(int apicid) 2273 { 2274 int i; 2275 2276 /* 2277 * cpuid <-> apicid mapping is persistent, so when a cpu is up, 2278 * check if the kernel has allocated a cpuid for it. 2279 */ 2280 for (i = 0; i < nr_logical_cpuids; i++) { 2281 if (cpuid_to_apicid[i] == apicid) 2282 return i; 2283 } 2284 2285 /* Allocate a new cpuid. */ 2286 if (nr_logical_cpuids >= nr_cpu_ids) { 2287 WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. " 2288 "Processor %d/0x%x and the rest are ignored.\n", 2289 nr_cpu_ids, nr_logical_cpuids, apicid); 2290 return -EINVAL; 2291 } 2292 2293 cpuid_to_apicid[nr_logical_cpuids] = apicid; 2294 return nr_logical_cpuids++; 2295 } 2296 2297 int generic_processor_info(int apicid, int version) 2298 { 2299 int cpu, max = nr_cpu_ids; 2300 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, 2301 phys_cpu_present_map); 2302 2303 /* 2304 * boot_cpu_physical_apicid is designed to have the apicid 2305 * returned by read_apic_id(), i.e, the apicid of the 2306 * currently booting-up processor. However, on some platforms, 2307 * it is temporarily modified by the apicid reported as BSP 2308 * through MP table. Concretely: 2309 * 2310 * - arch/x86/kernel/mpparse.c: MP_processor_info() 2311 * - arch/x86/mm/amdtopology.c: amd_numa_init() 2312 * 2313 * This function is executed with the modified 2314 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel 2315 * parameter doesn't work to disable APs on kdump 2nd kernel. 2316 * 2317 * Since fixing handling of boot_cpu_physical_apicid requires 2318 * another discussion and tests on each platform, we leave it 2319 * for now and here we use read_apic_id() directly in this 2320 * function, generic_processor_info(). 2321 */ 2322 if (disabled_cpu_apicid != BAD_APICID && 2323 disabled_cpu_apicid != read_apic_id() && 2324 disabled_cpu_apicid == apicid) { 2325 int thiscpu = num_processors + disabled_cpus; 2326 2327 pr_warning("APIC: Disabling requested cpu." 2328 " Processor %d/0x%x ignored.\n", 2329 thiscpu, apicid); 2330 2331 disabled_cpus++; 2332 return -ENODEV; 2333 } 2334 2335 /* 2336 * If boot cpu has not been detected yet, then only allow upto 2337 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu 2338 */ 2339 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && 2340 apicid != boot_cpu_physical_apicid) { 2341 int thiscpu = max + disabled_cpus - 1; 2342 2343 pr_warning( 2344 "APIC: NR_CPUS/possible_cpus limit of %i almost" 2345 " reached. Keeping one slot for boot cpu." 2346 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 2347 2348 disabled_cpus++; 2349 return -ENODEV; 2350 } 2351 2352 if (num_processors >= nr_cpu_ids) { 2353 int thiscpu = max + disabled_cpus; 2354 2355 pr_warning("APIC: NR_CPUS/possible_cpus limit of %i " 2356 "reached. Processor %d/0x%x ignored.\n", 2357 max, thiscpu, apicid); 2358 2359 disabled_cpus++; 2360 return -EINVAL; 2361 } 2362 2363 if (apicid == boot_cpu_physical_apicid) { 2364 /* 2365 * x86_bios_cpu_apicid is required to have processors listed 2366 * in same order as logical cpu numbers. Hence the first 2367 * entry is BSP, and so on. 2368 * boot_cpu_init() already hold bit 0 in cpu_present_mask 2369 * for BSP. 2370 */ 2371 cpu = 0; 2372 2373 /* Logical cpuid 0 is reserved for BSP. */ 2374 cpuid_to_apicid[0] = apicid; 2375 } else { 2376 cpu = allocate_logical_cpuid(apicid); 2377 if (cpu < 0) { 2378 disabled_cpus++; 2379 return -EINVAL; 2380 } 2381 } 2382 2383 /* 2384 * Validate version 2385 */ 2386 if (version == 0x0) { 2387 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", 2388 cpu, apicid); 2389 version = 0x10; 2390 } 2391 2392 if (version != boot_cpu_apic_version) { 2393 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", 2394 boot_cpu_apic_version, cpu, version); 2395 } 2396 2397 if (apicid > max_physical_apicid) 2398 max_physical_apicid = apicid; 2399 2400 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 2401 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 2402 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 2403 #endif 2404 #ifdef CONFIG_X86_32 2405 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 2406 apic->x86_32_early_logical_apicid(cpu); 2407 #endif 2408 set_cpu_possible(cpu, true); 2409 physid_set(apicid, phys_cpu_present_map); 2410 set_cpu_present(cpu, true); 2411 num_processors++; 2412 2413 return cpu; 2414 } 2415 2416 int hard_smp_processor_id(void) 2417 { 2418 return read_apic_id(); 2419 } 2420 2421 /* 2422 * Override the generic EOI implementation with an optimized version. 2423 * Only called during early boot when only one CPU is active and with 2424 * interrupts disabled, so we know this does not race with actual APIC driver 2425 * use. 2426 */ 2427 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) 2428 { 2429 struct apic **drv; 2430 2431 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { 2432 /* Should happen once for each apic */ 2433 WARN_ON((*drv)->eoi_write == eoi_write); 2434 (*drv)->native_eoi_write = (*drv)->eoi_write; 2435 (*drv)->eoi_write = eoi_write; 2436 } 2437 } 2438 2439 static void __init apic_bsp_up_setup(void) 2440 { 2441 #ifdef CONFIG_X86_64 2442 apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid)); 2443 #else 2444 /* 2445 * Hack: In case of kdump, after a crash, kernel might be booting 2446 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 2447 * might be zero if read from MP tables. Get it from LAPIC. 2448 */ 2449 # ifdef CONFIG_CRASH_DUMP 2450 boot_cpu_physical_apicid = read_apic_id(); 2451 # endif 2452 #endif 2453 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 2454 } 2455 2456 /** 2457 * apic_bsp_setup - Setup function for local apic and io-apic 2458 * @upmode: Force UP mode (for APIC_init_uniprocessor) 2459 */ 2460 static void __init apic_bsp_setup(bool upmode) 2461 { 2462 connect_bsp_APIC(); 2463 if (upmode) 2464 apic_bsp_up_setup(); 2465 setup_local_APIC(); 2466 2467 enable_IO_APIC(); 2468 end_local_APIC_setup(); 2469 irq_remap_enable_fault_handling(); 2470 setup_IO_APIC(); 2471 } 2472 2473 #ifdef CONFIG_UP_LATE_INIT 2474 void __init up_late_init(void) 2475 { 2476 if (apic_intr_mode == APIC_PIC) 2477 return; 2478 2479 /* Setup local timer */ 2480 x86_init.timers.setup_percpu_clockev(); 2481 } 2482 #endif 2483 2484 /* 2485 * Power management 2486 */ 2487 #ifdef CONFIG_PM 2488 2489 static struct { 2490 /* 2491 * 'active' is true if the local APIC was enabled by us and 2492 * not the BIOS; this signifies that we are also responsible 2493 * for disabling it before entering apm/acpi suspend 2494 */ 2495 int active; 2496 /* r/w apic fields */ 2497 unsigned int apic_id; 2498 unsigned int apic_taskpri; 2499 unsigned int apic_ldr; 2500 unsigned int apic_dfr; 2501 unsigned int apic_spiv; 2502 unsigned int apic_lvtt; 2503 unsigned int apic_lvtpc; 2504 unsigned int apic_lvt0; 2505 unsigned int apic_lvt1; 2506 unsigned int apic_lvterr; 2507 unsigned int apic_tmict; 2508 unsigned int apic_tdcr; 2509 unsigned int apic_thmr; 2510 unsigned int apic_cmci; 2511 } apic_pm_state; 2512 2513 static int lapic_suspend(void) 2514 { 2515 unsigned long flags; 2516 int maxlvt; 2517 2518 if (!apic_pm_state.active) 2519 return 0; 2520 2521 maxlvt = lapic_get_maxlvt(); 2522 2523 apic_pm_state.apic_id = apic_read(APIC_ID); 2524 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 2525 apic_pm_state.apic_ldr = apic_read(APIC_LDR); 2526 apic_pm_state.apic_dfr = apic_read(APIC_DFR); 2527 apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2528 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2529 if (maxlvt >= 4) 2530 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2531 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2532 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2533 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2534 apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2535 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 2536 #ifdef CONFIG_X86_THERMAL_VECTOR 2537 if (maxlvt >= 5) 2538 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2539 #endif 2540 #ifdef CONFIG_X86_MCE_INTEL 2541 if (maxlvt >= 6) 2542 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI); 2543 #endif 2544 2545 local_irq_save(flags); 2546 disable_local_APIC(); 2547 2548 irq_remapping_disable(); 2549 2550 local_irq_restore(flags); 2551 return 0; 2552 } 2553 2554 static void lapic_resume(void) 2555 { 2556 unsigned int l, h; 2557 unsigned long flags; 2558 int maxlvt; 2559 2560 if (!apic_pm_state.active) 2561 return; 2562 2563 local_irq_save(flags); 2564 2565 /* 2566 * IO-APIC and PIC have their own resume routines. 2567 * We just mask them here to make sure the interrupt 2568 * subsystem is completely quiet while we enable x2apic 2569 * and interrupt-remapping. 2570 */ 2571 mask_ioapic_entries(); 2572 legacy_pic->mask_all(); 2573 2574 if (x2apic_mode) { 2575 __x2apic_enable(); 2576 } else { 2577 /* 2578 * Make sure the APICBASE points to the right address 2579 * 2580 * FIXME! This will be wrong if we ever support suspend on 2581 * SMP! We'll need to do this as part of the CPU restore! 2582 */ 2583 if (boot_cpu_data.x86 >= 6) { 2584 rdmsr(MSR_IA32_APICBASE, l, h); 2585 l &= ~MSR_IA32_APICBASE_BASE; 2586 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2587 wrmsr(MSR_IA32_APICBASE, l, h); 2588 } 2589 } 2590 2591 maxlvt = lapic_get_maxlvt(); 2592 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2593 apic_write(APIC_ID, apic_pm_state.apic_id); 2594 apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2595 apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2596 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2597 apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2598 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2599 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 2600 #ifdef CONFIG_X86_THERMAL_VECTOR 2601 if (maxlvt >= 5) 2602 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2603 #endif 2604 #ifdef CONFIG_X86_MCE_INTEL 2605 if (maxlvt >= 6) 2606 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci); 2607 #endif 2608 if (maxlvt >= 4) 2609 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2610 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2611 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2612 apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2613 apic_write(APIC_ESR, 0); 2614 apic_read(APIC_ESR); 2615 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2616 apic_write(APIC_ESR, 0); 2617 apic_read(APIC_ESR); 2618 2619 irq_remapping_reenable(x2apic_mode); 2620 2621 local_irq_restore(flags); 2622 } 2623 2624 /* 2625 * This device has no shutdown method - fully functioning local APICs 2626 * are needed on every CPU up until machine_halt/restart/poweroff. 2627 */ 2628 2629 static struct syscore_ops lapic_syscore_ops = { 2630 .resume = lapic_resume, 2631 .suspend = lapic_suspend, 2632 }; 2633 2634 static void apic_pm_activate(void) 2635 { 2636 apic_pm_state.active = 1; 2637 } 2638 2639 static int __init init_lapic_sysfs(void) 2640 { 2641 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 2642 if (boot_cpu_has(X86_FEATURE_APIC)) 2643 register_syscore_ops(&lapic_syscore_ops); 2644 2645 return 0; 2646 } 2647 2648 /* local apic needs to resume before other devices access its registers. */ 2649 core_initcall(init_lapic_sysfs); 2650 2651 #else /* CONFIG_PM */ 2652 2653 static void apic_pm_activate(void) { } 2654 2655 #endif /* CONFIG_PM */ 2656 2657 #ifdef CONFIG_X86_64 2658 2659 static int multi_checked; 2660 static int multi; 2661 2662 static int set_multi(const struct dmi_system_id *d) 2663 { 2664 if (multi) 2665 return 0; 2666 pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2667 multi = 1; 2668 return 0; 2669 } 2670 2671 static const struct dmi_system_id multi_dmi_table[] = { 2672 { 2673 .callback = set_multi, 2674 .ident = "IBM System Summit2", 2675 .matches = { 2676 DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2677 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2678 }, 2679 }, 2680 {} 2681 }; 2682 2683 static void dmi_check_multi(void) 2684 { 2685 if (multi_checked) 2686 return; 2687 2688 dmi_check_system(multi_dmi_table); 2689 multi_checked = 1; 2690 } 2691 2692 /* 2693 * apic_is_clustered_box() -- Check if we can expect good TSC 2694 * 2695 * Thus far, the major user of this is IBM's Summit2 series: 2696 * Clustered boxes may have unsynced TSC problems if they are 2697 * multi-chassis. 2698 * Use DMI to check them 2699 */ 2700 int apic_is_clustered_box(void) 2701 { 2702 dmi_check_multi(); 2703 return multi; 2704 } 2705 #endif 2706 2707 /* 2708 * APIC command line parameters 2709 */ 2710 static int __init setup_disableapic(char *arg) 2711 { 2712 disable_apic = 1; 2713 setup_clear_cpu_cap(X86_FEATURE_APIC); 2714 return 0; 2715 } 2716 early_param("disableapic", setup_disableapic); 2717 2718 /* same as disableapic, for compatibility */ 2719 static int __init setup_nolapic(char *arg) 2720 { 2721 return setup_disableapic(arg); 2722 } 2723 early_param("nolapic", setup_nolapic); 2724 2725 static int __init parse_lapic_timer_c2_ok(char *arg) 2726 { 2727 local_apic_timer_c2_ok = 1; 2728 return 0; 2729 } 2730 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2731 2732 static int __init parse_disable_apic_timer(char *arg) 2733 { 2734 disable_apic_timer = 1; 2735 return 0; 2736 } 2737 early_param("noapictimer", parse_disable_apic_timer); 2738 2739 static int __init parse_nolapic_timer(char *arg) 2740 { 2741 disable_apic_timer = 1; 2742 return 0; 2743 } 2744 early_param("nolapic_timer", parse_nolapic_timer); 2745 2746 static int __init apic_set_verbosity(char *arg) 2747 { 2748 if (!arg) { 2749 #ifdef CONFIG_X86_64 2750 skip_ioapic_setup = 0; 2751 return 0; 2752 #endif 2753 return -EINVAL; 2754 } 2755 2756 if (strcmp("debug", arg) == 0) 2757 apic_verbosity = APIC_DEBUG; 2758 else if (strcmp("verbose", arg) == 0) 2759 apic_verbosity = APIC_VERBOSE; 2760 #ifdef CONFIG_X86_64 2761 else { 2762 pr_warning("APIC Verbosity level %s not recognised" 2763 " use apic=verbose or apic=debug\n", arg); 2764 return -EINVAL; 2765 } 2766 #endif 2767 2768 return 0; 2769 } 2770 early_param("apic", apic_set_verbosity); 2771 2772 static int __init lapic_insert_resource(void) 2773 { 2774 if (!apic_phys) 2775 return -1; 2776 2777 /* Put local APIC into the resource map. */ 2778 lapic_resource.start = apic_phys; 2779 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2780 insert_resource(&iomem_resource, &lapic_resource); 2781 2782 return 0; 2783 } 2784 2785 /* 2786 * need call insert after e820__reserve_resources() 2787 * that is using request_resource 2788 */ 2789 late_initcall(lapic_insert_resource); 2790 2791 static int __init apic_set_disabled_cpu_apicid(char *arg) 2792 { 2793 if (!arg || !get_option(&arg, &disabled_cpu_apicid)) 2794 return -EINVAL; 2795 2796 return 0; 2797 } 2798 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); 2799 2800 static int __init apic_set_extnmi(char *arg) 2801 { 2802 if (!arg) 2803 return -EINVAL; 2804 2805 if (!strncmp("all", arg, 3)) 2806 apic_extnmi = APIC_EXTNMI_ALL; 2807 else if (!strncmp("none", arg, 4)) 2808 apic_extnmi = APIC_EXTNMI_NONE; 2809 else if (!strncmp("bsp", arg, 3)) 2810 apic_extnmi = APIC_EXTNMI_BSP; 2811 else { 2812 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg); 2813 return -EINVAL; 2814 } 2815 2816 return 0; 2817 } 2818 early_param("apic_extnmi", apic_set_extnmi); 2819