1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Local APIC handling, local APIC timers 4 * 5 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * 7 * Fixes 8 * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 9 * thanks to Eric Gilmore 10 * and Rolf G. Tews 11 * for testing these extensively. 12 * Maciej W. Rozycki : Various updates and fixes. 13 * Mikael Pettersson : Power Management for UP-APIC. 14 * Pavel Machek and 15 * Mikael Pettersson : PM converted to driver model. 16 */ 17 18 #include <linux/perf_event.h> 19 #include <linux/kernel_stat.h> 20 #include <linux/mc146818rtc.h> 21 #include <linux/acpi_pmtmr.h> 22 #include <linux/clockchips.h> 23 #include <linux/interrupt.h> 24 #include <linux/memblock.h> 25 #include <linux/ftrace.h> 26 #include <linux/ioport.h> 27 #include <linux/export.h> 28 #include <linux/syscore_ops.h> 29 #include <linux/delay.h> 30 #include <linux/timex.h> 31 #include <linux/i8253.h> 32 #include <linux/dmar.h> 33 #include <linux/init.h> 34 #include <linux/cpu.h> 35 #include <linux/dmi.h> 36 #include <linux/smp.h> 37 #include <linux/mm.h> 38 39 #include <asm/trace/irq_vectors.h> 40 #include <asm/irq_remapping.h> 41 #include <asm/perf_event.h> 42 #include <asm/x86_init.h> 43 #include <asm/pgalloc.h> 44 #include <linux/atomic.h> 45 #include <asm/mpspec.h> 46 #include <asm/i8259.h> 47 #include <asm/proto.h> 48 #include <asm/traps.h> 49 #include <asm/apic.h> 50 #include <asm/io_apic.h> 51 #include <asm/desc.h> 52 #include <asm/hpet.h> 53 #include <asm/mtrr.h> 54 #include <asm/time.h> 55 #include <asm/smp.h> 56 #include <asm/mce.h> 57 #include <asm/tsc.h> 58 #include <asm/hypervisor.h> 59 #include <asm/cpu_device_id.h> 60 #include <asm/intel-family.h> 61 #include <asm/irq_regs.h> 62 63 unsigned int num_processors; 64 65 unsigned disabled_cpus; 66 67 /* Processor that is doing the boot up */ 68 unsigned int boot_cpu_physical_apicid __ro_after_init = -1U; 69 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); 70 71 u8 boot_cpu_apic_version __ro_after_init; 72 73 /* 74 * The highest APIC ID seen during enumeration. 75 */ 76 static unsigned int max_physical_apicid; 77 78 /* 79 * Bitmask of physically existing CPUs: 80 */ 81 physid_mask_t phys_cpu_present_map; 82 83 /* 84 * Processor to be disabled specified by kernel parameter 85 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to 86 * avoid undefined behaviour caused by sending INIT from AP to BSP. 87 */ 88 static unsigned int disabled_cpu_apicid __ro_after_init = BAD_APICID; 89 90 /* 91 * This variable controls which CPUs receive external NMIs. By default, 92 * external NMIs are delivered only to the BSP. 93 */ 94 static int apic_extnmi __ro_after_init = APIC_EXTNMI_BSP; 95 96 /* 97 * Map cpu index to physical APIC ID 98 */ 99 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); 100 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID); 101 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX); 102 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 103 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 104 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid); 105 106 #ifdef CONFIG_X86_32 107 108 /* 109 * On x86_32, the mapping between cpu and logical apicid may vary 110 * depending on apic in use. The following early percpu variable is 111 * used for the mapping. This is where the behaviors of x86_64 and 32 112 * actually diverge. Let's keep it ugly for now. 113 */ 114 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID); 115 116 /* Local APIC was disabled by the BIOS and enabled by the kernel */ 117 static int enabled_via_apicbase __ro_after_init; 118 119 /* 120 * Handle interrupt mode configuration register (IMCR). 121 * This register controls whether the interrupt signals 122 * that reach the BSP come from the master PIC or from the 123 * local APIC. Before entering Symmetric I/O Mode, either 124 * the BIOS or the operating system must switch out of 125 * PIC Mode by changing the IMCR. 126 */ 127 static inline void imcr_pic_to_apic(void) 128 { 129 /* select IMCR register */ 130 outb(0x70, 0x22); 131 /* NMI and 8259 INTR go through APIC */ 132 outb(0x01, 0x23); 133 } 134 135 static inline void imcr_apic_to_pic(void) 136 { 137 /* select IMCR register */ 138 outb(0x70, 0x22); 139 /* NMI and 8259 INTR go directly to BSP */ 140 outb(0x00, 0x23); 141 } 142 #endif 143 144 /* 145 * Knob to control our willingness to enable the local APIC. 146 * 147 * +1=force-enable 148 */ 149 static int force_enable_local_apic __initdata; 150 151 /* 152 * APIC command line parameters 153 */ 154 static int __init parse_lapic(char *arg) 155 { 156 if (IS_ENABLED(CONFIG_X86_32) && !arg) 157 force_enable_local_apic = 1; 158 else if (arg && !strncmp(arg, "notscdeadline", 13)) 159 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 160 return 0; 161 } 162 early_param("lapic", parse_lapic); 163 164 #ifdef CONFIG_X86_64 165 static int apic_calibrate_pmtmr __initdata; 166 static __init int setup_apicpmtimer(char *s) 167 { 168 apic_calibrate_pmtmr = 1; 169 notsc_setup(NULL); 170 return 0; 171 } 172 __setup("apicpmtimer", setup_apicpmtimer); 173 #endif 174 175 unsigned long mp_lapic_addr __ro_after_init; 176 int disable_apic __ro_after_init; 177 /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 178 static int disable_apic_timer __initdata; 179 /* Local APIC timer works in C2 */ 180 int local_apic_timer_c2_ok __ro_after_init; 181 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 182 183 /* 184 * Debug level, exported for io_apic.c 185 */ 186 int apic_verbosity __ro_after_init; 187 188 int pic_mode __ro_after_init; 189 190 /* Have we found an MP table */ 191 int smp_found_config __ro_after_init; 192 193 static struct resource lapic_resource = { 194 .name = "Local APIC", 195 .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 196 }; 197 198 unsigned int lapic_timer_period = 0; 199 200 static void apic_pm_activate(void); 201 202 static unsigned long apic_phys __ro_after_init; 203 204 /* 205 * Get the LAPIC version 206 */ 207 static inline int lapic_get_version(void) 208 { 209 return GET_APIC_VERSION(apic_read(APIC_LVR)); 210 } 211 212 /* 213 * Check, if the APIC is integrated or a separate chip 214 */ 215 static inline int lapic_is_integrated(void) 216 { 217 return APIC_INTEGRATED(lapic_get_version()); 218 } 219 220 /* 221 * Check, whether this is a modern or a first generation APIC 222 */ 223 static int modern_apic(void) 224 { 225 /* AMD systems use old APIC versions, so check the CPU */ 226 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 227 boot_cpu_data.x86 >= 0xf) 228 return 1; 229 230 /* Hygon systems use modern APIC */ 231 if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 232 return 1; 233 234 return lapic_get_version() >= 0x14; 235 } 236 237 /* 238 * right after this call apic become NOOP driven 239 * so apic->write/read doesn't do anything 240 */ 241 static void __init apic_disable(void) 242 { 243 pr_info("APIC: switched to apic NOOP\n"); 244 apic = &apic_noop; 245 } 246 247 void native_apic_wait_icr_idle(void) 248 { 249 while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 250 cpu_relax(); 251 } 252 253 u32 native_safe_apic_wait_icr_idle(void) 254 { 255 u32 send_status; 256 int timeout; 257 258 timeout = 0; 259 do { 260 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 261 if (!send_status) 262 break; 263 inc_irq_stat(icr_read_retry_count); 264 udelay(100); 265 } while (timeout++ < 1000); 266 267 return send_status; 268 } 269 270 void native_apic_icr_write(u32 low, u32 id) 271 { 272 unsigned long flags; 273 274 local_irq_save(flags); 275 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 276 apic_write(APIC_ICR, low); 277 local_irq_restore(flags); 278 } 279 280 u64 native_apic_icr_read(void) 281 { 282 u32 icr1, icr2; 283 284 icr2 = apic_read(APIC_ICR2); 285 icr1 = apic_read(APIC_ICR); 286 287 return icr1 | ((u64)icr2 << 32); 288 } 289 290 #ifdef CONFIG_X86_32 291 /** 292 * get_physical_broadcast - Get number of physical broadcast IDs 293 */ 294 int get_physical_broadcast(void) 295 { 296 return modern_apic() ? 0xff : 0xf; 297 } 298 #endif 299 300 /** 301 * lapic_get_maxlvt - get the maximum number of local vector table entries 302 */ 303 int lapic_get_maxlvt(void) 304 { 305 /* 306 * - we always have APIC integrated on 64bit mode 307 * - 82489DXs do not report # of LVT entries 308 */ 309 return lapic_is_integrated() ? GET_APIC_MAXLVT(apic_read(APIC_LVR)) : 2; 310 } 311 312 /* 313 * Local APIC timer 314 */ 315 316 /* Clock divisor */ 317 #define APIC_DIVISOR 16 318 #define TSC_DIVISOR 8 319 320 /* 321 * This function sets up the local APIC timer, with a timeout of 322 * 'clocks' APIC bus clock. During calibration we actually call 323 * this function twice on the boot CPU, once with a bogus timeout 324 * value, second time for real. The other (noncalibrating) CPUs 325 * call this function only once, with the real, calibrated value. 326 * 327 * We do reads before writes even if unnecessary, to get around the 328 * P5 APIC double write bug. 329 */ 330 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 331 { 332 unsigned int lvtt_value, tmp_value; 333 334 lvtt_value = LOCAL_TIMER_VECTOR; 335 if (!oneshot) 336 lvtt_value |= APIC_LVT_TIMER_PERIODIC; 337 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 338 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE; 339 340 if (!lapic_is_integrated()) 341 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 342 343 if (!irqen) 344 lvtt_value |= APIC_LVT_MASKED; 345 346 apic_write(APIC_LVTT, lvtt_value); 347 348 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { 349 /* 350 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, 351 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized. 352 * According to Intel, MFENCE can do the serialization here. 353 */ 354 asm volatile("mfence" : : : "memory"); 355 356 printk_once(KERN_DEBUG "TSC deadline timer enabled\n"); 357 return; 358 } 359 360 /* 361 * Divide PICLK by 16 362 */ 363 tmp_value = apic_read(APIC_TDCR); 364 apic_write(APIC_TDCR, 365 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 366 APIC_TDR_DIV_16); 367 368 if (!oneshot) 369 apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 370 } 371 372 /* 373 * Setup extended LVT, AMD specific 374 * 375 * Software should use the LVT offsets the BIOS provides. The offsets 376 * are determined by the subsystems using it like those for MCE 377 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts 378 * are supported. Beginning with family 10h at least 4 offsets are 379 * available. 380 * 381 * Since the offsets must be consistent for all cores, we keep track 382 * of the LVT offsets in software and reserve the offset for the same 383 * vector also to be used on other cores. An offset is freed by 384 * setting the entry to APIC_EILVT_MASKED. 385 * 386 * If the BIOS is right, there should be no conflicts. Otherwise a 387 * "[Firmware Bug]: ..." error message is generated. However, if 388 * software does not properly determines the offsets, it is not 389 * necessarily a BIOS bug. 390 */ 391 392 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; 393 394 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) 395 { 396 return (old & APIC_EILVT_MASKED) 397 || (new == APIC_EILVT_MASKED) 398 || ((new & ~APIC_EILVT_MASKED) == old); 399 } 400 401 static unsigned int reserve_eilvt_offset(int offset, unsigned int new) 402 { 403 unsigned int rsvd, vector; 404 405 if (offset >= APIC_EILVT_NR_MAX) 406 return ~0; 407 408 rsvd = atomic_read(&eilvt_offsets[offset]); 409 do { 410 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ 411 if (vector && !eilvt_entry_is_changeable(vector, new)) 412 /* may not change if vectors are different */ 413 return rsvd; 414 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); 415 } while (rsvd != new); 416 417 rsvd &= ~APIC_EILVT_MASKED; 418 if (rsvd && rsvd != vector) 419 pr_info("LVT offset %d assigned for vector 0x%02x\n", 420 offset, rsvd); 421 422 return new; 423 } 424 425 /* 426 * If mask=1, the LVT entry does not generate interrupts while mask=0 427 * enables the vector. See also the BKDGs. Must be called with 428 * preemption disabled. 429 */ 430 431 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) 432 { 433 unsigned long reg = APIC_EILVTn(offset); 434 unsigned int new, old, reserved; 435 436 new = (mask << 16) | (msg_type << 8) | vector; 437 old = apic_read(reg); 438 reserved = reserve_eilvt_offset(offset, new); 439 440 if (reserved != new) { 441 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 442 "vector 0x%x, but the register is already in use for " 443 "vector 0x%x on another cpu\n", 444 smp_processor_id(), reg, offset, new, reserved); 445 return -EINVAL; 446 } 447 448 if (!eilvt_entry_is_changeable(old, new)) { 449 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 450 "vector 0x%x, but the register is already in use for " 451 "vector 0x%x on this cpu\n", 452 smp_processor_id(), reg, offset, new, old); 453 return -EBUSY; 454 } 455 456 apic_write(reg, new); 457 458 return 0; 459 } 460 EXPORT_SYMBOL_GPL(setup_APIC_eilvt); 461 462 /* 463 * Program the next event, relative to now 464 */ 465 static int lapic_next_event(unsigned long delta, 466 struct clock_event_device *evt) 467 { 468 apic_write(APIC_TMICT, delta); 469 return 0; 470 } 471 472 static int lapic_next_deadline(unsigned long delta, 473 struct clock_event_device *evt) 474 { 475 u64 tsc; 476 477 tsc = rdtsc(); 478 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); 479 return 0; 480 } 481 482 static int lapic_timer_shutdown(struct clock_event_device *evt) 483 { 484 unsigned int v; 485 486 /* Lapic used as dummy for broadcast ? */ 487 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 488 return 0; 489 490 v = apic_read(APIC_LVTT); 491 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 492 apic_write(APIC_LVTT, v); 493 apic_write(APIC_TMICT, 0); 494 return 0; 495 } 496 497 static inline int 498 lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot) 499 { 500 /* Lapic used as dummy for broadcast ? */ 501 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 502 return 0; 503 504 __setup_APIC_LVTT(lapic_timer_period, oneshot, 1); 505 return 0; 506 } 507 508 static int lapic_timer_set_periodic(struct clock_event_device *evt) 509 { 510 return lapic_timer_set_periodic_oneshot(evt, false); 511 } 512 513 static int lapic_timer_set_oneshot(struct clock_event_device *evt) 514 { 515 return lapic_timer_set_periodic_oneshot(evt, true); 516 } 517 518 /* 519 * Local APIC timer broadcast function 520 */ 521 static void lapic_timer_broadcast(const struct cpumask *mask) 522 { 523 #ifdef CONFIG_SMP 524 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 525 #endif 526 } 527 528 529 /* 530 * The local apic timer can be used for any function which is CPU local. 531 */ 532 static struct clock_event_device lapic_clockevent = { 533 .name = "lapic", 534 .features = CLOCK_EVT_FEAT_PERIODIC | 535 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP 536 | CLOCK_EVT_FEAT_DUMMY, 537 .shift = 32, 538 .set_state_shutdown = lapic_timer_shutdown, 539 .set_state_periodic = lapic_timer_set_periodic, 540 .set_state_oneshot = lapic_timer_set_oneshot, 541 .set_state_oneshot_stopped = lapic_timer_shutdown, 542 .set_next_event = lapic_next_event, 543 .broadcast = lapic_timer_broadcast, 544 .rating = 100, 545 .irq = -1, 546 }; 547 static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 548 549 static u32 hsx_deadline_rev(void) 550 { 551 switch (boot_cpu_data.x86_stepping) { 552 case 0x02: return 0x3a; /* EP */ 553 case 0x04: return 0x0f; /* EX */ 554 } 555 556 return ~0U; 557 } 558 559 static u32 bdx_deadline_rev(void) 560 { 561 switch (boot_cpu_data.x86_stepping) { 562 case 0x02: return 0x00000011; 563 case 0x03: return 0x0700000e; 564 case 0x04: return 0x0f00000c; 565 case 0x05: return 0x0e000003; 566 } 567 568 return ~0U; 569 } 570 571 static u32 skx_deadline_rev(void) 572 { 573 switch (boot_cpu_data.x86_stepping) { 574 case 0x03: return 0x01000136; 575 case 0x04: return 0x02000014; 576 } 577 578 if (boot_cpu_data.x86_stepping > 4) 579 return 0; 580 581 return ~0U; 582 } 583 584 static const struct x86_cpu_id deadline_match[] = { 585 X86_MATCH_INTEL_FAM6_MODEL( HASWELL_X, &hsx_deadline_rev), 586 X86_MATCH_INTEL_FAM6_MODEL( BROADWELL_X, 0x0b000020), 587 X86_MATCH_INTEL_FAM6_MODEL( BROADWELL_D, &bdx_deadline_rev), 588 X86_MATCH_INTEL_FAM6_MODEL( SKYLAKE_X, &skx_deadline_rev), 589 590 X86_MATCH_INTEL_FAM6_MODEL( HASWELL, 0x22), 591 X86_MATCH_INTEL_FAM6_MODEL( HASWELL_L, 0x20), 592 X86_MATCH_INTEL_FAM6_MODEL( HASWELL_G, 0x17), 593 594 X86_MATCH_INTEL_FAM6_MODEL( BROADWELL, 0x25), 595 X86_MATCH_INTEL_FAM6_MODEL( BROADWELL_G, 0x17), 596 597 X86_MATCH_INTEL_FAM6_MODEL( SKYLAKE_L, 0xb2), 598 X86_MATCH_INTEL_FAM6_MODEL( SKYLAKE, 0xb2), 599 600 X86_MATCH_INTEL_FAM6_MODEL( KABYLAKE_L, 0x52), 601 X86_MATCH_INTEL_FAM6_MODEL( KABYLAKE, 0x52), 602 603 {}, 604 }; 605 606 static void apic_check_deadline_errata(void) 607 { 608 const struct x86_cpu_id *m; 609 u32 rev; 610 611 if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER) || 612 boot_cpu_has(X86_FEATURE_HYPERVISOR)) 613 return; 614 615 m = x86_match_cpu(deadline_match); 616 if (!m) 617 return; 618 619 /* 620 * Function pointers will have the MSB set due to address layout, 621 * immediate revisions will not. 622 */ 623 if ((long)m->driver_data < 0) 624 rev = ((u32 (*)(void))(m->driver_data))(); 625 else 626 rev = (u32)m->driver_data; 627 628 if (boot_cpu_data.microcode >= rev) 629 return; 630 631 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 632 pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; " 633 "please update microcode to version: 0x%x (or later)\n", rev); 634 } 635 636 /* 637 * Setup the local APIC timer for this CPU. Copy the initialized values 638 * of the boot CPU and register the clock event in the framework. 639 */ 640 static void setup_APIC_timer(void) 641 { 642 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 643 644 if (this_cpu_has(X86_FEATURE_ARAT)) { 645 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 646 /* Make LAPIC timer preferrable over percpu HPET */ 647 lapic_clockevent.rating = 150; 648 } 649 650 memcpy(levt, &lapic_clockevent, sizeof(*levt)); 651 levt->cpumask = cpumask_of(smp_processor_id()); 652 653 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 654 levt->name = "lapic-deadline"; 655 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | 656 CLOCK_EVT_FEAT_DUMMY); 657 levt->set_next_event = lapic_next_deadline; 658 clockevents_config_and_register(levt, 659 tsc_khz * (1000 / TSC_DIVISOR), 660 0xF, ~0UL); 661 } else 662 clockevents_register_device(levt); 663 } 664 665 /* 666 * Install the updated TSC frequency from recalibration at the TSC 667 * deadline clockevent devices. 668 */ 669 static void __lapic_update_tsc_freq(void *info) 670 { 671 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 672 673 if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 674 return; 675 676 clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR)); 677 } 678 679 void lapic_update_tsc_freq(void) 680 { 681 /* 682 * The clockevent device's ->mult and ->shift can both be 683 * changed. In order to avoid races, schedule the frequency 684 * update code on each CPU. 685 */ 686 on_each_cpu(__lapic_update_tsc_freq, NULL, 0); 687 } 688 689 /* 690 * In this functions we calibrate APIC bus clocks to the external timer. 691 * 692 * We want to do the calibration only once since we want to have local timer 693 * irqs syncron. CPUs connected by the same APIC bus have the very same bus 694 * frequency. 695 * 696 * This was previously done by reading the PIT/HPET and waiting for a wrap 697 * around to find out, that a tick has elapsed. I have a box, where the PIT 698 * readout is broken, so it never gets out of the wait loop again. This was 699 * also reported by others. 700 * 701 * Monitoring the jiffies value is inaccurate and the clockevents 702 * infrastructure allows us to do a simple substitution of the interrupt 703 * handler. 704 * 705 * The calibration routine also uses the pm_timer when possible, as the PIT 706 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 707 * back to normal later in the boot process). 708 */ 709 710 #define LAPIC_CAL_LOOPS (HZ/10) 711 712 static __initdata int lapic_cal_loops = -1; 713 static __initdata long lapic_cal_t1, lapic_cal_t2; 714 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 715 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 716 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 717 718 /* 719 * Temporary interrupt handler and polled calibration function. 720 */ 721 static void __init lapic_cal_handler(struct clock_event_device *dev) 722 { 723 unsigned long long tsc = 0; 724 long tapic = apic_read(APIC_TMCCT); 725 unsigned long pm = acpi_pm_read_early(); 726 727 if (boot_cpu_has(X86_FEATURE_TSC)) 728 tsc = rdtsc(); 729 730 switch (lapic_cal_loops++) { 731 case 0: 732 lapic_cal_t1 = tapic; 733 lapic_cal_tsc1 = tsc; 734 lapic_cal_pm1 = pm; 735 lapic_cal_j1 = jiffies; 736 break; 737 738 case LAPIC_CAL_LOOPS: 739 lapic_cal_t2 = tapic; 740 lapic_cal_tsc2 = tsc; 741 if (pm < lapic_cal_pm1) 742 pm += ACPI_PM_OVRRUN; 743 lapic_cal_pm2 = pm; 744 lapic_cal_j2 = jiffies; 745 break; 746 } 747 } 748 749 static int __init 750 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 751 { 752 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 753 const long pm_thresh = pm_100ms / 100; 754 unsigned long mult; 755 u64 res; 756 757 #ifndef CONFIG_X86_PM_TIMER 758 return -1; 759 #endif 760 761 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 762 763 /* Check, if the PM timer is available */ 764 if (!deltapm) 765 return -1; 766 767 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 768 769 if (deltapm > (pm_100ms - pm_thresh) && 770 deltapm < (pm_100ms + pm_thresh)) { 771 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 772 return 0; 773 } 774 775 res = (((u64)deltapm) * mult) >> 22; 776 do_div(res, 1000000); 777 pr_warn("APIC calibration not consistent " 778 "with PM-Timer: %ldms instead of 100ms\n", (long)res); 779 780 /* Correct the lapic counter value */ 781 res = (((u64)(*delta)) * pm_100ms); 782 do_div(res, deltapm); 783 pr_info("APIC delta adjusted to PM-Timer: " 784 "%lu (%ld)\n", (unsigned long)res, *delta); 785 *delta = (long)res; 786 787 /* Correct the tsc counter value */ 788 if (boot_cpu_has(X86_FEATURE_TSC)) { 789 res = (((u64)(*deltatsc)) * pm_100ms); 790 do_div(res, deltapm); 791 apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 792 "PM-Timer: %lu (%ld)\n", 793 (unsigned long)res, *deltatsc); 794 *deltatsc = (long)res; 795 } 796 797 return 0; 798 } 799 800 static int __init lapic_init_clockevent(void) 801 { 802 if (!lapic_timer_period) 803 return -1; 804 805 /* Calculate the scaled math multiplication factor */ 806 lapic_clockevent.mult = div_sc(lapic_timer_period/APIC_DIVISOR, 807 TICK_NSEC, lapic_clockevent.shift); 808 lapic_clockevent.max_delta_ns = 809 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); 810 lapic_clockevent.max_delta_ticks = 0x7FFFFFFF; 811 lapic_clockevent.min_delta_ns = 812 clockevent_delta2ns(0xF, &lapic_clockevent); 813 lapic_clockevent.min_delta_ticks = 0xF; 814 815 return 0; 816 } 817 818 bool __init apic_needs_pit(void) 819 { 820 /* 821 * If the frequencies are not known, PIT is required for both TSC 822 * and apic timer calibration. 823 */ 824 if (!tsc_khz || !cpu_khz) 825 return true; 826 827 /* Is there an APIC at all or is it disabled? */ 828 if (!boot_cpu_has(X86_FEATURE_APIC) || disable_apic) 829 return true; 830 831 /* 832 * If interrupt delivery mode is legacy PIC or virtual wire without 833 * configuration, the local APIC timer wont be set up. Make sure 834 * that the PIT is initialized. 835 */ 836 if (apic_intr_mode == APIC_PIC || 837 apic_intr_mode == APIC_VIRTUAL_WIRE_NO_CONFIG) 838 return true; 839 840 /* Virt guests may lack ARAT, but still have DEADLINE */ 841 if (!boot_cpu_has(X86_FEATURE_ARAT)) 842 return true; 843 844 /* Deadline timer is based on TSC so no further PIT action required */ 845 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 846 return false; 847 848 /* APIC timer disabled? */ 849 if (disable_apic_timer) 850 return true; 851 /* 852 * The APIC timer frequency is known already, no PIT calibration 853 * required. If unknown, let the PIT be initialized. 854 */ 855 return lapic_timer_period == 0; 856 } 857 858 static int __init calibrate_APIC_clock(void) 859 { 860 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 861 u64 tsc_perj = 0, tsc_start = 0; 862 unsigned long jif_start; 863 unsigned long deltaj; 864 long delta, deltatsc; 865 int pm_referenced = 0; 866 867 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 868 return 0; 869 870 /* 871 * Check if lapic timer has already been calibrated by platform 872 * specific routine, such as tsc calibration code. If so just fill 873 * in the clockevent structure and return. 874 */ 875 if (!lapic_init_clockevent()) { 876 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", 877 lapic_timer_period); 878 /* 879 * Direct calibration methods must have an always running 880 * local APIC timer, no need for broadcast timer. 881 */ 882 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 883 return 0; 884 } 885 886 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 887 "calibrating APIC timer ...\n"); 888 889 /* 890 * There are platforms w/o global clockevent devices. Instead of 891 * making the calibration conditional on that, use a polling based 892 * approach everywhere. 893 */ 894 local_irq_disable(); 895 896 /* 897 * Setup the APIC counter to maximum. There is no way the lapic 898 * can underflow in the 100ms detection time frame 899 */ 900 __setup_APIC_LVTT(0xffffffff, 0, 0); 901 902 /* 903 * Methods to terminate the calibration loop: 904 * 1) Global clockevent if available (jiffies) 905 * 2) TSC if available and frequency is known 906 */ 907 jif_start = READ_ONCE(jiffies); 908 909 if (tsc_khz) { 910 tsc_start = rdtsc(); 911 tsc_perj = div_u64((u64)tsc_khz * 1000, HZ); 912 } 913 914 /* 915 * Enable interrupts so the tick can fire, if a global 916 * clockevent device is available 917 */ 918 local_irq_enable(); 919 920 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) { 921 /* Wait for a tick to elapse */ 922 while (1) { 923 if (tsc_khz) { 924 u64 tsc_now = rdtsc(); 925 if ((tsc_now - tsc_start) >= tsc_perj) { 926 tsc_start += tsc_perj; 927 break; 928 } 929 } else { 930 unsigned long jif_now = READ_ONCE(jiffies); 931 932 if (time_after(jif_now, jif_start)) { 933 jif_start = jif_now; 934 break; 935 } 936 } 937 cpu_relax(); 938 } 939 940 /* Invoke the calibration routine */ 941 local_irq_disable(); 942 lapic_cal_handler(NULL); 943 local_irq_enable(); 944 } 945 946 local_irq_disable(); 947 948 /* Build delta t1-t2 as apic timer counts down */ 949 delta = lapic_cal_t1 - lapic_cal_t2; 950 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 951 952 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 953 954 /* we trust the PM based calibration if possible */ 955 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 956 &delta, &deltatsc); 957 958 lapic_timer_period = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 959 lapic_init_clockevent(); 960 961 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 962 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); 963 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 964 lapic_timer_period); 965 966 if (boot_cpu_has(X86_FEATURE_TSC)) { 967 apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 968 "%ld.%04ld MHz.\n", 969 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 970 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 971 } 972 973 apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 974 "%u.%04u MHz.\n", 975 lapic_timer_period / (1000000 / HZ), 976 lapic_timer_period % (1000000 / HZ)); 977 978 /* 979 * Do a sanity check on the APIC calibration result 980 */ 981 if (lapic_timer_period < (1000000 / HZ)) { 982 local_irq_enable(); 983 pr_warn("APIC frequency too slow, disabling apic timer\n"); 984 return -1; 985 } 986 987 levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 988 989 /* 990 * PM timer calibration failed or not turned on so lets try APIC 991 * timer based calibration, if a global clockevent device is 992 * available. 993 */ 994 if (!pm_referenced && global_clock_event) { 995 apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 996 997 /* 998 * Setup the apic timer manually 999 */ 1000 levt->event_handler = lapic_cal_handler; 1001 lapic_timer_set_periodic(levt); 1002 lapic_cal_loops = -1; 1003 1004 /* Let the interrupts run */ 1005 local_irq_enable(); 1006 1007 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 1008 cpu_relax(); 1009 1010 /* Stop the lapic timer */ 1011 local_irq_disable(); 1012 lapic_timer_shutdown(levt); 1013 1014 /* Jiffies delta */ 1015 deltaj = lapic_cal_j2 - lapic_cal_j1; 1016 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 1017 1018 /* Check, if the jiffies result is consistent */ 1019 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 1020 apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 1021 else 1022 levt->features |= CLOCK_EVT_FEAT_DUMMY; 1023 } 1024 local_irq_enable(); 1025 1026 if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 1027 pr_warn("APIC timer disabled due to verification failure\n"); 1028 return -1; 1029 } 1030 1031 return 0; 1032 } 1033 1034 /* 1035 * Setup the boot APIC 1036 * 1037 * Calibrate and verify the result. 1038 */ 1039 void __init setup_boot_APIC_clock(void) 1040 { 1041 /* 1042 * The local apic timer can be disabled via the kernel 1043 * commandline or from the CPU detection code. Register the lapic 1044 * timer as a dummy clock event source on SMP systems, so the 1045 * broadcast mechanism is used. On UP systems simply ignore it. 1046 */ 1047 if (disable_apic_timer) { 1048 pr_info("Disabling APIC timer\n"); 1049 /* No broadcast on UP ! */ 1050 if (num_possible_cpus() > 1) { 1051 lapic_clockevent.mult = 1; 1052 setup_APIC_timer(); 1053 } 1054 return; 1055 } 1056 1057 if (calibrate_APIC_clock()) { 1058 /* No broadcast on UP ! */ 1059 if (num_possible_cpus() > 1) 1060 setup_APIC_timer(); 1061 return; 1062 } 1063 1064 /* 1065 * If nmi_watchdog is set to IO_APIC, we need the 1066 * PIT/HPET going. Otherwise register lapic as a dummy 1067 * device. 1068 */ 1069 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 1070 1071 /* Setup the lapic or request the broadcast */ 1072 setup_APIC_timer(); 1073 amd_e400_c1e_apic_setup(); 1074 } 1075 1076 void setup_secondary_APIC_clock(void) 1077 { 1078 setup_APIC_timer(); 1079 amd_e400_c1e_apic_setup(); 1080 } 1081 1082 /* 1083 * The guts of the apic timer interrupt 1084 */ 1085 static void local_apic_timer_interrupt(void) 1086 { 1087 struct clock_event_device *evt = this_cpu_ptr(&lapic_events); 1088 1089 /* 1090 * Normally we should not be here till LAPIC has been initialized but 1091 * in some cases like kdump, its possible that there is a pending LAPIC 1092 * timer interrupt from previous kernel's context and is delivered in 1093 * new kernel the moment interrupts are enabled. 1094 * 1095 * Interrupts are enabled early and LAPIC is setup much later, hence 1096 * its possible that when we get here evt->event_handler is NULL. 1097 * Check for event_handler being NULL and discard the interrupt as 1098 * spurious. 1099 */ 1100 if (!evt->event_handler) { 1101 pr_warn("Spurious LAPIC timer interrupt on cpu %d\n", 1102 smp_processor_id()); 1103 /* Switch it off */ 1104 lapic_timer_shutdown(evt); 1105 return; 1106 } 1107 1108 /* 1109 * the NMI deadlock-detector uses this. 1110 */ 1111 inc_irq_stat(apic_timer_irqs); 1112 1113 evt->event_handler(evt); 1114 } 1115 1116 /* 1117 * Local APIC timer interrupt. This is the most natural way for doing 1118 * local interrupts, but local timer interrupts can be emulated by 1119 * broadcast interrupts too. [in case the hw doesn't support APIC timers] 1120 * 1121 * [ if a single-CPU system runs an SMP kernel then we call the local 1122 * interrupt as well. Thus we cannot inline the local irq ... ] 1123 */ 1124 __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) 1125 { 1126 struct pt_regs *old_regs = set_irq_regs(regs); 1127 1128 /* 1129 * NOTE! We'd better ACK the irq immediately, 1130 * because timer handling can be slow. 1131 * 1132 * update_process_times() expects us to have done irq_enter(). 1133 * Besides, if we don't timer interrupts ignore the global 1134 * interrupt lock, which is the WrongThing (tm) to do. 1135 */ 1136 entering_ack_irq(); 1137 trace_local_timer_entry(LOCAL_TIMER_VECTOR); 1138 local_apic_timer_interrupt(); 1139 trace_local_timer_exit(LOCAL_TIMER_VECTOR); 1140 exiting_irq(); 1141 1142 set_irq_regs(old_regs); 1143 } 1144 1145 int setup_profiling_timer(unsigned int multiplier) 1146 { 1147 return -EINVAL; 1148 } 1149 1150 /* 1151 * Local APIC start and shutdown 1152 */ 1153 1154 /** 1155 * clear_local_APIC - shutdown the local APIC 1156 * 1157 * This is called, when a CPU is disabled and before rebooting, so the state of 1158 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 1159 * leftovers during boot. 1160 */ 1161 void clear_local_APIC(void) 1162 { 1163 int maxlvt; 1164 u32 v; 1165 1166 /* APIC hasn't been mapped yet */ 1167 if (!x2apic_mode && !apic_phys) 1168 return; 1169 1170 maxlvt = lapic_get_maxlvt(); 1171 /* 1172 * Masking an LVT entry can trigger a local APIC error 1173 * if the vector is zero. Mask LVTERR first to prevent this. 1174 */ 1175 if (maxlvt >= 3) { 1176 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 1177 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 1178 } 1179 /* 1180 * Careful: we have to set masks only first to deassert 1181 * any level-triggered sources. 1182 */ 1183 v = apic_read(APIC_LVTT); 1184 apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 1185 v = apic_read(APIC_LVT0); 1186 apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 1187 v = apic_read(APIC_LVT1); 1188 apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 1189 if (maxlvt >= 4) { 1190 v = apic_read(APIC_LVTPC); 1191 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 1192 } 1193 1194 /* lets not touch this if we didn't frob it */ 1195 #ifdef CONFIG_X86_THERMAL_VECTOR 1196 if (maxlvt >= 5) { 1197 v = apic_read(APIC_LVTTHMR); 1198 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 1199 } 1200 #endif 1201 #ifdef CONFIG_X86_MCE_INTEL 1202 if (maxlvt >= 6) { 1203 v = apic_read(APIC_LVTCMCI); 1204 if (!(v & APIC_LVT_MASKED)) 1205 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 1206 } 1207 #endif 1208 1209 /* 1210 * Clean APIC state for other OSs: 1211 */ 1212 apic_write(APIC_LVTT, APIC_LVT_MASKED); 1213 apic_write(APIC_LVT0, APIC_LVT_MASKED); 1214 apic_write(APIC_LVT1, APIC_LVT_MASKED); 1215 if (maxlvt >= 3) 1216 apic_write(APIC_LVTERR, APIC_LVT_MASKED); 1217 if (maxlvt >= 4) 1218 apic_write(APIC_LVTPC, APIC_LVT_MASKED); 1219 1220 /* Integrated APIC (!82489DX) ? */ 1221 if (lapic_is_integrated()) { 1222 if (maxlvt > 3) 1223 /* Clear ESR due to Pentium errata 3AP and 11AP */ 1224 apic_write(APIC_ESR, 0); 1225 apic_read(APIC_ESR); 1226 } 1227 } 1228 1229 /** 1230 * apic_soft_disable - Clears and software disables the local APIC on hotplug 1231 * 1232 * Contrary to disable_local_APIC() this does not touch the enable bit in 1233 * MSR_IA32_APICBASE. Clearing that bit on systems based on the 3 wire APIC 1234 * bus would require a hardware reset as the APIC would lose track of bus 1235 * arbitration. On systems with FSB delivery APICBASE could be disabled, 1236 * but it has to be guaranteed that no interrupt is sent to the APIC while 1237 * in that state and it's not clear from the SDM whether it still responds 1238 * to INIT/SIPI messages. Stay on the safe side and use software disable. 1239 */ 1240 void apic_soft_disable(void) 1241 { 1242 u32 value; 1243 1244 clear_local_APIC(); 1245 1246 /* Soft disable APIC (implies clearing of registers for 82489DX!). */ 1247 value = apic_read(APIC_SPIV); 1248 value &= ~APIC_SPIV_APIC_ENABLED; 1249 apic_write(APIC_SPIV, value); 1250 } 1251 1252 /** 1253 * disable_local_APIC - clear and disable the local APIC 1254 */ 1255 void disable_local_APIC(void) 1256 { 1257 /* APIC hasn't been mapped yet */ 1258 if (!x2apic_mode && !apic_phys) 1259 return; 1260 1261 apic_soft_disable(); 1262 1263 #ifdef CONFIG_X86_32 1264 /* 1265 * When LAPIC was disabled by the BIOS and enabled by the kernel, 1266 * restore the disabled state. 1267 */ 1268 if (enabled_via_apicbase) { 1269 unsigned int l, h; 1270 1271 rdmsr(MSR_IA32_APICBASE, l, h); 1272 l &= ~MSR_IA32_APICBASE_ENABLE; 1273 wrmsr(MSR_IA32_APICBASE, l, h); 1274 } 1275 #endif 1276 } 1277 1278 /* 1279 * If Linux enabled the LAPIC against the BIOS default disable it down before 1280 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 1281 * not power-off. Additionally clear all LVT entries before disable_local_APIC 1282 * for the case where Linux didn't enable the LAPIC. 1283 */ 1284 void lapic_shutdown(void) 1285 { 1286 unsigned long flags; 1287 1288 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) 1289 return; 1290 1291 local_irq_save(flags); 1292 1293 #ifdef CONFIG_X86_32 1294 if (!enabled_via_apicbase) 1295 clear_local_APIC(); 1296 else 1297 #endif 1298 disable_local_APIC(); 1299 1300 1301 local_irq_restore(flags); 1302 } 1303 1304 /** 1305 * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1306 */ 1307 void __init sync_Arb_IDs(void) 1308 { 1309 /* 1310 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1311 * needed on AMD. 1312 */ 1313 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1314 return; 1315 1316 /* 1317 * Wait for idle. 1318 */ 1319 apic_wait_icr_idle(); 1320 1321 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1322 apic_write(APIC_ICR, APIC_DEST_ALLINC | 1323 APIC_INT_LEVELTRIG | APIC_DM_INIT); 1324 } 1325 1326 enum apic_intr_mode_id apic_intr_mode __ro_after_init; 1327 1328 static int __init __apic_intr_mode_select(void) 1329 { 1330 /* Check kernel option */ 1331 if (disable_apic) { 1332 pr_info("APIC disabled via kernel command line\n"); 1333 return APIC_PIC; 1334 } 1335 1336 /* Check BIOS */ 1337 #ifdef CONFIG_X86_64 1338 /* On 64-bit, the APIC must be integrated, Check local APIC only */ 1339 if (!boot_cpu_has(X86_FEATURE_APIC)) { 1340 disable_apic = 1; 1341 pr_info("APIC disabled by BIOS\n"); 1342 return APIC_PIC; 1343 } 1344 #else 1345 /* On 32-bit, the APIC may be integrated APIC or 82489DX */ 1346 1347 /* Neither 82489DX nor integrated APIC ? */ 1348 if (!boot_cpu_has(X86_FEATURE_APIC) && !smp_found_config) { 1349 disable_apic = 1; 1350 return APIC_PIC; 1351 } 1352 1353 /* If the BIOS pretends there is an integrated APIC ? */ 1354 if (!boot_cpu_has(X86_FEATURE_APIC) && 1355 APIC_INTEGRATED(boot_cpu_apic_version)) { 1356 disable_apic = 1; 1357 pr_err(FW_BUG "Local APIC %d not detected, force emulation\n", 1358 boot_cpu_physical_apicid); 1359 return APIC_PIC; 1360 } 1361 #endif 1362 1363 /* Check MP table or ACPI MADT configuration */ 1364 if (!smp_found_config) { 1365 disable_ioapic_support(); 1366 if (!acpi_lapic) { 1367 pr_info("APIC: ACPI MADT or MP tables are not detected\n"); 1368 return APIC_VIRTUAL_WIRE_NO_CONFIG; 1369 } 1370 return APIC_VIRTUAL_WIRE; 1371 } 1372 1373 #ifdef CONFIG_SMP 1374 /* If SMP should be disabled, then really disable it! */ 1375 if (!setup_max_cpus) { 1376 pr_info("APIC: SMP mode deactivated\n"); 1377 return APIC_SYMMETRIC_IO_NO_ROUTING; 1378 } 1379 1380 if (read_apic_id() != boot_cpu_physical_apicid) { 1381 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1382 read_apic_id(), boot_cpu_physical_apicid); 1383 /* Or can we switch back to PIC here? */ 1384 } 1385 #endif 1386 1387 return APIC_SYMMETRIC_IO; 1388 } 1389 1390 /* Select the interrupt delivery mode for the BSP */ 1391 void __init apic_intr_mode_select(void) 1392 { 1393 apic_intr_mode = __apic_intr_mode_select(); 1394 } 1395 1396 /* 1397 * An initial setup of the virtual wire mode. 1398 */ 1399 void __init init_bsp_APIC(void) 1400 { 1401 unsigned int value; 1402 1403 /* 1404 * Don't do the setup now if we have a SMP BIOS as the 1405 * through-I/O-APIC virtual wire mode might be active. 1406 */ 1407 if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC)) 1408 return; 1409 1410 /* 1411 * Do not trust the local APIC being empty at bootup. 1412 */ 1413 clear_local_APIC(); 1414 1415 /* 1416 * Enable APIC. 1417 */ 1418 value = apic_read(APIC_SPIV); 1419 value &= ~APIC_VECTOR_MASK; 1420 value |= APIC_SPIV_APIC_ENABLED; 1421 1422 #ifdef CONFIG_X86_32 1423 /* This bit is reserved on P4/Xeon and should be cleared */ 1424 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1425 (boot_cpu_data.x86 == 15)) 1426 value &= ~APIC_SPIV_FOCUS_DISABLED; 1427 else 1428 #endif 1429 value |= APIC_SPIV_FOCUS_DISABLED; 1430 value |= SPURIOUS_APIC_VECTOR; 1431 apic_write(APIC_SPIV, value); 1432 1433 /* 1434 * Set up the virtual wire mode. 1435 */ 1436 apic_write(APIC_LVT0, APIC_DM_EXTINT); 1437 value = APIC_DM_NMI; 1438 if (!lapic_is_integrated()) /* 82489DX */ 1439 value |= APIC_LVT_LEVEL_TRIGGER; 1440 if (apic_extnmi == APIC_EXTNMI_NONE) 1441 value |= APIC_LVT_MASKED; 1442 apic_write(APIC_LVT1, value); 1443 } 1444 1445 static void __init apic_bsp_setup(bool upmode); 1446 1447 /* Init the interrupt delivery mode for the BSP */ 1448 void __init apic_intr_mode_init(void) 1449 { 1450 bool upmode = IS_ENABLED(CONFIG_UP_LATE_INIT); 1451 1452 switch (apic_intr_mode) { 1453 case APIC_PIC: 1454 pr_info("APIC: Keep in PIC mode(8259)\n"); 1455 return; 1456 case APIC_VIRTUAL_WIRE: 1457 pr_info("APIC: Switch to virtual wire mode setup\n"); 1458 default_setup_apic_routing(); 1459 break; 1460 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1461 pr_info("APIC: Switch to virtual wire mode setup with no configuration\n"); 1462 upmode = true; 1463 default_setup_apic_routing(); 1464 break; 1465 case APIC_SYMMETRIC_IO: 1466 pr_info("APIC: Switch to symmetric I/O mode setup\n"); 1467 default_setup_apic_routing(); 1468 break; 1469 case APIC_SYMMETRIC_IO_NO_ROUTING: 1470 pr_info("APIC: Switch to symmetric I/O mode setup in no SMP routine\n"); 1471 break; 1472 } 1473 1474 apic_bsp_setup(upmode); 1475 } 1476 1477 static void lapic_setup_esr(void) 1478 { 1479 unsigned int oldvalue, value, maxlvt; 1480 1481 if (!lapic_is_integrated()) { 1482 pr_info("No ESR for 82489DX.\n"); 1483 return; 1484 } 1485 1486 if (apic->disable_esr) { 1487 /* 1488 * Something untraceable is creating bad interrupts on 1489 * secondary quads ... for the moment, just leave the 1490 * ESR disabled - we can't do anything useful with the 1491 * errors anyway - mbligh 1492 */ 1493 pr_info("Leaving ESR disabled.\n"); 1494 return; 1495 } 1496 1497 maxlvt = lapic_get_maxlvt(); 1498 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1499 apic_write(APIC_ESR, 0); 1500 oldvalue = apic_read(APIC_ESR); 1501 1502 /* enables sending errors */ 1503 value = ERROR_APIC_VECTOR; 1504 apic_write(APIC_LVTERR, value); 1505 1506 /* 1507 * spec says clear errors after enabling vector. 1508 */ 1509 if (maxlvt > 3) 1510 apic_write(APIC_ESR, 0); 1511 value = apic_read(APIC_ESR); 1512 if (value != oldvalue) 1513 apic_printk(APIC_VERBOSE, "ESR value before enabling " 1514 "vector: 0x%08x after: 0x%08x\n", 1515 oldvalue, value); 1516 } 1517 1518 #define APIC_IR_REGS APIC_ISR_NR 1519 #define APIC_IR_BITS (APIC_IR_REGS * 32) 1520 #define APIC_IR_MAPSIZE (APIC_IR_BITS / BITS_PER_LONG) 1521 1522 union apic_ir { 1523 unsigned long map[APIC_IR_MAPSIZE]; 1524 u32 regs[APIC_IR_REGS]; 1525 }; 1526 1527 static bool apic_check_and_ack(union apic_ir *irr, union apic_ir *isr) 1528 { 1529 int i, bit; 1530 1531 /* Read the IRRs */ 1532 for (i = 0; i < APIC_IR_REGS; i++) 1533 irr->regs[i] = apic_read(APIC_IRR + i * 0x10); 1534 1535 /* Read the ISRs */ 1536 for (i = 0; i < APIC_IR_REGS; i++) 1537 isr->regs[i] = apic_read(APIC_ISR + i * 0x10); 1538 1539 /* 1540 * If the ISR map is not empty. ACK the APIC and run another round 1541 * to verify whether a pending IRR has been unblocked and turned 1542 * into a ISR. 1543 */ 1544 if (!bitmap_empty(isr->map, APIC_IR_BITS)) { 1545 /* 1546 * There can be multiple ISR bits set when a high priority 1547 * interrupt preempted a lower priority one. Issue an ACK 1548 * per set bit. 1549 */ 1550 for_each_set_bit(bit, isr->map, APIC_IR_BITS) 1551 ack_APIC_irq(); 1552 return true; 1553 } 1554 1555 return !bitmap_empty(irr->map, APIC_IR_BITS); 1556 } 1557 1558 /* 1559 * After a crash, we no longer service the interrupts and a pending 1560 * interrupt from previous kernel might still have ISR bit set. 1561 * 1562 * Most probably by now the CPU has serviced that pending interrupt and it 1563 * might not have done the ack_APIC_irq() because it thought, interrupt 1564 * came from i8259 as ExtInt. LAPIC did not get EOI so it does not clear 1565 * the ISR bit and cpu thinks it has already serivced the interrupt. Hence 1566 * a vector might get locked. It was noticed for timer irq (vector 1567 * 0x31). Issue an extra EOI to clear ISR. 1568 * 1569 * If there are pending IRR bits they turn into ISR bits after a higher 1570 * priority ISR bit has been acked. 1571 */ 1572 static void apic_pending_intr_clear(void) 1573 { 1574 union apic_ir irr, isr; 1575 unsigned int i; 1576 1577 /* 512 loops are way oversized and give the APIC a chance to obey. */ 1578 for (i = 0; i < 512; i++) { 1579 if (!apic_check_and_ack(&irr, &isr)) 1580 return; 1581 } 1582 /* Dump the IRR/ISR content if that failed */ 1583 pr_warn("APIC: Stale IRR: %256pb ISR: %256pb\n", irr.map, isr.map); 1584 } 1585 1586 /** 1587 * setup_local_APIC - setup the local APIC 1588 * 1589 * Used to setup local APIC while initializing BSP or bringing up APs. 1590 * Always called with preemption disabled. 1591 */ 1592 static void setup_local_APIC(void) 1593 { 1594 int cpu = smp_processor_id(); 1595 unsigned int value; 1596 1597 if (disable_apic) { 1598 disable_ioapic_support(); 1599 return; 1600 } 1601 1602 /* 1603 * If this comes from kexec/kcrash the APIC might be enabled in 1604 * SPIV. Soft disable it before doing further initialization. 1605 */ 1606 value = apic_read(APIC_SPIV); 1607 value &= ~APIC_SPIV_APIC_ENABLED; 1608 apic_write(APIC_SPIV, value); 1609 1610 #ifdef CONFIG_X86_32 1611 /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1612 if (lapic_is_integrated() && apic->disable_esr) { 1613 apic_write(APIC_ESR, 0); 1614 apic_write(APIC_ESR, 0); 1615 apic_write(APIC_ESR, 0); 1616 apic_write(APIC_ESR, 0); 1617 } 1618 #endif 1619 /* 1620 * Double-check whether this APIC is really registered. 1621 * This is meaningless in clustered apic mode, so we skip it. 1622 */ 1623 BUG_ON(!apic->apic_id_registered()); 1624 1625 /* 1626 * Intel recommends to set DFR, LDR and TPR before enabling 1627 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1628 * document number 292116). So here it goes... 1629 */ 1630 apic->init_apic_ldr(); 1631 1632 #ifdef CONFIG_X86_32 1633 if (apic->dest_logical) { 1634 int logical_apicid, ldr_apicid; 1635 1636 /* 1637 * APIC LDR is initialized. If logical_apicid mapping was 1638 * initialized during get_smp_config(), make sure it matches 1639 * the actual value. 1640 */ 1641 logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu); 1642 ldr_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 1643 if (logical_apicid != BAD_APICID) 1644 WARN_ON(logical_apicid != ldr_apicid); 1645 /* Always use the value from LDR. */ 1646 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = ldr_apicid; 1647 } 1648 #endif 1649 1650 /* 1651 * Set Task Priority to 'accept all except vectors 0-31'. An APIC 1652 * vector in the 16-31 range could be delivered if TPR == 0, but we 1653 * would think it's an exception and terrible things will happen. We 1654 * never change this later on. 1655 */ 1656 value = apic_read(APIC_TASKPRI); 1657 value &= ~APIC_TPRI_MASK; 1658 value |= 0x10; 1659 apic_write(APIC_TASKPRI, value); 1660 1661 /* Clear eventually stale ISR/IRR bits */ 1662 apic_pending_intr_clear(); 1663 1664 /* 1665 * Now that we are all set up, enable the APIC 1666 */ 1667 value = apic_read(APIC_SPIV); 1668 value &= ~APIC_VECTOR_MASK; 1669 /* 1670 * Enable APIC 1671 */ 1672 value |= APIC_SPIV_APIC_ENABLED; 1673 1674 #ifdef CONFIG_X86_32 1675 /* 1676 * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1677 * certain networking cards. If high frequency interrupts are 1678 * happening on a particular IOAPIC pin, plus the IOAPIC routing 1679 * entry is masked/unmasked at a high rate as well then sooner or 1680 * later IOAPIC line gets 'stuck', no more interrupts are received 1681 * from the device. If focus CPU is disabled then the hang goes 1682 * away, oh well :-( 1683 * 1684 * [ This bug can be reproduced easily with a level-triggered 1685 * PCI Ne2000 networking cards and PII/PIII processors, dual 1686 * BX chipset. ] 1687 */ 1688 /* 1689 * Actually disabling the focus CPU check just makes the hang less 1690 * frequent as it makes the interrupt distributon model be more 1691 * like LRU than MRU (the short-term load is more even across CPUs). 1692 */ 1693 1694 /* 1695 * - enable focus processor (bit==0) 1696 * - 64bit mode always use processor focus 1697 * so no need to set it 1698 */ 1699 value &= ~APIC_SPIV_FOCUS_DISABLED; 1700 #endif 1701 1702 /* 1703 * Set spurious IRQ vector 1704 */ 1705 value |= SPURIOUS_APIC_VECTOR; 1706 apic_write(APIC_SPIV, value); 1707 1708 perf_events_lapic_init(); 1709 1710 /* 1711 * Set up LVT0, LVT1: 1712 * 1713 * set up through-local-APIC on the boot CPU's LINT0. This is not 1714 * strictly necessary in pure symmetric-IO mode, but sometimes 1715 * we delegate interrupts to the 8259A. 1716 */ 1717 /* 1718 * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1719 */ 1720 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 1721 if (!cpu && (pic_mode || !value || skip_ioapic_setup)) { 1722 value = APIC_DM_EXTINT; 1723 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); 1724 } else { 1725 value = APIC_DM_EXTINT | APIC_LVT_MASKED; 1726 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); 1727 } 1728 apic_write(APIC_LVT0, value); 1729 1730 /* 1731 * Only the BSP sees the LINT1 NMI signal by default. This can be 1732 * modified by apic_extnmi= boot option. 1733 */ 1734 if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) || 1735 apic_extnmi == APIC_EXTNMI_ALL) 1736 value = APIC_DM_NMI; 1737 else 1738 value = APIC_DM_NMI | APIC_LVT_MASKED; 1739 1740 /* Is 82489DX ? */ 1741 if (!lapic_is_integrated()) 1742 value |= APIC_LVT_LEVEL_TRIGGER; 1743 apic_write(APIC_LVT1, value); 1744 1745 #ifdef CONFIG_X86_MCE_INTEL 1746 /* Recheck CMCI information after local APIC is up on CPU #0 */ 1747 if (!cpu) 1748 cmci_recheck(); 1749 #endif 1750 } 1751 1752 static void end_local_APIC_setup(void) 1753 { 1754 lapic_setup_esr(); 1755 1756 #ifdef CONFIG_X86_32 1757 { 1758 unsigned int value; 1759 /* Disable the local apic timer */ 1760 value = apic_read(APIC_LVTT); 1761 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1762 apic_write(APIC_LVTT, value); 1763 } 1764 #endif 1765 1766 apic_pm_activate(); 1767 } 1768 1769 /* 1770 * APIC setup function for application processors. Called from smpboot.c 1771 */ 1772 void apic_ap_setup(void) 1773 { 1774 setup_local_APIC(); 1775 end_local_APIC_setup(); 1776 } 1777 1778 #ifdef CONFIG_X86_X2APIC 1779 int x2apic_mode; 1780 1781 enum { 1782 X2APIC_OFF, 1783 X2APIC_ON, 1784 X2APIC_DISABLED, 1785 }; 1786 static int x2apic_state; 1787 1788 static void __x2apic_disable(void) 1789 { 1790 u64 msr; 1791 1792 if (!boot_cpu_has(X86_FEATURE_APIC)) 1793 return; 1794 1795 rdmsrl(MSR_IA32_APICBASE, msr); 1796 if (!(msr & X2APIC_ENABLE)) 1797 return; 1798 /* Disable xapic and x2apic first and then reenable xapic mode */ 1799 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); 1800 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); 1801 printk_once(KERN_INFO "x2apic disabled\n"); 1802 } 1803 1804 static void __x2apic_enable(void) 1805 { 1806 u64 msr; 1807 1808 rdmsrl(MSR_IA32_APICBASE, msr); 1809 if (msr & X2APIC_ENABLE) 1810 return; 1811 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); 1812 printk_once(KERN_INFO "x2apic enabled\n"); 1813 } 1814 1815 static int __init setup_nox2apic(char *str) 1816 { 1817 if (x2apic_enabled()) { 1818 int apicid = native_apic_msr_read(APIC_ID); 1819 1820 if (apicid >= 255) { 1821 pr_warn("Apicid: %08x, cannot enforce nox2apic\n", 1822 apicid); 1823 return 0; 1824 } 1825 pr_warn("x2apic already enabled.\n"); 1826 __x2apic_disable(); 1827 } 1828 setup_clear_cpu_cap(X86_FEATURE_X2APIC); 1829 x2apic_state = X2APIC_DISABLED; 1830 x2apic_mode = 0; 1831 return 0; 1832 } 1833 early_param("nox2apic", setup_nox2apic); 1834 1835 /* Called from cpu_init() to enable x2apic on (secondary) cpus */ 1836 void x2apic_setup(void) 1837 { 1838 /* 1839 * If x2apic is not in ON state, disable it if already enabled 1840 * from BIOS. 1841 */ 1842 if (x2apic_state != X2APIC_ON) { 1843 __x2apic_disable(); 1844 return; 1845 } 1846 __x2apic_enable(); 1847 } 1848 1849 static __init void x2apic_disable(void) 1850 { 1851 u32 x2apic_id, state = x2apic_state; 1852 1853 x2apic_mode = 0; 1854 x2apic_state = X2APIC_DISABLED; 1855 1856 if (state != X2APIC_ON) 1857 return; 1858 1859 x2apic_id = read_apic_id(); 1860 if (x2apic_id >= 255) 1861 panic("Cannot disable x2apic, id: %08x\n", x2apic_id); 1862 1863 __x2apic_disable(); 1864 register_lapic_address(mp_lapic_addr); 1865 } 1866 1867 static __init void x2apic_enable(void) 1868 { 1869 if (x2apic_state != X2APIC_OFF) 1870 return; 1871 1872 x2apic_mode = 1; 1873 x2apic_state = X2APIC_ON; 1874 __x2apic_enable(); 1875 } 1876 1877 static __init void try_to_enable_x2apic(int remap_mode) 1878 { 1879 if (x2apic_state == X2APIC_DISABLED) 1880 return; 1881 1882 if (remap_mode != IRQ_REMAP_X2APIC_MODE) { 1883 /* IR is required if there is APIC ID > 255 even when running 1884 * under KVM 1885 */ 1886 if (max_physical_apicid > 255 || 1887 !x86_init.hyper.x2apic_available()) { 1888 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n"); 1889 x2apic_disable(); 1890 return; 1891 } 1892 1893 /* 1894 * without IR all CPUs can be addressed by IOAPIC/MSI 1895 * only in physical mode 1896 */ 1897 x2apic_phys = 1; 1898 } 1899 x2apic_enable(); 1900 } 1901 1902 void __init check_x2apic(void) 1903 { 1904 if (x2apic_enabled()) { 1905 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n"); 1906 x2apic_mode = 1; 1907 x2apic_state = X2APIC_ON; 1908 } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) { 1909 x2apic_state = X2APIC_DISABLED; 1910 } 1911 } 1912 #else /* CONFIG_X86_X2APIC */ 1913 static int __init validate_x2apic(void) 1914 { 1915 if (!apic_is_x2apic_enabled()) 1916 return 0; 1917 /* 1918 * Checkme: Can we simply turn off x2apic here instead of panic? 1919 */ 1920 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n"); 1921 } 1922 early_initcall(validate_x2apic); 1923 1924 static inline void try_to_enable_x2apic(int remap_mode) { } 1925 static inline void __x2apic_enable(void) { } 1926 #endif /* !CONFIG_X86_X2APIC */ 1927 1928 void __init enable_IR_x2apic(void) 1929 { 1930 unsigned long flags; 1931 int ret, ir_stat; 1932 1933 if (skip_ioapic_setup) { 1934 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n"); 1935 return; 1936 } 1937 1938 ir_stat = irq_remapping_prepare(); 1939 if (ir_stat < 0 && !x2apic_supported()) 1940 return; 1941 1942 ret = save_ioapic_entries(); 1943 if (ret) { 1944 pr_info("Saving IO-APIC state failed: %d\n", ret); 1945 return; 1946 } 1947 1948 local_irq_save(flags); 1949 legacy_pic->mask_all(); 1950 mask_ioapic_entries(); 1951 1952 /* If irq_remapping_prepare() succeeded, try to enable it */ 1953 if (ir_stat >= 0) 1954 ir_stat = irq_remapping_enable(); 1955 /* ir_stat contains the remap mode or an error code */ 1956 try_to_enable_x2apic(ir_stat); 1957 1958 if (ir_stat < 0) 1959 restore_ioapic_entries(); 1960 legacy_pic->restore_mask(); 1961 local_irq_restore(flags); 1962 } 1963 1964 #ifdef CONFIG_X86_64 1965 /* 1966 * Detect and enable local APICs on non-SMP boards. 1967 * Original code written by Keir Fraser. 1968 * On AMD64 we trust the BIOS - if it says no APIC it is likely 1969 * not correctly set up (usually the APIC timer won't work etc.) 1970 */ 1971 static int __init detect_init_APIC(void) 1972 { 1973 if (!boot_cpu_has(X86_FEATURE_APIC)) { 1974 pr_info("No local APIC present\n"); 1975 return -1; 1976 } 1977 1978 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1979 return 0; 1980 } 1981 #else 1982 1983 static int __init apic_verify(void) 1984 { 1985 u32 features, h, l; 1986 1987 /* 1988 * The APIC feature bit should now be enabled 1989 * in `cpuid' 1990 */ 1991 features = cpuid_edx(1); 1992 if (!(features & (1 << X86_FEATURE_APIC))) { 1993 pr_warn("Could not enable APIC!\n"); 1994 return -1; 1995 } 1996 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 1997 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1998 1999 /* The BIOS may have set up the APIC at some other address */ 2000 if (boot_cpu_data.x86 >= 6) { 2001 rdmsr(MSR_IA32_APICBASE, l, h); 2002 if (l & MSR_IA32_APICBASE_ENABLE) 2003 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 2004 } 2005 2006 pr_info("Found and enabled local APIC!\n"); 2007 return 0; 2008 } 2009 2010 int __init apic_force_enable(unsigned long addr) 2011 { 2012 u32 h, l; 2013 2014 if (disable_apic) 2015 return -1; 2016 2017 /* 2018 * Some BIOSes disable the local APIC in the APIC_BASE 2019 * MSR. This can only be done in software for Intel P6 or later 2020 * and AMD K7 (Model > 1) or later. 2021 */ 2022 if (boot_cpu_data.x86 >= 6) { 2023 rdmsr(MSR_IA32_APICBASE, l, h); 2024 if (!(l & MSR_IA32_APICBASE_ENABLE)) { 2025 pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 2026 l &= ~MSR_IA32_APICBASE_BASE; 2027 l |= MSR_IA32_APICBASE_ENABLE | addr; 2028 wrmsr(MSR_IA32_APICBASE, l, h); 2029 enabled_via_apicbase = 1; 2030 } 2031 } 2032 return apic_verify(); 2033 } 2034 2035 /* 2036 * Detect and initialize APIC 2037 */ 2038 static int __init detect_init_APIC(void) 2039 { 2040 /* Disabled by kernel option? */ 2041 if (disable_apic) 2042 return -1; 2043 2044 switch (boot_cpu_data.x86_vendor) { 2045 case X86_VENDOR_AMD: 2046 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 2047 (boot_cpu_data.x86 >= 15)) 2048 break; 2049 goto no_apic; 2050 case X86_VENDOR_HYGON: 2051 break; 2052 case X86_VENDOR_INTEL: 2053 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 2054 (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC))) 2055 break; 2056 goto no_apic; 2057 default: 2058 goto no_apic; 2059 } 2060 2061 if (!boot_cpu_has(X86_FEATURE_APIC)) { 2062 /* 2063 * Over-ride BIOS and try to enable the local APIC only if 2064 * "lapic" specified. 2065 */ 2066 if (!force_enable_local_apic) { 2067 pr_info("Local APIC disabled by BIOS -- " 2068 "you can enable it with \"lapic\"\n"); 2069 return -1; 2070 } 2071 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) 2072 return -1; 2073 } else { 2074 if (apic_verify()) 2075 return -1; 2076 } 2077 2078 apic_pm_activate(); 2079 2080 return 0; 2081 2082 no_apic: 2083 pr_info("No local APIC present or hardware disabled\n"); 2084 return -1; 2085 } 2086 #endif 2087 2088 /** 2089 * init_apic_mappings - initialize APIC mappings 2090 */ 2091 void __init init_apic_mappings(void) 2092 { 2093 unsigned int new_apicid; 2094 2095 apic_check_deadline_errata(); 2096 2097 if (x2apic_mode) { 2098 boot_cpu_physical_apicid = read_apic_id(); 2099 return; 2100 } 2101 2102 /* If no local APIC can be found return early */ 2103 if (!smp_found_config && detect_init_APIC()) { 2104 /* lets NOP'ify apic operations */ 2105 pr_info("APIC: disable apic facility\n"); 2106 apic_disable(); 2107 } else { 2108 apic_phys = mp_lapic_addr; 2109 2110 /* 2111 * If the system has ACPI MADT tables or MP info, the LAPIC 2112 * address is already registered. 2113 */ 2114 if (!acpi_lapic && !smp_found_config) 2115 register_lapic_address(apic_phys); 2116 } 2117 2118 /* 2119 * Fetch the APIC ID of the BSP in case we have a 2120 * default configuration (or the MP table is broken). 2121 */ 2122 new_apicid = read_apic_id(); 2123 if (boot_cpu_physical_apicid != new_apicid) { 2124 boot_cpu_physical_apicid = new_apicid; 2125 /* 2126 * yeah -- we lie about apic_version 2127 * in case if apic was disabled via boot option 2128 * but it's not a problem for SMP compiled kernel 2129 * since apic_intr_mode_select is prepared for such 2130 * a case and disable smp mode 2131 */ 2132 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 2133 } 2134 } 2135 2136 void __init register_lapic_address(unsigned long address) 2137 { 2138 mp_lapic_addr = address; 2139 2140 if (!x2apic_mode) { 2141 set_fixmap_nocache(FIX_APIC_BASE, address); 2142 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 2143 APIC_BASE, address); 2144 } 2145 if (boot_cpu_physical_apicid == -1U) { 2146 boot_cpu_physical_apicid = read_apic_id(); 2147 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 2148 } 2149 } 2150 2151 /* 2152 * Local APIC interrupts 2153 */ 2154 2155 /* 2156 * This interrupt should _never_ happen with our APIC/SMP architecture 2157 */ 2158 __visible void __irq_entry smp_spurious_interrupt(struct pt_regs *regs) 2159 { 2160 u8 vector = ~regs->orig_ax; 2161 u32 v; 2162 2163 entering_irq(); 2164 trace_spurious_apic_entry(vector); 2165 2166 inc_irq_stat(irq_spurious_count); 2167 2168 /* 2169 * If this is a spurious interrupt then do not acknowledge 2170 */ 2171 if (vector == SPURIOUS_APIC_VECTOR) { 2172 /* See SDM vol 3 */ 2173 pr_info("Spurious APIC interrupt (vector 0xFF) on CPU#%d, should never happen.\n", 2174 smp_processor_id()); 2175 goto out; 2176 } 2177 2178 /* 2179 * If it is a vectored one, verify it's set in the ISR. If set, 2180 * acknowledge it. 2181 */ 2182 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1)); 2183 if (v & (1 << (vector & 0x1f))) { 2184 pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Acked\n", 2185 vector, smp_processor_id()); 2186 ack_APIC_irq(); 2187 } else { 2188 pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Not pending!\n", 2189 vector, smp_processor_id()); 2190 } 2191 out: 2192 trace_spurious_apic_exit(vector); 2193 exiting_irq(); 2194 } 2195 2196 /* 2197 * This interrupt should never happen with our APIC/SMP architecture 2198 */ 2199 __visible void __irq_entry smp_error_interrupt(struct pt_regs *regs) 2200 { 2201 static const char * const error_interrupt_reason[] = { 2202 "Send CS error", /* APIC Error Bit 0 */ 2203 "Receive CS error", /* APIC Error Bit 1 */ 2204 "Send accept error", /* APIC Error Bit 2 */ 2205 "Receive accept error", /* APIC Error Bit 3 */ 2206 "Redirectable IPI", /* APIC Error Bit 4 */ 2207 "Send illegal vector", /* APIC Error Bit 5 */ 2208 "Received illegal vector", /* APIC Error Bit 6 */ 2209 "Illegal register address", /* APIC Error Bit 7 */ 2210 }; 2211 u32 v, i = 0; 2212 2213 entering_irq(); 2214 trace_error_apic_entry(ERROR_APIC_VECTOR); 2215 2216 /* First tickle the hardware, only then report what went on. -- REW */ 2217 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */ 2218 apic_write(APIC_ESR, 0); 2219 v = apic_read(APIC_ESR); 2220 ack_APIC_irq(); 2221 atomic_inc(&irq_err_count); 2222 2223 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x", 2224 smp_processor_id(), v); 2225 2226 v &= 0xff; 2227 while (v) { 2228 if (v & 0x1) 2229 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); 2230 i++; 2231 v >>= 1; 2232 } 2233 2234 apic_printk(APIC_DEBUG, KERN_CONT "\n"); 2235 2236 trace_error_apic_exit(ERROR_APIC_VECTOR); 2237 exiting_irq(); 2238 } 2239 2240 /** 2241 * connect_bsp_APIC - attach the APIC to the interrupt system 2242 */ 2243 static void __init connect_bsp_APIC(void) 2244 { 2245 #ifdef CONFIG_X86_32 2246 if (pic_mode) { 2247 /* 2248 * Do not trust the local APIC being empty at bootup. 2249 */ 2250 clear_local_APIC(); 2251 /* 2252 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 2253 * local APIC to INT and NMI lines. 2254 */ 2255 apic_printk(APIC_VERBOSE, "leaving PIC mode, " 2256 "enabling APIC mode.\n"); 2257 imcr_pic_to_apic(); 2258 } 2259 #endif 2260 } 2261 2262 /** 2263 * disconnect_bsp_APIC - detach the APIC from the interrupt system 2264 * @virt_wire_setup: indicates, whether virtual wire mode is selected 2265 * 2266 * Virtual wire mode is necessary to deliver legacy interrupts even when the 2267 * APIC is disabled. 2268 */ 2269 void disconnect_bsp_APIC(int virt_wire_setup) 2270 { 2271 unsigned int value; 2272 2273 #ifdef CONFIG_X86_32 2274 if (pic_mode) { 2275 /* 2276 * Put the board back into PIC mode (has an effect only on 2277 * certain older boards). Note that APIC interrupts, including 2278 * IPIs, won't work beyond this point! The only exception are 2279 * INIT IPIs. 2280 */ 2281 apic_printk(APIC_VERBOSE, "disabling APIC mode, " 2282 "entering PIC mode.\n"); 2283 imcr_apic_to_pic(); 2284 return; 2285 } 2286 #endif 2287 2288 /* Go back to Virtual Wire compatibility mode */ 2289 2290 /* For the spurious interrupt use vector F, and enable it */ 2291 value = apic_read(APIC_SPIV); 2292 value &= ~APIC_VECTOR_MASK; 2293 value |= APIC_SPIV_APIC_ENABLED; 2294 value |= 0xf; 2295 apic_write(APIC_SPIV, value); 2296 2297 if (!virt_wire_setup) { 2298 /* 2299 * For LVT0 make it edge triggered, active high, 2300 * external and enabled 2301 */ 2302 value = apic_read(APIC_LVT0); 2303 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2304 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2305 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2306 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2307 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 2308 apic_write(APIC_LVT0, value); 2309 } else { 2310 /* Disable LVT0 */ 2311 apic_write(APIC_LVT0, APIC_LVT_MASKED); 2312 } 2313 2314 /* 2315 * For LVT1 make it edge triggered, active high, 2316 * nmi and enabled 2317 */ 2318 value = apic_read(APIC_LVT1); 2319 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2320 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2321 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2322 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2323 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 2324 apic_write(APIC_LVT1, value); 2325 } 2326 2327 /* 2328 * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated 2329 * contiguously, it equals to current allocated max logical CPU ID plus 1. 2330 * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range, 2331 * so the maximum of nr_logical_cpuids is nr_cpu_ids. 2332 * 2333 * NOTE: Reserve 0 for BSP. 2334 */ 2335 static int nr_logical_cpuids = 1; 2336 2337 /* 2338 * Used to store mapping between logical CPU IDs and APIC IDs. 2339 */ 2340 static int cpuid_to_apicid[] = { 2341 [0 ... NR_CPUS - 1] = -1, 2342 }; 2343 2344 #ifdef CONFIG_SMP 2345 /** 2346 * apic_id_is_primary_thread - Check whether APIC ID belongs to a primary thread 2347 * @apicid: APIC ID to check 2348 */ 2349 bool apic_id_is_primary_thread(unsigned int apicid) 2350 { 2351 u32 mask; 2352 2353 if (smp_num_siblings == 1) 2354 return true; 2355 /* Isolate the SMT bit(s) in the APICID and check for 0 */ 2356 mask = (1U << (fls(smp_num_siblings) - 1)) - 1; 2357 return !(apicid & mask); 2358 } 2359 #endif 2360 2361 /* 2362 * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids 2363 * and cpuid_to_apicid[] synchronized. 2364 */ 2365 static int allocate_logical_cpuid(int apicid) 2366 { 2367 int i; 2368 2369 /* 2370 * cpuid <-> apicid mapping is persistent, so when a cpu is up, 2371 * check if the kernel has allocated a cpuid for it. 2372 */ 2373 for (i = 0; i < nr_logical_cpuids; i++) { 2374 if (cpuid_to_apicid[i] == apicid) 2375 return i; 2376 } 2377 2378 /* Allocate a new cpuid. */ 2379 if (nr_logical_cpuids >= nr_cpu_ids) { 2380 WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. " 2381 "Processor %d/0x%x and the rest are ignored.\n", 2382 nr_cpu_ids, nr_logical_cpuids, apicid); 2383 return -EINVAL; 2384 } 2385 2386 cpuid_to_apicid[nr_logical_cpuids] = apicid; 2387 return nr_logical_cpuids++; 2388 } 2389 2390 int generic_processor_info(int apicid, int version) 2391 { 2392 int cpu, max = nr_cpu_ids; 2393 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, 2394 phys_cpu_present_map); 2395 2396 /* 2397 * boot_cpu_physical_apicid is designed to have the apicid 2398 * returned by read_apic_id(), i.e, the apicid of the 2399 * currently booting-up processor. However, on some platforms, 2400 * it is temporarily modified by the apicid reported as BSP 2401 * through MP table. Concretely: 2402 * 2403 * - arch/x86/kernel/mpparse.c: MP_processor_info() 2404 * - arch/x86/mm/amdtopology.c: amd_numa_init() 2405 * 2406 * This function is executed with the modified 2407 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel 2408 * parameter doesn't work to disable APs on kdump 2nd kernel. 2409 * 2410 * Since fixing handling of boot_cpu_physical_apicid requires 2411 * another discussion and tests on each platform, we leave it 2412 * for now and here we use read_apic_id() directly in this 2413 * function, generic_processor_info(). 2414 */ 2415 if (disabled_cpu_apicid != BAD_APICID && 2416 disabled_cpu_apicid != read_apic_id() && 2417 disabled_cpu_apicid == apicid) { 2418 int thiscpu = num_processors + disabled_cpus; 2419 2420 pr_warn("APIC: Disabling requested cpu." 2421 " Processor %d/0x%x ignored.\n", thiscpu, apicid); 2422 2423 disabled_cpus++; 2424 return -ENODEV; 2425 } 2426 2427 /* 2428 * If boot cpu has not been detected yet, then only allow upto 2429 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu 2430 */ 2431 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && 2432 apicid != boot_cpu_physical_apicid) { 2433 int thiscpu = max + disabled_cpus - 1; 2434 2435 pr_warn("APIC: NR_CPUS/possible_cpus limit of %i almost" 2436 " reached. Keeping one slot for boot cpu." 2437 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 2438 2439 disabled_cpus++; 2440 return -ENODEV; 2441 } 2442 2443 if (num_processors >= nr_cpu_ids) { 2444 int thiscpu = max + disabled_cpus; 2445 2446 pr_warn("APIC: NR_CPUS/possible_cpus limit of %i reached. " 2447 "Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 2448 2449 disabled_cpus++; 2450 return -EINVAL; 2451 } 2452 2453 if (apicid == boot_cpu_physical_apicid) { 2454 /* 2455 * x86_bios_cpu_apicid is required to have processors listed 2456 * in same order as logical cpu numbers. Hence the first 2457 * entry is BSP, and so on. 2458 * boot_cpu_init() already hold bit 0 in cpu_present_mask 2459 * for BSP. 2460 */ 2461 cpu = 0; 2462 2463 /* Logical cpuid 0 is reserved for BSP. */ 2464 cpuid_to_apicid[0] = apicid; 2465 } else { 2466 cpu = allocate_logical_cpuid(apicid); 2467 if (cpu < 0) { 2468 disabled_cpus++; 2469 return -EINVAL; 2470 } 2471 } 2472 2473 /* 2474 * Validate version 2475 */ 2476 if (version == 0x0) { 2477 pr_warn("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", 2478 cpu, apicid); 2479 version = 0x10; 2480 } 2481 2482 if (version != boot_cpu_apic_version) { 2483 pr_warn("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", 2484 boot_cpu_apic_version, cpu, version); 2485 } 2486 2487 if (apicid > max_physical_apicid) 2488 max_physical_apicid = apicid; 2489 2490 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 2491 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 2492 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 2493 #endif 2494 #ifdef CONFIG_X86_32 2495 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 2496 apic->x86_32_early_logical_apicid(cpu); 2497 #endif 2498 set_cpu_possible(cpu, true); 2499 physid_set(apicid, phys_cpu_present_map); 2500 set_cpu_present(cpu, true); 2501 num_processors++; 2502 2503 return cpu; 2504 } 2505 2506 int hard_smp_processor_id(void) 2507 { 2508 return read_apic_id(); 2509 } 2510 2511 /* 2512 * Override the generic EOI implementation with an optimized version. 2513 * Only called during early boot when only one CPU is active and with 2514 * interrupts disabled, so we know this does not race with actual APIC driver 2515 * use. 2516 */ 2517 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) 2518 { 2519 struct apic **drv; 2520 2521 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { 2522 /* Should happen once for each apic */ 2523 WARN_ON((*drv)->eoi_write == eoi_write); 2524 (*drv)->native_eoi_write = (*drv)->eoi_write; 2525 (*drv)->eoi_write = eoi_write; 2526 } 2527 } 2528 2529 static void __init apic_bsp_up_setup(void) 2530 { 2531 #ifdef CONFIG_X86_64 2532 apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid)); 2533 #else 2534 /* 2535 * Hack: In case of kdump, after a crash, kernel might be booting 2536 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 2537 * might be zero if read from MP tables. Get it from LAPIC. 2538 */ 2539 # ifdef CONFIG_CRASH_DUMP 2540 boot_cpu_physical_apicid = read_apic_id(); 2541 # endif 2542 #endif 2543 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 2544 } 2545 2546 /** 2547 * apic_bsp_setup - Setup function for local apic and io-apic 2548 * @upmode: Force UP mode (for APIC_init_uniprocessor) 2549 */ 2550 static void __init apic_bsp_setup(bool upmode) 2551 { 2552 connect_bsp_APIC(); 2553 if (upmode) 2554 apic_bsp_up_setup(); 2555 setup_local_APIC(); 2556 2557 enable_IO_APIC(); 2558 end_local_APIC_setup(); 2559 irq_remap_enable_fault_handling(); 2560 setup_IO_APIC(); 2561 } 2562 2563 #ifdef CONFIG_UP_LATE_INIT 2564 void __init up_late_init(void) 2565 { 2566 if (apic_intr_mode == APIC_PIC) 2567 return; 2568 2569 /* Setup local timer */ 2570 x86_init.timers.setup_percpu_clockev(); 2571 } 2572 #endif 2573 2574 /* 2575 * Power management 2576 */ 2577 #ifdef CONFIG_PM 2578 2579 static struct { 2580 /* 2581 * 'active' is true if the local APIC was enabled by us and 2582 * not the BIOS; this signifies that we are also responsible 2583 * for disabling it before entering apm/acpi suspend 2584 */ 2585 int active; 2586 /* r/w apic fields */ 2587 unsigned int apic_id; 2588 unsigned int apic_taskpri; 2589 unsigned int apic_ldr; 2590 unsigned int apic_dfr; 2591 unsigned int apic_spiv; 2592 unsigned int apic_lvtt; 2593 unsigned int apic_lvtpc; 2594 unsigned int apic_lvt0; 2595 unsigned int apic_lvt1; 2596 unsigned int apic_lvterr; 2597 unsigned int apic_tmict; 2598 unsigned int apic_tdcr; 2599 unsigned int apic_thmr; 2600 unsigned int apic_cmci; 2601 } apic_pm_state; 2602 2603 static int lapic_suspend(void) 2604 { 2605 unsigned long flags; 2606 int maxlvt; 2607 2608 if (!apic_pm_state.active) 2609 return 0; 2610 2611 maxlvt = lapic_get_maxlvt(); 2612 2613 apic_pm_state.apic_id = apic_read(APIC_ID); 2614 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 2615 apic_pm_state.apic_ldr = apic_read(APIC_LDR); 2616 apic_pm_state.apic_dfr = apic_read(APIC_DFR); 2617 apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2618 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2619 if (maxlvt >= 4) 2620 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2621 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2622 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2623 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2624 apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2625 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 2626 #ifdef CONFIG_X86_THERMAL_VECTOR 2627 if (maxlvt >= 5) 2628 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2629 #endif 2630 #ifdef CONFIG_X86_MCE_INTEL 2631 if (maxlvt >= 6) 2632 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI); 2633 #endif 2634 2635 local_irq_save(flags); 2636 2637 /* 2638 * Mask IOAPIC before disabling the local APIC to prevent stale IRR 2639 * entries on some implementations. 2640 */ 2641 mask_ioapic_entries(); 2642 2643 disable_local_APIC(); 2644 2645 irq_remapping_disable(); 2646 2647 local_irq_restore(flags); 2648 return 0; 2649 } 2650 2651 static void lapic_resume(void) 2652 { 2653 unsigned int l, h; 2654 unsigned long flags; 2655 int maxlvt; 2656 2657 if (!apic_pm_state.active) 2658 return; 2659 2660 local_irq_save(flags); 2661 2662 /* 2663 * IO-APIC and PIC have their own resume routines. 2664 * We just mask them here to make sure the interrupt 2665 * subsystem is completely quiet while we enable x2apic 2666 * and interrupt-remapping. 2667 */ 2668 mask_ioapic_entries(); 2669 legacy_pic->mask_all(); 2670 2671 if (x2apic_mode) { 2672 __x2apic_enable(); 2673 } else { 2674 /* 2675 * Make sure the APICBASE points to the right address 2676 * 2677 * FIXME! This will be wrong if we ever support suspend on 2678 * SMP! We'll need to do this as part of the CPU restore! 2679 */ 2680 if (boot_cpu_data.x86 >= 6) { 2681 rdmsr(MSR_IA32_APICBASE, l, h); 2682 l &= ~MSR_IA32_APICBASE_BASE; 2683 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2684 wrmsr(MSR_IA32_APICBASE, l, h); 2685 } 2686 } 2687 2688 maxlvt = lapic_get_maxlvt(); 2689 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2690 apic_write(APIC_ID, apic_pm_state.apic_id); 2691 apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2692 apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2693 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2694 apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2695 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2696 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 2697 #ifdef CONFIG_X86_THERMAL_VECTOR 2698 if (maxlvt >= 5) 2699 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2700 #endif 2701 #ifdef CONFIG_X86_MCE_INTEL 2702 if (maxlvt >= 6) 2703 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci); 2704 #endif 2705 if (maxlvt >= 4) 2706 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2707 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2708 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2709 apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2710 apic_write(APIC_ESR, 0); 2711 apic_read(APIC_ESR); 2712 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2713 apic_write(APIC_ESR, 0); 2714 apic_read(APIC_ESR); 2715 2716 irq_remapping_reenable(x2apic_mode); 2717 2718 local_irq_restore(flags); 2719 } 2720 2721 /* 2722 * This device has no shutdown method - fully functioning local APICs 2723 * are needed on every CPU up until machine_halt/restart/poweroff. 2724 */ 2725 2726 static struct syscore_ops lapic_syscore_ops = { 2727 .resume = lapic_resume, 2728 .suspend = lapic_suspend, 2729 }; 2730 2731 static void apic_pm_activate(void) 2732 { 2733 apic_pm_state.active = 1; 2734 } 2735 2736 static int __init init_lapic_sysfs(void) 2737 { 2738 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 2739 if (boot_cpu_has(X86_FEATURE_APIC)) 2740 register_syscore_ops(&lapic_syscore_ops); 2741 2742 return 0; 2743 } 2744 2745 /* local apic needs to resume before other devices access its registers. */ 2746 core_initcall(init_lapic_sysfs); 2747 2748 #else /* CONFIG_PM */ 2749 2750 static void apic_pm_activate(void) { } 2751 2752 #endif /* CONFIG_PM */ 2753 2754 #ifdef CONFIG_X86_64 2755 2756 static int multi_checked; 2757 static int multi; 2758 2759 static int set_multi(const struct dmi_system_id *d) 2760 { 2761 if (multi) 2762 return 0; 2763 pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2764 multi = 1; 2765 return 0; 2766 } 2767 2768 static const struct dmi_system_id multi_dmi_table[] = { 2769 { 2770 .callback = set_multi, 2771 .ident = "IBM System Summit2", 2772 .matches = { 2773 DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2774 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2775 }, 2776 }, 2777 {} 2778 }; 2779 2780 static void dmi_check_multi(void) 2781 { 2782 if (multi_checked) 2783 return; 2784 2785 dmi_check_system(multi_dmi_table); 2786 multi_checked = 1; 2787 } 2788 2789 /* 2790 * apic_is_clustered_box() -- Check if we can expect good TSC 2791 * 2792 * Thus far, the major user of this is IBM's Summit2 series: 2793 * Clustered boxes may have unsynced TSC problems if they are 2794 * multi-chassis. 2795 * Use DMI to check them 2796 */ 2797 int apic_is_clustered_box(void) 2798 { 2799 dmi_check_multi(); 2800 return multi; 2801 } 2802 #endif 2803 2804 /* 2805 * APIC command line parameters 2806 */ 2807 static int __init setup_disableapic(char *arg) 2808 { 2809 disable_apic = 1; 2810 setup_clear_cpu_cap(X86_FEATURE_APIC); 2811 return 0; 2812 } 2813 early_param("disableapic", setup_disableapic); 2814 2815 /* same as disableapic, for compatibility */ 2816 static int __init setup_nolapic(char *arg) 2817 { 2818 return setup_disableapic(arg); 2819 } 2820 early_param("nolapic", setup_nolapic); 2821 2822 static int __init parse_lapic_timer_c2_ok(char *arg) 2823 { 2824 local_apic_timer_c2_ok = 1; 2825 return 0; 2826 } 2827 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2828 2829 static int __init parse_disable_apic_timer(char *arg) 2830 { 2831 disable_apic_timer = 1; 2832 return 0; 2833 } 2834 early_param("noapictimer", parse_disable_apic_timer); 2835 2836 static int __init parse_nolapic_timer(char *arg) 2837 { 2838 disable_apic_timer = 1; 2839 return 0; 2840 } 2841 early_param("nolapic_timer", parse_nolapic_timer); 2842 2843 static int __init apic_set_verbosity(char *arg) 2844 { 2845 if (!arg) { 2846 #ifdef CONFIG_X86_64 2847 skip_ioapic_setup = 0; 2848 return 0; 2849 #endif 2850 return -EINVAL; 2851 } 2852 2853 if (strcmp("debug", arg) == 0) 2854 apic_verbosity = APIC_DEBUG; 2855 else if (strcmp("verbose", arg) == 0) 2856 apic_verbosity = APIC_VERBOSE; 2857 #ifdef CONFIG_X86_64 2858 else { 2859 pr_warn("APIC Verbosity level %s not recognised" 2860 " use apic=verbose or apic=debug\n", arg); 2861 return -EINVAL; 2862 } 2863 #endif 2864 2865 return 0; 2866 } 2867 early_param("apic", apic_set_verbosity); 2868 2869 static int __init lapic_insert_resource(void) 2870 { 2871 if (!apic_phys) 2872 return -1; 2873 2874 /* Put local APIC into the resource map. */ 2875 lapic_resource.start = apic_phys; 2876 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2877 insert_resource(&iomem_resource, &lapic_resource); 2878 2879 return 0; 2880 } 2881 2882 /* 2883 * need call insert after e820__reserve_resources() 2884 * that is using request_resource 2885 */ 2886 late_initcall(lapic_insert_resource); 2887 2888 static int __init apic_set_disabled_cpu_apicid(char *arg) 2889 { 2890 if (!arg || !get_option(&arg, &disabled_cpu_apicid)) 2891 return -EINVAL; 2892 2893 return 0; 2894 } 2895 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); 2896 2897 static int __init apic_set_extnmi(char *arg) 2898 { 2899 if (!arg) 2900 return -EINVAL; 2901 2902 if (!strncmp("all", arg, 3)) 2903 apic_extnmi = APIC_EXTNMI_ALL; 2904 else if (!strncmp("none", arg, 4)) 2905 apic_extnmi = APIC_EXTNMI_NONE; 2906 else if (!strncmp("bsp", arg, 3)) 2907 apic_extnmi = APIC_EXTNMI_BSP; 2908 else { 2909 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg); 2910 return -EINVAL; 2911 } 2912 2913 return 0; 2914 } 2915 early_param("apic_extnmi", apic_set_extnmi); 2916