1 /* 2 * Local APIC handling, local APIC timers 3 * 4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 5 * 6 * Fixes 7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 8 * thanks to Eric Gilmore 9 * and Rolf G. Tews 10 * for testing these extensively. 11 * Maciej W. Rozycki : Various updates and fixes. 12 * Mikael Pettersson : Power Management for UP-APIC. 13 * Pavel Machek and 14 * Mikael Pettersson : PM converted to driver model. 15 */ 16 17 #include <linux/perf_event.h> 18 #include <linux/kernel_stat.h> 19 #include <linux/mc146818rtc.h> 20 #include <linux/acpi_pmtmr.h> 21 #include <linux/clockchips.h> 22 #include <linux/interrupt.h> 23 #include <linux/bootmem.h> 24 #include <linux/ftrace.h> 25 #include <linux/ioport.h> 26 #include <linux/module.h> 27 #include <linux/syscore_ops.h> 28 #include <linux/delay.h> 29 #include <linux/timex.h> 30 #include <linux/i8253.h> 31 #include <linux/dmar.h> 32 #include <linux/init.h> 33 #include <linux/cpu.h> 34 #include <linux/dmi.h> 35 #include <linux/smp.h> 36 #include <linux/mm.h> 37 38 #include <asm/trace/irq_vectors.h> 39 #include <asm/irq_remapping.h> 40 #include <asm/perf_event.h> 41 #include <asm/x86_init.h> 42 #include <asm/pgalloc.h> 43 #include <linux/atomic.h> 44 #include <asm/mpspec.h> 45 #include <asm/i8259.h> 46 #include <asm/proto.h> 47 #include <asm/apic.h> 48 #include <asm/io_apic.h> 49 #include <asm/desc.h> 50 #include <asm/hpet.h> 51 #include <asm/idle.h> 52 #include <asm/mtrr.h> 53 #include <asm/time.h> 54 #include <asm/smp.h> 55 #include <asm/mce.h> 56 #include <asm/tsc.h> 57 #include <asm/hypervisor.h> 58 59 unsigned int num_processors; 60 61 unsigned disabled_cpus; 62 63 /* Processor that is doing the boot up */ 64 unsigned int boot_cpu_physical_apicid = -1U; 65 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); 66 67 /* 68 * The highest APIC ID seen during enumeration. 69 */ 70 static unsigned int max_physical_apicid; 71 72 /* 73 * Bitmask of physically existing CPUs: 74 */ 75 physid_mask_t phys_cpu_present_map; 76 77 /* 78 * Processor to be disabled specified by kernel parameter 79 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to 80 * avoid undefined behaviour caused by sending INIT from AP to BSP. 81 */ 82 static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID; 83 84 /* 85 * This variable controls which CPUs receive external NMIs. By default, 86 * external NMIs are delivered only to the BSP. 87 */ 88 static int apic_extnmi = APIC_EXTNMI_BSP; 89 90 /* 91 * Map cpu index to physical APIC ID 92 */ 93 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); 94 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID); 95 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 96 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 97 98 #ifdef CONFIG_X86_32 99 100 /* 101 * On x86_32, the mapping between cpu and logical apicid may vary 102 * depending on apic in use. The following early percpu variable is 103 * used for the mapping. This is where the behaviors of x86_64 and 32 104 * actually diverge. Let's keep it ugly for now. 105 */ 106 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID); 107 108 /* Local APIC was disabled by the BIOS and enabled by the kernel */ 109 static int enabled_via_apicbase; 110 111 /* 112 * Handle interrupt mode configuration register (IMCR). 113 * This register controls whether the interrupt signals 114 * that reach the BSP come from the master PIC or from the 115 * local APIC. Before entering Symmetric I/O Mode, either 116 * the BIOS or the operating system must switch out of 117 * PIC Mode by changing the IMCR. 118 */ 119 static inline void imcr_pic_to_apic(void) 120 { 121 /* select IMCR register */ 122 outb(0x70, 0x22); 123 /* NMI and 8259 INTR go through APIC */ 124 outb(0x01, 0x23); 125 } 126 127 static inline void imcr_apic_to_pic(void) 128 { 129 /* select IMCR register */ 130 outb(0x70, 0x22); 131 /* NMI and 8259 INTR go directly to BSP */ 132 outb(0x00, 0x23); 133 } 134 #endif 135 136 /* 137 * Knob to control our willingness to enable the local APIC. 138 * 139 * +1=force-enable 140 */ 141 static int force_enable_local_apic __initdata; 142 143 /* 144 * APIC command line parameters 145 */ 146 static int __init parse_lapic(char *arg) 147 { 148 if (config_enabled(CONFIG_X86_32) && !arg) 149 force_enable_local_apic = 1; 150 else if (arg && !strncmp(arg, "notscdeadline", 13)) 151 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 152 return 0; 153 } 154 early_param("lapic", parse_lapic); 155 156 #ifdef CONFIG_X86_64 157 static int apic_calibrate_pmtmr __initdata; 158 static __init int setup_apicpmtimer(char *s) 159 { 160 apic_calibrate_pmtmr = 1; 161 notsc_setup(NULL); 162 return 0; 163 } 164 __setup("apicpmtimer", setup_apicpmtimer); 165 #endif 166 167 unsigned long mp_lapic_addr; 168 int disable_apic; 169 /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 170 static int disable_apic_timer __initdata; 171 /* Local APIC timer works in C2 */ 172 int local_apic_timer_c2_ok; 173 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 174 175 int first_system_vector = FIRST_SYSTEM_VECTOR; 176 177 /* 178 * Debug level, exported for io_apic.c 179 */ 180 unsigned int apic_verbosity; 181 182 int pic_mode; 183 184 /* Have we found an MP table */ 185 int smp_found_config; 186 187 static struct resource lapic_resource = { 188 .name = "Local APIC", 189 .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 190 }; 191 192 unsigned int lapic_timer_frequency = 0; 193 194 static void apic_pm_activate(void); 195 196 static unsigned long apic_phys; 197 198 /* 199 * Get the LAPIC version 200 */ 201 static inline int lapic_get_version(void) 202 { 203 return GET_APIC_VERSION(apic_read(APIC_LVR)); 204 } 205 206 /* 207 * Check, if the APIC is integrated or a separate chip 208 */ 209 static inline int lapic_is_integrated(void) 210 { 211 #ifdef CONFIG_X86_64 212 return 1; 213 #else 214 return APIC_INTEGRATED(lapic_get_version()); 215 #endif 216 } 217 218 /* 219 * Check, whether this is a modern or a first generation APIC 220 */ 221 static int modern_apic(void) 222 { 223 /* AMD systems use old APIC versions, so check the CPU */ 224 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 225 boot_cpu_data.x86 >= 0xf) 226 return 1; 227 return lapic_get_version() >= 0x14; 228 } 229 230 /* 231 * right after this call apic become NOOP driven 232 * so apic->write/read doesn't do anything 233 */ 234 static void __init apic_disable(void) 235 { 236 pr_info("APIC: switched to apic NOOP\n"); 237 apic = &apic_noop; 238 } 239 240 void native_apic_wait_icr_idle(void) 241 { 242 while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 243 cpu_relax(); 244 } 245 246 u32 native_safe_apic_wait_icr_idle(void) 247 { 248 u32 send_status; 249 int timeout; 250 251 timeout = 0; 252 do { 253 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 254 if (!send_status) 255 break; 256 inc_irq_stat(icr_read_retry_count); 257 udelay(100); 258 } while (timeout++ < 1000); 259 260 return send_status; 261 } 262 263 void native_apic_icr_write(u32 low, u32 id) 264 { 265 unsigned long flags; 266 267 local_irq_save(flags); 268 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 269 apic_write(APIC_ICR, low); 270 local_irq_restore(flags); 271 } 272 273 u64 native_apic_icr_read(void) 274 { 275 u32 icr1, icr2; 276 277 icr2 = apic_read(APIC_ICR2); 278 icr1 = apic_read(APIC_ICR); 279 280 return icr1 | ((u64)icr2 << 32); 281 } 282 283 #ifdef CONFIG_X86_32 284 /** 285 * get_physical_broadcast - Get number of physical broadcast IDs 286 */ 287 int get_physical_broadcast(void) 288 { 289 return modern_apic() ? 0xff : 0xf; 290 } 291 #endif 292 293 /** 294 * lapic_get_maxlvt - get the maximum number of local vector table entries 295 */ 296 int lapic_get_maxlvt(void) 297 { 298 unsigned int v; 299 300 v = apic_read(APIC_LVR); 301 /* 302 * - we always have APIC integrated on 64bit mode 303 * - 82489DXs do not report # of LVT entries 304 */ 305 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; 306 } 307 308 /* 309 * Local APIC timer 310 */ 311 312 /* Clock divisor */ 313 #define APIC_DIVISOR 16 314 #define TSC_DIVISOR 32 315 316 /* 317 * This function sets up the local APIC timer, with a timeout of 318 * 'clocks' APIC bus clock. During calibration we actually call 319 * this function twice on the boot CPU, once with a bogus timeout 320 * value, second time for real. The other (noncalibrating) CPUs 321 * call this function only once, with the real, calibrated value. 322 * 323 * We do reads before writes even if unnecessary, to get around the 324 * P5 APIC double write bug. 325 */ 326 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 327 { 328 unsigned int lvtt_value, tmp_value; 329 330 lvtt_value = LOCAL_TIMER_VECTOR; 331 if (!oneshot) 332 lvtt_value |= APIC_LVT_TIMER_PERIODIC; 333 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 334 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE; 335 336 if (!lapic_is_integrated()) 337 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 338 339 if (!irqen) 340 lvtt_value |= APIC_LVT_MASKED; 341 342 apic_write(APIC_LVTT, lvtt_value); 343 344 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { 345 /* 346 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, 347 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized. 348 * According to Intel, MFENCE can do the serialization here. 349 */ 350 asm volatile("mfence" : : : "memory"); 351 352 printk_once(KERN_DEBUG "TSC deadline timer enabled\n"); 353 return; 354 } 355 356 /* 357 * Divide PICLK by 16 358 */ 359 tmp_value = apic_read(APIC_TDCR); 360 apic_write(APIC_TDCR, 361 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 362 APIC_TDR_DIV_16); 363 364 if (!oneshot) 365 apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 366 } 367 368 /* 369 * Setup extended LVT, AMD specific 370 * 371 * Software should use the LVT offsets the BIOS provides. The offsets 372 * are determined by the subsystems using it like those for MCE 373 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts 374 * are supported. Beginning with family 10h at least 4 offsets are 375 * available. 376 * 377 * Since the offsets must be consistent for all cores, we keep track 378 * of the LVT offsets in software and reserve the offset for the same 379 * vector also to be used on other cores. An offset is freed by 380 * setting the entry to APIC_EILVT_MASKED. 381 * 382 * If the BIOS is right, there should be no conflicts. Otherwise a 383 * "[Firmware Bug]: ..." error message is generated. However, if 384 * software does not properly determines the offsets, it is not 385 * necessarily a BIOS bug. 386 */ 387 388 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; 389 390 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) 391 { 392 return (old & APIC_EILVT_MASKED) 393 || (new == APIC_EILVT_MASKED) 394 || ((new & ~APIC_EILVT_MASKED) == old); 395 } 396 397 static unsigned int reserve_eilvt_offset(int offset, unsigned int new) 398 { 399 unsigned int rsvd, vector; 400 401 if (offset >= APIC_EILVT_NR_MAX) 402 return ~0; 403 404 rsvd = atomic_read(&eilvt_offsets[offset]); 405 do { 406 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ 407 if (vector && !eilvt_entry_is_changeable(vector, new)) 408 /* may not change if vectors are different */ 409 return rsvd; 410 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); 411 } while (rsvd != new); 412 413 rsvd &= ~APIC_EILVT_MASKED; 414 if (rsvd && rsvd != vector) 415 pr_info("LVT offset %d assigned for vector 0x%02x\n", 416 offset, rsvd); 417 418 return new; 419 } 420 421 /* 422 * If mask=1, the LVT entry does not generate interrupts while mask=0 423 * enables the vector. See also the BKDGs. Must be called with 424 * preemption disabled. 425 */ 426 427 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) 428 { 429 unsigned long reg = APIC_EILVTn(offset); 430 unsigned int new, old, reserved; 431 432 new = (mask << 16) | (msg_type << 8) | vector; 433 old = apic_read(reg); 434 reserved = reserve_eilvt_offset(offset, new); 435 436 if (reserved != new) { 437 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 438 "vector 0x%x, but the register is already in use for " 439 "vector 0x%x on another cpu\n", 440 smp_processor_id(), reg, offset, new, reserved); 441 return -EINVAL; 442 } 443 444 if (!eilvt_entry_is_changeable(old, new)) { 445 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 446 "vector 0x%x, but the register is already in use for " 447 "vector 0x%x on this cpu\n", 448 smp_processor_id(), reg, offset, new, old); 449 return -EBUSY; 450 } 451 452 apic_write(reg, new); 453 454 return 0; 455 } 456 EXPORT_SYMBOL_GPL(setup_APIC_eilvt); 457 458 /* 459 * Program the next event, relative to now 460 */ 461 static int lapic_next_event(unsigned long delta, 462 struct clock_event_device *evt) 463 { 464 apic_write(APIC_TMICT, delta); 465 return 0; 466 } 467 468 static int lapic_next_deadline(unsigned long delta, 469 struct clock_event_device *evt) 470 { 471 u64 tsc; 472 473 tsc = rdtsc(); 474 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); 475 return 0; 476 } 477 478 static int lapic_timer_shutdown(struct clock_event_device *evt) 479 { 480 unsigned int v; 481 482 /* Lapic used as dummy for broadcast ? */ 483 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 484 return 0; 485 486 v = apic_read(APIC_LVTT); 487 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 488 apic_write(APIC_LVTT, v); 489 apic_write(APIC_TMICT, 0); 490 return 0; 491 } 492 493 static inline int 494 lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot) 495 { 496 /* Lapic used as dummy for broadcast ? */ 497 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 498 return 0; 499 500 __setup_APIC_LVTT(lapic_timer_frequency, oneshot, 1); 501 return 0; 502 } 503 504 static int lapic_timer_set_periodic(struct clock_event_device *evt) 505 { 506 return lapic_timer_set_periodic_oneshot(evt, false); 507 } 508 509 static int lapic_timer_set_oneshot(struct clock_event_device *evt) 510 { 511 return lapic_timer_set_periodic_oneshot(evt, true); 512 } 513 514 /* 515 * Local APIC timer broadcast function 516 */ 517 static void lapic_timer_broadcast(const struct cpumask *mask) 518 { 519 #ifdef CONFIG_SMP 520 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 521 #endif 522 } 523 524 525 /* 526 * The local apic timer can be used for any function which is CPU local. 527 */ 528 static struct clock_event_device lapic_clockevent = { 529 .name = "lapic", 530 .features = CLOCK_EVT_FEAT_PERIODIC | 531 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP 532 | CLOCK_EVT_FEAT_DUMMY, 533 .shift = 32, 534 .set_state_shutdown = lapic_timer_shutdown, 535 .set_state_periodic = lapic_timer_set_periodic, 536 .set_state_oneshot = lapic_timer_set_oneshot, 537 .set_next_event = lapic_next_event, 538 .broadcast = lapic_timer_broadcast, 539 .rating = 100, 540 .irq = -1, 541 }; 542 static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 543 544 /* 545 * Setup the local APIC timer for this CPU. Copy the initialized values 546 * of the boot CPU and register the clock event in the framework. 547 */ 548 static void setup_APIC_timer(void) 549 { 550 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 551 552 if (this_cpu_has(X86_FEATURE_ARAT)) { 553 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 554 /* Make LAPIC timer preferrable over percpu HPET */ 555 lapic_clockevent.rating = 150; 556 } 557 558 memcpy(levt, &lapic_clockevent, sizeof(*levt)); 559 levt->cpumask = cpumask_of(smp_processor_id()); 560 561 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 562 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | 563 CLOCK_EVT_FEAT_DUMMY); 564 levt->set_next_event = lapic_next_deadline; 565 clockevents_config_and_register(levt, 566 (tsc_khz / TSC_DIVISOR) * 1000, 567 0xF, ~0UL); 568 } else 569 clockevents_register_device(levt); 570 } 571 572 /* 573 * In this functions we calibrate APIC bus clocks to the external timer. 574 * 575 * We want to do the calibration only once since we want to have local timer 576 * irqs syncron. CPUs connected by the same APIC bus have the very same bus 577 * frequency. 578 * 579 * This was previously done by reading the PIT/HPET and waiting for a wrap 580 * around to find out, that a tick has elapsed. I have a box, where the PIT 581 * readout is broken, so it never gets out of the wait loop again. This was 582 * also reported by others. 583 * 584 * Monitoring the jiffies value is inaccurate and the clockevents 585 * infrastructure allows us to do a simple substitution of the interrupt 586 * handler. 587 * 588 * The calibration routine also uses the pm_timer when possible, as the PIT 589 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 590 * back to normal later in the boot process). 591 */ 592 593 #define LAPIC_CAL_LOOPS (HZ/10) 594 595 static __initdata int lapic_cal_loops = -1; 596 static __initdata long lapic_cal_t1, lapic_cal_t2; 597 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 598 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 599 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 600 601 /* 602 * Temporary interrupt handler. 603 */ 604 static void __init lapic_cal_handler(struct clock_event_device *dev) 605 { 606 unsigned long long tsc = 0; 607 long tapic = apic_read(APIC_TMCCT); 608 unsigned long pm = acpi_pm_read_early(); 609 610 if (cpu_has_tsc) 611 tsc = rdtsc(); 612 613 switch (lapic_cal_loops++) { 614 case 0: 615 lapic_cal_t1 = tapic; 616 lapic_cal_tsc1 = tsc; 617 lapic_cal_pm1 = pm; 618 lapic_cal_j1 = jiffies; 619 break; 620 621 case LAPIC_CAL_LOOPS: 622 lapic_cal_t2 = tapic; 623 lapic_cal_tsc2 = tsc; 624 if (pm < lapic_cal_pm1) 625 pm += ACPI_PM_OVRRUN; 626 lapic_cal_pm2 = pm; 627 lapic_cal_j2 = jiffies; 628 break; 629 } 630 } 631 632 static int __init 633 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 634 { 635 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 636 const long pm_thresh = pm_100ms / 100; 637 unsigned long mult; 638 u64 res; 639 640 #ifndef CONFIG_X86_PM_TIMER 641 return -1; 642 #endif 643 644 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 645 646 /* Check, if the PM timer is available */ 647 if (!deltapm) 648 return -1; 649 650 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 651 652 if (deltapm > (pm_100ms - pm_thresh) && 653 deltapm < (pm_100ms + pm_thresh)) { 654 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 655 return 0; 656 } 657 658 res = (((u64)deltapm) * mult) >> 22; 659 do_div(res, 1000000); 660 pr_warning("APIC calibration not consistent " 661 "with PM-Timer: %ldms instead of 100ms\n",(long)res); 662 663 /* Correct the lapic counter value */ 664 res = (((u64)(*delta)) * pm_100ms); 665 do_div(res, deltapm); 666 pr_info("APIC delta adjusted to PM-Timer: " 667 "%lu (%ld)\n", (unsigned long)res, *delta); 668 *delta = (long)res; 669 670 /* Correct the tsc counter value */ 671 if (cpu_has_tsc) { 672 res = (((u64)(*deltatsc)) * pm_100ms); 673 do_div(res, deltapm); 674 apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 675 "PM-Timer: %lu (%ld)\n", 676 (unsigned long)res, *deltatsc); 677 *deltatsc = (long)res; 678 } 679 680 return 0; 681 } 682 683 static int __init calibrate_APIC_clock(void) 684 { 685 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 686 void (*real_handler)(struct clock_event_device *dev); 687 unsigned long deltaj; 688 long delta, deltatsc; 689 int pm_referenced = 0; 690 691 /** 692 * check if lapic timer has already been calibrated by platform 693 * specific routine, such as tsc calibration code. if so, we just fill 694 * in the clockevent structure and return. 695 */ 696 697 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 698 return 0; 699 } else if (lapic_timer_frequency) { 700 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", 701 lapic_timer_frequency); 702 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR, 703 TICK_NSEC, lapic_clockevent.shift); 704 lapic_clockevent.max_delta_ns = 705 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); 706 lapic_clockevent.min_delta_ns = 707 clockevent_delta2ns(0xF, &lapic_clockevent); 708 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 709 return 0; 710 } 711 712 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 713 "calibrating APIC timer ...\n"); 714 715 local_irq_disable(); 716 717 /* Replace the global interrupt handler */ 718 real_handler = global_clock_event->event_handler; 719 global_clock_event->event_handler = lapic_cal_handler; 720 721 /* 722 * Setup the APIC counter to maximum. There is no way the lapic 723 * can underflow in the 100ms detection time frame 724 */ 725 __setup_APIC_LVTT(0xffffffff, 0, 0); 726 727 /* Let the interrupts run */ 728 local_irq_enable(); 729 730 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 731 cpu_relax(); 732 733 local_irq_disable(); 734 735 /* Restore the real event handler */ 736 global_clock_event->event_handler = real_handler; 737 738 /* Build delta t1-t2 as apic timer counts down */ 739 delta = lapic_cal_t1 - lapic_cal_t2; 740 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 741 742 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 743 744 /* we trust the PM based calibration if possible */ 745 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 746 &delta, &deltatsc); 747 748 /* Calculate the scaled math multiplication factor */ 749 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 750 lapic_clockevent.shift); 751 lapic_clockevent.max_delta_ns = 752 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); 753 lapic_clockevent.min_delta_ns = 754 clockevent_delta2ns(0xF, &lapic_clockevent); 755 756 lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 757 758 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 759 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); 760 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 761 lapic_timer_frequency); 762 763 if (cpu_has_tsc) { 764 apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 765 "%ld.%04ld MHz.\n", 766 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 767 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 768 } 769 770 apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 771 "%u.%04u MHz.\n", 772 lapic_timer_frequency / (1000000 / HZ), 773 lapic_timer_frequency % (1000000 / HZ)); 774 775 /* 776 * Do a sanity check on the APIC calibration result 777 */ 778 if (lapic_timer_frequency < (1000000 / HZ)) { 779 local_irq_enable(); 780 pr_warning("APIC frequency too slow, disabling apic timer\n"); 781 return -1; 782 } 783 784 levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 785 786 /* 787 * PM timer calibration failed or not turned on 788 * so lets try APIC timer based calibration 789 */ 790 if (!pm_referenced) { 791 apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 792 793 /* 794 * Setup the apic timer manually 795 */ 796 levt->event_handler = lapic_cal_handler; 797 lapic_timer_set_periodic(levt); 798 lapic_cal_loops = -1; 799 800 /* Let the interrupts run */ 801 local_irq_enable(); 802 803 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 804 cpu_relax(); 805 806 /* Stop the lapic timer */ 807 local_irq_disable(); 808 lapic_timer_shutdown(levt); 809 810 /* Jiffies delta */ 811 deltaj = lapic_cal_j2 - lapic_cal_j1; 812 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 813 814 /* Check, if the jiffies result is consistent */ 815 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 816 apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 817 else 818 levt->features |= CLOCK_EVT_FEAT_DUMMY; 819 } 820 local_irq_enable(); 821 822 if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 823 pr_warning("APIC timer disabled due to verification failure\n"); 824 return -1; 825 } 826 827 return 0; 828 } 829 830 /* 831 * Setup the boot APIC 832 * 833 * Calibrate and verify the result. 834 */ 835 void __init setup_boot_APIC_clock(void) 836 { 837 /* 838 * The local apic timer can be disabled via the kernel 839 * commandline or from the CPU detection code. Register the lapic 840 * timer as a dummy clock event source on SMP systems, so the 841 * broadcast mechanism is used. On UP systems simply ignore it. 842 */ 843 if (disable_apic_timer) { 844 pr_info("Disabling APIC timer\n"); 845 /* No broadcast on UP ! */ 846 if (num_possible_cpus() > 1) { 847 lapic_clockevent.mult = 1; 848 setup_APIC_timer(); 849 } 850 return; 851 } 852 853 if (calibrate_APIC_clock()) { 854 /* No broadcast on UP ! */ 855 if (num_possible_cpus() > 1) 856 setup_APIC_timer(); 857 return; 858 } 859 860 /* 861 * If nmi_watchdog is set to IO_APIC, we need the 862 * PIT/HPET going. Otherwise register lapic as a dummy 863 * device. 864 */ 865 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 866 867 /* Setup the lapic or request the broadcast */ 868 setup_APIC_timer(); 869 } 870 871 void setup_secondary_APIC_clock(void) 872 { 873 setup_APIC_timer(); 874 } 875 876 /* 877 * The guts of the apic timer interrupt 878 */ 879 static void local_apic_timer_interrupt(void) 880 { 881 int cpu = smp_processor_id(); 882 struct clock_event_device *evt = &per_cpu(lapic_events, cpu); 883 884 /* 885 * Normally we should not be here till LAPIC has been initialized but 886 * in some cases like kdump, its possible that there is a pending LAPIC 887 * timer interrupt from previous kernel's context and is delivered in 888 * new kernel the moment interrupts are enabled. 889 * 890 * Interrupts are enabled early and LAPIC is setup much later, hence 891 * its possible that when we get here evt->event_handler is NULL. 892 * Check for event_handler being NULL and discard the interrupt as 893 * spurious. 894 */ 895 if (!evt->event_handler) { 896 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); 897 /* Switch it off */ 898 lapic_timer_shutdown(evt); 899 return; 900 } 901 902 /* 903 * the NMI deadlock-detector uses this. 904 */ 905 inc_irq_stat(apic_timer_irqs); 906 907 evt->event_handler(evt); 908 } 909 910 /* 911 * Local APIC timer interrupt. This is the most natural way for doing 912 * local interrupts, but local timer interrupts can be emulated by 913 * broadcast interrupts too. [in case the hw doesn't support APIC timers] 914 * 915 * [ if a single-CPU system runs an SMP kernel then we call the local 916 * interrupt as well. Thus we cannot inline the local irq ... ] 917 */ 918 __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) 919 { 920 struct pt_regs *old_regs = set_irq_regs(regs); 921 922 /* 923 * NOTE! We'd better ACK the irq immediately, 924 * because timer handling can be slow. 925 * 926 * update_process_times() expects us to have done irq_enter(). 927 * Besides, if we don't timer interrupts ignore the global 928 * interrupt lock, which is the WrongThing (tm) to do. 929 */ 930 entering_ack_irq(); 931 local_apic_timer_interrupt(); 932 exiting_irq(); 933 934 set_irq_regs(old_regs); 935 } 936 937 __visible void __irq_entry smp_trace_apic_timer_interrupt(struct pt_regs *regs) 938 { 939 struct pt_regs *old_regs = set_irq_regs(regs); 940 941 /* 942 * NOTE! We'd better ACK the irq immediately, 943 * because timer handling can be slow. 944 * 945 * update_process_times() expects us to have done irq_enter(). 946 * Besides, if we don't timer interrupts ignore the global 947 * interrupt lock, which is the WrongThing (tm) to do. 948 */ 949 entering_ack_irq(); 950 trace_local_timer_entry(LOCAL_TIMER_VECTOR); 951 local_apic_timer_interrupt(); 952 trace_local_timer_exit(LOCAL_TIMER_VECTOR); 953 exiting_irq(); 954 955 set_irq_regs(old_regs); 956 } 957 958 int setup_profiling_timer(unsigned int multiplier) 959 { 960 return -EINVAL; 961 } 962 963 /* 964 * Local APIC start and shutdown 965 */ 966 967 /** 968 * clear_local_APIC - shutdown the local APIC 969 * 970 * This is called, when a CPU is disabled and before rebooting, so the state of 971 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 972 * leftovers during boot. 973 */ 974 void clear_local_APIC(void) 975 { 976 int maxlvt; 977 u32 v; 978 979 /* APIC hasn't been mapped yet */ 980 if (!x2apic_mode && !apic_phys) 981 return; 982 983 maxlvt = lapic_get_maxlvt(); 984 /* 985 * Masking an LVT entry can trigger a local APIC error 986 * if the vector is zero. Mask LVTERR first to prevent this. 987 */ 988 if (maxlvt >= 3) { 989 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 990 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 991 } 992 /* 993 * Careful: we have to set masks only first to deassert 994 * any level-triggered sources. 995 */ 996 v = apic_read(APIC_LVTT); 997 apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 998 v = apic_read(APIC_LVT0); 999 apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 1000 v = apic_read(APIC_LVT1); 1001 apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 1002 if (maxlvt >= 4) { 1003 v = apic_read(APIC_LVTPC); 1004 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 1005 } 1006 1007 /* lets not touch this if we didn't frob it */ 1008 #ifdef CONFIG_X86_THERMAL_VECTOR 1009 if (maxlvt >= 5) { 1010 v = apic_read(APIC_LVTTHMR); 1011 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 1012 } 1013 #endif 1014 #ifdef CONFIG_X86_MCE_INTEL 1015 if (maxlvt >= 6) { 1016 v = apic_read(APIC_LVTCMCI); 1017 if (!(v & APIC_LVT_MASKED)) 1018 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 1019 } 1020 #endif 1021 1022 /* 1023 * Clean APIC state for other OSs: 1024 */ 1025 apic_write(APIC_LVTT, APIC_LVT_MASKED); 1026 apic_write(APIC_LVT0, APIC_LVT_MASKED); 1027 apic_write(APIC_LVT1, APIC_LVT_MASKED); 1028 if (maxlvt >= 3) 1029 apic_write(APIC_LVTERR, APIC_LVT_MASKED); 1030 if (maxlvt >= 4) 1031 apic_write(APIC_LVTPC, APIC_LVT_MASKED); 1032 1033 /* Integrated APIC (!82489DX) ? */ 1034 if (lapic_is_integrated()) { 1035 if (maxlvt > 3) 1036 /* Clear ESR due to Pentium errata 3AP and 11AP */ 1037 apic_write(APIC_ESR, 0); 1038 apic_read(APIC_ESR); 1039 } 1040 } 1041 1042 /** 1043 * disable_local_APIC - clear and disable the local APIC 1044 */ 1045 void disable_local_APIC(void) 1046 { 1047 unsigned int value; 1048 1049 /* APIC hasn't been mapped yet */ 1050 if (!x2apic_mode && !apic_phys) 1051 return; 1052 1053 clear_local_APIC(); 1054 1055 /* 1056 * Disable APIC (implies clearing of registers 1057 * for 82489DX!). 1058 */ 1059 value = apic_read(APIC_SPIV); 1060 value &= ~APIC_SPIV_APIC_ENABLED; 1061 apic_write(APIC_SPIV, value); 1062 1063 #ifdef CONFIG_X86_32 1064 /* 1065 * When LAPIC was disabled by the BIOS and enabled by the kernel, 1066 * restore the disabled state. 1067 */ 1068 if (enabled_via_apicbase) { 1069 unsigned int l, h; 1070 1071 rdmsr(MSR_IA32_APICBASE, l, h); 1072 l &= ~MSR_IA32_APICBASE_ENABLE; 1073 wrmsr(MSR_IA32_APICBASE, l, h); 1074 } 1075 #endif 1076 } 1077 1078 /* 1079 * If Linux enabled the LAPIC against the BIOS default disable it down before 1080 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 1081 * not power-off. Additionally clear all LVT entries before disable_local_APIC 1082 * for the case where Linux didn't enable the LAPIC. 1083 */ 1084 void lapic_shutdown(void) 1085 { 1086 unsigned long flags; 1087 1088 if (!cpu_has_apic && !apic_from_smp_config()) 1089 return; 1090 1091 local_irq_save(flags); 1092 1093 #ifdef CONFIG_X86_32 1094 if (!enabled_via_apicbase) 1095 clear_local_APIC(); 1096 else 1097 #endif 1098 disable_local_APIC(); 1099 1100 1101 local_irq_restore(flags); 1102 } 1103 1104 /** 1105 * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1106 */ 1107 void __init sync_Arb_IDs(void) 1108 { 1109 /* 1110 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1111 * needed on AMD. 1112 */ 1113 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1114 return; 1115 1116 /* 1117 * Wait for idle. 1118 */ 1119 apic_wait_icr_idle(); 1120 1121 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1122 apic_write(APIC_ICR, APIC_DEST_ALLINC | 1123 APIC_INT_LEVELTRIG | APIC_DM_INIT); 1124 } 1125 1126 /* 1127 * An initial setup of the virtual wire mode. 1128 */ 1129 void __init init_bsp_APIC(void) 1130 { 1131 unsigned int value; 1132 1133 /* 1134 * Don't do the setup now if we have a SMP BIOS as the 1135 * through-I/O-APIC virtual wire mode might be active. 1136 */ 1137 if (smp_found_config || !cpu_has_apic) 1138 return; 1139 1140 /* 1141 * Do not trust the local APIC being empty at bootup. 1142 */ 1143 clear_local_APIC(); 1144 1145 /* 1146 * Enable APIC. 1147 */ 1148 value = apic_read(APIC_SPIV); 1149 value &= ~APIC_VECTOR_MASK; 1150 value |= APIC_SPIV_APIC_ENABLED; 1151 1152 #ifdef CONFIG_X86_32 1153 /* This bit is reserved on P4/Xeon and should be cleared */ 1154 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1155 (boot_cpu_data.x86 == 15)) 1156 value &= ~APIC_SPIV_FOCUS_DISABLED; 1157 else 1158 #endif 1159 value |= APIC_SPIV_FOCUS_DISABLED; 1160 value |= SPURIOUS_APIC_VECTOR; 1161 apic_write(APIC_SPIV, value); 1162 1163 /* 1164 * Set up the virtual wire mode. 1165 */ 1166 apic_write(APIC_LVT0, APIC_DM_EXTINT); 1167 value = APIC_DM_NMI; 1168 if (!lapic_is_integrated()) /* 82489DX */ 1169 value |= APIC_LVT_LEVEL_TRIGGER; 1170 if (apic_extnmi == APIC_EXTNMI_NONE) 1171 value |= APIC_LVT_MASKED; 1172 apic_write(APIC_LVT1, value); 1173 } 1174 1175 static void lapic_setup_esr(void) 1176 { 1177 unsigned int oldvalue, value, maxlvt; 1178 1179 if (!lapic_is_integrated()) { 1180 pr_info("No ESR for 82489DX.\n"); 1181 return; 1182 } 1183 1184 if (apic->disable_esr) { 1185 /* 1186 * Something untraceable is creating bad interrupts on 1187 * secondary quads ... for the moment, just leave the 1188 * ESR disabled - we can't do anything useful with the 1189 * errors anyway - mbligh 1190 */ 1191 pr_info("Leaving ESR disabled.\n"); 1192 return; 1193 } 1194 1195 maxlvt = lapic_get_maxlvt(); 1196 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1197 apic_write(APIC_ESR, 0); 1198 oldvalue = apic_read(APIC_ESR); 1199 1200 /* enables sending errors */ 1201 value = ERROR_APIC_VECTOR; 1202 apic_write(APIC_LVTERR, value); 1203 1204 /* 1205 * spec says clear errors after enabling vector. 1206 */ 1207 if (maxlvt > 3) 1208 apic_write(APIC_ESR, 0); 1209 value = apic_read(APIC_ESR); 1210 if (value != oldvalue) 1211 apic_printk(APIC_VERBOSE, "ESR value before enabling " 1212 "vector: 0x%08x after: 0x%08x\n", 1213 oldvalue, value); 1214 } 1215 1216 /** 1217 * setup_local_APIC - setup the local APIC 1218 * 1219 * Used to setup local APIC while initializing BSP or bringin up APs. 1220 * Always called with preemption disabled. 1221 */ 1222 void setup_local_APIC(void) 1223 { 1224 int cpu = smp_processor_id(); 1225 unsigned int value, queued; 1226 int i, j, acked = 0; 1227 unsigned long long tsc = 0, ntsc; 1228 long long max_loops = cpu_khz ? cpu_khz : 1000000; 1229 1230 if (cpu_has_tsc) 1231 tsc = rdtsc(); 1232 1233 if (disable_apic) { 1234 disable_ioapic_support(); 1235 return; 1236 } 1237 1238 #ifdef CONFIG_X86_32 1239 /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1240 if (lapic_is_integrated() && apic->disable_esr) { 1241 apic_write(APIC_ESR, 0); 1242 apic_write(APIC_ESR, 0); 1243 apic_write(APIC_ESR, 0); 1244 apic_write(APIC_ESR, 0); 1245 } 1246 #endif 1247 perf_events_lapic_init(); 1248 1249 /* 1250 * Double-check whether this APIC is really registered. 1251 * This is meaningless in clustered apic mode, so we skip it. 1252 */ 1253 BUG_ON(!apic->apic_id_registered()); 1254 1255 /* 1256 * Intel recommends to set DFR, LDR and TPR before enabling 1257 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1258 * document number 292116). So here it goes... 1259 */ 1260 apic->init_apic_ldr(); 1261 1262 #ifdef CONFIG_X86_32 1263 /* 1264 * APIC LDR is initialized. If logical_apicid mapping was 1265 * initialized during get_smp_config(), make sure it matches the 1266 * actual value. 1267 */ 1268 i = early_per_cpu(x86_cpu_to_logical_apicid, cpu); 1269 WARN_ON(i != BAD_APICID && i != logical_smp_processor_id()); 1270 /* always use the value from LDR */ 1271 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 1272 logical_smp_processor_id(); 1273 #endif 1274 1275 /* 1276 * Set Task Priority to 'accept all'. We never change this 1277 * later on. 1278 */ 1279 value = apic_read(APIC_TASKPRI); 1280 value &= ~APIC_TPRI_MASK; 1281 apic_write(APIC_TASKPRI, value); 1282 1283 /* 1284 * After a crash, we no longer service the interrupts and a pending 1285 * interrupt from previous kernel might still have ISR bit set. 1286 * 1287 * Most probably by now CPU has serviced that pending interrupt and 1288 * it might not have done the ack_APIC_irq() because it thought, 1289 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it 1290 * does not clear the ISR bit and cpu thinks it has already serivced 1291 * the interrupt. Hence a vector might get locked. It was noticed 1292 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. 1293 */ 1294 do { 1295 queued = 0; 1296 for (i = APIC_ISR_NR - 1; i >= 0; i--) 1297 queued |= apic_read(APIC_IRR + i*0x10); 1298 1299 for (i = APIC_ISR_NR - 1; i >= 0; i--) { 1300 value = apic_read(APIC_ISR + i*0x10); 1301 for (j = 31; j >= 0; j--) { 1302 if (value & (1<<j)) { 1303 ack_APIC_irq(); 1304 acked++; 1305 } 1306 } 1307 } 1308 if (acked > 256) { 1309 printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n", 1310 acked); 1311 break; 1312 } 1313 if (queued) { 1314 if (cpu_has_tsc && cpu_khz) { 1315 ntsc = rdtsc(); 1316 max_loops = (cpu_khz << 10) - (ntsc - tsc); 1317 } else 1318 max_loops--; 1319 } 1320 } while (queued && max_loops > 0); 1321 WARN_ON(max_loops <= 0); 1322 1323 /* 1324 * Now that we are all set up, enable the APIC 1325 */ 1326 value = apic_read(APIC_SPIV); 1327 value &= ~APIC_VECTOR_MASK; 1328 /* 1329 * Enable APIC 1330 */ 1331 value |= APIC_SPIV_APIC_ENABLED; 1332 1333 #ifdef CONFIG_X86_32 1334 /* 1335 * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1336 * certain networking cards. If high frequency interrupts are 1337 * happening on a particular IOAPIC pin, plus the IOAPIC routing 1338 * entry is masked/unmasked at a high rate as well then sooner or 1339 * later IOAPIC line gets 'stuck', no more interrupts are received 1340 * from the device. If focus CPU is disabled then the hang goes 1341 * away, oh well :-( 1342 * 1343 * [ This bug can be reproduced easily with a level-triggered 1344 * PCI Ne2000 networking cards and PII/PIII processors, dual 1345 * BX chipset. ] 1346 */ 1347 /* 1348 * Actually disabling the focus CPU check just makes the hang less 1349 * frequent as it makes the interrupt distributon model be more 1350 * like LRU than MRU (the short-term load is more even across CPUs). 1351 * See also the comment in end_level_ioapic_irq(). --macro 1352 */ 1353 1354 /* 1355 * - enable focus processor (bit==0) 1356 * - 64bit mode always use processor focus 1357 * so no need to set it 1358 */ 1359 value &= ~APIC_SPIV_FOCUS_DISABLED; 1360 #endif 1361 1362 /* 1363 * Set spurious IRQ vector 1364 */ 1365 value |= SPURIOUS_APIC_VECTOR; 1366 apic_write(APIC_SPIV, value); 1367 1368 /* 1369 * Set up LVT0, LVT1: 1370 * 1371 * set up through-local-APIC on the BP's LINT0. This is not 1372 * strictly necessary in pure symmetric-IO mode, but sometimes 1373 * we delegate interrupts to the 8259A. 1374 */ 1375 /* 1376 * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1377 */ 1378 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 1379 if (!cpu && (pic_mode || !value)) { 1380 value = APIC_DM_EXTINT; 1381 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); 1382 } else { 1383 value = APIC_DM_EXTINT | APIC_LVT_MASKED; 1384 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); 1385 } 1386 apic_write(APIC_LVT0, value); 1387 1388 /* 1389 * Only the BSP sees the LINT1 NMI signal by default. This can be 1390 * modified by apic_extnmi= boot option. 1391 */ 1392 if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) || 1393 apic_extnmi == APIC_EXTNMI_ALL) 1394 value = APIC_DM_NMI; 1395 else 1396 value = APIC_DM_NMI | APIC_LVT_MASKED; 1397 if (!lapic_is_integrated()) /* 82489DX */ 1398 value |= APIC_LVT_LEVEL_TRIGGER; 1399 apic_write(APIC_LVT1, value); 1400 1401 #ifdef CONFIG_X86_MCE_INTEL 1402 /* Recheck CMCI information after local APIC is up on CPU #0 */ 1403 if (!cpu) 1404 cmci_recheck(); 1405 #endif 1406 } 1407 1408 static void end_local_APIC_setup(void) 1409 { 1410 lapic_setup_esr(); 1411 1412 #ifdef CONFIG_X86_32 1413 { 1414 unsigned int value; 1415 /* Disable the local apic timer */ 1416 value = apic_read(APIC_LVTT); 1417 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1418 apic_write(APIC_LVTT, value); 1419 } 1420 #endif 1421 1422 apic_pm_activate(); 1423 } 1424 1425 /* 1426 * APIC setup function for application processors. Called from smpboot.c 1427 */ 1428 void apic_ap_setup(void) 1429 { 1430 setup_local_APIC(); 1431 end_local_APIC_setup(); 1432 } 1433 1434 #ifdef CONFIG_X86_X2APIC 1435 int x2apic_mode; 1436 1437 enum { 1438 X2APIC_OFF, 1439 X2APIC_ON, 1440 X2APIC_DISABLED, 1441 }; 1442 static int x2apic_state; 1443 1444 static void __x2apic_disable(void) 1445 { 1446 u64 msr; 1447 1448 if (!cpu_has_apic) 1449 return; 1450 1451 rdmsrl(MSR_IA32_APICBASE, msr); 1452 if (!(msr & X2APIC_ENABLE)) 1453 return; 1454 /* Disable xapic and x2apic first and then reenable xapic mode */ 1455 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); 1456 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); 1457 printk_once(KERN_INFO "x2apic disabled\n"); 1458 } 1459 1460 static void __x2apic_enable(void) 1461 { 1462 u64 msr; 1463 1464 rdmsrl(MSR_IA32_APICBASE, msr); 1465 if (msr & X2APIC_ENABLE) 1466 return; 1467 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); 1468 printk_once(KERN_INFO "x2apic enabled\n"); 1469 } 1470 1471 static int __init setup_nox2apic(char *str) 1472 { 1473 if (x2apic_enabled()) { 1474 int apicid = native_apic_msr_read(APIC_ID); 1475 1476 if (apicid >= 255) { 1477 pr_warning("Apicid: %08x, cannot enforce nox2apic\n", 1478 apicid); 1479 return 0; 1480 } 1481 pr_warning("x2apic already enabled.\n"); 1482 __x2apic_disable(); 1483 } 1484 setup_clear_cpu_cap(X86_FEATURE_X2APIC); 1485 x2apic_state = X2APIC_DISABLED; 1486 x2apic_mode = 0; 1487 return 0; 1488 } 1489 early_param("nox2apic", setup_nox2apic); 1490 1491 /* Called from cpu_init() to enable x2apic on (secondary) cpus */ 1492 void x2apic_setup(void) 1493 { 1494 /* 1495 * If x2apic is not in ON state, disable it if already enabled 1496 * from BIOS. 1497 */ 1498 if (x2apic_state != X2APIC_ON) { 1499 __x2apic_disable(); 1500 return; 1501 } 1502 __x2apic_enable(); 1503 } 1504 1505 static __init void x2apic_disable(void) 1506 { 1507 u32 x2apic_id, state = x2apic_state; 1508 1509 x2apic_mode = 0; 1510 x2apic_state = X2APIC_DISABLED; 1511 1512 if (state != X2APIC_ON) 1513 return; 1514 1515 x2apic_id = read_apic_id(); 1516 if (x2apic_id >= 255) 1517 panic("Cannot disable x2apic, id: %08x\n", x2apic_id); 1518 1519 __x2apic_disable(); 1520 register_lapic_address(mp_lapic_addr); 1521 } 1522 1523 static __init void x2apic_enable(void) 1524 { 1525 if (x2apic_state != X2APIC_OFF) 1526 return; 1527 1528 x2apic_mode = 1; 1529 x2apic_state = X2APIC_ON; 1530 __x2apic_enable(); 1531 } 1532 1533 static __init void try_to_enable_x2apic(int remap_mode) 1534 { 1535 if (x2apic_state == X2APIC_DISABLED) 1536 return; 1537 1538 if (remap_mode != IRQ_REMAP_X2APIC_MODE) { 1539 /* IR is required if there is APIC ID > 255 even when running 1540 * under KVM 1541 */ 1542 if (max_physical_apicid > 255 || 1543 !hypervisor_x2apic_available()) { 1544 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n"); 1545 x2apic_disable(); 1546 return; 1547 } 1548 1549 /* 1550 * without IR all CPUs can be addressed by IOAPIC/MSI 1551 * only in physical mode 1552 */ 1553 x2apic_phys = 1; 1554 } 1555 x2apic_enable(); 1556 } 1557 1558 void __init check_x2apic(void) 1559 { 1560 if (x2apic_enabled()) { 1561 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n"); 1562 x2apic_mode = 1; 1563 x2apic_state = X2APIC_ON; 1564 } else if (!cpu_has_x2apic) { 1565 x2apic_state = X2APIC_DISABLED; 1566 } 1567 } 1568 #else /* CONFIG_X86_X2APIC */ 1569 static int __init validate_x2apic(void) 1570 { 1571 if (!apic_is_x2apic_enabled()) 1572 return 0; 1573 /* 1574 * Checkme: Can we simply turn off x2apic here instead of panic? 1575 */ 1576 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n"); 1577 } 1578 early_initcall(validate_x2apic); 1579 1580 static inline void try_to_enable_x2apic(int remap_mode) { } 1581 static inline void __x2apic_enable(void) { } 1582 #endif /* !CONFIG_X86_X2APIC */ 1583 1584 static int __init try_to_enable_IR(void) 1585 { 1586 #ifdef CONFIG_X86_IO_APIC 1587 if (!x2apic_enabled() && skip_ioapic_setup) { 1588 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n"); 1589 return -1; 1590 } 1591 #endif 1592 return irq_remapping_enable(); 1593 } 1594 1595 void __init enable_IR_x2apic(void) 1596 { 1597 unsigned long flags; 1598 int ret, ir_stat; 1599 1600 ir_stat = irq_remapping_prepare(); 1601 if (ir_stat < 0 && !x2apic_supported()) 1602 return; 1603 1604 ret = save_ioapic_entries(); 1605 if (ret) { 1606 pr_info("Saving IO-APIC state failed: %d\n", ret); 1607 return; 1608 } 1609 1610 local_irq_save(flags); 1611 legacy_pic->mask_all(); 1612 mask_ioapic_entries(); 1613 1614 /* If irq_remapping_prepare() succeded, try to enable it */ 1615 if (ir_stat >= 0) 1616 ir_stat = try_to_enable_IR(); 1617 /* ir_stat contains the remap mode or an error code */ 1618 try_to_enable_x2apic(ir_stat); 1619 1620 if (ir_stat < 0) 1621 restore_ioapic_entries(); 1622 legacy_pic->restore_mask(); 1623 local_irq_restore(flags); 1624 } 1625 1626 #ifdef CONFIG_X86_64 1627 /* 1628 * Detect and enable local APICs on non-SMP boards. 1629 * Original code written by Keir Fraser. 1630 * On AMD64 we trust the BIOS - if it says no APIC it is likely 1631 * not correctly set up (usually the APIC timer won't work etc.) 1632 */ 1633 static int __init detect_init_APIC(void) 1634 { 1635 if (!cpu_has_apic) { 1636 pr_info("No local APIC present\n"); 1637 return -1; 1638 } 1639 1640 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1641 return 0; 1642 } 1643 #else 1644 1645 static int __init apic_verify(void) 1646 { 1647 u32 features, h, l; 1648 1649 /* 1650 * The APIC feature bit should now be enabled 1651 * in `cpuid' 1652 */ 1653 features = cpuid_edx(1); 1654 if (!(features & (1 << X86_FEATURE_APIC))) { 1655 pr_warning("Could not enable APIC!\n"); 1656 return -1; 1657 } 1658 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 1659 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1660 1661 /* The BIOS may have set up the APIC at some other address */ 1662 if (boot_cpu_data.x86 >= 6) { 1663 rdmsr(MSR_IA32_APICBASE, l, h); 1664 if (l & MSR_IA32_APICBASE_ENABLE) 1665 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 1666 } 1667 1668 pr_info("Found and enabled local APIC!\n"); 1669 return 0; 1670 } 1671 1672 int __init apic_force_enable(unsigned long addr) 1673 { 1674 u32 h, l; 1675 1676 if (disable_apic) 1677 return -1; 1678 1679 /* 1680 * Some BIOSes disable the local APIC in the APIC_BASE 1681 * MSR. This can only be done in software for Intel P6 or later 1682 * and AMD K7 (Model > 1) or later. 1683 */ 1684 if (boot_cpu_data.x86 >= 6) { 1685 rdmsr(MSR_IA32_APICBASE, l, h); 1686 if (!(l & MSR_IA32_APICBASE_ENABLE)) { 1687 pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 1688 l &= ~MSR_IA32_APICBASE_BASE; 1689 l |= MSR_IA32_APICBASE_ENABLE | addr; 1690 wrmsr(MSR_IA32_APICBASE, l, h); 1691 enabled_via_apicbase = 1; 1692 } 1693 } 1694 return apic_verify(); 1695 } 1696 1697 /* 1698 * Detect and initialize APIC 1699 */ 1700 static int __init detect_init_APIC(void) 1701 { 1702 /* Disabled by kernel option? */ 1703 if (disable_apic) 1704 return -1; 1705 1706 switch (boot_cpu_data.x86_vendor) { 1707 case X86_VENDOR_AMD: 1708 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 1709 (boot_cpu_data.x86 >= 15)) 1710 break; 1711 goto no_apic; 1712 case X86_VENDOR_INTEL: 1713 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 1714 (boot_cpu_data.x86 == 5 && cpu_has_apic)) 1715 break; 1716 goto no_apic; 1717 default: 1718 goto no_apic; 1719 } 1720 1721 if (!cpu_has_apic) { 1722 /* 1723 * Over-ride BIOS and try to enable the local APIC only if 1724 * "lapic" specified. 1725 */ 1726 if (!force_enable_local_apic) { 1727 pr_info("Local APIC disabled by BIOS -- " 1728 "you can enable it with \"lapic\"\n"); 1729 return -1; 1730 } 1731 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) 1732 return -1; 1733 } else { 1734 if (apic_verify()) 1735 return -1; 1736 } 1737 1738 apic_pm_activate(); 1739 1740 return 0; 1741 1742 no_apic: 1743 pr_info("No local APIC present or hardware disabled\n"); 1744 return -1; 1745 } 1746 #endif 1747 1748 /** 1749 * init_apic_mappings - initialize APIC mappings 1750 */ 1751 void __init init_apic_mappings(void) 1752 { 1753 unsigned int new_apicid; 1754 1755 if (x2apic_mode) { 1756 boot_cpu_physical_apicid = read_apic_id(); 1757 return; 1758 } 1759 1760 /* If no local APIC can be found return early */ 1761 if (!smp_found_config && detect_init_APIC()) { 1762 /* lets NOP'ify apic operations */ 1763 pr_info("APIC: disable apic facility\n"); 1764 apic_disable(); 1765 } else { 1766 apic_phys = mp_lapic_addr; 1767 1768 /* 1769 * acpi lapic path already maps that address in 1770 * acpi_register_lapic_address() 1771 */ 1772 if (!acpi_lapic && !smp_found_config) 1773 register_lapic_address(apic_phys); 1774 } 1775 1776 /* 1777 * Fetch the APIC ID of the BSP in case we have a 1778 * default configuration (or the MP table is broken). 1779 */ 1780 new_apicid = read_apic_id(); 1781 if (boot_cpu_physical_apicid != new_apicid) { 1782 boot_cpu_physical_apicid = new_apicid; 1783 /* 1784 * yeah -- we lie about apic_version 1785 * in case if apic was disabled via boot option 1786 * but it's not a problem for SMP compiled kernel 1787 * since smp_sanity_check is prepared for such a case 1788 * and disable smp mode 1789 */ 1790 apic_version[new_apicid] = 1791 GET_APIC_VERSION(apic_read(APIC_LVR)); 1792 } 1793 } 1794 1795 void __init register_lapic_address(unsigned long address) 1796 { 1797 mp_lapic_addr = address; 1798 1799 if (!x2apic_mode) { 1800 set_fixmap_nocache(FIX_APIC_BASE, address); 1801 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 1802 APIC_BASE, mp_lapic_addr); 1803 } 1804 if (boot_cpu_physical_apicid == -1U) { 1805 boot_cpu_physical_apicid = read_apic_id(); 1806 apic_version[boot_cpu_physical_apicid] = 1807 GET_APIC_VERSION(apic_read(APIC_LVR)); 1808 } 1809 } 1810 1811 int apic_version[MAX_LOCAL_APIC]; 1812 1813 /* 1814 * Local APIC interrupts 1815 */ 1816 1817 /* 1818 * This interrupt should _never_ happen with our APIC/SMP architecture 1819 */ 1820 static void __smp_spurious_interrupt(u8 vector) 1821 { 1822 u32 v; 1823 1824 /* 1825 * Check if this really is a spurious interrupt and ACK it 1826 * if it is a vectored one. Just in case... 1827 * Spurious interrupts should not be ACKed. 1828 */ 1829 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1)); 1830 if (v & (1 << (vector & 0x1f))) 1831 ack_APIC_irq(); 1832 1833 inc_irq_stat(irq_spurious_count); 1834 1835 /* see sw-dev-man vol 3, chapter 7.4.13.5 */ 1836 pr_info("spurious APIC interrupt through vector %02x on CPU#%d, " 1837 "should never happen.\n", vector, smp_processor_id()); 1838 } 1839 1840 __visible void smp_spurious_interrupt(struct pt_regs *regs) 1841 { 1842 entering_irq(); 1843 __smp_spurious_interrupt(~regs->orig_ax); 1844 exiting_irq(); 1845 } 1846 1847 __visible void smp_trace_spurious_interrupt(struct pt_regs *regs) 1848 { 1849 u8 vector = ~regs->orig_ax; 1850 1851 entering_irq(); 1852 trace_spurious_apic_entry(vector); 1853 __smp_spurious_interrupt(vector); 1854 trace_spurious_apic_exit(vector); 1855 exiting_irq(); 1856 } 1857 1858 /* 1859 * This interrupt should never happen with our APIC/SMP architecture 1860 */ 1861 static void __smp_error_interrupt(struct pt_regs *regs) 1862 { 1863 u32 v; 1864 u32 i = 0; 1865 static const char * const error_interrupt_reason[] = { 1866 "Send CS error", /* APIC Error Bit 0 */ 1867 "Receive CS error", /* APIC Error Bit 1 */ 1868 "Send accept error", /* APIC Error Bit 2 */ 1869 "Receive accept error", /* APIC Error Bit 3 */ 1870 "Redirectable IPI", /* APIC Error Bit 4 */ 1871 "Send illegal vector", /* APIC Error Bit 5 */ 1872 "Received illegal vector", /* APIC Error Bit 6 */ 1873 "Illegal register address", /* APIC Error Bit 7 */ 1874 }; 1875 1876 /* First tickle the hardware, only then report what went on. -- REW */ 1877 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */ 1878 apic_write(APIC_ESR, 0); 1879 v = apic_read(APIC_ESR); 1880 ack_APIC_irq(); 1881 atomic_inc(&irq_err_count); 1882 1883 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x", 1884 smp_processor_id(), v); 1885 1886 v &= 0xff; 1887 while (v) { 1888 if (v & 0x1) 1889 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); 1890 i++; 1891 v >>= 1; 1892 } 1893 1894 apic_printk(APIC_DEBUG, KERN_CONT "\n"); 1895 1896 } 1897 1898 __visible void smp_error_interrupt(struct pt_regs *regs) 1899 { 1900 entering_irq(); 1901 __smp_error_interrupt(regs); 1902 exiting_irq(); 1903 } 1904 1905 __visible void smp_trace_error_interrupt(struct pt_regs *regs) 1906 { 1907 entering_irq(); 1908 trace_error_apic_entry(ERROR_APIC_VECTOR); 1909 __smp_error_interrupt(regs); 1910 trace_error_apic_exit(ERROR_APIC_VECTOR); 1911 exiting_irq(); 1912 } 1913 1914 /** 1915 * connect_bsp_APIC - attach the APIC to the interrupt system 1916 */ 1917 static void __init connect_bsp_APIC(void) 1918 { 1919 #ifdef CONFIG_X86_32 1920 if (pic_mode) { 1921 /* 1922 * Do not trust the local APIC being empty at bootup. 1923 */ 1924 clear_local_APIC(); 1925 /* 1926 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 1927 * local APIC to INT and NMI lines. 1928 */ 1929 apic_printk(APIC_VERBOSE, "leaving PIC mode, " 1930 "enabling APIC mode.\n"); 1931 imcr_pic_to_apic(); 1932 } 1933 #endif 1934 } 1935 1936 /** 1937 * disconnect_bsp_APIC - detach the APIC from the interrupt system 1938 * @virt_wire_setup: indicates, whether virtual wire mode is selected 1939 * 1940 * Virtual wire mode is necessary to deliver legacy interrupts even when the 1941 * APIC is disabled. 1942 */ 1943 void disconnect_bsp_APIC(int virt_wire_setup) 1944 { 1945 unsigned int value; 1946 1947 #ifdef CONFIG_X86_32 1948 if (pic_mode) { 1949 /* 1950 * Put the board back into PIC mode (has an effect only on 1951 * certain older boards). Note that APIC interrupts, including 1952 * IPIs, won't work beyond this point! The only exception are 1953 * INIT IPIs. 1954 */ 1955 apic_printk(APIC_VERBOSE, "disabling APIC mode, " 1956 "entering PIC mode.\n"); 1957 imcr_apic_to_pic(); 1958 return; 1959 } 1960 #endif 1961 1962 /* Go back to Virtual Wire compatibility mode */ 1963 1964 /* For the spurious interrupt use vector F, and enable it */ 1965 value = apic_read(APIC_SPIV); 1966 value &= ~APIC_VECTOR_MASK; 1967 value |= APIC_SPIV_APIC_ENABLED; 1968 value |= 0xf; 1969 apic_write(APIC_SPIV, value); 1970 1971 if (!virt_wire_setup) { 1972 /* 1973 * For LVT0 make it edge triggered, active high, 1974 * external and enabled 1975 */ 1976 value = apic_read(APIC_LVT0); 1977 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 1978 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 1979 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 1980 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 1981 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 1982 apic_write(APIC_LVT0, value); 1983 } else { 1984 /* Disable LVT0 */ 1985 apic_write(APIC_LVT0, APIC_LVT_MASKED); 1986 } 1987 1988 /* 1989 * For LVT1 make it edge triggered, active high, 1990 * nmi and enabled 1991 */ 1992 value = apic_read(APIC_LVT1); 1993 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 1994 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 1995 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 1996 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 1997 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 1998 apic_write(APIC_LVT1, value); 1999 } 2000 2001 int generic_processor_info(int apicid, int version) 2002 { 2003 int cpu, max = nr_cpu_ids; 2004 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, 2005 phys_cpu_present_map); 2006 2007 /* 2008 * boot_cpu_physical_apicid is designed to have the apicid 2009 * returned by read_apic_id(), i.e, the apicid of the 2010 * currently booting-up processor. However, on some platforms, 2011 * it is temporarily modified by the apicid reported as BSP 2012 * through MP table. Concretely: 2013 * 2014 * - arch/x86/kernel/mpparse.c: MP_processor_info() 2015 * - arch/x86/mm/amdtopology.c: amd_numa_init() 2016 * 2017 * This function is executed with the modified 2018 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel 2019 * parameter doesn't work to disable APs on kdump 2nd kernel. 2020 * 2021 * Since fixing handling of boot_cpu_physical_apicid requires 2022 * another discussion and tests on each platform, we leave it 2023 * for now and here we use read_apic_id() directly in this 2024 * function, generic_processor_info(). 2025 */ 2026 if (disabled_cpu_apicid != BAD_APICID && 2027 disabled_cpu_apicid != read_apic_id() && 2028 disabled_cpu_apicid == apicid) { 2029 int thiscpu = num_processors + disabled_cpus; 2030 2031 pr_warning("APIC: Disabling requested cpu." 2032 " Processor %d/0x%x ignored.\n", 2033 thiscpu, apicid); 2034 2035 disabled_cpus++; 2036 return -ENODEV; 2037 } 2038 2039 /* 2040 * If boot cpu has not been detected yet, then only allow upto 2041 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu 2042 */ 2043 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && 2044 apicid != boot_cpu_physical_apicid) { 2045 int thiscpu = max + disabled_cpus - 1; 2046 2047 pr_warning( 2048 "ACPI: NR_CPUS/possible_cpus limit of %i almost" 2049 " reached. Keeping one slot for boot cpu." 2050 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 2051 2052 disabled_cpus++; 2053 return -ENODEV; 2054 } 2055 2056 if (num_processors >= nr_cpu_ids) { 2057 int thiscpu = max + disabled_cpus; 2058 2059 pr_warning( 2060 "ACPI: NR_CPUS/possible_cpus limit of %i reached." 2061 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 2062 2063 disabled_cpus++; 2064 return -EINVAL; 2065 } 2066 2067 num_processors++; 2068 if (apicid == boot_cpu_physical_apicid) { 2069 /* 2070 * x86_bios_cpu_apicid is required to have processors listed 2071 * in same order as logical cpu numbers. Hence the first 2072 * entry is BSP, and so on. 2073 * boot_cpu_init() already hold bit 0 in cpu_present_mask 2074 * for BSP. 2075 */ 2076 cpu = 0; 2077 } else 2078 cpu = cpumask_next_zero(-1, cpu_present_mask); 2079 2080 /* 2081 * Validate version 2082 */ 2083 if (version == 0x0) { 2084 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", 2085 cpu, apicid); 2086 version = 0x10; 2087 } 2088 apic_version[apicid] = version; 2089 2090 if (version != apic_version[boot_cpu_physical_apicid]) { 2091 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", 2092 apic_version[boot_cpu_physical_apicid], cpu, version); 2093 } 2094 2095 physid_set(apicid, phys_cpu_present_map); 2096 if (apicid > max_physical_apicid) 2097 max_physical_apicid = apicid; 2098 2099 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 2100 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 2101 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 2102 #endif 2103 #ifdef CONFIG_X86_32 2104 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 2105 apic->x86_32_early_logical_apicid(cpu); 2106 #endif 2107 set_cpu_possible(cpu, true); 2108 set_cpu_present(cpu, true); 2109 2110 return cpu; 2111 } 2112 2113 int hard_smp_processor_id(void) 2114 { 2115 return read_apic_id(); 2116 } 2117 2118 void default_init_apic_ldr(void) 2119 { 2120 unsigned long val; 2121 2122 apic_write(APIC_DFR, APIC_DFR_VALUE); 2123 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; 2124 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); 2125 apic_write(APIC_LDR, val); 2126 } 2127 2128 int default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 2129 const struct cpumask *andmask, 2130 unsigned int *apicid) 2131 { 2132 unsigned int cpu; 2133 2134 for_each_cpu_and(cpu, cpumask, andmask) { 2135 if (cpumask_test_cpu(cpu, cpu_online_mask)) 2136 break; 2137 } 2138 2139 if (likely(cpu < nr_cpu_ids)) { 2140 *apicid = per_cpu(x86_cpu_to_apicid, cpu); 2141 return 0; 2142 } 2143 2144 return -EINVAL; 2145 } 2146 2147 /* 2148 * Override the generic EOI implementation with an optimized version. 2149 * Only called during early boot when only one CPU is active and with 2150 * interrupts disabled, so we know this does not race with actual APIC driver 2151 * use. 2152 */ 2153 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) 2154 { 2155 struct apic **drv; 2156 2157 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { 2158 /* Should happen once for each apic */ 2159 WARN_ON((*drv)->eoi_write == eoi_write); 2160 (*drv)->eoi_write = eoi_write; 2161 } 2162 } 2163 2164 static void __init apic_bsp_up_setup(void) 2165 { 2166 #ifdef CONFIG_X86_64 2167 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); 2168 #else 2169 /* 2170 * Hack: In case of kdump, after a crash, kernel might be booting 2171 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 2172 * might be zero if read from MP tables. Get it from LAPIC. 2173 */ 2174 # ifdef CONFIG_CRASH_DUMP 2175 boot_cpu_physical_apicid = read_apic_id(); 2176 # endif 2177 #endif 2178 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 2179 } 2180 2181 /** 2182 * apic_bsp_setup - Setup function for local apic and io-apic 2183 * @upmode: Force UP mode (for APIC_init_uniprocessor) 2184 * 2185 * Returns: 2186 * apic_id of BSP APIC 2187 */ 2188 int __init apic_bsp_setup(bool upmode) 2189 { 2190 int id; 2191 2192 connect_bsp_APIC(); 2193 if (upmode) 2194 apic_bsp_up_setup(); 2195 setup_local_APIC(); 2196 2197 if (x2apic_mode) 2198 id = apic_read(APIC_LDR); 2199 else 2200 id = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 2201 2202 enable_IO_APIC(); 2203 end_local_APIC_setup(); 2204 irq_remap_enable_fault_handling(); 2205 setup_IO_APIC(); 2206 /* Setup local timer */ 2207 x86_init.timers.setup_percpu_clockev(); 2208 return id; 2209 } 2210 2211 /* 2212 * This initializes the IO-APIC and APIC hardware if this is 2213 * a UP kernel. 2214 */ 2215 int __init APIC_init_uniprocessor(void) 2216 { 2217 if (disable_apic) { 2218 pr_info("Apic disabled\n"); 2219 return -1; 2220 } 2221 #ifdef CONFIG_X86_64 2222 if (!cpu_has_apic) { 2223 disable_apic = 1; 2224 pr_info("Apic disabled by BIOS\n"); 2225 return -1; 2226 } 2227 #else 2228 if (!smp_found_config && !cpu_has_apic) 2229 return -1; 2230 2231 /* 2232 * Complain if the BIOS pretends there is one. 2233 */ 2234 if (!cpu_has_apic && 2235 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 2236 pr_err("BIOS bug, local APIC 0x%x not detected!...\n", 2237 boot_cpu_physical_apicid); 2238 return -1; 2239 } 2240 #endif 2241 2242 if (!smp_found_config) 2243 disable_ioapic_support(); 2244 2245 default_setup_apic_routing(); 2246 apic_bsp_setup(true); 2247 return 0; 2248 } 2249 2250 #ifdef CONFIG_UP_LATE_INIT 2251 void __init up_late_init(void) 2252 { 2253 APIC_init_uniprocessor(); 2254 } 2255 #endif 2256 2257 /* 2258 * Power management 2259 */ 2260 #ifdef CONFIG_PM 2261 2262 static struct { 2263 /* 2264 * 'active' is true if the local APIC was enabled by us and 2265 * not the BIOS; this signifies that we are also responsible 2266 * for disabling it before entering apm/acpi suspend 2267 */ 2268 int active; 2269 /* r/w apic fields */ 2270 unsigned int apic_id; 2271 unsigned int apic_taskpri; 2272 unsigned int apic_ldr; 2273 unsigned int apic_dfr; 2274 unsigned int apic_spiv; 2275 unsigned int apic_lvtt; 2276 unsigned int apic_lvtpc; 2277 unsigned int apic_lvt0; 2278 unsigned int apic_lvt1; 2279 unsigned int apic_lvterr; 2280 unsigned int apic_tmict; 2281 unsigned int apic_tdcr; 2282 unsigned int apic_thmr; 2283 unsigned int apic_cmci; 2284 } apic_pm_state; 2285 2286 static int lapic_suspend(void) 2287 { 2288 unsigned long flags; 2289 int maxlvt; 2290 2291 if (!apic_pm_state.active) 2292 return 0; 2293 2294 maxlvt = lapic_get_maxlvt(); 2295 2296 apic_pm_state.apic_id = apic_read(APIC_ID); 2297 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 2298 apic_pm_state.apic_ldr = apic_read(APIC_LDR); 2299 apic_pm_state.apic_dfr = apic_read(APIC_DFR); 2300 apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2301 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2302 if (maxlvt >= 4) 2303 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2304 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2305 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2306 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2307 apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2308 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 2309 #ifdef CONFIG_X86_THERMAL_VECTOR 2310 if (maxlvt >= 5) 2311 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2312 #endif 2313 #ifdef CONFIG_X86_MCE_INTEL 2314 if (maxlvt >= 6) 2315 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI); 2316 #endif 2317 2318 local_irq_save(flags); 2319 disable_local_APIC(); 2320 2321 irq_remapping_disable(); 2322 2323 local_irq_restore(flags); 2324 return 0; 2325 } 2326 2327 static void lapic_resume(void) 2328 { 2329 unsigned int l, h; 2330 unsigned long flags; 2331 int maxlvt; 2332 2333 if (!apic_pm_state.active) 2334 return; 2335 2336 local_irq_save(flags); 2337 2338 /* 2339 * IO-APIC and PIC have their own resume routines. 2340 * We just mask them here to make sure the interrupt 2341 * subsystem is completely quiet while we enable x2apic 2342 * and interrupt-remapping. 2343 */ 2344 mask_ioapic_entries(); 2345 legacy_pic->mask_all(); 2346 2347 if (x2apic_mode) { 2348 __x2apic_enable(); 2349 } else { 2350 /* 2351 * Make sure the APICBASE points to the right address 2352 * 2353 * FIXME! This will be wrong if we ever support suspend on 2354 * SMP! We'll need to do this as part of the CPU restore! 2355 */ 2356 if (boot_cpu_data.x86 >= 6) { 2357 rdmsr(MSR_IA32_APICBASE, l, h); 2358 l &= ~MSR_IA32_APICBASE_BASE; 2359 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2360 wrmsr(MSR_IA32_APICBASE, l, h); 2361 } 2362 } 2363 2364 maxlvt = lapic_get_maxlvt(); 2365 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2366 apic_write(APIC_ID, apic_pm_state.apic_id); 2367 apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2368 apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2369 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2370 apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2371 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2372 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 2373 #ifdef CONFIG_X86_THERMAL_VECTOR 2374 if (maxlvt >= 5) 2375 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2376 #endif 2377 #ifdef CONFIG_X86_MCE_INTEL 2378 if (maxlvt >= 6) 2379 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci); 2380 #endif 2381 if (maxlvt >= 4) 2382 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2383 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2384 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2385 apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2386 apic_write(APIC_ESR, 0); 2387 apic_read(APIC_ESR); 2388 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2389 apic_write(APIC_ESR, 0); 2390 apic_read(APIC_ESR); 2391 2392 irq_remapping_reenable(x2apic_mode); 2393 2394 local_irq_restore(flags); 2395 } 2396 2397 /* 2398 * This device has no shutdown method - fully functioning local APICs 2399 * are needed on every CPU up until machine_halt/restart/poweroff. 2400 */ 2401 2402 static struct syscore_ops lapic_syscore_ops = { 2403 .resume = lapic_resume, 2404 .suspend = lapic_suspend, 2405 }; 2406 2407 static void apic_pm_activate(void) 2408 { 2409 apic_pm_state.active = 1; 2410 } 2411 2412 static int __init init_lapic_sysfs(void) 2413 { 2414 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 2415 if (cpu_has_apic) 2416 register_syscore_ops(&lapic_syscore_ops); 2417 2418 return 0; 2419 } 2420 2421 /* local apic needs to resume before other devices access its registers. */ 2422 core_initcall(init_lapic_sysfs); 2423 2424 #else /* CONFIG_PM */ 2425 2426 static void apic_pm_activate(void) { } 2427 2428 #endif /* CONFIG_PM */ 2429 2430 #ifdef CONFIG_X86_64 2431 2432 static int multi_checked; 2433 static int multi; 2434 2435 static int set_multi(const struct dmi_system_id *d) 2436 { 2437 if (multi) 2438 return 0; 2439 pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2440 multi = 1; 2441 return 0; 2442 } 2443 2444 static const struct dmi_system_id multi_dmi_table[] = { 2445 { 2446 .callback = set_multi, 2447 .ident = "IBM System Summit2", 2448 .matches = { 2449 DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2450 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2451 }, 2452 }, 2453 {} 2454 }; 2455 2456 static void dmi_check_multi(void) 2457 { 2458 if (multi_checked) 2459 return; 2460 2461 dmi_check_system(multi_dmi_table); 2462 multi_checked = 1; 2463 } 2464 2465 /* 2466 * apic_is_clustered_box() -- Check if we can expect good TSC 2467 * 2468 * Thus far, the major user of this is IBM's Summit2 series: 2469 * Clustered boxes may have unsynced TSC problems if they are 2470 * multi-chassis. 2471 * Use DMI to check them 2472 */ 2473 int apic_is_clustered_box(void) 2474 { 2475 dmi_check_multi(); 2476 return multi; 2477 } 2478 #endif 2479 2480 /* 2481 * APIC command line parameters 2482 */ 2483 static int __init setup_disableapic(char *arg) 2484 { 2485 disable_apic = 1; 2486 setup_clear_cpu_cap(X86_FEATURE_APIC); 2487 return 0; 2488 } 2489 early_param("disableapic", setup_disableapic); 2490 2491 /* same as disableapic, for compatibility */ 2492 static int __init setup_nolapic(char *arg) 2493 { 2494 return setup_disableapic(arg); 2495 } 2496 early_param("nolapic", setup_nolapic); 2497 2498 static int __init parse_lapic_timer_c2_ok(char *arg) 2499 { 2500 local_apic_timer_c2_ok = 1; 2501 return 0; 2502 } 2503 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2504 2505 static int __init parse_disable_apic_timer(char *arg) 2506 { 2507 disable_apic_timer = 1; 2508 return 0; 2509 } 2510 early_param("noapictimer", parse_disable_apic_timer); 2511 2512 static int __init parse_nolapic_timer(char *arg) 2513 { 2514 disable_apic_timer = 1; 2515 return 0; 2516 } 2517 early_param("nolapic_timer", parse_nolapic_timer); 2518 2519 static int __init apic_set_verbosity(char *arg) 2520 { 2521 if (!arg) { 2522 #ifdef CONFIG_X86_64 2523 skip_ioapic_setup = 0; 2524 return 0; 2525 #endif 2526 return -EINVAL; 2527 } 2528 2529 if (strcmp("debug", arg) == 0) 2530 apic_verbosity = APIC_DEBUG; 2531 else if (strcmp("verbose", arg) == 0) 2532 apic_verbosity = APIC_VERBOSE; 2533 else { 2534 pr_warning("APIC Verbosity level %s not recognised" 2535 " use apic=verbose or apic=debug\n", arg); 2536 return -EINVAL; 2537 } 2538 2539 return 0; 2540 } 2541 early_param("apic", apic_set_verbosity); 2542 2543 static int __init lapic_insert_resource(void) 2544 { 2545 if (!apic_phys) 2546 return -1; 2547 2548 /* Put local APIC into the resource map. */ 2549 lapic_resource.start = apic_phys; 2550 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2551 insert_resource(&iomem_resource, &lapic_resource); 2552 2553 return 0; 2554 } 2555 2556 /* 2557 * need call insert after e820_reserve_resources() 2558 * that is using request_resource 2559 */ 2560 late_initcall(lapic_insert_resource); 2561 2562 static int __init apic_set_disabled_cpu_apicid(char *arg) 2563 { 2564 if (!arg || !get_option(&arg, &disabled_cpu_apicid)) 2565 return -EINVAL; 2566 2567 return 0; 2568 } 2569 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); 2570 2571 static int __init apic_set_extnmi(char *arg) 2572 { 2573 if (!arg) 2574 return -EINVAL; 2575 2576 if (!strncmp("all", arg, 3)) 2577 apic_extnmi = APIC_EXTNMI_ALL; 2578 else if (!strncmp("none", arg, 4)) 2579 apic_extnmi = APIC_EXTNMI_NONE; 2580 else if (!strncmp("bsp", arg, 3)) 2581 apic_extnmi = APIC_EXTNMI_BSP; 2582 else { 2583 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg); 2584 return -EINVAL; 2585 } 2586 2587 return 0; 2588 } 2589 early_param("apic_extnmi", apic_set_extnmi); 2590