1 /* 2 * Local APIC handling, local APIC timers 3 * 4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 5 * 6 * Fixes 7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 8 * thanks to Eric Gilmore 9 * and Rolf G. Tews 10 * for testing these extensively. 11 * Maciej W. Rozycki : Various updates and fixes. 12 * Mikael Pettersson : Power Management for UP-APIC. 13 * Pavel Machek and 14 * Mikael Pettersson : PM converted to driver model. 15 */ 16 17 #include <linux/perf_event.h> 18 #include <linux/kernel_stat.h> 19 #include <linux/mc146818rtc.h> 20 #include <linux/acpi_pmtmr.h> 21 #include <linux/clockchips.h> 22 #include <linux/interrupt.h> 23 #include <linux/bootmem.h> 24 #include <linux/ftrace.h> 25 #include <linux/ioport.h> 26 #include <linux/export.h> 27 #include <linux/syscore_ops.h> 28 #include <linux/delay.h> 29 #include <linux/timex.h> 30 #include <linux/i8253.h> 31 #include <linux/dmar.h> 32 #include <linux/init.h> 33 #include <linux/cpu.h> 34 #include <linux/dmi.h> 35 #include <linux/smp.h> 36 #include <linux/mm.h> 37 38 #include <asm/trace/irq_vectors.h> 39 #include <asm/irq_remapping.h> 40 #include <asm/perf_event.h> 41 #include <asm/x86_init.h> 42 #include <asm/pgalloc.h> 43 #include <linux/atomic.h> 44 #include <asm/mpspec.h> 45 #include <asm/i8259.h> 46 #include <asm/proto.h> 47 #include <asm/apic.h> 48 #include <asm/io_apic.h> 49 #include <asm/desc.h> 50 #include <asm/hpet.h> 51 #include <asm/mtrr.h> 52 #include <asm/time.h> 53 #include <asm/smp.h> 54 #include <asm/mce.h> 55 #include <asm/tsc.h> 56 #include <asm/hypervisor.h> 57 58 unsigned int num_processors; 59 60 unsigned disabled_cpus; 61 62 /* Processor that is doing the boot up */ 63 unsigned int boot_cpu_physical_apicid = -1U; 64 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); 65 66 u8 boot_cpu_apic_version; 67 68 /* 69 * The highest APIC ID seen during enumeration. 70 */ 71 static unsigned int max_physical_apicid; 72 73 /* 74 * Bitmask of physically existing CPUs: 75 */ 76 physid_mask_t phys_cpu_present_map; 77 78 /* 79 * Processor to be disabled specified by kernel parameter 80 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to 81 * avoid undefined behaviour caused by sending INIT from AP to BSP. 82 */ 83 static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID; 84 85 /* 86 * This variable controls which CPUs receive external NMIs. By default, 87 * external NMIs are delivered only to the BSP. 88 */ 89 static int apic_extnmi = APIC_EXTNMI_BSP; 90 91 /* 92 * Map cpu index to physical APIC ID 93 */ 94 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); 95 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID); 96 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX); 97 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 98 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 99 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid); 100 101 #ifdef CONFIG_X86_32 102 103 /* 104 * On x86_32, the mapping between cpu and logical apicid may vary 105 * depending on apic in use. The following early percpu variable is 106 * used for the mapping. This is where the behaviors of x86_64 and 32 107 * actually diverge. Let's keep it ugly for now. 108 */ 109 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID); 110 111 /* Local APIC was disabled by the BIOS and enabled by the kernel */ 112 static int enabled_via_apicbase; 113 114 /* 115 * Handle interrupt mode configuration register (IMCR). 116 * This register controls whether the interrupt signals 117 * that reach the BSP come from the master PIC or from the 118 * local APIC. Before entering Symmetric I/O Mode, either 119 * the BIOS or the operating system must switch out of 120 * PIC Mode by changing the IMCR. 121 */ 122 static inline void imcr_pic_to_apic(void) 123 { 124 /* select IMCR register */ 125 outb(0x70, 0x22); 126 /* NMI and 8259 INTR go through APIC */ 127 outb(0x01, 0x23); 128 } 129 130 static inline void imcr_apic_to_pic(void) 131 { 132 /* select IMCR register */ 133 outb(0x70, 0x22); 134 /* NMI and 8259 INTR go directly to BSP */ 135 outb(0x00, 0x23); 136 } 137 #endif 138 139 /* 140 * Knob to control our willingness to enable the local APIC. 141 * 142 * +1=force-enable 143 */ 144 static int force_enable_local_apic __initdata; 145 146 /* 147 * APIC command line parameters 148 */ 149 static int __init parse_lapic(char *arg) 150 { 151 if (IS_ENABLED(CONFIG_X86_32) && !arg) 152 force_enable_local_apic = 1; 153 else if (arg && !strncmp(arg, "notscdeadline", 13)) 154 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 155 return 0; 156 } 157 early_param("lapic", parse_lapic); 158 159 #ifdef CONFIG_X86_64 160 static int apic_calibrate_pmtmr __initdata; 161 static __init int setup_apicpmtimer(char *s) 162 { 163 apic_calibrate_pmtmr = 1; 164 notsc_setup(NULL); 165 return 0; 166 } 167 __setup("apicpmtimer", setup_apicpmtimer); 168 #endif 169 170 unsigned long mp_lapic_addr; 171 int disable_apic; 172 /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 173 static int disable_apic_timer __initdata; 174 /* Local APIC timer works in C2 */ 175 int local_apic_timer_c2_ok; 176 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 177 178 int first_system_vector = FIRST_SYSTEM_VECTOR; 179 180 /* 181 * Debug level, exported for io_apic.c 182 */ 183 unsigned int apic_verbosity; 184 185 int pic_mode; 186 187 /* Have we found an MP table */ 188 int smp_found_config; 189 190 static struct resource lapic_resource = { 191 .name = "Local APIC", 192 .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 193 }; 194 195 unsigned int lapic_timer_frequency = 0; 196 197 static void apic_pm_activate(void); 198 199 static unsigned long apic_phys; 200 201 /* 202 * Get the LAPIC version 203 */ 204 static inline int lapic_get_version(void) 205 { 206 return GET_APIC_VERSION(apic_read(APIC_LVR)); 207 } 208 209 /* 210 * Check, if the APIC is integrated or a separate chip 211 */ 212 static inline int lapic_is_integrated(void) 213 { 214 #ifdef CONFIG_X86_64 215 return 1; 216 #else 217 return APIC_INTEGRATED(lapic_get_version()); 218 #endif 219 } 220 221 /* 222 * Check, whether this is a modern or a first generation APIC 223 */ 224 static int modern_apic(void) 225 { 226 /* AMD systems use old APIC versions, so check the CPU */ 227 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 228 boot_cpu_data.x86 >= 0xf) 229 return 1; 230 return lapic_get_version() >= 0x14; 231 } 232 233 /* 234 * right after this call apic become NOOP driven 235 * so apic->write/read doesn't do anything 236 */ 237 static void __init apic_disable(void) 238 { 239 pr_info("APIC: switched to apic NOOP\n"); 240 apic = &apic_noop; 241 } 242 243 void native_apic_wait_icr_idle(void) 244 { 245 while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 246 cpu_relax(); 247 } 248 249 u32 native_safe_apic_wait_icr_idle(void) 250 { 251 u32 send_status; 252 int timeout; 253 254 timeout = 0; 255 do { 256 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 257 if (!send_status) 258 break; 259 inc_irq_stat(icr_read_retry_count); 260 udelay(100); 261 } while (timeout++ < 1000); 262 263 return send_status; 264 } 265 266 void native_apic_icr_write(u32 low, u32 id) 267 { 268 unsigned long flags; 269 270 local_irq_save(flags); 271 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 272 apic_write(APIC_ICR, low); 273 local_irq_restore(flags); 274 } 275 276 u64 native_apic_icr_read(void) 277 { 278 u32 icr1, icr2; 279 280 icr2 = apic_read(APIC_ICR2); 281 icr1 = apic_read(APIC_ICR); 282 283 return icr1 | ((u64)icr2 << 32); 284 } 285 286 #ifdef CONFIG_X86_32 287 /** 288 * get_physical_broadcast - Get number of physical broadcast IDs 289 */ 290 int get_physical_broadcast(void) 291 { 292 return modern_apic() ? 0xff : 0xf; 293 } 294 #endif 295 296 /** 297 * lapic_get_maxlvt - get the maximum number of local vector table entries 298 */ 299 int lapic_get_maxlvt(void) 300 { 301 unsigned int v; 302 303 v = apic_read(APIC_LVR); 304 /* 305 * - we always have APIC integrated on 64bit mode 306 * - 82489DXs do not report # of LVT entries 307 */ 308 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; 309 } 310 311 /* 312 * Local APIC timer 313 */ 314 315 /* Clock divisor */ 316 #define APIC_DIVISOR 16 317 #define TSC_DIVISOR 8 318 319 /* 320 * This function sets up the local APIC timer, with a timeout of 321 * 'clocks' APIC bus clock. During calibration we actually call 322 * this function twice on the boot CPU, once with a bogus timeout 323 * value, second time for real. The other (noncalibrating) CPUs 324 * call this function only once, with the real, calibrated value. 325 * 326 * We do reads before writes even if unnecessary, to get around the 327 * P5 APIC double write bug. 328 */ 329 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 330 { 331 unsigned int lvtt_value, tmp_value; 332 333 lvtt_value = LOCAL_TIMER_VECTOR; 334 if (!oneshot) 335 lvtt_value |= APIC_LVT_TIMER_PERIODIC; 336 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 337 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE; 338 339 if (!lapic_is_integrated()) 340 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 341 342 if (!irqen) 343 lvtt_value |= APIC_LVT_MASKED; 344 345 apic_write(APIC_LVTT, lvtt_value); 346 347 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { 348 /* 349 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, 350 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized. 351 * According to Intel, MFENCE can do the serialization here. 352 */ 353 asm volatile("mfence" : : : "memory"); 354 355 printk_once(KERN_DEBUG "TSC deadline timer enabled\n"); 356 return; 357 } 358 359 /* 360 * Divide PICLK by 16 361 */ 362 tmp_value = apic_read(APIC_TDCR); 363 apic_write(APIC_TDCR, 364 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 365 APIC_TDR_DIV_16); 366 367 if (!oneshot) 368 apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 369 } 370 371 /* 372 * Setup extended LVT, AMD specific 373 * 374 * Software should use the LVT offsets the BIOS provides. The offsets 375 * are determined by the subsystems using it like those for MCE 376 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts 377 * are supported. Beginning with family 10h at least 4 offsets are 378 * available. 379 * 380 * Since the offsets must be consistent for all cores, we keep track 381 * of the LVT offsets in software and reserve the offset for the same 382 * vector also to be used on other cores. An offset is freed by 383 * setting the entry to APIC_EILVT_MASKED. 384 * 385 * If the BIOS is right, there should be no conflicts. Otherwise a 386 * "[Firmware Bug]: ..." error message is generated. However, if 387 * software does not properly determines the offsets, it is not 388 * necessarily a BIOS bug. 389 */ 390 391 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; 392 393 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) 394 { 395 return (old & APIC_EILVT_MASKED) 396 || (new == APIC_EILVT_MASKED) 397 || ((new & ~APIC_EILVT_MASKED) == old); 398 } 399 400 static unsigned int reserve_eilvt_offset(int offset, unsigned int new) 401 { 402 unsigned int rsvd, vector; 403 404 if (offset >= APIC_EILVT_NR_MAX) 405 return ~0; 406 407 rsvd = atomic_read(&eilvt_offsets[offset]); 408 do { 409 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ 410 if (vector && !eilvt_entry_is_changeable(vector, new)) 411 /* may not change if vectors are different */ 412 return rsvd; 413 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); 414 } while (rsvd != new); 415 416 rsvd &= ~APIC_EILVT_MASKED; 417 if (rsvd && rsvd != vector) 418 pr_info("LVT offset %d assigned for vector 0x%02x\n", 419 offset, rsvd); 420 421 return new; 422 } 423 424 /* 425 * If mask=1, the LVT entry does not generate interrupts while mask=0 426 * enables the vector. See also the BKDGs. Must be called with 427 * preemption disabled. 428 */ 429 430 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) 431 { 432 unsigned long reg = APIC_EILVTn(offset); 433 unsigned int new, old, reserved; 434 435 new = (mask << 16) | (msg_type << 8) | vector; 436 old = apic_read(reg); 437 reserved = reserve_eilvt_offset(offset, new); 438 439 if (reserved != new) { 440 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 441 "vector 0x%x, but the register is already in use for " 442 "vector 0x%x on another cpu\n", 443 smp_processor_id(), reg, offset, new, reserved); 444 return -EINVAL; 445 } 446 447 if (!eilvt_entry_is_changeable(old, new)) { 448 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 449 "vector 0x%x, but the register is already in use for " 450 "vector 0x%x on this cpu\n", 451 smp_processor_id(), reg, offset, new, old); 452 return -EBUSY; 453 } 454 455 apic_write(reg, new); 456 457 return 0; 458 } 459 EXPORT_SYMBOL_GPL(setup_APIC_eilvt); 460 461 /* 462 * Program the next event, relative to now 463 */ 464 static int lapic_next_event(unsigned long delta, 465 struct clock_event_device *evt) 466 { 467 apic_write(APIC_TMICT, delta); 468 return 0; 469 } 470 471 static int lapic_next_deadline(unsigned long delta, 472 struct clock_event_device *evt) 473 { 474 u64 tsc; 475 476 tsc = rdtsc(); 477 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); 478 return 0; 479 } 480 481 static int lapic_timer_shutdown(struct clock_event_device *evt) 482 { 483 unsigned int v; 484 485 /* Lapic used as dummy for broadcast ? */ 486 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 487 return 0; 488 489 v = apic_read(APIC_LVTT); 490 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 491 apic_write(APIC_LVTT, v); 492 apic_write(APIC_TMICT, 0); 493 return 0; 494 } 495 496 static inline int 497 lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot) 498 { 499 /* Lapic used as dummy for broadcast ? */ 500 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 501 return 0; 502 503 __setup_APIC_LVTT(lapic_timer_frequency, oneshot, 1); 504 return 0; 505 } 506 507 static int lapic_timer_set_periodic(struct clock_event_device *evt) 508 { 509 return lapic_timer_set_periodic_oneshot(evt, false); 510 } 511 512 static int lapic_timer_set_oneshot(struct clock_event_device *evt) 513 { 514 return lapic_timer_set_periodic_oneshot(evt, true); 515 } 516 517 /* 518 * Local APIC timer broadcast function 519 */ 520 static void lapic_timer_broadcast(const struct cpumask *mask) 521 { 522 #ifdef CONFIG_SMP 523 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 524 #endif 525 } 526 527 528 /* 529 * The local apic timer can be used for any function which is CPU local. 530 */ 531 static struct clock_event_device lapic_clockevent = { 532 .name = "lapic", 533 .features = CLOCK_EVT_FEAT_PERIODIC | 534 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP 535 | CLOCK_EVT_FEAT_DUMMY, 536 .shift = 32, 537 .set_state_shutdown = lapic_timer_shutdown, 538 .set_state_periodic = lapic_timer_set_periodic, 539 .set_state_oneshot = lapic_timer_set_oneshot, 540 .set_state_oneshot_stopped = lapic_timer_shutdown, 541 .set_next_event = lapic_next_event, 542 .broadcast = lapic_timer_broadcast, 543 .rating = 100, 544 .irq = -1, 545 }; 546 static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 547 548 /* 549 * Setup the local APIC timer for this CPU. Copy the initialized values 550 * of the boot CPU and register the clock event in the framework. 551 */ 552 static void setup_APIC_timer(void) 553 { 554 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 555 556 if (this_cpu_has(X86_FEATURE_ARAT)) { 557 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 558 /* Make LAPIC timer preferrable over percpu HPET */ 559 lapic_clockevent.rating = 150; 560 } 561 562 memcpy(levt, &lapic_clockevent, sizeof(*levt)); 563 levt->cpumask = cpumask_of(smp_processor_id()); 564 565 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 566 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | 567 CLOCK_EVT_FEAT_DUMMY); 568 levt->set_next_event = lapic_next_deadline; 569 clockevents_config_and_register(levt, 570 tsc_khz * (1000 / TSC_DIVISOR), 571 0xF, ~0UL); 572 } else 573 clockevents_register_device(levt); 574 } 575 576 /* 577 * Install the updated TSC frequency from recalibration at the TSC 578 * deadline clockevent devices. 579 */ 580 static void __lapic_update_tsc_freq(void *info) 581 { 582 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 583 584 if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 585 return; 586 587 clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR)); 588 } 589 590 void lapic_update_tsc_freq(void) 591 { 592 /* 593 * The clockevent device's ->mult and ->shift can both be 594 * changed. In order to avoid races, schedule the frequency 595 * update code on each CPU. 596 */ 597 on_each_cpu(__lapic_update_tsc_freq, NULL, 0); 598 } 599 600 /* 601 * In this functions we calibrate APIC bus clocks to the external timer. 602 * 603 * We want to do the calibration only once since we want to have local timer 604 * irqs syncron. CPUs connected by the same APIC bus have the very same bus 605 * frequency. 606 * 607 * This was previously done by reading the PIT/HPET and waiting for a wrap 608 * around to find out, that a tick has elapsed. I have a box, where the PIT 609 * readout is broken, so it never gets out of the wait loop again. This was 610 * also reported by others. 611 * 612 * Monitoring the jiffies value is inaccurate and the clockevents 613 * infrastructure allows us to do a simple substitution of the interrupt 614 * handler. 615 * 616 * The calibration routine also uses the pm_timer when possible, as the PIT 617 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 618 * back to normal later in the boot process). 619 */ 620 621 #define LAPIC_CAL_LOOPS (HZ/10) 622 623 static __initdata int lapic_cal_loops = -1; 624 static __initdata long lapic_cal_t1, lapic_cal_t2; 625 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 626 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 627 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 628 629 /* 630 * Temporary interrupt handler. 631 */ 632 static void __init lapic_cal_handler(struct clock_event_device *dev) 633 { 634 unsigned long long tsc = 0; 635 long tapic = apic_read(APIC_TMCCT); 636 unsigned long pm = acpi_pm_read_early(); 637 638 if (boot_cpu_has(X86_FEATURE_TSC)) 639 tsc = rdtsc(); 640 641 switch (lapic_cal_loops++) { 642 case 0: 643 lapic_cal_t1 = tapic; 644 lapic_cal_tsc1 = tsc; 645 lapic_cal_pm1 = pm; 646 lapic_cal_j1 = jiffies; 647 break; 648 649 case LAPIC_CAL_LOOPS: 650 lapic_cal_t2 = tapic; 651 lapic_cal_tsc2 = tsc; 652 if (pm < lapic_cal_pm1) 653 pm += ACPI_PM_OVRRUN; 654 lapic_cal_pm2 = pm; 655 lapic_cal_j2 = jiffies; 656 break; 657 } 658 } 659 660 static int __init 661 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 662 { 663 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 664 const long pm_thresh = pm_100ms / 100; 665 unsigned long mult; 666 u64 res; 667 668 #ifndef CONFIG_X86_PM_TIMER 669 return -1; 670 #endif 671 672 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 673 674 /* Check, if the PM timer is available */ 675 if (!deltapm) 676 return -1; 677 678 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 679 680 if (deltapm > (pm_100ms - pm_thresh) && 681 deltapm < (pm_100ms + pm_thresh)) { 682 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 683 return 0; 684 } 685 686 res = (((u64)deltapm) * mult) >> 22; 687 do_div(res, 1000000); 688 pr_warning("APIC calibration not consistent " 689 "with PM-Timer: %ldms instead of 100ms\n",(long)res); 690 691 /* Correct the lapic counter value */ 692 res = (((u64)(*delta)) * pm_100ms); 693 do_div(res, deltapm); 694 pr_info("APIC delta adjusted to PM-Timer: " 695 "%lu (%ld)\n", (unsigned long)res, *delta); 696 *delta = (long)res; 697 698 /* Correct the tsc counter value */ 699 if (boot_cpu_has(X86_FEATURE_TSC)) { 700 res = (((u64)(*deltatsc)) * pm_100ms); 701 do_div(res, deltapm); 702 apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 703 "PM-Timer: %lu (%ld)\n", 704 (unsigned long)res, *deltatsc); 705 *deltatsc = (long)res; 706 } 707 708 return 0; 709 } 710 711 static int __init calibrate_APIC_clock(void) 712 { 713 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 714 void (*real_handler)(struct clock_event_device *dev); 715 unsigned long deltaj; 716 long delta, deltatsc; 717 int pm_referenced = 0; 718 719 /** 720 * check if lapic timer has already been calibrated by platform 721 * specific routine, such as tsc calibration code. if so, we just fill 722 * in the clockevent structure and return. 723 */ 724 725 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 726 return 0; 727 } else if (lapic_timer_frequency) { 728 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", 729 lapic_timer_frequency); 730 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR, 731 TICK_NSEC, lapic_clockevent.shift); 732 lapic_clockevent.max_delta_ns = 733 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); 734 lapic_clockevent.max_delta_ticks = 0x7FFFFF; 735 lapic_clockevent.min_delta_ns = 736 clockevent_delta2ns(0xF, &lapic_clockevent); 737 lapic_clockevent.min_delta_ticks = 0xF; 738 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 739 return 0; 740 } 741 742 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 743 "calibrating APIC timer ...\n"); 744 745 local_irq_disable(); 746 747 /* Replace the global interrupt handler */ 748 real_handler = global_clock_event->event_handler; 749 global_clock_event->event_handler = lapic_cal_handler; 750 751 /* 752 * Setup the APIC counter to maximum. There is no way the lapic 753 * can underflow in the 100ms detection time frame 754 */ 755 __setup_APIC_LVTT(0xffffffff, 0, 0); 756 757 /* Let the interrupts run */ 758 local_irq_enable(); 759 760 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 761 cpu_relax(); 762 763 local_irq_disable(); 764 765 /* Restore the real event handler */ 766 global_clock_event->event_handler = real_handler; 767 768 /* Build delta t1-t2 as apic timer counts down */ 769 delta = lapic_cal_t1 - lapic_cal_t2; 770 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 771 772 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 773 774 /* we trust the PM based calibration if possible */ 775 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 776 &delta, &deltatsc); 777 778 /* Calculate the scaled math multiplication factor */ 779 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 780 lapic_clockevent.shift); 781 lapic_clockevent.max_delta_ns = 782 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); 783 lapic_clockevent.max_delta_ticks = 0x7FFFFFFF; 784 lapic_clockevent.min_delta_ns = 785 clockevent_delta2ns(0xF, &lapic_clockevent); 786 lapic_clockevent.min_delta_ticks = 0xF; 787 788 lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 789 790 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 791 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); 792 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 793 lapic_timer_frequency); 794 795 if (boot_cpu_has(X86_FEATURE_TSC)) { 796 apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 797 "%ld.%04ld MHz.\n", 798 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 799 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 800 } 801 802 apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 803 "%u.%04u MHz.\n", 804 lapic_timer_frequency / (1000000 / HZ), 805 lapic_timer_frequency % (1000000 / HZ)); 806 807 /* 808 * Do a sanity check on the APIC calibration result 809 */ 810 if (lapic_timer_frequency < (1000000 / HZ)) { 811 local_irq_enable(); 812 pr_warning("APIC frequency too slow, disabling apic timer\n"); 813 return -1; 814 } 815 816 levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 817 818 /* 819 * PM timer calibration failed or not turned on 820 * so lets try APIC timer based calibration 821 */ 822 if (!pm_referenced) { 823 apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 824 825 /* 826 * Setup the apic timer manually 827 */ 828 levt->event_handler = lapic_cal_handler; 829 lapic_timer_set_periodic(levt); 830 lapic_cal_loops = -1; 831 832 /* Let the interrupts run */ 833 local_irq_enable(); 834 835 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 836 cpu_relax(); 837 838 /* Stop the lapic timer */ 839 local_irq_disable(); 840 lapic_timer_shutdown(levt); 841 842 /* Jiffies delta */ 843 deltaj = lapic_cal_j2 - lapic_cal_j1; 844 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 845 846 /* Check, if the jiffies result is consistent */ 847 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 848 apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 849 else 850 levt->features |= CLOCK_EVT_FEAT_DUMMY; 851 } 852 local_irq_enable(); 853 854 if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 855 pr_warning("APIC timer disabled due to verification failure\n"); 856 return -1; 857 } 858 859 return 0; 860 } 861 862 /* 863 * Setup the boot APIC 864 * 865 * Calibrate and verify the result. 866 */ 867 void __init setup_boot_APIC_clock(void) 868 { 869 /* 870 * The local apic timer can be disabled via the kernel 871 * commandline or from the CPU detection code. Register the lapic 872 * timer as a dummy clock event source on SMP systems, so the 873 * broadcast mechanism is used. On UP systems simply ignore it. 874 */ 875 if (disable_apic_timer) { 876 pr_info("Disabling APIC timer\n"); 877 /* No broadcast on UP ! */ 878 if (num_possible_cpus() > 1) { 879 lapic_clockevent.mult = 1; 880 setup_APIC_timer(); 881 } 882 return; 883 } 884 885 if (calibrate_APIC_clock()) { 886 /* No broadcast on UP ! */ 887 if (num_possible_cpus() > 1) 888 setup_APIC_timer(); 889 return; 890 } 891 892 /* 893 * If nmi_watchdog is set to IO_APIC, we need the 894 * PIT/HPET going. Otherwise register lapic as a dummy 895 * device. 896 */ 897 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 898 899 /* Setup the lapic or request the broadcast */ 900 setup_APIC_timer(); 901 amd_e400_c1e_apic_setup(); 902 } 903 904 void setup_secondary_APIC_clock(void) 905 { 906 setup_APIC_timer(); 907 amd_e400_c1e_apic_setup(); 908 } 909 910 /* 911 * The guts of the apic timer interrupt 912 */ 913 static void local_apic_timer_interrupt(void) 914 { 915 int cpu = smp_processor_id(); 916 struct clock_event_device *evt = &per_cpu(lapic_events, cpu); 917 918 /* 919 * Normally we should not be here till LAPIC has been initialized but 920 * in some cases like kdump, its possible that there is a pending LAPIC 921 * timer interrupt from previous kernel's context and is delivered in 922 * new kernel the moment interrupts are enabled. 923 * 924 * Interrupts are enabled early and LAPIC is setup much later, hence 925 * its possible that when we get here evt->event_handler is NULL. 926 * Check for event_handler being NULL and discard the interrupt as 927 * spurious. 928 */ 929 if (!evt->event_handler) { 930 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); 931 /* Switch it off */ 932 lapic_timer_shutdown(evt); 933 return; 934 } 935 936 /* 937 * the NMI deadlock-detector uses this. 938 */ 939 inc_irq_stat(apic_timer_irqs); 940 941 evt->event_handler(evt); 942 } 943 944 /* 945 * Local APIC timer interrupt. This is the most natural way for doing 946 * local interrupts, but local timer interrupts can be emulated by 947 * broadcast interrupts too. [in case the hw doesn't support APIC timers] 948 * 949 * [ if a single-CPU system runs an SMP kernel then we call the local 950 * interrupt as well. Thus we cannot inline the local irq ... ] 951 */ 952 __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) 953 { 954 struct pt_regs *old_regs = set_irq_regs(regs); 955 956 /* 957 * NOTE! We'd better ACK the irq immediately, 958 * because timer handling can be slow. 959 * 960 * update_process_times() expects us to have done irq_enter(). 961 * Besides, if we don't timer interrupts ignore the global 962 * interrupt lock, which is the WrongThing (tm) to do. 963 */ 964 entering_ack_irq(); 965 local_apic_timer_interrupt(); 966 exiting_irq(); 967 968 set_irq_regs(old_regs); 969 } 970 971 __visible void __irq_entry smp_trace_apic_timer_interrupt(struct pt_regs *regs) 972 { 973 struct pt_regs *old_regs = set_irq_regs(regs); 974 975 /* 976 * NOTE! We'd better ACK the irq immediately, 977 * because timer handling can be slow. 978 * 979 * update_process_times() expects us to have done irq_enter(). 980 * Besides, if we don't timer interrupts ignore the global 981 * interrupt lock, which is the WrongThing (tm) to do. 982 */ 983 entering_ack_irq(); 984 trace_local_timer_entry(LOCAL_TIMER_VECTOR); 985 local_apic_timer_interrupt(); 986 trace_local_timer_exit(LOCAL_TIMER_VECTOR); 987 exiting_irq(); 988 989 set_irq_regs(old_regs); 990 } 991 992 int setup_profiling_timer(unsigned int multiplier) 993 { 994 return -EINVAL; 995 } 996 997 /* 998 * Local APIC start and shutdown 999 */ 1000 1001 /** 1002 * clear_local_APIC - shutdown the local APIC 1003 * 1004 * This is called, when a CPU is disabled and before rebooting, so the state of 1005 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 1006 * leftovers during boot. 1007 */ 1008 void clear_local_APIC(void) 1009 { 1010 int maxlvt; 1011 u32 v; 1012 1013 /* APIC hasn't been mapped yet */ 1014 if (!x2apic_mode && !apic_phys) 1015 return; 1016 1017 maxlvt = lapic_get_maxlvt(); 1018 /* 1019 * Masking an LVT entry can trigger a local APIC error 1020 * if the vector is zero. Mask LVTERR first to prevent this. 1021 */ 1022 if (maxlvt >= 3) { 1023 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 1024 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 1025 } 1026 /* 1027 * Careful: we have to set masks only first to deassert 1028 * any level-triggered sources. 1029 */ 1030 v = apic_read(APIC_LVTT); 1031 apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 1032 v = apic_read(APIC_LVT0); 1033 apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 1034 v = apic_read(APIC_LVT1); 1035 apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 1036 if (maxlvt >= 4) { 1037 v = apic_read(APIC_LVTPC); 1038 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 1039 } 1040 1041 /* lets not touch this if we didn't frob it */ 1042 #ifdef CONFIG_X86_THERMAL_VECTOR 1043 if (maxlvt >= 5) { 1044 v = apic_read(APIC_LVTTHMR); 1045 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 1046 } 1047 #endif 1048 #ifdef CONFIG_X86_MCE_INTEL 1049 if (maxlvt >= 6) { 1050 v = apic_read(APIC_LVTCMCI); 1051 if (!(v & APIC_LVT_MASKED)) 1052 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 1053 } 1054 #endif 1055 1056 /* 1057 * Clean APIC state for other OSs: 1058 */ 1059 apic_write(APIC_LVTT, APIC_LVT_MASKED); 1060 apic_write(APIC_LVT0, APIC_LVT_MASKED); 1061 apic_write(APIC_LVT1, APIC_LVT_MASKED); 1062 if (maxlvt >= 3) 1063 apic_write(APIC_LVTERR, APIC_LVT_MASKED); 1064 if (maxlvt >= 4) 1065 apic_write(APIC_LVTPC, APIC_LVT_MASKED); 1066 1067 /* Integrated APIC (!82489DX) ? */ 1068 if (lapic_is_integrated()) { 1069 if (maxlvt > 3) 1070 /* Clear ESR due to Pentium errata 3AP and 11AP */ 1071 apic_write(APIC_ESR, 0); 1072 apic_read(APIC_ESR); 1073 } 1074 } 1075 1076 /** 1077 * disable_local_APIC - clear and disable the local APIC 1078 */ 1079 void disable_local_APIC(void) 1080 { 1081 unsigned int value; 1082 1083 /* APIC hasn't been mapped yet */ 1084 if (!x2apic_mode && !apic_phys) 1085 return; 1086 1087 clear_local_APIC(); 1088 1089 /* 1090 * Disable APIC (implies clearing of registers 1091 * for 82489DX!). 1092 */ 1093 value = apic_read(APIC_SPIV); 1094 value &= ~APIC_SPIV_APIC_ENABLED; 1095 apic_write(APIC_SPIV, value); 1096 1097 #ifdef CONFIG_X86_32 1098 /* 1099 * When LAPIC was disabled by the BIOS and enabled by the kernel, 1100 * restore the disabled state. 1101 */ 1102 if (enabled_via_apicbase) { 1103 unsigned int l, h; 1104 1105 rdmsr(MSR_IA32_APICBASE, l, h); 1106 l &= ~MSR_IA32_APICBASE_ENABLE; 1107 wrmsr(MSR_IA32_APICBASE, l, h); 1108 } 1109 #endif 1110 } 1111 1112 /* 1113 * If Linux enabled the LAPIC against the BIOS default disable it down before 1114 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 1115 * not power-off. Additionally clear all LVT entries before disable_local_APIC 1116 * for the case where Linux didn't enable the LAPIC. 1117 */ 1118 void lapic_shutdown(void) 1119 { 1120 unsigned long flags; 1121 1122 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) 1123 return; 1124 1125 local_irq_save(flags); 1126 1127 #ifdef CONFIG_X86_32 1128 if (!enabled_via_apicbase) 1129 clear_local_APIC(); 1130 else 1131 #endif 1132 disable_local_APIC(); 1133 1134 1135 local_irq_restore(flags); 1136 } 1137 1138 /** 1139 * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1140 */ 1141 void __init sync_Arb_IDs(void) 1142 { 1143 /* 1144 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1145 * needed on AMD. 1146 */ 1147 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1148 return; 1149 1150 /* 1151 * Wait for idle. 1152 */ 1153 apic_wait_icr_idle(); 1154 1155 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1156 apic_write(APIC_ICR, APIC_DEST_ALLINC | 1157 APIC_INT_LEVELTRIG | APIC_DM_INIT); 1158 } 1159 1160 /* 1161 * An initial setup of the virtual wire mode. 1162 */ 1163 void __init init_bsp_APIC(void) 1164 { 1165 unsigned int value; 1166 1167 /* 1168 * Don't do the setup now if we have a SMP BIOS as the 1169 * through-I/O-APIC virtual wire mode might be active. 1170 */ 1171 if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC)) 1172 return; 1173 1174 /* 1175 * Do not trust the local APIC being empty at bootup. 1176 */ 1177 clear_local_APIC(); 1178 1179 /* 1180 * Enable APIC. 1181 */ 1182 value = apic_read(APIC_SPIV); 1183 value &= ~APIC_VECTOR_MASK; 1184 value |= APIC_SPIV_APIC_ENABLED; 1185 1186 #ifdef CONFIG_X86_32 1187 /* This bit is reserved on P4/Xeon and should be cleared */ 1188 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1189 (boot_cpu_data.x86 == 15)) 1190 value &= ~APIC_SPIV_FOCUS_DISABLED; 1191 else 1192 #endif 1193 value |= APIC_SPIV_FOCUS_DISABLED; 1194 value |= SPURIOUS_APIC_VECTOR; 1195 apic_write(APIC_SPIV, value); 1196 1197 /* 1198 * Set up the virtual wire mode. 1199 */ 1200 apic_write(APIC_LVT0, APIC_DM_EXTINT); 1201 value = APIC_DM_NMI; 1202 if (!lapic_is_integrated()) /* 82489DX */ 1203 value |= APIC_LVT_LEVEL_TRIGGER; 1204 if (apic_extnmi == APIC_EXTNMI_NONE) 1205 value |= APIC_LVT_MASKED; 1206 apic_write(APIC_LVT1, value); 1207 } 1208 1209 static void lapic_setup_esr(void) 1210 { 1211 unsigned int oldvalue, value, maxlvt; 1212 1213 if (!lapic_is_integrated()) { 1214 pr_info("No ESR for 82489DX.\n"); 1215 return; 1216 } 1217 1218 if (apic->disable_esr) { 1219 /* 1220 * Something untraceable is creating bad interrupts on 1221 * secondary quads ... for the moment, just leave the 1222 * ESR disabled - we can't do anything useful with the 1223 * errors anyway - mbligh 1224 */ 1225 pr_info("Leaving ESR disabled.\n"); 1226 return; 1227 } 1228 1229 maxlvt = lapic_get_maxlvt(); 1230 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1231 apic_write(APIC_ESR, 0); 1232 oldvalue = apic_read(APIC_ESR); 1233 1234 /* enables sending errors */ 1235 value = ERROR_APIC_VECTOR; 1236 apic_write(APIC_LVTERR, value); 1237 1238 /* 1239 * spec says clear errors after enabling vector. 1240 */ 1241 if (maxlvt > 3) 1242 apic_write(APIC_ESR, 0); 1243 value = apic_read(APIC_ESR); 1244 if (value != oldvalue) 1245 apic_printk(APIC_VERBOSE, "ESR value before enabling " 1246 "vector: 0x%08x after: 0x%08x\n", 1247 oldvalue, value); 1248 } 1249 1250 /** 1251 * setup_local_APIC - setup the local APIC 1252 * 1253 * Used to setup local APIC while initializing BSP or bringing up APs. 1254 * Always called with preemption disabled. 1255 */ 1256 void setup_local_APIC(void) 1257 { 1258 int cpu = smp_processor_id(); 1259 unsigned int value, queued; 1260 int i, j, acked = 0; 1261 unsigned long long tsc = 0, ntsc; 1262 long long max_loops = cpu_khz ? cpu_khz : 1000000; 1263 1264 if (boot_cpu_has(X86_FEATURE_TSC)) 1265 tsc = rdtsc(); 1266 1267 if (disable_apic) { 1268 disable_ioapic_support(); 1269 return; 1270 } 1271 1272 #ifdef CONFIG_X86_32 1273 /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1274 if (lapic_is_integrated() && apic->disable_esr) { 1275 apic_write(APIC_ESR, 0); 1276 apic_write(APIC_ESR, 0); 1277 apic_write(APIC_ESR, 0); 1278 apic_write(APIC_ESR, 0); 1279 } 1280 #endif 1281 perf_events_lapic_init(); 1282 1283 /* 1284 * Double-check whether this APIC is really registered. 1285 * This is meaningless in clustered apic mode, so we skip it. 1286 */ 1287 BUG_ON(!apic->apic_id_registered()); 1288 1289 /* 1290 * Intel recommends to set DFR, LDR and TPR before enabling 1291 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1292 * document number 292116). So here it goes... 1293 */ 1294 apic->init_apic_ldr(); 1295 1296 #ifdef CONFIG_X86_32 1297 /* 1298 * APIC LDR is initialized. If logical_apicid mapping was 1299 * initialized during get_smp_config(), make sure it matches the 1300 * actual value. 1301 */ 1302 i = early_per_cpu(x86_cpu_to_logical_apicid, cpu); 1303 WARN_ON(i != BAD_APICID && i != logical_smp_processor_id()); 1304 /* always use the value from LDR */ 1305 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 1306 logical_smp_processor_id(); 1307 #endif 1308 1309 /* 1310 * Set Task Priority to 'accept all'. We never change this 1311 * later on. 1312 */ 1313 value = apic_read(APIC_TASKPRI); 1314 value &= ~APIC_TPRI_MASK; 1315 apic_write(APIC_TASKPRI, value); 1316 1317 /* 1318 * After a crash, we no longer service the interrupts and a pending 1319 * interrupt from previous kernel might still have ISR bit set. 1320 * 1321 * Most probably by now CPU has serviced that pending interrupt and 1322 * it might not have done the ack_APIC_irq() because it thought, 1323 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it 1324 * does not clear the ISR bit and cpu thinks it has already serivced 1325 * the interrupt. Hence a vector might get locked. It was noticed 1326 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. 1327 */ 1328 do { 1329 queued = 0; 1330 for (i = APIC_ISR_NR - 1; i >= 0; i--) 1331 queued |= apic_read(APIC_IRR + i*0x10); 1332 1333 for (i = APIC_ISR_NR - 1; i >= 0; i--) { 1334 value = apic_read(APIC_ISR + i*0x10); 1335 for (j = 31; j >= 0; j--) { 1336 if (value & (1<<j)) { 1337 ack_APIC_irq(); 1338 acked++; 1339 } 1340 } 1341 } 1342 if (acked > 256) { 1343 printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n", 1344 acked); 1345 break; 1346 } 1347 if (queued) { 1348 if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) { 1349 ntsc = rdtsc(); 1350 max_loops = (cpu_khz << 10) - (ntsc - tsc); 1351 } else 1352 max_loops--; 1353 } 1354 } while (queued && max_loops > 0); 1355 WARN_ON(max_loops <= 0); 1356 1357 /* 1358 * Now that we are all set up, enable the APIC 1359 */ 1360 value = apic_read(APIC_SPIV); 1361 value &= ~APIC_VECTOR_MASK; 1362 /* 1363 * Enable APIC 1364 */ 1365 value |= APIC_SPIV_APIC_ENABLED; 1366 1367 #ifdef CONFIG_X86_32 1368 /* 1369 * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1370 * certain networking cards. If high frequency interrupts are 1371 * happening on a particular IOAPIC pin, plus the IOAPIC routing 1372 * entry is masked/unmasked at a high rate as well then sooner or 1373 * later IOAPIC line gets 'stuck', no more interrupts are received 1374 * from the device. If focus CPU is disabled then the hang goes 1375 * away, oh well :-( 1376 * 1377 * [ This bug can be reproduced easily with a level-triggered 1378 * PCI Ne2000 networking cards and PII/PIII processors, dual 1379 * BX chipset. ] 1380 */ 1381 /* 1382 * Actually disabling the focus CPU check just makes the hang less 1383 * frequent as it makes the interrupt distributon model be more 1384 * like LRU than MRU (the short-term load is more even across CPUs). 1385 */ 1386 1387 /* 1388 * - enable focus processor (bit==0) 1389 * - 64bit mode always use processor focus 1390 * so no need to set it 1391 */ 1392 value &= ~APIC_SPIV_FOCUS_DISABLED; 1393 #endif 1394 1395 /* 1396 * Set spurious IRQ vector 1397 */ 1398 value |= SPURIOUS_APIC_VECTOR; 1399 apic_write(APIC_SPIV, value); 1400 1401 /* 1402 * Set up LVT0, LVT1: 1403 * 1404 * set up through-local-APIC on the BP's LINT0. This is not 1405 * strictly necessary in pure symmetric-IO mode, but sometimes 1406 * we delegate interrupts to the 8259A. 1407 */ 1408 /* 1409 * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1410 */ 1411 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 1412 if (!cpu && (pic_mode || !value)) { 1413 value = APIC_DM_EXTINT; 1414 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); 1415 } else { 1416 value = APIC_DM_EXTINT | APIC_LVT_MASKED; 1417 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); 1418 } 1419 apic_write(APIC_LVT0, value); 1420 1421 /* 1422 * Only the BSP sees the LINT1 NMI signal by default. This can be 1423 * modified by apic_extnmi= boot option. 1424 */ 1425 if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) || 1426 apic_extnmi == APIC_EXTNMI_ALL) 1427 value = APIC_DM_NMI; 1428 else 1429 value = APIC_DM_NMI | APIC_LVT_MASKED; 1430 if (!lapic_is_integrated()) /* 82489DX */ 1431 value |= APIC_LVT_LEVEL_TRIGGER; 1432 apic_write(APIC_LVT1, value); 1433 1434 #ifdef CONFIG_X86_MCE_INTEL 1435 /* Recheck CMCI information after local APIC is up on CPU #0 */ 1436 if (!cpu) 1437 cmci_recheck(); 1438 #endif 1439 } 1440 1441 static void end_local_APIC_setup(void) 1442 { 1443 lapic_setup_esr(); 1444 1445 #ifdef CONFIG_X86_32 1446 { 1447 unsigned int value; 1448 /* Disable the local apic timer */ 1449 value = apic_read(APIC_LVTT); 1450 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1451 apic_write(APIC_LVTT, value); 1452 } 1453 #endif 1454 1455 apic_pm_activate(); 1456 } 1457 1458 /* 1459 * APIC setup function for application processors. Called from smpboot.c 1460 */ 1461 void apic_ap_setup(void) 1462 { 1463 setup_local_APIC(); 1464 end_local_APIC_setup(); 1465 } 1466 1467 #ifdef CONFIG_X86_X2APIC 1468 int x2apic_mode; 1469 1470 enum { 1471 X2APIC_OFF, 1472 X2APIC_ON, 1473 X2APIC_DISABLED, 1474 }; 1475 static int x2apic_state; 1476 1477 static void __x2apic_disable(void) 1478 { 1479 u64 msr; 1480 1481 if (!boot_cpu_has(X86_FEATURE_APIC)) 1482 return; 1483 1484 rdmsrl(MSR_IA32_APICBASE, msr); 1485 if (!(msr & X2APIC_ENABLE)) 1486 return; 1487 /* Disable xapic and x2apic first and then reenable xapic mode */ 1488 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); 1489 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); 1490 printk_once(KERN_INFO "x2apic disabled\n"); 1491 } 1492 1493 static void __x2apic_enable(void) 1494 { 1495 u64 msr; 1496 1497 rdmsrl(MSR_IA32_APICBASE, msr); 1498 if (msr & X2APIC_ENABLE) 1499 return; 1500 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); 1501 printk_once(KERN_INFO "x2apic enabled\n"); 1502 } 1503 1504 static int __init setup_nox2apic(char *str) 1505 { 1506 if (x2apic_enabled()) { 1507 int apicid = native_apic_msr_read(APIC_ID); 1508 1509 if (apicid >= 255) { 1510 pr_warning("Apicid: %08x, cannot enforce nox2apic\n", 1511 apicid); 1512 return 0; 1513 } 1514 pr_warning("x2apic already enabled.\n"); 1515 __x2apic_disable(); 1516 } 1517 setup_clear_cpu_cap(X86_FEATURE_X2APIC); 1518 x2apic_state = X2APIC_DISABLED; 1519 x2apic_mode = 0; 1520 return 0; 1521 } 1522 early_param("nox2apic", setup_nox2apic); 1523 1524 /* Called from cpu_init() to enable x2apic on (secondary) cpus */ 1525 void x2apic_setup(void) 1526 { 1527 /* 1528 * If x2apic is not in ON state, disable it if already enabled 1529 * from BIOS. 1530 */ 1531 if (x2apic_state != X2APIC_ON) { 1532 __x2apic_disable(); 1533 return; 1534 } 1535 __x2apic_enable(); 1536 } 1537 1538 static __init void x2apic_disable(void) 1539 { 1540 u32 x2apic_id, state = x2apic_state; 1541 1542 x2apic_mode = 0; 1543 x2apic_state = X2APIC_DISABLED; 1544 1545 if (state != X2APIC_ON) 1546 return; 1547 1548 x2apic_id = read_apic_id(); 1549 if (x2apic_id >= 255) 1550 panic("Cannot disable x2apic, id: %08x\n", x2apic_id); 1551 1552 __x2apic_disable(); 1553 register_lapic_address(mp_lapic_addr); 1554 } 1555 1556 static __init void x2apic_enable(void) 1557 { 1558 if (x2apic_state != X2APIC_OFF) 1559 return; 1560 1561 x2apic_mode = 1; 1562 x2apic_state = X2APIC_ON; 1563 __x2apic_enable(); 1564 } 1565 1566 static __init void try_to_enable_x2apic(int remap_mode) 1567 { 1568 if (x2apic_state == X2APIC_DISABLED) 1569 return; 1570 1571 if (remap_mode != IRQ_REMAP_X2APIC_MODE) { 1572 /* IR is required if there is APIC ID > 255 even when running 1573 * under KVM 1574 */ 1575 if (max_physical_apicid > 255 || 1576 !hypervisor_x2apic_available()) { 1577 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n"); 1578 x2apic_disable(); 1579 return; 1580 } 1581 1582 /* 1583 * without IR all CPUs can be addressed by IOAPIC/MSI 1584 * only in physical mode 1585 */ 1586 x2apic_phys = 1; 1587 } 1588 x2apic_enable(); 1589 } 1590 1591 void __init check_x2apic(void) 1592 { 1593 if (x2apic_enabled()) { 1594 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n"); 1595 x2apic_mode = 1; 1596 x2apic_state = X2APIC_ON; 1597 } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) { 1598 x2apic_state = X2APIC_DISABLED; 1599 } 1600 } 1601 #else /* CONFIG_X86_X2APIC */ 1602 static int __init validate_x2apic(void) 1603 { 1604 if (!apic_is_x2apic_enabled()) 1605 return 0; 1606 /* 1607 * Checkme: Can we simply turn off x2apic here instead of panic? 1608 */ 1609 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n"); 1610 } 1611 early_initcall(validate_x2apic); 1612 1613 static inline void try_to_enable_x2apic(int remap_mode) { } 1614 static inline void __x2apic_enable(void) { } 1615 #endif /* !CONFIG_X86_X2APIC */ 1616 1617 void __init enable_IR_x2apic(void) 1618 { 1619 unsigned long flags; 1620 int ret, ir_stat; 1621 1622 if (skip_ioapic_setup) { 1623 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n"); 1624 return; 1625 } 1626 1627 ir_stat = irq_remapping_prepare(); 1628 if (ir_stat < 0 && !x2apic_supported()) 1629 return; 1630 1631 ret = save_ioapic_entries(); 1632 if (ret) { 1633 pr_info("Saving IO-APIC state failed: %d\n", ret); 1634 return; 1635 } 1636 1637 local_irq_save(flags); 1638 legacy_pic->mask_all(); 1639 mask_ioapic_entries(); 1640 1641 /* If irq_remapping_prepare() succeeded, try to enable it */ 1642 if (ir_stat >= 0) 1643 ir_stat = irq_remapping_enable(); 1644 /* ir_stat contains the remap mode or an error code */ 1645 try_to_enable_x2apic(ir_stat); 1646 1647 if (ir_stat < 0) 1648 restore_ioapic_entries(); 1649 legacy_pic->restore_mask(); 1650 local_irq_restore(flags); 1651 } 1652 1653 #ifdef CONFIG_X86_64 1654 /* 1655 * Detect and enable local APICs on non-SMP boards. 1656 * Original code written by Keir Fraser. 1657 * On AMD64 we trust the BIOS - if it says no APIC it is likely 1658 * not correctly set up (usually the APIC timer won't work etc.) 1659 */ 1660 static int __init detect_init_APIC(void) 1661 { 1662 if (!boot_cpu_has(X86_FEATURE_APIC)) { 1663 pr_info("No local APIC present\n"); 1664 return -1; 1665 } 1666 1667 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1668 return 0; 1669 } 1670 #else 1671 1672 static int __init apic_verify(void) 1673 { 1674 u32 features, h, l; 1675 1676 /* 1677 * The APIC feature bit should now be enabled 1678 * in `cpuid' 1679 */ 1680 features = cpuid_edx(1); 1681 if (!(features & (1 << X86_FEATURE_APIC))) { 1682 pr_warning("Could not enable APIC!\n"); 1683 return -1; 1684 } 1685 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 1686 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1687 1688 /* The BIOS may have set up the APIC at some other address */ 1689 if (boot_cpu_data.x86 >= 6) { 1690 rdmsr(MSR_IA32_APICBASE, l, h); 1691 if (l & MSR_IA32_APICBASE_ENABLE) 1692 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 1693 } 1694 1695 pr_info("Found and enabled local APIC!\n"); 1696 return 0; 1697 } 1698 1699 int __init apic_force_enable(unsigned long addr) 1700 { 1701 u32 h, l; 1702 1703 if (disable_apic) 1704 return -1; 1705 1706 /* 1707 * Some BIOSes disable the local APIC in the APIC_BASE 1708 * MSR. This can only be done in software for Intel P6 or later 1709 * and AMD K7 (Model > 1) or later. 1710 */ 1711 if (boot_cpu_data.x86 >= 6) { 1712 rdmsr(MSR_IA32_APICBASE, l, h); 1713 if (!(l & MSR_IA32_APICBASE_ENABLE)) { 1714 pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 1715 l &= ~MSR_IA32_APICBASE_BASE; 1716 l |= MSR_IA32_APICBASE_ENABLE | addr; 1717 wrmsr(MSR_IA32_APICBASE, l, h); 1718 enabled_via_apicbase = 1; 1719 } 1720 } 1721 return apic_verify(); 1722 } 1723 1724 /* 1725 * Detect and initialize APIC 1726 */ 1727 static int __init detect_init_APIC(void) 1728 { 1729 /* Disabled by kernel option? */ 1730 if (disable_apic) 1731 return -1; 1732 1733 switch (boot_cpu_data.x86_vendor) { 1734 case X86_VENDOR_AMD: 1735 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 1736 (boot_cpu_data.x86 >= 15)) 1737 break; 1738 goto no_apic; 1739 case X86_VENDOR_INTEL: 1740 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 1741 (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC))) 1742 break; 1743 goto no_apic; 1744 default: 1745 goto no_apic; 1746 } 1747 1748 if (!boot_cpu_has(X86_FEATURE_APIC)) { 1749 /* 1750 * Over-ride BIOS and try to enable the local APIC only if 1751 * "lapic" specified. 1752 */ 1753 if (!force_enable_local_apic) { 1754 pr_info("Local APIC disabled by BIOS -- " 1755 "you can enable it with \"lapic\"\n"); 1756 return -1; 1757 } 1758 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) 1759 return -1; 1760 } else { 1761 if (apic_verify()) 1762 return -1; 1763 } 1764 1765 apic_pm_activate(); 1766 1767 return 0; 1768 1769 no_apic: 1770 pr_info("No local APIC present or hardware disabled\n"); 1771 return -1; 1772 } 1773 #endif 1774 1775 /** 1776 * init_apic_mappings - initialize APIC mappings 1777 */ 1778 void __init init_apic_mappings(void) 1779 { 1780 unsigned int new_apicid; 1781 1782 if (x2apic_mode) { 1783 boot_cpu_physical_apicid = read_apic_id(); 1784 return; 1785 } 1786 1787 /* If no local APIC can be found return early */ 1788 if (!smp_found_config && detect_init_APIC()) { 1789 /* lets NOP'ify apic operations */ 1790 pr_info("APIC: disable apic facility\n"); 1791 apic_disable(); 1792 } else { 1793 apic_phys = mp_lapic_addr; 1794 1795 /* 1796 * If the system has ACPI MADT tables or MP info, the LAPIC 1797 * address is already registered. 1798 */ 1799 if (!acpi_lapic && !smp_found_config) 1800 register_lapic_address(apic_phys); 1801 } 1802 1803 /* 1804 * Fetch the APIC ID of the BSP in case we have a 1805 * default configuration (or the MP table is broken). 1806 */ 1807 new_apicid = read_apic_id(); 1808 if (boot_cpu_physical_apicid != new_apicid) { 1809 boot_cpu_physical_apicid = new_apicid; 1810 /* 1811 * yeah -- we lie about apic_version 1812 * in case if apic was disabled via boot option 1813 * but it's not a problem for SMP compiled kernel 1814 * since smp_sanity_check is prepared for such a case 1815 * and disable smp mode 1816 */ 1817 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 1818 } 1819 } 1820 1821 void __init register_lapic_address(unsigned long address) 1822 { 1823 mp_lapic_addr = address; 1824 1825 if (!x2apic_mode) { 1826 set_fixmap_nocache(FIX_APIC_BASE, address); 1827 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 1828 APIC_BASE, address); 1829 } 1830 if (boot_cpu_physical_apicid == -1U) { 1831 boot_cpu_physical_apicid = read_apic_id(); 1832 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 1833 } 1834 } 1835 1836 /* 1837 * Local APIC interrupts 1838 */ 1839 1840 /* 1841 * This interrupt should _never_ happen with our APIC/SMP architecture 1842 */ 1843 static void __smp_spurious_interrupt(u8 vector) 1844 { 1845 u32 v; 1846 1847 /* 1848 * Check if this really is a spurious interrupt and ACK it 1849 * if it is a vectored one. Just in case... 1850 * Spurious interrupts should not be ACKed. 1851 */ 1852 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1)); 1853 if (v & (1 << (vector & 0x1f))) 1854 ack_APIC_irq(); 1855 1856 inc_irq_stat(irq_spurious_count); 1857 1858 /* see sw-dev-man vol 3, chapter 7.4.13.5 */ 1859 pr_info("spurious APIC interrupt through vector %02x on CPU#%d, " 1860 "should never happen.\n", vector, smp_processor_id()); 1861 } 1862 1863 __visible void __irq_entry smp_spurious_interrupt(struct pt_regs *regs) 1864 { 1865 entering_irq(); 1866 __smp_spurious_interrupt(~regs->orig_ax); 1867 exiting_irq(); 1868 } 1869 1870 __visible void __irq_entry smp_trace_spurious_interrupt(struct pt_regs *regs) 1871 { 1872 u8 vector = ~regs->orig_ax; 1873 1874 entering_irq(); 1875 trace_spurious_apic_entry(vector); 1876 __smp_spurious_interrupt(vector); 1877 trace_spurious_apic_exit(vector); 1878 exiting_irq(); 1879 } 1880 1881 /* 1882 * This interrupt should never happen with our APIC/SMP architecture 1883 */ 1884 static void __smp_error_interrupt(struct pt_regs *regs) 1885 { 1886 u32 v; 1887 u32 i = 0; 1888 static const char * const error_interrupt_reason[] = { 1889 "Send CS error", /* APIC Error Bit 0 */ 1890 "Receive CS error", /* APIC Error Bit 1 */ 1891 "Send accept error", /* APIC Error Bit 2 */ 1892 "Receive accept error", /* APIC Error Bit 3 */ 1893 "Redirectable IPI", /* APIC Error Bit 4 */ 1894 "Send illegal vector", /* APIC Error Bit 5 */ 1895 "Received illegal vector", /* APIC Error Bit 6 */ 1896 "Illegal register address", /* APIC Error Bit 7 */ 1897 }; 1898 1899 /* First tickle the hardware, only then report what went on. -- REW */ 1900 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */ 1901 apic_write(APIC_ESR, 0); 1902 v = apic_read(APIC_ESR); 1903 ack_APIC_irq(); 1904 atomic_inc(&irq_err_count); 1905 1906 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x", 1907 smp_processor_id(), v); 1908 1909 v &= 0xff; 1910 while (v) { 1911 if (v & 0x1) 1912 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); 1913 i++; 1914 v >>= 1; 1915 } 1916 1917 apic_printk(APIC_DEBUG, KERN_CONT "\n"); 1918 1919 } 1920 1921 __visible void __irq_entry smp_error_interrupt(struct pt_regs *regs) 1922 { 1923 entering_irq(); 1924 __smp_error_interrupt(regs); 1925 exiting_irq(); 1926 } 1927 1928 __visible void __irq_entry smp_trace_error_interrupt(struct pt_regs *regs) 1929 { 1930 entering_irq(); 1931 trace_error_apic_entry(ERROR_APIC_VECTOR); 1932 __smp_error_interrupt(regs); 1933 trace_error_apic_exit(ERROR_APIC_VECTOR); 1934 exiting_irq(); 1935 } 1936 1937 /** 1938 * connect_bsp_APIC - attach the APIC to the interrupt system 1939 */ 1940 static void __init connect_bsp_APIC(void) 1941 { 1942 #ifdef CONFIG_X86_32 1943 if (pic_mode) { 1944 /* 1945 * Do not trust the local APIC being empty at bootup. 1946 */ 1947 clear_local_APIC(); 1948 /* 1949 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 1950 * local APIC to INT and NMI lines. 1951 */ 1952 apic_printk(APIC_VERBOSE, "leaving PIC mode, " 1953 "enabling APIC mode.\n"); 1954 imcr_pic_to_apic(); 1955 } 1956 #endif 1957 } 1958 1959 /** 1960 * disconnect_bsp_APIC - detach the APIC from the interrupt system 1961 * @virt_wire_setup: indicates, whether virtual wire mode is selected 1962 * 1963 * Virtual wire mode is necessary to deliver legacy interrupts even when the 1964 * APIC is disabled. 1965 */ 1966 void disconnect_bsp_APIC(int virt_wire_setup) 1967 { 1968 unsigned int value; 1969 1970 #ifdef CONFIG_X86_32 1971 if (pic_mode) { 1972 /* 1973 * Put the board back into PIC mode (has an effect only on 1974 * certain older boards). Note that APIC interrupts, including 1975 * IPIs, won't work beyond this point! The only exception are 1976 * INIT IPIs. 1977 */ 1978 apic_printk(APIC_VERBOSE, "disabling APIC mode, " 1979 "entering PIC mode.\n"); 1980 imcr_apic_to_pic(); 1981 return; 1982 } 1983 #endif 1984 1985 /* Go back to Virtual Wire compatibility mode */ 1986 1987 /* For the spurious interrupt use vector F, and enable it */ 1988 value = apic_read(APIC_SPIV); 1989 value &= ~APIC_VECTOR_MASK; 1990 value |= APIC_SPIV_APIC_ENABLED; 1991 value |= 0xf; 1992 apic_write(APIC_SPIV, value); 1993 1994 if (!virt_wire_setup) { 1995 /* 1996 * For LVT0 make it edge triggered, active high, 1997 * external and enabled 1998 */ 1999 value = apic_read(APIC_LVT0); 2000 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2001 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2002 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2003 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2004 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 2005 apic_write(APIC_LVT0, value); 2006 } else { 2007 /* Disable LVT0 */ 2008 apic_write(APIC_LVT0, APIC_LVT_MASKED); 2009 } 2010 2011 /* 2012 * For LVT1 make it edge triggered, active high, 2013 * nmi and enabled 2014 */ 2015 value = apic_read(APIC_LVT1); 2016 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2017 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2018 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2019 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2020 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 2021 apic_write(APIC_LVT1, value); 2022 } 2023 2024 /* 2025 * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated 2026 * contiguously, it equals to current allocated max logical CPU ID plus 1. 2027 * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range, 2028 * so the maximum of nr_logical_cpuids is nr_cpu_ids. 2029 * 2030 * NOTE: Reserve 0 for BSP. 2031 */ 2032 static int nr_logical_cpuids = 1; 2033 2034 /* 2035 * Used to store mapping between logical CPU IDs and APIC IDs. 2036 */ 2037 static int cpuid_to_apicid[] = { 2038 [0 ... NR_CPUS - 1] = -1, 2039 }; 2040 2041 /* 2042 * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids 2043 * and cpuid_to_apicid[] synchronized. 2044 */ 2045 static int allocate_logical_cpuid(int apicid) 2046 { 2047 int i; 2048 2049 /* 2050 * cpuid <-> apicid mapping is persistent, so when a cpu is up, 2051 * check if the kernel has allocated a cpuid for it. 2052 */ 2053 for (i = 0; i < nr_logical_cpuids; i++) { 2054 if (cpuid_to_apicid[i] == apicid) 2055 return i; 2056 } 2057 2058 /* Allocate a new cpuid. */ 2059 if (nr_logical_cpuids >= nr_cpu_ids) { 2060 WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %i reached. " 2061 "Processor %d/0x%x and the rest are ignored.\n", 2062 nr_cpu_ids, nr_logical_cpuids, apicid); 2063 return -EINVAL; 2064 } 2065 2066 cpuid_to_apicid[nr_logical_cpuids] = apicid; 2067 return nr_logical_cpuids++; 2068 } 2069 2070 int generic_processor_info(int apicid, int version) 2071 { 2072 int cpu, max = nr_cpu_ids; 2073 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, 2074 phys_cpu_present_map); 2075 2076 /* 2077 * boot_cpu_physical_apicid is designed to have the apicid 2078 * returned by read_apic_id(), i.e, the apicid of the 2079 * currently booting-up processor. However, on some platforms, 2080 * it is temporarily modified by the apicid reported as BSP 2081 * through MP table. Concretely: 2082 * 2083 * - arch/x86/kernel/mpparse.c: MP_processor_info() 2084 * - arch/x86/mm/amdtopology.c: amd_numa_init() 2085 * 2086 * This function is executed with the modified 2087 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel 2088 * parameter doesn't work to disable APs on kdump 2nd kernel. 2089 * 2090 * Since fixing handling of boot_cpu_physical_apicid requires 2091 * another discussion and tests on each platform, we leave it 2092 * for now and here we use read_apic_id() directly in this 2093 * function, __generic_processor_info(). 2094 */ 2095 if (disabled_cpu_apicid != BAD_APICID && 2096 disabled_cpu_apicid != read_apic_id() && 2097 disabled_cpu_apicid == apicid) { 2098 int thiscpu = num_processors + disabled_cpus; 2099 2100 pr_warning("APIC: Disabling requested cpu." 2101 " Processor %d/0x%x ignored.\n", 2102 thiscpu, apicid); 2103 2104 disabled_cpus++; 2105 return -ENODEV; 2106 } 2107 2108 /* 2109 * If boot cpu has not been detected yet, then only allow upto 2110 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu 2111 */ 2112 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && 2113 apicid != boot_cpu_physical_apicid) { 2114 int thiscpu = max + disabled_cpus - 1; 2115 2116 pr_warning( 2117 "APIC: NR_CPUS/possible_cpus limit of %i almost" 2118 " reached. Keeping one slot for boot cpu." 2119 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 2120 2121 disabled_cpus++; 2122 return -ENODEV; 2123 } 2124 2125 if (num_processors >= nr_cpu_ids) { 2126 int thiscpu = max + disabled_cpus; 2127 2128 pr_warning("APIC: NR_CPUS/possible_cpus limit of %i " 2129 "reached. Processor %d/0x%x ignored.\n", 2130 max, thiscpu, apicid); 2131 2132 disabled_cpus++; 2133 return -EINVAL; 2134 } 2135 2136 if (apicid == boot_cpu_physical_apicid) { 2137 /* 2138 * x86_bios_cpu_apicid is required to have processors listed 2139 * in same order as logical cpu numbers. Hence the first 2140 * entry is BSP, and so on. 2141 * boot_cpu_init() already hold bit 0 in cpu_present_mask 2142 * for BSP. 2143 */ 2144 cpu = 0; 2145 2146 /* Logical cpuid 0 is reserved for BSP. */ 2147 cpuid_to_apicid[0] = apicid; 2148 } else { 2149 cpu = allocate_logical_cpuid(apicid); 2150 if (cpu < 0) { 2151 disabled_cpus++; 2152 return -EINVAL; 2153 } 2154 } 2155 2156 /* 2157 * Validate version 2158 */ 2159 if (version == 0x0) { 2160 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", 2161 cpu, apicid); 2162 version = 0x10; 2163 } 2164 2165 if (version != boot_cpu_apic_version) { 2166 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", 2167 boot_cpu_apic_version, cpu, version); 2168 } 2169 2170 if (apicid > max_physical_apicid) 2171 max_physical_apicid = apicid; 2172 2173 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 2174 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 2175 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 2176 #endif 2177 #ifdef CONFIG_X86_32 2178 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 2179 apic->x86_32_early_logical_apicid(cpu); 2180 #endif 2181 set_cpu_possible(cpu, true); 2182 physid_set(apicid, phys_cpu_present_map); 2183 set_cpu_present(cpu, true); 2184 num_processors++; 2185 2186 return cpu; 2187 } 2188 2189 int hard_smp_processor_id(void) 2190 { 2191 return read_apic_id(); 2192 } 2193 2194 void default_init_apic_ldr(void) 2195 { 2196 unsigned long val; 2197 2198 apic_write(APIC_DFR, APIC_DFR_VALUE); 2199 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; 2200 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); 2201 apic_write(APIC_LDR, val); 2202 } 2203 2204 int default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 2205 const struct cpumask *andmask, 2206 unsigned int *apicid) 2207 { 2208 unsigned int cpu; 2209 2210 for_each_cpu_and(cpu, cpumask, andmask) { 2211 if (cpumask_test_cpu(cpu, cpu_online_mask)) 2212 break; 2213 } 2214 2215 if (likely(cpu < nr_cpu_ids)) { 2216 *apicid = per_cpu(x86_cpu_to_apicid, cpu); 2217 return 0; 2218 } 2219 2220 return -EINVAL; 2221 } 2222 2223 /* 2224 * Override the generic EOI implementation with an optimized version. 2225 * Only called during early boot when only one CPU is active and with 2226 * interrupts disabled, so we know this does not race with actual APIC driver 2227 * use. 2228 */ 2229 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) 2230 { 2231 struct apic **drv; 2232 2233 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { 2234 /* Should happen once for each apic */ 2235 WARN_ON((*drv)->eoi_write == eoi_write); 2236 (*drv)->native_eoi_write = (*drv)->eoi_write; 2237 (*drv)->eoi_write = eoi_write; 2238 } 2239 } 2240 2241 static void __init apic_bsp_up_setup(void) 2242 { 2243 #ifdef CONFIG_X86_64 2244 apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid)); 2245 #else 2246 /* 2247 * Hack: In case of kdump, after a crash, kernel might be booting 2248 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 2249 * might be zero if read from MP tables. Get it from LAPIC. 2250 */ 2251 # ifdef CONFIG_CRASH_DUMP 2252 boot_cpu_physical_apicid = read_apic_id(); 2253 # endif 2254 #endif 2255 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 2256 } 2257 2258 /** 2259 * apic_bsp_setup - Setup function for local apic and io-apic 2260 * @upmode: Force UP mode (for APIC_init_uniprocessor) 2261 * 2262 * Returns: 2263 * apic_id of BSP APIC 2264 */ 2265 int __init apic_bsp_setup(bool upmode) 2266 { 2267 int id; 2268 2269 connect_bsp_APIC(); 2270 if (upmode) 2271 apic_bsp_up_setup(); 2272 setup_local_APIC(); 2273 2274 if (x2apic_mode) 2275 id = apic_read(APIC_LDR); 2276 else 2277 id = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 2278 2279 enable_IO_APIC(); 2280 end_local_APIC_setup(); 2281 irq_remap_enable_fault_handling(); 2282 setup_IO_APIC(); 2283 /* Setup local timer */ 2284 x86_init.timers.setup_percpu_clockev(); 2285 return id; 2286 } 2287 2288 /* 2289 * This initializes the IO-APIC and APIC hardware if this is 2290 * a UP kernel. 2291 */ 2292 int __init APIC_init_uniprocessor(void) 2293 { 2294 if (disable_apic) { 2295 pr_info("Apic disabled\n"); 2296 return -1; 2297 } 2298 #ifdef CONFIG_X86_64 2299 if (!boot_cpu_has(X86_FEATURE_APIC)) { 2300 disable_apic = 1; 2301 pr_info("Apic disabled by BIOS\n"); 2302 return -1; 2303 } 2304 #else 2305 if (!smp_found_config && !boot_cpu_has(X86_FEATURE_APIC)) 2306 return -1; 2307 2308 /* 2309 * Complain if the BIOS pretends there is one. 2310 */ 2311 if (!boot_cpu_has(X86_FEATURE_APIC) && 2312 APIC_INTEGRATED(boot_cpu_apic_version)) { 2313 pr_err("BIOS bug, local APIC 0x%x not detected!...\n", 2314 boot_cpu_physical_apicid); 2315 return -1; 2316 } 2317 #endif 2318 2319 if (!smp_found_config) 2320 disable_ioapic_support(); 2321 2322 default_setup_apic_routing(); 2323 apic_bsp_setup(true); 2324 return 0; 2325 } 2326 2327 #ifdef CONFIG_UP_LATE_INIT 2328 void __init up_late_init(void) 2329 { 2330 APIC_init_uniprocessor(); 2331 } 2332 #endif 2333 2334 /* 2335 * Power management 2336 */ 2337 #ifdef CONFIG_PM 2338 2339 static struct { 2340 /* 2341 * 'active' is true if the local APIC was enabled by us and 2342 * not the BIOS; this signifies that we are also responsible 2343 * for disabling it before entering apm/acpi suspend 2344 */ 2345 int active; 2346 /* r/w apic fields */ 2347 unsigned int apic_id; 2348 unsigned int apic_taskpri; 2349 unsigned int apic_ldr; 2350 unsigned int apic_dfr; 2351 unsigned int apic_spiv; 2352 unsigned int apic_lvtt; 2353 unsigned int apic_lvtpc; 2354 unsigned int apic_lvt0; 2355 unsigned int apic_lvt1; 2356 unsigned int apic_lvterr; 2357 unsigned int apic_tmict; 2358 unsigned int apic_tdcr; 2359 unsigned int apic_thmr; 2360 unsigned int apic_cmci; 2361 } apic_pm_state; 2362 2363 static int lapic_suspend(void) 2364 { 2365 unsigned long flags; 2366 int maxlvt; 2367 2368 if (!apic_pm_state.active) 2369 return 0; 2370 2371 maxlvt = lapic_get_maxlvt(); 2372 2373 apic_pm_state.apic_id = apic_read(APIC_ID); 2374 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 2375 apic_pm_state.apic_ldr = apic_read(APIC_LDR); 2376 apic_pm_state.apic_dfr = apic_read(APIC_DFR); 2377 apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2378 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2379 if (maxlvt >= 4) 2380 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2381 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2382 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2383 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2384 apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2385 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 2386 #ifdef CONFIG_X86_THERMAL_VECTOR 2387 if (maxlvt >= 5) 2388 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2389 #endif 2390 #ifdef CONFIG_X86_MCE_INTEL 2391 if (maxlvt >= 6) 2392 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI); 2393 #endif 2394 2395 local_irq_save(flags); 2396 disable_local_APIC(); 2397 2398 irq_remapping_disable(); 2399 2400 local_irq_restore(flags); 2401 return 0; 2402 } 2403 2404 static void lapic_resume(void) 2405 { 2406 unsigned int l, h; 2407 unsigned long flags; 2408 int maxlvt; 2409 2410 if (!apic_pm_state.active) 2411 return; 2412 2413 local_irq_save(flags); 2414 2415 /* 2416 * IO-APIC and PIC have their own resume routines. 2417 * We just mask them here to make sure the interrupt 2418 * subsystem is completely quiet while we enable x2apic 2419 * and interrupt-remapping. 2420 */ 2421 mask_ioapic_entries(); 2422 legacy_pic->mask_all(); 2423 2424 if (x2apic_mode) { 2425 __x2apic_enable(); 2426 } else { 2427 /* 2428 * Make sure the APICBASE points to the right address 2429 * 2430 * FIXME! This will be wrong if we ever support suspend on 2431 * SMP! We'll need to do this as part of the CPU restore! 2432 */ 2433 if (boot_cpu_data.x86 >= 6) { 2434 rdmsr(MSR_IA32_APICBASE, l, h); 2435 l &= ~MSR_IA32_APICBASE_BASE; 2436 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2437 wrmsr(MSR_IA32_APICBASE, l, h); 2438 } 2439 } 2440 2441 maxlvt = lapic_get_maxlvt(); 2442 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2443 apic_write(APIC_ID, apic_pm_state.apic_id); 2444 apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2445 apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2446 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2447 apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2448 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2449 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 2450 #ifdef CONFIG_X86_THERMAL_VECTOR 2451 if (maxlvt >= 5) 2452 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2453 #endif 2454 #ifdef CONFIG_X86_MCE_INTEL 2455 if (maxlvt >= 6) 2456 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci); 2457 #endif 2458 if (maxlvt >= 4) 2459 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2460 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2461 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2462 apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2463 apic_write(APIC_ESR, 0); 2464 apic_read(APIC_ESR); 2465 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2466 apic_write(APIC_ESR, 0); 2467 apic_read(APIC_ESR); 2468 2469 irq_remapping_reenable(x2apic_mode); 2470 2471 local_irq_restore(flags); 2472 } 2473 2474 /* 2475 * This device has no shutdown method - fully functioning local APICs 2476 * are needed on every CPU up until machine_halt/restart/poweroff. 2477 */ 2478 2479 static struct syscore_ops lapic_syscore_ops = { 2480 .resume = lapic_resume, 2481 .suspend = lapic_suspend, 2482 }; 2483 2484 static void apic_pm_activate(void) 2485 { 2486 apic_pm_state.active = 1; 2487 } 2488 2489 static int __init init_lapic_sysfs(void) 2490 { 2491 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 2492 if (boot_cpu_has(X86_FEATURE_APIC)) 2493 register_syscore_ops(&lapic_syscore_ops); 2494 2495 return 0; 2496 } 2497 2498 /* local apic needs to resume before other devices access its registers. */ 2499 core_initcall(init_lapic_sysfs); 2500 2501 #else /* CONFIG_PM */ 2502 2503 static void apic_pm_activate(void) { } 2504 2505 #endif /* CONFIG_PM */ 2506 2507 #ifdef CONFIG_X86_64 2508 2509 static int multi_checked; 2510 static int multi; 2511 2512 static int set_multi(const struct dmi_system_id *d) 2513 { 2514 if (multi) 2515 return 0; 2516 pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2517 multi = 1; 2518 return 0; 2519 } 2520 2521 static const struct dmi_system_id multi_dmi_table[] = { 2522 { 2523 .callback = set_multi, 2524 .ident = "IBM System Summit2", 2525 .matches = { 2526 DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2527 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2528 }, 2529 }, 2530 {} 2531 }; 2532 2533 static void dmi_check_multi(void) 2534 { 2535 if (multi_checked) 2536 return; 2537 2538 dmi_check_system(multi_dmi_table); 2539 multi_checked = 1; 2540 } 2541 2542 /* 2543 * apic_is_clustered_box() -- Check if we can expect good TSC 2544 * 2545 * Thus far, the major user of this is IBM's Summit2 series: 2546 * Clustered boxes may have unsynced TSC problems if they are 2547 * multi-chassis. 2548 * Use DMI to check them 2549 */ 2550 int apic_is_clustered_box(void) 2551 { 2552 dmi_check_multi(); 2553 return multi; 2554 } 2555 #endif 2556 2557 /* 2558 * APIC command line parameters 2559 */ 2560 static int __init setup_disableapic(char *arg) 2561 { 2562 disable_apic = 1; 2563 setup_clear_cpu_cap(X86_FEATURE_APIC); 2564 return 0; 2565 } 2566 early_param("disableapic", setup_disableapic); 2567 2568 /* same as disableapic, for compatibility */ 2569 static int __init setup_nolapic(char *arg) 2570 { 2571 return setup_disableapic(arg); 2572 } 2573 early_param("nolapic", setup_nolapic); 2574 2575 static int __init parse_lapic_timer_c2_ok(char *arg) 2576 { 2577 local_apic_timer_c2_ok = 1; 2578 return 0; 2579 } 2580 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2581 2582 static int __init parse_disable_apic_timer(char *arg) 2583 { 2584 disable_apic_timer = 1; 2585 return 0; 2586 } 2587 early_param("noapictimer", parse_disable_apic_timer); 2588 2589 static int __init parse_nolapic_timer(char *arg) 2590 { 2591 disable_apic_timer = 1; 2592 return 0; 2593 } 2594 early_param("nolapic_timer", parse_nolapic_timer); 2595 2596 static int __init apic_set_verbosity(char *arg) 2597 { 2598 if (!arg) { 2599 #ifdef CONFIG_X86_64 2600 skip_ioapic_setup = 0; 2601 return 0; 2602 #endif 2603 return -EINVAL; 2604 } 2605 2606 if (strcmp("debug", arg) == 0) 2607 apic_verbosity = APIC_DEBUG; 2608 else if (strcmp("verbose", arg) == 0) 2609 apic_verbosity = APIC_VERBOSE; 2610 else { 2611 pr_warning("APIC Verbosity level %s not recognised" 2612 " use apic=verbose or apic=debug\n", arg); 2613 return -EINVAL; 2614 } 2615 2616 return 0; 2617 } 2618 early_param("apic", apic_set_verbosity); 2619 2620 static int __init lapic_insert_resource(void) 2621 { 2622 if (!apic_phys) 2623 return -1; 2624 2625 /* Put local APIC into the resource map. */ 2626 lapic_resource.start = apic_phys; 2627 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2628 insert_resource(&iomem_resource, &lapic_resource); 2629 2630 return 0; 2631 } 2632 2633 /* 2634 * need call insert after e820__reserve_resources() 2635 * that is using request_resource 2636 */ 2637 late_initcall(lapic_insert_resource); 2638 2639 static int __init apic_set_disabled_cpu_apicid(char *arg) 2640 { 2641 if (!arg || !get_option(&arg, &disabled_cpu_apicid)) 2642 return -EINVAL; 2643 2644 return 0; 2645 } 2646 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); 2647 2648 static int __init apic_set_extnmi(char *arg) 2649 { 2650 if (!arg) 2651 return -EINVAL; 2652 2653 if (!strncmp("all", arg, 3)) 2654 apic_extnmi = APIC_EXTNMI_ALL; 2655 else if (!strncmp("none", arg, 4)) 2656 apic_extnmi = APIC_EXTNMI_NONE; 2657 else if (!strncmp("bsp", arg, 3)) 2658 apic_extnmi = APIC_EXTNMI_BSP; 2659 else { 2660 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg); 2661 return -EINVAL; 2662 } 2663 2664 return 0; 2665 } 2666 early_param("apic_extnmi", apic_set_extnmi); 2667