1 /* 2 * Local APIC handling, local APIC timers 3 * 4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 5 * 6 * Fixes 7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 8 * thanks to Eric Gilmore 9 * and Rolf G. Tews 10 * for testing these extensively. 11 * Maciej W. Rozycki : Various updates and fixes. 12 * Mikael Pettersson : Power Management for UP-APIC. 13 * Pavel Machek and 14 * Mikael Pettersson : PM converted to driver model. 15 */ 16 17 #include <linux/perf_event.h> 18 #include <linux/kernel_stat.h> 19 #include <linux/mc146818rtc.h> 20 #include <linux/acpi_pmtmr.h> 21 #include <linux/clockchips.h> 22 #include <linux/interrupt.h> 23 #include <linux/bootmem.h> 24 #include <linux/ftrace.h> 25 #include <linux/ioport.h> 26 #include <linux/module.h> 27 #include <linux/sysdev.h> 28 #include <linux/delay.h> 29 #include <linux/timex.h> 30 #include <linux/dmar.h> 31 #include <linux/init.h> 32 #include <linux/cpu.h> 33 #include <linux/dmi.h> 34 #include <linux/nmi.h> 35 #include <linux/smp.h> 36 #include <linux/mm.h> 37 38 #include <asm/perf_event.h> 39 #include <asm/x86_init.h> 40 #include <asm/pgalloc.h> 41 #include <asm/atomic.h> 42 #include <asm/mpspec.h> 43 #include <asm/i8253.h> 44 #include <asm/i8259.h> 45 #include <asm/proto.h> 46 #include <asm/apic.h> 47 #include <asm/desc.h> 48 #include <asm/hpet.h> 49 #include <asm/idle.h> 50 #include <asm/mtrr.h> 51 #include <asm/smp.h> 52 #include <asm/mce.h> 53 #include <asm/kvm_para.h> 54 55 unsigned int num_processors; 56 57 unsigned disabled_cpus __cpuinitdata; 58 59 /* Processor that is doing the boot up */ 60 unsigned int boot_cpu_physical_apicid = -1U; 61 62 /* 63 * The highest APIC ID seen during enumeration. 64 * 65 * This determines the messaging protocol we can use: if all APIC IDs 66 * are in the 0 ... 7 range, then we can use logical addressing which 67 * has some performance advantages (better broadcasting). 68 * 69 * If there's an APIC ID above 8, we use physical addressing. 70 */ 71 unsigned int max_physical_apicid; 72 73 /* 74 * Bitmask of physically existing CPUs: 75 */ 76 physid_mask_t phys_cpu_present_map; 77 78 /* 79 * Map cpu index to physical APIC ID 80 */ 81 DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID); 82 DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID); 83 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 84 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 85 86 #ifdef CONFIG_X86_32 87 /* 88 * Knob to control our willingness to enable the local APIC. 89 * 90 * +1=force-enable 91 */ 92 static int force_enable_local_apic; 93 /* 94 * APIC command line parameters 95 */ 96 static int __init parse_lapic(char *arg) 97 { 98 force_enable_local_apic = 1; 99 return 0; 100 } 101 early_param("lapic", parse_lapic); 102 /* Local APIC was disabled by the BIOS and enabled by the kernel */ 103 static int enabled_via_apicbase; 104 105 /* 106 * Handle interrupt mode configuration register (IMCR). 107 * This register controls whether the interrupt signals 108 * that reach the BSP come from the master PIC or from the 109 * local APIC. Before entering Symmetric I/O Mode, either 110 * the BIOS or the operating system must switch out of 111 * PIC Mode by changing the IMCR. 112 */ 113 static inline void imcr_pic_to_apic(void) 114 { 115 /* select IMCR register */ 116 outb(0x70, 0x22); 117 /* NMI and 8259 INTR go through APIC */ 118 outb(0x01, 0x23); 119 } 120 121 static inline void imcr_apic_to_pic(void) 122 { 123 /* select IMCR register */ 124 outb(0x70, 0x22); 125 /* NMI and 8259 INTR go directly to BSP */ 126 outb(0x00, 0x23); 127 } 128 #endif 129 130 #ifdef CONFIG_X86_64 131 static int apic_calibrate_pmtmr __initdata; 132 static __init int setup_apicpmtimer(char *s) 133 { 134 apic_calibrate_pmtmr = 1; 135 notsc_setup(NULL); 136 return 0; 137 } 138 __setup("apicpmtimer", setup_apicpmtimer); 139 #endif 140 141 int x2apic_mode; 142 #ifdef CONFIG_X86_X2APIC 143 /* x2apic enabled before OS handover */ 144 static int x2apic_preenabled; 145 static __init int setup_nox2apic(char *str) 146 { 147 if (x2apic_enabled()) { 148 pr_warning("Bios already enabled x2apic, " 149 "can't enforce nox2apic"); 150 return 0; 151 } 152 153 setup_clear_cpu_cap(X86_FEATURE_X2APIC); 154 return 0; 155 } 156 early_param("nox2apic", setup_nox2apic); 157 #endif 158 159 unsigned long mp_lapic_addr; 160 int disable_apic; 161 /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 162 static int disable_apic_timer __cpuinitdata; 163 /* Local APIC timer works in C2 */ 164 int local_apic_timer_c2_ok; 165 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 166 167 int first_system_vector = 0xfe; 168 169 /* 170 * Debug level, exported for io_apic.c 171 */ 172 unsigned int apic_verbosity; 173 174 int pic_mode; 175 176 /* Have we found an MP table */ 177 int smp_found_config; 178 179 static struct resource lapic_resource = { 180 .name = "Local APIC", 181 .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 182 }; 183 184 static unsigned int calibration_result; 185 186 static int lapic_next_event(unsigned long delta, 187 struct clock_event_device *evt); 188 static void lapic_timer_setup(enum clock_event_mode mode, 189 struct clock_event_device *evt); 190 static void lapic_timer_broadcast(const struct cpumask *mask); 191 static void apic_pm_activate(void); 192 193 /* 194 * The local apic timer can be used for any function which is CPU local. 195 */ 196 static struct clock_event_device lapic_clockevent = { 197 .name = "lapic", 198 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT 199 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, 200 .shift = 32, 201 .set_mode = lapic_timer_setup, 202 .set_next_event = lapic_next_event, 203 .broadcast = lapic_timer_broadcast, 204 .rating = 100, 205 .irq = -1, 206 }; 207 static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 208 209 static unsigned long apic_phys; 210 211 /* 212 * Get the LAPIC version 213 */ 214 static inline int lapic_get_version(void) 215 { 216 return GET_APIC_VERSION(apic_read(APIC_LVR)); 217 } 218 219 /* 220 * Check, if the APIC is integrated or a separate chip 221 */ 222 static inline int lapic_is_integrated(void) 223 { 224 #ifdef CONFIG_X86_64 225 return 1; 226 #else 227 return APIC_INTEGRATED(lapic_get_version()); 228 #endif 229 } 230 231 /* 232 * Check, whether this is a modern or a first generation APIC 233 */ 234 static int modern_apic(void) 235 { 236 /* AMD systems use old APIC versions, so check the CPU */ 237 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 238 boot_cpu_data.x86 >= 0xf) 239 return 1; 240 return lapic_get_version() >= 0x14; 241 } 242 243 /* 244 * right after this call apic become NOOP driven 245 * so apic->write/read doesn't do anything 246 */ 247 void apic_disable(void) 248 { 249 pr_info("APIC: switched to apic NOOP\n"); 250 apic = &apic_noop; 251 } 252 253 void native_apic_wait_icr_idle(void) 254 { 255 while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 256 cpu_relax(); 257 } 258 259 u32 native_safe_apic_wait_icr_idle(void) 260 { 261 u32 send_status; 262 int timeout; 263 264 timeout = 0; 265 do { 266 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 267 if (!send_status) 268 break; 269 udelay(100); 270 } while (timeout++ < 1000); 271 272 return send_status; 273 } 274 275 void native_apic_icr_write(u32 low, u32 id) 276 { 277 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 278 apic_write(APIC_ICR, low); 279 } 280 281 u64 native_apic_icr_read(void) 282 { 283 u32 icr1, icr2; 284 285 icr2 = apic_read(APIC_ICR2); 286 icr1 = apic_read(APIC_ICR); 287 288 return icr1 | ((u64)icr2 << 32); 289 } 290 291 /** 292 * enable_NMI_through_LVT0 - enable NMI through local vector table 0 293 */ 294 void __cpuinit enable_NMI_through_LVT0(void) 295 { 296 unsigned int v; 297 298 /* unmask and set to NMI */ 299 v = APIC_DM_NMI; 300 301 /* Level triggered for 82489DX (32bit mode) */ 302 if (!lapic_is_integrated()) 303 v |= APIC_LVT_LEVEL_TRIGGER; 304 305 apic_write(APIC_LVT0, v); 306 } 307 308 #ifdef CONFIG_X86_32 309 /** 310 * get_physical_broadcast - Get number of physical broadcast IDs 311 */ 312 int get_physical_broadcast(void) 313 { 314 return modern_apic() ? 0xff : 0xf; 315 } 316 #endif 317 318 /** 319 * lapic_get_maxlvt - get the maximum number of local vector table entries 320 */ 321 int lapic_get_maxlvt(void) 322 { 323 unsigned int v; 324 325 v = apic_read(APIC_LVR); 326 /* 327 * - we always have APIC integrated on 64bit mode 328 * - 82489DXs do not report # of LVT entries 329 */ 330 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; 331 } 332 333 /* 334 * Local APIC timer 335 */ 336 337 /* Clock divisor */ 338 #define APIC_DIVISOR 16 339 340 /* 341 * This function sets up the local APIC timer, with a timeout of 342 * 'clocks' APIC bus clock. During calibration we actually call 343 * this function twice on the boot CPU, once with a bogus timeout 344 * value, second time for real. The other (noncalibrating) CPUs 345 * call this function only once, with the real, calibrated value. 346 * 347 * We do reads before writes even if unnecessary, to get around the 348 * P5 APIC double write bug. 349 */ 350 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 351 { 352 unsigned int lvtt_value, tmp_value; 353 354 lvtt_value = LOCAL_TIMER_VECTOR; 355 if (!oneshot) 356 lvtt_value |= APIC_LVT_TIMER_PERIODIC; 357 if (!lapic_is_integrated()) 358 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 359 360 if (!irqen) 361 lvtt_value |= APIC_LVT_MASKED; 362 363 apic_write(APIC_LVTT, lvtt_value); 364 365 /* 366 * Divide PICLK by 16 367 */ 368 tmp_value = apic_read(APIC_TDCR); 369 apic_write(APIC_TDCR, 370 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 371 APIC_TDR_DIV_16); 372 373 if (!oneshot) 374 apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 375 } 376 377 /* 378 * Setup extended LVT, AMD specific (K8, family 10h) 379 * 380 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and 381 * MCE interrupts are supported. Thus MCE offset must be set to 0. 382 * 383 * If mask=1, the LVT entry does not generate interrupts while mask=0 384 * enables the vector. See also the BKDGs. 385 */ 386 387 #define APIC_EILVT_LVTOFF_MCE 0 388 #define APIC_EILVT_LVTOFF_IBS 1 389 390 static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) 391 { 392 unsigned long reg = (lvt_off << 4) + APIC_EILVTn(0); 393 unsigned int v = (mask << 16) | (msg_type << 8) | vector; 394 395 apic_write(reg, v); 396 } 397 398 u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) 399 { 400 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); 401 return APIC_EILVT_LVTOFF_MCE; 402 } 403 404 u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) 405 { 406 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); 407 return APIC_EILVT_LVTOFF_IBS; 408 } 409 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs); 410 411 /* 412 * Program the next event, relative to now 413 */ 414 static int lapic_next_event(unsigned long delta, 415 struct clock_event_device *evt) 416 { 417 apic_write(APIC_TMICT, delta); 418 return 0; 419 } 420 421 /* 422 * Setup the lapic timer in periodic or oneshot mode 423 */ 424 static void lapic_timer_setup(enum clock_event_mode mode, 425 struct clock_event_device *evt) 426 { 427 unsigned long flags; 428 unsigned int v; 429 430 /* Lapic used as dummy for broadcast ? */ 431 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 432 return; 433 434 local_irq_save(flags); 435 436 switch (mode) { 437 case CLOCK_EVT_MODE_PERIODIC: 438 case CLOCK_EVT_MODE_ONESHOT: 439 __setup_APIC_LVTT(calibration_result, 440 mode != CLOCK_EVT_MODE_PERIODIC, 1); 441 break; 442 case CLOCK_EVT_MODE_UNUSED: 443 case CLOCK_EVT_MODE_SHUTDOWN: 444 v = apic_read(APIC_LVTT); 445 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 446 apic_write(APIC_LVTT, v); 447 apic_write(APIC_TMICT, 0); 448 break; 449 case CLOCK_EVT_MODE_RESUME: 450 /* Nothing to do here */ 451 break; 452 } 453 454 local_irq_restore(flags); 455 } 456 457 /* 458 * Local APIC timer broadcast function 459 */ 460 static void lapic_timer_broadcast(const struct cpumask *mask) 461 { 462 #ifdef CONFIG_SMP 463 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 464 #endif 465 } 466 467 /* 468 * Setup the local APIC timer for this CPU. Copy the initilized values 469 * of the boot CPU and register the clock event in the framework. 470 */ 471 static void __cpuinit setup_APIC_timer(void) 472 { 473 struct clock_event_device *levt = &__get_cpu_var(lapic_events); 474 475 if (cpu_has(¤t_cpu_data, X86_FEATURE_ARAT)) { 476 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 477 /* Make LAPIC timer preferrable over percpu HPET */ 478 lapic_clockevent.rating = 150; 479 } 480 481 memcpy(levt, &lapic_clockevent, sizeof(*levt)); 482 levt->cpumask = cpumask_of(smp_processor_id()); 483 484 clockevents_register_device(levt); 485 } 486 487 /* 488 * In this functions we calibrate APIC bus clocks to the external timer. 489 * 490 * We want to do the calibration only once since we want to have local timer 491 * irqs syncron. CPUs connected by the same APIC bus have the very same bus 492 * frequency. 493 * 494 * This was previously done by reading the PIT/HPET and waiting for a wrap 495 * around to find out, that a tick has elapsed. I have a box, where the PIT 496 * readout is broken, so it never gets out of the wait loop again. This was 497 * also reported by others. 498 * 499 * Monitoring the jiffies value is inaccurate and the clockevents 500 * infrastructure allows us to do a simple substitution of the interrupt 501 * handler. 502 * 503 * The calibration routine also uses the pm_timer when possible, as the PIT 504 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 505 * back to normal later in the boot process). 506 */ 507 508 #define LAPIC_CAL_LOOPS (HZ/10) 509 510 static __initdata int lapic_cal_loops = -1; 511 static __initdata long lapic_cal_t1, lapic_cal_t2; 512 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 513 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 514 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 515 516 /* 517 * Temporary interrupt handler. 518 */ 519 static void __init lapic_cal_handler(struct clock_event_device *dev) 520 { 521 unsigned long long tsc = 0; 522 long tapic = apic_read(APIC_TMCCT); 523 unsigned long pm = acpi_pm_read_early(); 524 525 if (cpu_has_tsc) 526 rdtscll(tsc); 527 528 switch (lapic_cal_loops++) { 529 case 0: 530 lapic_cal_t1 = tapic; 531 lapic_cal_tsc1 = tsc; 532 lapic_cal_pm1 = pm; 533 lapic_cal_j1 = jiffies; 534 break; 535 536 case LAPIC_CAL_LOOPS: 537 lapic_cal_t2 = tapic; 538 lapic_cal_tsc2 = tsc; 539 if (pm < lapic_cal_pm1) 540 pm += ACPI_PM_OVRRUN; 541 lapic_cal_pm2 = pm; 542 lapic_cal_j2 = jiffies; 543 break; 544 } 545 } 546 547 static int __init 548 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 549 { 550 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 551 const long pm_thresh = pm_100ms / 100; 552 unsigned long mult; 553 u64 res; 554 555 #ifndef CONFIG_X86_PM_TIMER 556 return -1; 557 #endif 558 559 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 560 561 /* Check, if the PM timer is available */ 562 if (!deltapm) 563 return -1; 564 565 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 566 567 if (deltapm > (pm_100ms - pm_thresh) && 568 deltapm < (pm_100ms + pm_thresh)) { 569 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 570 return 0; 571 } 572 573 res = (((u64)deltapm) * mult) >> 22; 574 do_div(res, 1000000); 575 pr_warning("APIC calibration not consistent " 576 "with PM-Timer: %ldms instead of 100ms\n",(long)res); 577 578 /* Correct the lapic counter value */ 579 res = (((u64)(*delta)) * pm_100ms); 580 do_div(res, deltapm); 581 pr_info("APIC delta adjusted to PM-Timer: " 582 "%lu (%ld)\n", (unsigned long)res, *delta); 583 *delta = (long)res; 584 585 /* Correct the tsc counter value */ 586 if (cpu_has_tsc) { 587 res = (((u64)(*deltatsc)) * pm_100ms); 588 do_div(res, deltapm); 589 apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 590 "PM-Timer: %lu (%ld) \n", 591 (unsigned long)res, *deltatsc); 592 *deltatsc = (long)res; 593 } 594 595 return 0; 596 } 597 598 static int __init calibrate_APIC_clock(void) 599 { 600 struct clock_event_device *levt = &__get_cpu_var(lapic_events); 601 void (*real_handler)(struct clock_event_device *dev); 602 unsigned long deltaj; 603 long delta, deltatsc; 604 int pm_referenced = 0; 605 606 local_irq_disable(); 607 608 /* Replace the global interrupt handler */ 609 real_handler = global_clock_event->event_handler; 610 global_clock_event->event_handler = lapic_cal_handler; 611 612 /* 613 * Setup the APIC counter to maximum. There is no way the lapic 614 * can underflow in the 100ms detection time frame 615 */ 616 __setup_APIC_LVTT(0xffffffff, 0, 0); 617 618 /* Let the interrupts run */ 619 local_irq_enable(); 620 621 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 622 cpu_relax(); 623 624 local_irq_disable(); 625 626 /* Restore the real event handler */ 627 global_clock_event->event_handler = real_handler; 628 629 /* Build delta t1-t2 as apic timer counts down */ 630 delta = lapic_cal_t1 - lapic_cal_t2; 631 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 632 633 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 634 635 /* we trust the PM based calibration if possible */ 636 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 637 &delta, &deltatsc); 638 639 /* Calculate the scaled math multiplication factor */ 640 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 641 lapic_clockevent.shift); 642 lapic_clockevent.max_delta_ns = 643 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); 644 lapic_clockevent.min_delta_ns = 645 clockevent_delta2ns(0xF, &lapic_clockevent); 646 647 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 648 649 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 650 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); 651 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 652 calibration_result); 653 654 if (cpu_has_tsc) { 655 apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 656 "%ld.%04ld MHz.\n", 657 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 658 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 659 } 660 661 apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 662 "%u.%04u MHz.\n", 663 calibration_result / (1000000 / HZ), 664 calibration_result % (1000000 / HZ)); 665 666 /* 667 * Do a sanity check on the APIC calibration result 668 */ 669 if (calibration_result < (1000000 / HZ)) { 670 local_irq_enable(); 671 pr_warning("APIC frequency too slow, disabling apic timer\n"); 672 return -1; 673 } 674 675 levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 676 677 /* 678 * PM timer calibration failed or not turned on 679 * so lets try APIC timer based calibration 680 */ 681 if (!pm_referenced) { 682 apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 683 684 /* 685 * Setup the apic timer manually 686 */ 687 levt->event_handler = lapic_cal_handler; 688 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); 689 lapic_cal_loops = -1; 690 691 /* Let the interrupts run */ 692 local_irq_enable(); 693 694 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 695 cpu_relax(); 696 697 /* Stop the lapic timer */ 698 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); 699 700 /* Jiffies delta */ 701 deltaj = lapic_cal_j2 - lapic_cal_j1; 702 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 703 704 /* Check, if the jiffies result is consistent */ 705 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 706 apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 707 else 708 levt->features |= CLOCK_EVT_FEAT_DUMMY; 709 } else 710 local_irq_enable(); 711 712 if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 713 pr_warning("APIC timer disabled due to verification failure\n"); 714 return -1; 715 } 716 717 return 0; 718 } 719 720 /* 721 * Setup the boot APIC 722 * 723 * Calibrate and verify the result. 724 */ 725 void __init setup_boot_APIC_clock(void) 726 { 727 /* 728 * The local apic timer can be disabled via the kernel 729 * commandline or from the CPU detection code. Register the lapic 730 * timer as a dummy clock event source on SMP systems, so the 731 * broadcast mechanism is used. On UP systems simply ignore it. 732 */ 733 if (disable_apic_timer) { 734 pr_info("Disabling APIC timer\n"); 735 /* No broadcast on UP ! */ 736 if (num_possible_cpus() > 1) { 737 lapic_clockevent.mult = 1; 738 setup_APIC_timer(); 739 } 740 return; 741 } 742 743 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 744 "calibrating APIC timer ...\n"); 745 746 if (calibrate_APIC_clock()) { 747 /* No broadcast on UP ! */ 748 if (num_possible_cpus() > 1) 749 setup_APIC_timer(); 750 return; 751 } 752 753 /* 754 * If nmi_watchdog is set to IO_APIC, we need the 755 * PIT/HPET going. Otherwise register lapic as a dummy 756 * device. 757 */ 758 if (nmi_watchdog != NMI_IO_APIC) 759 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 760 else 761 pr_warning("APIC timer registered as dummy," 762 " due to nmi_watchdog=%d!\n", nmi_watchdog); 763 764 /* Setup the lapic or request the broadcast */ 765 setup_APIC_timer(); 766 } 767 768 void __cpuinit setup_secondary_APIC_clock(void) 769 { 770 setup_APIC_timer(); 771 } 772 773 /* 774 * The guts of the apic timer interrupt 775 */ 776 static void local_apic_timer_interrupt(void) 777 { 778 int cpu = smp_processor_id(); 779 struct clock_event_device *evt = &per_cpu(lapic_events, cpu); 780 781 /* 782 * Normally we should not be here till LAPIC has been initialized but 783 * in some cases like kdump, its possible that there is a pending LAPIC 784 * timer interrupt from previous kernel's context and is delivered in 785 * new kernel the moment interrupts are enabled. 786 * 787 * Interrupts are enabled early and LAPIC is setup much later, hence 788 * its possible that when we get here evt->event_handler is NULL. 789 * Check for event_handler being NULL and discard the interrupt as 790 * spurious. 791 */ 792 if (!evt->event_handler) { 793 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); 794 /* Switch it off */ 795 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); 796 return; 797 } 798 799 /* 800 * the NMI deadlock-detector uses this. 801 */ 802 inc_irq_stat(apic_timer_irqs); 803 804 evt->event_handler(evt); 805 } 806 807 /* 808 * Local APIC timer interrupt. This is the most natural way for doing 809 * local interrupts, but local timer interrupts can be emulated by 810 * broadcast interrupts too. [in case the hw doesn't support APIC timers] 811 * 812 * [ if a single-CPU system runs an SMP kernel then we call the local 813 * interrupt as well. Thus we cannot inline the local irq ... ] 814 */ 815 void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) 816 { 817 struct pt_regs *old_regs = set_irq_regs(regs); 818 819 /* 820 * NOTE! We'd better ACK the irq immediately, 821 * because timer handling can be slow. 822 */ 823 ack_APIC_irq(); 824 /* 825 * update_process_times() expects us to have done irq_enter(). 826 * Besides, if we don't timer interrupts ignore the global 827 * interrupt lock, which is the WrongThing (tm) to do. 828 */ 829 exit_idle(); 830 irq_enter(); 831 local_apic_timer_interrupt(); 832 irq_exit(); 833 834 set_irq_regs(old_regs); 835 } 836 837 int setup_profiling_timer(unsigned int multiplier) 838 { 839 return -EINVAL; 840 } 841 842 /* 843 * Local APIC start and shutdown 844 */ 845 846 /** 847 * clear_local_APIC - shutdown the local APIC 848 * 849 * This is called, when a CPU is disabled and before rebooting, so the state of 850 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 851 * leftovers during boot. 852 */ 853 void clear_local_APIC(void) 854 { 855 int maxlvt; 856 u32 v; 857 858 /* APIC hasn't been mapped yet */ 859 if (!x2apic_mode && !apic_phys) 860 return; 861 862 maxlvt = lapic_get_maxlvt(); 863 /* 864 * Masking an LVT entry can trigger a local APIC error 865 * if the vector is zero. Mask LVTERR first to prevent this. 866 */ 867 if (maxlvt >= 3) { 868 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 869 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 870 } 871 /* 872 * Careful: we have to set masks only first to deassert 873 * any level-triggered sources. 874 */ 875 v = apic_read(APIC_LVTT); 876 apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 877 v = apic_read(APIC_LVT0); 878 apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 879 v = apic_read(APIC_LVT1); 880 apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 881 if (maxlvt >= 4) { 882 v = apic_read(APIC_LVTPC); 883 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 884 } 885 886 /* lets not touch this if we didn't frob it */ 887 #ifdef CONFIG_X86_THERMAL_VECTOR 888 if (maxlvt >= 5) { 889 v = apic_read(APIC_LVTTHMR); 890 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 891 } 892 #endif 893 #ifdef CONFIG_X86_MCE_INTEL 894 if (maxlvt >= 6) { 895 v = apic_read(APIC_LVTCMCI); 896 if (!(v & APIC_LVT_MASKED)) 897 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 898 } 899 #endif 900 901 /* 902 * Clean APIC state for other OSs: 903 */ 904 apic_write(APIC_LVTT, APIC_LVT_MASKED); 905 apic_write(APIC_LVT0, APIC_LVT_MASKED); 906 apic_write(APIC_LVT1, APIC_LVT_MASKED); 907 if (maxlvt >= 3) 908 apic_write(APIC_LVTERR, APIC_LVT_MASKED); 909 if (maxlvt >= 4) 910 apic_write(APIC_LVTPC, APIC_LVT_MASKED); 911 912 /* Integrated APIC (!82489DX) ? */ 913 if (lapic_is_integrated()) { 914 if (maxlvt > 3) 915 /* Clear ESR due to Pentium errata 3AP and 11AP */ 916 apic_write(APIC_ESR, 0); 917 apic_read(APIC_ESR); 918 } 919 } 920 921 /** 922 * disable_local_APIC - clear and disable the local APIC 923 */ 924 void disable_local_APIC(void) 925 { 926 unsigned int value; 927 928 /* APIC hasn't been mapped yet */ 929 if (!apic_phys) 930 return; 931 932 clear_local_APIC(); 933 934 /* 935 * Disable APIC (implies clearing of registers 936 * for 82489DX!). 937 */ 938 value = apic_read(APIC_SPIV); 939 value &= ~APIC_SPIV_APIC_ENABLED; 940 apic_write(APIC_SPIV, value); 941 942 #ifdef CONFIG_X86_32 943 /* 944 * When LAPIC was disabled by the BIOS and enabled by the kernel, 945 * restore the disabled state. 946 */ 947 if (enabled_via_apicbase) { 948 unsigned int l, h; 949 950 rdmsr(MSR_IA32_APICBASE, l, h); 951 l &= ~MSR_IA32_APICBASE_ENABLE; 952 wrmsr(MSR_IA32_APICBASE, l, h); 953 } 954 #endif 955 } 956 957 /* 958 * If Linux enabled the LAPIC against the BIOS default disable it down before 959 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 960 * not power-off. Additionally clear all LVT entries before disable_local_APIC 961 * for the case where Linux didn't enable the LAPIC. 962 */ 963 void lapic_shutdown(void) 964 { 965 unsigned long flags; 966 967 if (!cpu_has_apic && !apic_from_smp_config()) 968 return; 969 970 local_irq_save(flags); 971 972 #ifdef CONFIG_X86_32 973 if (!enabled_via_apicbase) 974 clear_local_APIC(); 975 else 976 #endif 977 disable_local_APIC(); 978 979 980 local_irq_restore(flags); 981 } 982 983 /* 984 * This is to verify that we're looking at a real local APIC. 985 * Check these against your board if the CPUs aren't getting 986 * started for no apparent reason. 987 */ 988 int __init verify_local_APIC(void) 989 { 990 unsigned int reg0, reg1; 991 992 /* 993 * The version register is read-only in a real APIC. 994 */ 995 reg0 = apic_read(APIC_LVR); 996 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); 997 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); 998 reg1 = apic_read(APIC_LVR); 999 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); 1000 1001 /* 1002 * The two version reads above should print the same 1003 * numbers. If the second one is different, then we 1004 * poke at a non-APIC. 1005 */ 1006 if (reg1 != reg0) 1007 return 0; 1008 1009 /* 1010 * Check if the version looks reasonably. 1011 */ 1012 reg1 = GET_APIC_VERSION(reg0); 1013 if (reg1 == 0x00 || reg1 == 0xff) 1014 return 0; 1015 reg1 = lapic_get_maxlvt(); 1016 if (reg1 < 0x02 || reg1 == 0xff) 1017 return 0; 1018 1019 /* 1020 * The ID register is read/write in a real APIC. 1021 */ 1022 reg0 = apic_read(APIC_ID); 1023 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); 1024 apic_write(APIC_ID, reg0 ^ apic->apic_id_mask); 1025 reg1 = apic_read(APIC_ID); 1026 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); 1027 apic_write(APIC_ID, reg0); 1028 if (reg1 != (reg0 ^ apic->apic_id_mask)) 1029 return 0; 1030 1031 /* 1032 * The next two are just to see if we have sane values. 1033 * They're only really relevant if we're in Virtual Wire 1034 * compatibility mode, but most boxes are anymore. 1035 */ 1036 reg0 = apic_read(APIC_LVT0); 1037 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); 1038 reg1 = apic_read(APIC_LVT1); 1039 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); 1040 1041 return 1; 1042 } 1043 1044 /** 1045 * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1046 */ 1047 void __init sync_Arb_IDs(void) 1048 { 1049 /* 1050 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1051 * needed on AMD. 1052 */ 1053 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1054 return; 1055 1056 /* 1057 * Wait for idle. 1058 */ 1059 apic_wait_icr_idle(); 1060 1061 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1062 apic_write(APIC_ICR, APIC_DEST_ALLINC | 1063 APIC_INT_LEVELTRIG | APIC_DM_INIT); 1064 } 1065 1066 /* 1067 * An initial setup of the virtual wire mode. 1068 */ 1069 void __init init_bsp_APIC(void) 1070 { 1071 unsigned int value; 1072 1073 /* 1074 * Don't do the setup now if we have a SMP BIOS as the 1075 * through-I/O-APIC virtual wire mode might be active. 1076 */ 1077 if (smp_found_config || !cpu_has_apic) 1078 return; 1079 1080 /* 1081 * Do not trust the local APIC being empty at bootup. 1082 */ 1083 clear_local_APIC(); 1084 1085 /* 1086 * Enable APIC. 1087 */ 1088 value = apic_read(APIC_SPIV); 1089 value &= ~APIC_VECTOR_MASK; 1090 value |= APIC_SPIV_APIC_ENABLED; 1091 1092 #ifdef CONFIG_X86_32 1093 /* This bit is reserved on P4/Xeon and should be cleared */ 1094 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1095 (boot_cpu_data.x86 == 15)) 1096 value &= ~APIC_SPIV_FOCUS_DISABLED; 1097 else 1098 #endif 1099 value |= APIC_SPIV_FOCUS_DISABLED; 1100 value |= SPURIOUS_APIC_VECTOR; 1101 apic_write(APIC_SPIV, value); 1102 1103 /* 1104 * Set up the virtual wire mode. 1105 */ 1106 apic_write(APIC_LVT0, APIC_DM_EXTINT); 1107 value = APIC_DM_NMI; 1108 if (!lapic_is_integrated()) /* 82489DX */ 1109 value |= APIC_LVT_LEVEL_TRIGGER; 1110 apic_write(APIC_LVT1, value); 1111 } 1112 1113 static void __cpuinit lapic_setup_esr(void) 1114 { 1115 unsigned int oldvalue, value, maxlvt; 1116 1117 if (!lapic_is_integrated()) { 1118 pr_info("No ESR for 82489DX.\n"); 1119 return; 1120 } 1121 1122 if (apic->disable_esr) { 1123 /* 1124 * Something untraceable is creating bad interrupts on 1125 * secondary quads ... for the moment, just leave the 1126 * ESR disabled - we can't do anything useful with the 1127 * errors anyway - mbligh 1128 */ 1129 pr_info("Leaving ESR disabled.\n"); 1130 return; 1131 } 1132 1133 maxlvt = lapic_get_maxlvt(); 1134 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1135 apic_write(APIC_ESR, 0); 1136 oldvalue = apic_read(APIC_ESR); 1137 1138 /* enables sending errors */ 1139 value = ERROR_APIC_VECTOR; 1140 apic_write(APIC_LVTERR, value); 1141 1142 /* 1143 * spec says clear errors after enabling vector. 1144 */ 1145 if (maxlvt > 3) 1146 apic_write(APIC_ESR, 0); 1147 value = apic_read(APIC_ESR); 1148 if (value != oldvalue) 1149 apic_printk(APIC_VERBOSE, "ESR value before enabling " 1150 "vector: 0x%08x after: 0x%08x\n", 1151 oldvalue, value); 1152 } 1153 1154 1155 /** 1156 * setup_local_APIC - setup the local APIC 1157 */ 1158 void __cpuinit setup_local_APIC(void) 1159 { 1160 unsigned int value; 1161 int i, j; 1162 1163 if (disable_apic) { 1164 arch_disable_smp_support(); 1165 return; 1166 } 1167 1168 #ifdef CONFIG_X86_32 1169 /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1170 if (lapic_is_integrated() && apic->disable_esr) { 1171 apic_write(APIC_ESR, 0); 1172 apic_write(APIC_ESR, 0); 1173 apic_write(APIC_ESR, 0); 1174 apic_write(APIC_ESR, 0); 1175 } 1176 #endif 1177 perf_events_lapic_init(); 1178 1179 preempt_disable(); 1180 1181 /* 1182 * Double-check whether this APIC is really registered. 1183 * This is meaningless in clustered apic mode, so we skip it. 1184 */ 1185 BUG_ON(!apic->apic_id_registered()); 1186 1187 /* 1188 * Intel recommends to set DFR, LDR and TPR before enabling 1189 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1190 * document number 292116). So here it goes... 1191 */ 1192 apic->init_apic_ldr(); 1193 1194 /* 1195 * Set Task Priority to 'accept all'. We never change this 1196 * later on. 1197 */ 1198 value = apic_read(APIC_TASKPRI); 1199 value &= ~APIC_TPRI_MASK; 1200 apic_write(APIC_TASKPRI, value); 1201 1202 /* 1203 * After a crash, we no longer service the interrupts and a pending 1204 * interrupt from previous kernel might still have ISR bit set. 1205 * 1206 * Most probably by now CPU has serviced that pending interrupt and 1207 * it might not have done the ack_APIC_irq() because it thought, 1208 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it 1209 * does not clear the ISR bit and cpu thinks it has already serivced 1210 * the interrupt. Hence a vector might get locked. It was noticed 1211 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. 1212 */ 1213 for (i = APIC_ISR_NR - 1; i >= 0; i--) { 1214 value = apic_read(APIC_ISR + i*0x10); 1215 for (j = 31; j >= 0; j--) { 1216 if (value & (1<<j)) 1217 ack_APIC_irq(); 1218 } 1219 } 1220 1221 /* 1222 * Now that we are all set up, enable the APIC 1223 */ 1224 value = apic_read(APIC_SPIV); 1225 value &= ~APIC_VECTOR_MASK; 1226 /* 1227 * Enable APIC 1228 */ 1229 value |= APIC_SPIV_APIC_ENABLED; 1230 1231 #ifdef CONFIG_X86_32 1232 /* 1233 * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1234 * certain networking cards. If high frequency interrupts are 1235 * happening on a particular IOAPIC pin, plus the IOAPIC routing 1236 * entry is masked/unmasked at a high rate as well then sooner or 1237 * later IOAPIC line gets 'stuck', no more interrupts are received 1238 * from the device. If focus CPU is disabled then the hang goes 1239 * away, oh well :-( 1240 * 1241 * [ This bug can be reproduced easily with a level-triggered 1242 * PCI Ne2000 networking cards and PII/PIII processors, dual 1243 * BX chipset. ] 1244 */ 1245 /* 1246 * Actually disabling the focus CPU check just makes the hang less 1247 * frequent as it makes the interrupt distributon model be more 1248 * like LRU than MRU (the short-term load is more even across CPUs). 1249 * See also the comment in end_level_ioapic_irq(). --macro 1250 */ 1251 1252 /* 1253 * - enable focus processor (bit==0) 1254 * - 64bit mode always use processor focus 1255 * so no need to set it 1256 */ 1257 value &= ~APIC_SPIV_FOCUS_DISABLED; 1258 #endif 1259 1260 /* 1261 * Set spurious IRQ vector 1262 */ 1263 value |= SPURIOUS_APIC_VECTOR; 1264 apic_write(APIC_SPIV, value); 1265 1266 /* 1267 * Set up LVT0, LVT1: 1268 * 1269 * set up through-local-APIC on the BP's LINT0. This is not 1270 * strictly necessary in pure symmetric-IO mode, but sometimes 1271 * we delegate interrupts to the 8259A. 1272 */ 1273 /* 1274 * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1275 */ 1276 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 1277 if (!smp_processor_id() && (pic_mode || !value)) { 1278 value = APIC_DM_EXTINT; 1279 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", 1280 smp_processor_id()); 1281 } else { 1282 value = APIC_DM_EXTINT | APIC_LVT_MASKED; 1283 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", 1284 smp_processor_id()); 1285 } 1286 apic_write(APIC_LVT0, value); 1287 1288 /* 1289 * only the BP should see the LINT1 NMI signal, obviously. 1290 */ 1291 if (!smp_processor_id()) 1292 value = APIC_DM_NMI; 1293 else 1294 value = APIC_DM_NMI | APIC_LVT_MASKED; 1295 if (!lapic_is_integrated()) /* 82489DX */ 1296 value |= APIC_LVT_LEVEL_TRIGGER; 1297 apic_write(APIC_LVT1, value); 1298 1299 preempt_enable(); 1300 1301 #ifdef CONFIG_X86_MCE_INTEL 1302 /* Recheck CMCI information after local APIC is up on CPU #0 */ 1303 if (smp_processor_id() == 0) 1304 cmci_recheck(); 1305 #endif 1306 } 1307 1308 void __cpuinit end_local_APIC_setup(void) 1309 { 1310 lapic_setup_esr(); 1311 1312 #ifdef CONFIG_X86_32 1313 { 1314 unsigned int value; 1315 /* Disable the local apic timer */ 1316 value = apic_read(APIC_LVTT); 1317 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1318 apic_write(APIC_LVTT, value); 1319 } 1320 #endif 1321 1322 setup_apic_nmi_watchdog(NULL); 1323 apic_pm_activate(); 1324 } 1325 1326 #ifdef CONFIG_X86_X2APIC 1327 void check_x2apic(void) 1328 { 1329 if (x2apic_enabled()) { 1330 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n"); 1331 x2apic_preenabled = x2apic_mode = 1; 1332 } 1333 } 1334 1335 void enable_x2apic(void) 1336 { 1337 int msr, msr2; 1338 1339 if (!x2apic_mode) 1340 return; 1341 1342 rdmsr(MSR_IA32_APICBASE, msr, msr2); 1343 if (!(msr & X2APIC_ENABLE)) { 1344 printk_once(KERN_INFO "Enabling x2apic\n"); 1345 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); 1346 } 1347 } 1348 #endif /* CONFIG_X86_X2APIC */ 1349 1350 int __init enable_IR(void) 1351 { 1352 #ifdef CONFIG_INTR_REMAP 1353 if (!intr_remapping_supported()) { 1354 pr_debug("intr-remapping not supported\n"); 1355 return 0; 1356 } 1357 1358 if (!x2apic_preenabled && skip_ioapic_setup) { 1359 pr_info("Skipped enabling intr-remap because of skipping " 1360 "io-apic setup\n"); 1361 return 0; 1362 } 1363 1364 if (enable_intr_remapping(x2apic_supported())) 1365 return 0; 1366 1367 pr_info("Enabled Interrupt-remapping\n"); 1368 1369 return 1; 1370 1371 #endif 1372 return 0; 1373 } 1374 1375 void __init enable_IR_x2apic(void) 1376 { 1377 unsigned long flags; 1378 struct IO_APIC_route_entry **ioapic_entries = NULL; 1379 int ret, x2apic_enabled = 0; 1380 int dmar_table_init_ret; 1381 1382 dmar_table_init_ret = dmar_table_init(); 1383 if (dmar_table_init_ret && !x2apic_supported()) 1384 return; 1385 1386 ioapic_entries = alloc_ioapic_entries(); 1387 if (!ioapic_entries) { 1388 pr_err("Allocate ioapic_entries failed\n"); 1389 goto out; 1390 } 1391 1392 ret = save_IO_APIC_setup(ioapic_entries); 1393 if (ret) { 1394 pr_info("Saving IO-APIC state failed: %d\n", ret); 1395 goto out; 1396 } 1397 1398 local_irq_save(flags); 1399 mask_8259A(); 1400 mask_IO_APIC_setup(ioapic_entries); 1401 1402 if (dmar_table_init_ret) 1403 ret = 0; 1404 else 1405 ret = enable_IR(); 1406 1407 if (!ret) { 1408 /* IR is required if there is APIC ID > 255 even when running 1409 * under KVM 1410 */ 1411 if (max_physical_apicid > 255 || !kvm_para_available()) 1412 goto nox2apic; 1413 /* 1414 * without IR all CPUs can be addressed by IOAPIC/MSI 1415 * only in physical mode 1416 */ 1417 x2apic_force_phys(); 1418 } 1419 1420 x2apic_enabled = 1; 1421 1422 if (x2apic_supported() && !x2apic_mode) { 1423 x2apic_mode = 1; 1424 enable_x2apic(); 1425 pr_info("Enabled x2apic\n"); 1426 } 1427 1428 nox2apic: 1429 if (!ret) /* IR enabling failed */ 1430 restore_IO_APIC_setup(ioapic_entries); 1431 unmask_8259A(); 1432 local_irq_restore(flags); 1433 1434 out: 1435 if (ioapic_entries) 1436 free_ioapic_entries(ioapic_entries); 1437 1438 if (x2apic_enabled) 1439 return; 1440 1441 if (x2apic_preenabled) 1442 panic("x2apic: enabled by BIOS but kernel init failed."); 1443 else if (cpu_has_x2apic) 1444 pr_info("Not enabling x2apic, Intr-remapping init failed.\n"); 1445 } 1446 1447 #ifdef CONFIG_X86_64 1448 /* 1449 * Detect and enable local APICs on non-SMP boards. 1450 * Original code written by Keir Fraser. 1451 * On AMD64 we trust the BIOS - if it says no APIC it is likely 1452 * not correctly set up (usually the APIC timer won't work etc.) 1453 */ 1454 static int __init detect_init_APIC(void) 1455 { 1456 if (!cpu_has_apic) { 1457 pr_info("No local APIC present\n"); 1458 return -1; 1459 } 1460 1461 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1462 return 0; 1463 } 1464 #else 1465 /* 1466 * Detect and initialize APIC 1467 */ 1468 static int __init detect_init_APIC(void) 1469 { 1470 u32 h, l, features; 1471 1472 /* Disabled by kernel option? */ 1473 if (disable_apic) 1474 return -1; 1475 1476 switch (boot_cpu_data.x86_vendor) { 1477 case X86_VENDOR_AMD: 1478 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 1479 (boot_cpu_data.x86 >= 15)) 1480 break; 1481 goto no_apic; 1482 case X86_VENDOR_INTEL: 1483 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 1484 (boot_cpu_data.x86 == 5 && cpu_has_apic)) 1485 break; 1486 goto no_apic; 1487 default: 1488 goto no_apic; 1489 } 1490 1491 if (!cpu_has_apic) { 1492 /* 1493 * Over-ride BIOS and try to enable the local APIC only if 1494 * "lapic" specified. 1495 */ 1496 if (!force_enable_local_apic) { 1497 pr_info("Local APIC disabled by BIOS -- " 1498 "you can enable it with \"lapic\"\n"); 1499 return -1; 1500 } 1501 /* 1502 * Some BIOSes disable the local APIC in the APIC_BASE 1503 * MSR. This can only be done in software for Intel P6 or later 1504 * and AMD K7 (Model > 1) or later. 1505 */ 1506 rdmsr(MSR_IA32_APICBASE, l, h); 1507 if (!(l & MSR_IA32_APICBASE_ENABLE)) { 1508 pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 1509 l &= ~MSR_IA32_APICBASE_BASE; 1510 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; 1511 wrmsr(MSR_IA32_APICBASE, l, h); 1512 enabled_via_apicbase = 1; 1513 } 1514 } 1515 /* 1516 * The APIC feature bit should now be enabled 1517 * in `cpuid' 1518 */ 1519 features = cpuid_edx(1); 1520 if (!(features & (1 << X86_FEATURE_APIC))) { 1521 pr_warning("Could not enable APIC!\n"); 1522 return -1; 1523 } 1524 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 1525 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1526 1527 /* The BIOS may have set up the APIC at some other address */ 1528 rdmsr(MSR_IA32_APICBASE, l, h); 1529 if (l & MSR_IA32_APICBASE_ENABLE) 1530 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 1531 1532 pr_info("Found and enabled local APIC!\n"); 1533 1534 apic_pm_activate(); 1535 1536 return 0; 1537 1538 no_apic: 1539 pr_info("No local APIC present or hardware disabled\n"); 1540 return -1; 1541 } 1542 #endif 1543 1544 #ifdef CONFIG_X86_64 1545 void __init early_init_lapic_mapping(void) 1546 { 1547 /* 1548 * If no local APIC can be found then go out 1549 * : it means there is no mpatable and MADT 1550 */ 1551 if (!smp_found_config) 1552 return; 1553 1554 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr); 1555 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 1556 APIC_BASE, mp_lapic_addr); 1557 1558 /* 1559 * Fetch the APIC ID of the BSP in case we have a 1560 * default configuration (or the MP table is broken). 1561 */ 1562 boot_cpu_physical_apicid = read_apic_id(); 1563 } 1564 #endif 1565 1566 /** 1567 * init_apic_mappings - initialize APIC mappings 1568 */ 1569 void __init init_apic_mappings(void) 1570 { 1571 unsigned int new_apicid; 1572 1573 if (x2apic_mode) { 1574 boot_cpu_physical_apicid = read_apic_id(); 1575 return; 1576 } 1577 1578 /* If no local APIC can be found return early */ 1579 if (!smp_found_config && detect_init_APIC()) { 1580 /* lets NOP'ify apic operations */ 1581 pr_info("APIC: disable apic facility\n"); 1582 apic_disable(); 1583 } else { 1584 apic_phys = mp_lapic_addr; 1585 1586 /* 1587 * acpi lapic path already maps that address in 1588 * acpi_register_lapic_address() 1589 */ 1590 if (!acpi_lapic) 1591 set_fixmap_nocache(FIX_APIC_BASE, apic_phys); 1592 1593 apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n", 1594 APIC_BASE, apic_phys); 1595 } 1596 1597 /* 1598 * Fetch the APIC ID of the BSP in case we have a 1599 * default configuration (or the MP table is broken). 1600 */ 1601 new_apicid = read_apic_id(); 1602 if (boot_cpu_physical_apicid != new_apicid) { 1603 boot_cpu_physical_apicid = new_apicid; 1604 /* 1605 * yeah -- we lie about apic_version 1606 * in case if apic was disabled via boot option 1607 * but it's not a problem for SMP compiled kernel 1608 * since smp_sanity_check is prepared for such a case 1609 * and disable smp mode 1610 */ 1611 apic_version[new_apicid] = 1612 GET_APIC_VERSION(apic_read(APIC_LVR)); 1613 } 1614 } 1615 1616 /* 1617 * This initializes the IO-APIC and APIC hardware if this is 1618 * a UP kernel. 1619 */ 1620 int apic_version[MAX_APICS]; 1621 1622 int __init APIC_init_uniprocessor(void) 1623 { 1624 if (disable_apic) { 1625 pr_info("Apic disabled\n"); 1626 return -1; 1627 } 1628 #ifdef CONFIG_X86_64 1629 if (!cpu_has_apic) { 1630 disable_apic = 1; 1631 pr_info("Apic disabled by BIOS\n"); 1632 return -1; 1633 } 1634 #else 1635 if (!smp_found_config && !cpu_has_apic) 1636 return -1; 1637 1638 /* 1639 * Complain if the BIOS pretends there is one. 1640 */ 1641 if (!cpu_has_apic && 1642 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 1643 pr_err("BIOS bug, local APIC 0x%x not detected!...\n", 1644 boot_cpu_physical_apicid); 1645 return -1; 1646 } 1647 #endif 1648 1649 enable_IR_x2apic(); 1650 #ifdef CONFIG_X86_64 1651 default_setup_apic_routing(); 1652 #endif 1653 1654 verify_local_APIC(); 1655 connect_bsp_APIC(); 1656 1657 #ifdef CONFIG_X86_64 1658 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); 1659 #else 1660 /* 1661 * Hack: In case of kdump, after a crash, kernel might be booting 1662 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 1663 * might be zero if read from MP tables. Get it from LAPIC. 1664 */ 1665 # ifdef CONFIG_CRASH_DUMP 1666 boot_cpu_physical_apicid = read_apic_id(); 1667 # endif 1668 #endif 1669 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1670 setup_local_APIC(); 1671 1672 #ifdef CONFIG_X86_IO_APIC 1673 /* 1674 * Now enable IO-APICs, actually call clear_IO_APIC 1675 * We need clear_IO_APIC before enabling error vector 1676 */ 1677 if (!skip_ioapic_setup && nr_ioapics) 1678 enable_IO_APIC(); 1679 #endif 1680 1681 end_local_APIC_setup(); 1682 1683 #ifdef CONFIG_X86_IO_APIC 1684 if (smp_found_config && !skip_ioapic_setup && nr_ioapics) 1685 setup_IO_APIC(); 1686 else { 1687 nr_ioapics = 0; 1688 localise_nmi_watchdog(); 1689 } 1690 #else 1691 localise_nmi_watchdog(); 1692 #endif 1693 1694 x86_init.timers.setup_percpu_clockev(); 1695 #ifdef CONFIG_X86_64 1696 check_nmi_watchdog(); 1697 #endif 1698 1699 return 0; 1700 } 1701 1702 /* 1703 * Local APIC interrupts 1704 */ 1705 1706 /* 1707 * This interrupt should _never_ happen with our APIC/SMP architecture 1708 */ 1709 void smp_spurious_interrupt(struct pt_regs *regs) 1710 { 1711 u32 v; 1712 1713 exit_idle(); 1714 irq_enter(); 1715 /* 1716 * Check if this really is a spurious interrupt and ACK it 1717 * if it is a vectored one. Just in case... 1718 * Spurious interrupts should not be ACKed. 1719 */ 1720 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); 1721 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) 1722 ack_APIC_irq(); 1723 1724 inc_irq_stat(irq_spurious_count); 1725 1726 /* see sw-dev-man vol 3, chapter 7.4.13.5 */ 1727 pr_info("spurious APIC interrupt on CPU#%d, " 1728 "should never happen.\n", smp_processor_id()); 1729 irq_exit(); 1730 } 1731 1732 /* 1733 * This interrupt should never happen with our APIC/SMP architecture 1734 */ 1735 void smp_error_interrupt(struct pt_regs *regs) 1736 { 1737 u32 v, v1; 1738 1739 exit_idle(); 1740 irq_enter(); 1741 /* First tickle the hardware, only then report what went on. -- REW */ 1742 v = apic_read(APIC_ESR); 1743 apic_write(APIC_ESR, 0); 1744 v1 = apic_read(APIC_ESR); 1745 ack_APIC_irq(); 1746 atomic_inc(&irq_err_count); 1747 1748 /* 1749 * Here is what the APIC error bits mean: 1750 * 0: Send CS error 1751 * 1: Receive CS error 1752 * 2: Send accept error 1753 * 3: Receive accept error 1754 * 4: Reserved 1755 * 5: Send illegal vector 1756 * 6: Received illegal vector 1757 * 7: Illegal register address 1758 */ 1759 pr_debug("APIC error on CPU%d: %02x(%02x)\n", 1760 smp_processor_id(), v , v1); 1761 irq_exit(); 1762 } 1763 1764 /** 1765 * connect_bsp_APIC - attach the APIC to the interrupt system 1766 */ 1767 void __init connect_bsp_APIC(void) 1768 { 1769 #ifdef CONFIG_X86_32 1770 if (pic_mode) { 1771 /* 1772 * Do not trust the local APIC being empty at bootup. 1773 */ 1774 clear_local_APIC(); 1775 /* 1776 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 1777 * local APIC to INT and NMI lines. 1778 */ 1779 apic_printk(APIC_VERBOSE, "leaving PIC mode, " 1780 "enabling APIC mode.\n"); 1781 imcr_pic_to_apic(); 1782 } 1783 #endif 1784 if (apic->enable_apic_mode) 1785 apic->enable_apic_mode(); 1786 } 1787 1788 /** 1789 * disconnect_bsp_APIC - detach the APIC from the interrupt system 1790 * @virt_wire_setup: indicates, whether virtual wire mode is selected 1791 * 1792 * Virtual wire mode is necessary to deliver legacy interrupts even when the 1793 * APIC is disabled. 1794 */ 1795 void disconnect_bsp_APIC(int virt_wire_setup) 1796 { 1797 unsigned int value; 1798 1799 #ifdef CONFIG_X86_32 1800 if (pic_mode) { 1801 /* 1802 * Put the board back into PIC mode (has an effect only on 1803 * certain older boards). Note that APIC interrupts, including 1804 * IPIs, won't work beyond this point! The only exception are 1805 * INIT IPIs. 1806 */ 1807 apic_printk(APIC_VERBOSE, "disabling APIC mode, " 1808 "entering PIC mode.\n"); 1809 imcr_apic_to_pic(); 1810 return; 1811 } 1812 #endif 1813 1814 /* Go back to Virtual Wire compatibility mode */ 1815 1816 /* For the spurious interrupt use vector F, and enable it */ 1817 value = apic_read(APIC_SPIV); 1818 value &= ~APIC_VECTOR_MASK; 1819 value |= APIC_SPIV_APIC_ENABLED; 1820 value |= 0xf; 1821 apic_write(APIC_SPIV, value); 1822 1823 if (!virt_wire_setup) { 1824 /* 1825 * For LVT0 make it edge triggered, active high, 1826 * external and enabled 1827 */ 1828 value = apic_read(APIC_LVT0); 1829 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 1830 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 1831 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 1832 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 1833 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 1834 apic_write(APIC_LVT0, value); 1835 } else { 1836 /* Disable LVT0 */ 1837 apic_write(APIC_LVT0, APIC_LVT_MASKED); 1838 } 1839 1840 /* 1841 * For LVT1 make it edge triggered, active high, 1842 * nmi and enabled 1843 */ 1844 value = apic_read(APIC_LVT1); 1845 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 1846 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 1847 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 1848 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 1849 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 1850 apic_write(APIC_LVT1, value); 1851 } 1852 1853 void __cpuinit generic_processor_info(int apicid, int version) 1854 { 1855 int cpu; 1856 1857 /* 1858 * Validate version 1859 */ 1860 if (version == 0x0) { 1861 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! " 1862 "fixing up to 0x10. (tell your hw vendor)\n", 1863 version); 1864 version = 0x10; 1865 } 1866 apic_version[apicid] = version; 1867 1868 if (num_processors >= nr_cpu_ids) { 1869 int max = nr_cpu_ids; 1870 int thiscpu = max + disabled_cpus; 1871 1872 pr_warning( 1873 "ACPI: NR_CPUS/possible_cpus limit of %i reached." 1874 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 1875 1876 disabled_cpus++; 1877 return; 1878 } 1879 1880 num_processors++; 1881 cpu = cpumask_next_zero(-1, cpu_present_mask); 1882 1883 if (version != apic_version[boot_cpu_physical_apicid]) 1884 WARN_ONCE(1, 1885 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n", 1886 apic_version[boot_cpu_physical_apicid], cpu, version); 1887 1888 physid_set(apicid, phys_cpu_present_map); 1889 if (apicid == boot_cpu_physical_apicid) { 1890 /* 1891 * x86_bios_cpu_apicid is required to have processors listed 1892 * in same order as logical cpu numbers. Hence the first 1893 * entry is BSP, and so on. 1894 */ 1895 cpu = 0; 1896 } 1897 if (apicid > max_physical_apicid) 1898 max_physical_apicid = apicid; 1899 1900 #ifdef CONFIG_X86_32 1901 /* 1902 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y 1903 * but we need to work other dependencies like SMP_SUSPEND etc 1904 * before this can be done without some confusion. 1905 * if (CPU_HOTPLUG_ENABLED || num_processors > 8) 1906 * - Ashok Raj <ashok.raj@intel.com> 1907 */ 1908 if (max_physical_apicid >= 8) { 1909 switch (boot_cpu_data.x86_vendor) { 1910 case X86_VENDOR_INTEL: 1911 if (!APIC_XAPIC(version)) { 1912 def_to_bigsmp = 0; 1913 break; 1914 } 1915 /* If P4 and above fall through */ 1916 case X86_VENDOR_AMD: 1917 def_to_bigsmp = 1; 1918 } 1919 } 1920 #endif 1921 1922 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 1923 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 1924 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 1925 #endif 1926 1927 set_cpu_possible(cpu, true); 1928 set_cpu_present(cpu, true); 1929 } 1930 1931 int hard_smp_processor_id(void) 1932 { 1933 return read_apic_id(); 1934 } 1935 1936 void default_init_apic_ldr(void) 1937 { 1938 unsigned long val; 1939 1940 apic_write(APIC_DFR, APIC_DFR_VALUE); 1941 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; 1942 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); 1943 apic_write(APIC_LDR, val); 1944 } 1945 1946 #ifdef CONFIG_X86_32 1947 int default_apicid_to_node(int logical_apicid) 1948 { 1949 #ifdef CONFIG_SMP 1950 return apicid_2_node[hard_smp_processor_id()]; 1951 #else 1952 return 0; 1953 #endif 1954 } 1955 #endif 1956 1957 /* 1958 * Power management 1959 */ 1960 #ifdef CONFIG_PM 1961 1962 static struct { 1963 /* 1964 * 'active' is true if the local APIC was enabled by us and 1965 * not the BIOS; this signifies that we are also responsible 1966 * for disabling it before entering apm/acpi suspend 1967 */ 1968 int active; 1969 /* r/w apic fields */ 1970 unsigned int apic_id; 1971 unsigned int apic_taskpri; 1972 unsigned int apic_ldr; 1973 unsigned int apic_dfr; 1974 unsigned int apic_spiv; 1975 unsigned int apic_lvtt; 1976 unsigned int apic_lvtpc; 1977 unsigned int apic_lvt0; 1978 unsigned int apic_lvt1; 1979 unsigned int apic_lvterr; 1980 unsigned int apic_tmict; 1981 unsigned int apic_tdcr; 1982 unsigned int apic_thmr; 1983 } apic_pm_state; 1984 1985 static int lapic_suspend(struct sys_device *dev, pm_message_t state) 1986 { 1987 unsigned long flags; 1988 int maxlvt; 1989 1990 if (!apic_pm_state.active) 1991 return 0; 1992 1993 maxlvt = lapic_get_maxlvt(); 1994 1995 apic_pm_state.apic_id = apic_read(APIC_ID); 1996 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 1997 apic_pm_state.apic_ldr = apic_read(APIC_LDR); 1998 apic_pm_state.apic_dfr = apic_read(APIC_DFR); 1999 apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2000 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2001 if (maxlvt >= 4) 2002 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2003 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2004 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2005 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2006 apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2007 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 2008 #ifdef CONFIG_X86_THERMAL_VECTOR 2009 if (maxlvt >= 5) 2010 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2011 #endif 2012 2013 local_irq_save(flags); 2014 disable_local_APIC(); 2015 2016 if (intr_remapping_enabled) 2017 disable_intr_remapping(); 2018 2019 local_irq_restore(flags); 2020 return 0; 2021 } 2022 2023 static int lapic_resume(struct sys_device *dev) 2024 { 2025 unsigned int l, h; 2026 unsigned long flags; 2027 int maxlvt; 2028 int ret = 0; 2029 struct IO_APIC_route_entry **ioapic_entries = NULL; 2030 2031 if (!apic_pm_state.active) 2032 return 0; 2033 2034 local_irq_save(flags); 2035 if (intr_remapping_enabled) { 2036 ioapic_entries = alloc_ioapic_entries(); 2037 if (!ioapic_entries) { 2038 WARN(1, "Alloc ioapic_entries in lapic resume failed."); 2039 ret = -ENOMEM; 2040 goto restore; 2041 } 2042 2043 ret = save_IO_APIC_setup(ioapic_entries); 2044 if (ret) { 2045 WARN(1, "Saving IO-APIC state failed: %d\n", ret); 2046 free_ioapic_entries(ioapic_entries); 2047 goto restore; 2048 } 2049 2050 mask_IO_APIC_setup(ioapic_entries); 2051 mask_8259A(); 2052 } 2053 2054 if (x2apic_mode) 2055 enable_x2apic(); 2056 else { 2057 /* 2058 * Make sure the APICBASE points to the right address 2059 * 2060 * FIXME! This will be wrong if we ever support suspend on 2061 * SMP! We'll need to do this as part of the CPU restore! 2062 */ 2063 rdmsr(MSR_IA32_APICBASE, l, h); 2064 l &= ~MSR_IA32_APICBASE_BASE; 2065 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2066 wrmsr(MSR_IA32_APICBASE, l, h); 2067 } 2068 2069 maxlvt = lapic_get_maxlvt(); 2070 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2071 apic_write(APIC_ID, apic_pm_state.apic_id); 2072 apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2073 apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2074 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2075 apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2076 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2077 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 2078 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) 2079 if (maxlvt >= 5) 2080 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2081 #endif 2082 if (maxlvt >= 4) 2083 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2084 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2085 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2086 apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2087 apic_write(APIC_ESR, 0); 2088 apic_read(APIC_ESR); 2089 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2090 apic_write(APIC_ESR, 0); 2091 apic_read(APIC_ESR); 2092 2093 if (intr_remapping_enabled) { 2094 reenable_intr_remapping(x2apic_mode); 2095 unmask_8259A(); 2096 restore_IO_APIC_setup(ioapic_entries); 2097 free_ioapic_entries(ioapic_entries); 2098 } 2099 restore: 2100 local_irq_restore(flags); 2101 2102 return ret; 2103 } 2104 2105 /* 2106 * This device has no shutdown method - fully functioning local APICs 2107 * are needed on every CPU up until machine_halt/restart/poweroff. 2108 */ 2109 2110 static struct sysdev_class lapic_sysclass = { 2111 .name = "lapic", 2112 .resume = lapic_resume, 2113 .suspend = lapic_suspend, 2114 }; 2115 2116 static struct sys_device device_lapic = { 2117 .id = 0, 2118 .cls = &lapic_sysclass, 2119 }; 2120 2121 static void __cpuinit apic_pm_activate(void) 2122 { 2123 apic_pm_state.active = 1; 2124 } 2125 2126 static int __init init_lapic_sysfs(void) 2127 { 2128 int error; 2129 2130 if (!cpu_has_apic) 2131 return 0; 2132 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 2133 2134 error = sysdev_class_register(&lapic_sysclass); 2135 if (!error) 2136 error = sysdev_register(&device_lapic); 2137 return error; 2138 } 2139 2140 /* local apic needs to resume before other devices access its registers. */ 2141 core_initcall(init_lapic_sysfs); 2142 2143 #else /* CONFIG_PM */ 2144 2145 static void apic_pm_activate(void) { } 2146 2147 #endif /* CONFIG_PM */ 2148 2149 #ifdef CONFIG_X86_64 2150 2151 static int __cpuinit apic_cluster_num(void) 2152 { 2153 int i, clusters, zeros; 2154 unsigned id; 2155 u16 *bios_cpu_apicid; 2156 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); 2157 2158 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); 2159 bitmap_zero(clustermap, NUM_APIC_CLUSTERS); 2160 2161 for (i = 0; i < nr_cpu_ids; i++) { 2162 /* are we being called early in kernel startup? */ 2163 if (bios_cpu_apicid) { 2164 id = bios_cpu_apicid[i]; 2165 } else if (i < nr_cpu_ids) { 2166 if (cpu_present(i)) 2167 id = per_cpu(x86_bios_cpu_apicid, i); 2168 else 2169 continue; 2170 } else 2171 break; 2172 2173 if (id != BAD_APICID) 2174 __set_bit(APIC_CLUSTERID(id), clustermap); 2175 } 2176 2177 /* Problem: Partially populated chassis may not have CPUs in some of 2178 * the APIC clusters they have been allocated. Only present CPUs have 2179 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. 2180 * Since clusters are allocated sequentially, count zeros only if 2181 * they are bounded by ones. 2182 */ 2183 clusters = 0; 2184 zeros = 0; 2185 for (i = 0; i < NUM_APIC_CLUSTERS; i++) { 2186 if (test_bit(i, clustermap)) { 2187 clusters += 1 + zeros; 2188 zeros = 0; 2189 } else 2190 ++zeros; 2191 } 2192 2193 return clusters; 2194 } 2195 2196 static int __cpuinitdata multi_checked; 2197 static int __cpuinitdata multi; 2198 2199 static int __cpuinit set_multi(const struct dmi_system_id *d) 2200 { 2201 if (multi) 2202 return 0; 2203 pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2204 multi = 1; 2205 return 0; 2206 } 2207 2208 static const __cpuinitconst struct dmi_system_id multi_dmi_table[] = { 2209 { 2210 .callback = set_multi, 2211 .ident = "IBM System Summit2", 2212 .matches = { 2213 DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2214 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2215 }, 2216 }, 2217 {} 2218 }; 2219 2220 static void __cpuinit dmi_check_multi(void) 2221 { 2222 if (multi_checked) 2223 return; 2224 2225 dmi_check_system(multi_dmi_table); 2226 multi_checked = 1; 2227 } 2228 2229 /* 2230 * apic_is_clustered_box() -- Check if we can expect good TSC 2231 * 2232 * Thus far, the major user of this is IBM's Summit2 series: 2233 * Clustered boxes may have unsynced TSC problems if they are 2234 * multi-chassis. 2235 * Use DMI to check them 2236 */ 2237 __cpuinit int apic_is_clustered_box(void) 2238 { 2239 dmi_check_multi(); 2240 if (multi) 2241 return 1; 2242 2243 if (!is_vsmp_box()) 2244 return 0; 2245 2246 /* 2247 * ScaleMP vSMPowered boxes have one cluster per board and TSCs are 2248 * not guaranteed to be synced between boards 2249 */ 2250 if (apic_cluster_num() > 1) 2251 return 1; 2252 2253 return 0; 2254 } 2255 #endif 2256 2257 /* 2258 * APIC command line parameters 2259 */ 2260 static int __init setup_disableapic(char *arg) 2261 { 2262 disable_apic = 1; 2263 setup_clear_cpu_cap(X86_FEATURE_APIC); 2264 return 0; 2265 } 2266 early_param("disableapic", setup_disableapic); 2267 2268 /* same as disableapic, for compatibility */ 2269 static int __init setup_nolapic(char *arg) 2270 { 2271 return setup_disableapic(arg); 2272 } 2273 early_param("nolapic", setup_nolapic); 2274 2275 static int __init parse_lapic_timer_c2_ok(char *arg) 2276 { 2277 local_apic_timer_c2_ok = 1; 2278 return 0; 2279 } 2280 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2281 2282 static int __init parse_disable_apic_timer(char *arg) 2283 { 2284 disable_apic_timer = 1; 2285 return 0; 2286 } 2287 early_param("noapictimer", parse_disable_apic_timer); 2288 2289 static int __init parse_nolapic_timer(char *arg) 2290 { 2291 disable_apic_timer = 1; 2292 return 0; 2293 } 2294 early_param("nolapic_timer", parse_nolapic_timer); 2295 2296 static int __init apic_set_verbosity(char *arg) 2297 { 2298 if (!arg) { 2299 #ifdef CONFIG_X86_64 2300 skip_ioapic_setup = 0; 2301 return 0; 2302 #endif 2303 return -EINVAL; 2304 } 2305 2306 if (strcmp("debug", arg) == 0) 2307 apic_verbosity = APIC_DEBUG; 2308 else if (strcmp("verbose", arg) == 0) 2309 apic_verbosity = APIC_VERBOSE; 2310 else { 2311 pr_warning("APIC Verbosity level %s not recognised" 2312 " use apic=verbose or apic=debug\n", arg); 2313 return -EINVAL; 2314 } 2315 2316 return 0; 2317 } 2318 early_param("apic", apic_set_verbosity); 2319 2320 static int __init lapic_insert_resource(void) 2321 { 2322 if (!apic_phys) 2323 return -1; 2324 2325 /* Put local APIC into the resource map. */ 2326 lapic_resource.start = apic_phys; 2327 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2328 insert_resource(&iomem_resource, &lapic_resource); 2329 2330 return 0; 2331 } 2332 2333 /* 2334 * need call insert after e820_reserve_resources() 2335 * that is using request_resource 2336 */ 2337 late_initcall(lapic_insert_resource); 2338