1 /* 2 * Local APIC handling, local APIC timers 3 * 4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 5 * 6 * Fixes 7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 8 * thanks to Eric Gilmore 9 * and Rolf G. Tews 10 * for testing these extensively. 11 * Maciej W. Rozycki : Various updates and fixes. 12 * Mikael Pettersson : Power Management for UP-APIC. 13 * Pavel Machek and 14 * Mikael Pettersson : PM converted to driver model. 15 */ 16 17 #include <linux/perf_event.h> 18 #include <linux/kernel_stat.h> 19 #include <linux/mc146818rtc.h> 20 #include <linux/acpi_pmtmr.h> 21 #include <linux/clockchips.h> 22 #include <linux/interrupt.h> 23 #include <linux/bootmem.h> 24 #include <linux/ftrace.h> 25 #include <linux/ioport.h> 26 #include <linux/export.h> 27 #include <linux/syscore_ops.h> 28 #include <linux/delay.h> 29 #include <linux/timex.h> 30 #include <linux/i8253.h> 31 #include <linux/dmar.h> 32 #include <linux/init.h> 33 #include <linux/cpu.h> 34 #include <linux/dmi.h> 35 #include <linux/smp.h> 36 #include <linux/mm.h> 37 38 #include <asm/trace/irq_vectors.h> 39 #include <asm/irq_remapping.h> 40 #include <asm/perf_event.h> 41 #include <asm/x86_init.h> 42 #include <asm/pgalloc.h> 43 #include <linux/atomic.h> 44 #include <asm/mpspec.h> 45 #include <asm/i8259.h> 46 #include <asm/proto.h> 47 #include <asm/apic.h> 48 #include <asm/io_apic.h> 49 #include <asm/desc.h> 50 #include <asm/hpet.h> 51 #include <asm/mtrr.h> 52 #include <asm/time.h> 53 #include <asm/smp.h> 54 #include <asm/mce.h> 55 #include <asm/tsc.h> 56 #include <asm/hypervisor.h> 57 #include <asm/cpu_device_id.h> 58 #include <asm/intel-family.h> 59 #include <asm/irq_regs.h> 60 61 unsigned int num_processors; 62 63 unsigned disabled_cpus; 64 65 /* Processor that is doing the boot up */ 66 unsigned int boot_cpu_physical_apicid = -1U; 67 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); 68 69 u8 boot_cpu_apic_version; 70 71 /* 72 * The highest APIC ID seen during enumeration. 73 */ 74 static unsigned int max_physical_apicid; 75 76 /* 77 * Bitmask of physically existing CPUs: 78 */ 79 physid_mask_t phys_cpu_present_map; 80 81 /* 82 * Processor to be disabled specified by kernel parameter 83 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to 84 * avoid undefined behaviour caused by sending INIT from AP to BSP. 85 */ 86 static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID; 87 88 /* 89 * This variable controls which CPUs receive external NMIs. By default, 90 * external NMIs are delivered only to the BSP. 91 */ 92 static int apic_extnmi = APIC_EXTNMI_BSP; 93 94 /* 95 * Map cpu index to physical APIC ID 96 */ 97 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); 98 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID); 99 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX); 100 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 101 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 102 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid); 103 104 #ifdef CONFIG_X86_32 105 106 /* 107 * On x86_32, the mapping between cpu and logical apicid may vary 108 * depending on apic in use. The following early percpu variable is 109 * used for the mapping. This is where the behaviors of x86_64 and 32 110 * actually diverge. Let's keep it ugly for now. 111 */ 112 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID); 113 114 /* Local APIC was disabled by the BIOS and enabled by the kernel */ 115 static int enabled_via_apicbase; 116 117 /* 118 * Handle interrupt mode configuration register (IMCR). 119 * This register controls whether the interrupt signals 120 * that reach the BSP come from the master PIC or from the 121 * local APIC. Before entering Symmetric I/O Mode, either 122 * the BIOS or the operating system must switch out of 123 * PIC Mode by changing the IMCR. 124 */ 125 static inline void imcr_pic_to_apic(void) 126 { 127 /* select IMCR register */ 128 outb(0x70, 0x22); 129 /* NMI and 8259 INTR go through APIC */ 130 outb(0x01, 0x23); 131 } 132 133 static inline void imcr_apic_to_pic(void) 134 { 135 /* select IMCR register */ 136 outb(0x70, 0x22); 137 /* NMI and 8259 INTR go directly to BSP */ 138 outb(0x00, 0x23); 139 } 140 #endif 141 142 /* 143 * Knob to control our willingness to enable the local APIC. 144 * 145 * +1=force-enable 146 */ 147 static int force_enable_local_apic __initdata; 148 149 /* 150 * APIC command line parameters 151 */ 152 static int __init parse_lapic(char *arg) 153 { 154 if (IS_ENABLED(CONFIG_X86_32) && !arg) 155 force_enable_local_apic = 1; 156 else if (arg && !strncmp(arg, "notscdeadline", 13)) 157 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 158 return 0; 159 } 160 early_param("lapic", parse_lapic); 161 162 #ifdef CONFIG_X86_64 163 static int apic_calibrate_pmtmr __initdata; 164 static __init int setup_apicpmtimer(char *s) 165 { 166 apic_calibrate_pmtmr = 1; 167 notsc_setup(NULL); 168 return 0; 169 } 170 __setup("apicpmtimer", setup_apicpmtimer); 171 #endif 172 173 unsigned long mp_lapic_addr; 174 int disable_apic; 175 /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 176 static int disable_apic_timer __initdata; 177 /* Local APIC timer works in C2 */ 178 int local_apic_timer_c2_ok; 179 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 180 181 /* 182 * Debug level, exported for io_apic.c 183 */ 184 unsigned int apic_verbosity; 185 186 int pic_mode; 187 188 /* Have we found an MP table */ 189 int smp_found_config; 190 191 static struct resource lapic_resource = { 192 .name = "Local APIC", 193 .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 194 }; 195 196 unsigned int lapic_timer_frequency = 0; 197 198 static void apic_pm_activate(void); 199 200 static unsigned long apic_phys; 201 202 /* 203 * Get the LAPIC version 204 */ 205 static inline int lapic_get_version(void) 206 { 207 return GET_APIC_VERSION(apic_read(APIC_LVR)); 208 } 209 210 /* 211 * Check, if the APIC is integrated or a separate chip 212 */ 213 static inline int lapic_is_integrated(void) 214 { 215 return APIC_INTEGRATED(lapic_get_version()); 216 } 217 218 /* 219 * Check, whether this is a modern or a first generation APIC 220 */ 221 static int modern_apic(void) 222 { 223 /* AMD systems use old APIC versions, so check the CPU */ 224 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 225 boot_cpu_data.x86 >= 0xf) 226 return 1; 227 return lapic_get_version() >= 0x14; 228 } 229 230 /* 231 * right after this call apic become NOOP driven 232 * so apic->write/read doesn't do anything 233 */ 234 static void __init apic_disable(void) 235 { 236 pr_info("APIC: switched to apic NOOP\n"); 237 apic = &apic_noop; 238 } 239 240 void native_apic_wait_icr_idle(void) 241 { 242 while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 243 cpu_relax(); 244 } 245 246 u32 native_safe_apic_wait_icr_idle(void) 247 { 248 u32 send_status; 249 int timeout; 250 251 timeout = 0; 252 do { 253 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 254 if (!send_status) 255 break; 256 inc_irq_stat(icr_read_retry_count); 257 udelay(100); 258 } while (timeout++ < 1000); 259 260 return send_status; 261 } 262 263 void native_apic_icr_write(u32 low, u32 id) 264 { 265 unsigned long flags; 266 267 local_irq_save(flags); 268 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 269 apic_write(APIC_ICR, low); 270 local_irq_restore(flags); 271 } 272 273 u64 native_apic_icr_read(void) 274 { 275 u32 icr1, icr2; 276 277 icr2 = apic_read(APIC_ICR2); 278 icr1 = apic_read(APIC_ICR); 279 280 return icr1 | ((u64)icr2 << 32); 281 } 282 283 #ifdef CONFIG_X86_32 284 /** 285 * get_physical_broadcast - Get number of physical broadcast IDs 286 */ 287 int get_physical_broadcast(void) 288 { 289 return modern_apic() ? 0xff : 0xf; 290 } 291 #endif 292 293 /** 294 * lapic_get_maxlvt - get the maximum number of local vector table entries 295 */ 296 int lapic_get_maxlvt(void) 297 { 298 /* 299 * - we always have APIC integrated on 64bit mode 300 * - 82489DXs do not report # of LVT entries 301 */ 302 return lapic_is_integrated() ? GET_APIC_MAXLVT(apic_read(APIC_LVR)) : 2; 303 } 304 305 /* 306 * Local APIC timer 307 */ 308 309 /* Clock divisor */ 310 #define APIC_DIVISOR 16 311 #define TSC_DIVISOR 8 312 313 /* 314 * This function sets up the local APIC timer, with a timeout of 315 * 'clocks' APIC bus clock. During calibration we actually call 316 * this function twice on the boot CPU, once with a bogus timeout 317 * value, second time for real. The other (noncalibrating) CPUs 318 * call this function only once, with the real, calibrated value. 319 * 320 * We do reads before writes even if unnecessary, to get around the 321 * P5 APIC double write bug. 322 */ 323 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 324 { 325 unsigned int lvtt_value, tmp_value; 326 327 lvtt_value = LOCAL_TIMER_VECTOR; 328 if (!oneshot) 329 lvtt_value |= APIC_LVT_TIMER_PERIODIC; 330 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 331 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE; 332 333 if (!lapic_is_integrated()) 334 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 335 336 if (!irqen) 337 lvtt_value |= APIC_LVT_MASKED; 338 339 apic_write(APIC_LVTT, lvtt_value); 340 341 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { 342 /* 343 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, 344 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized. 345 * According to Intel, MFENCE can do the serialization here. 346 */ 347 asm volatile("mfence" : : : "memory"); 348 349 printk_once(KERN_DEBUG "TSC deadline timer enabled\n"); 350 return; 351 } 352 353 /* 354 * Divide PICLK by 16 355 */ 356 tmp_value = apic_read(APIC_TDCR); 357 apic_write(APIC_TDCR, 358 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 359 APIC_TDR_DIV_16); 360 361 if (!oneshot) 362 apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 363 } 364 365 /* 366 * Setup extended LVT, AMD specific 367 * 368 * Software should use the LVT offsets the BIOS provides. The offsets 369 * are determined by the subsystems using it like those for MCE 370 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts 371 * are supported. Beginning with family 10h at least 4 offsets are 372 * available. 373 * 374 * Since the offsets must be consistent for all cores, we keep track 375 * of the LVT offsets in software and reserve the offset for the same 376 * vector also to be used on other cores. An offset is freed by 377 * setting the entry to APIC_EILVT_MASKED. 378 * 379 * If the BIOS is right, there should be no conflicts. Otherwise a 380 * "[Firmware Bug]: ..." error message is generated. However, if 381 * software does not properly determines the offsets, it is not 382 * necessarily a BIOS bug. 383 */ 384 385 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; 386 387 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) 388 { 389 return (old & APIC_EILVT_MASKED) 390 || (new == APIC_EILVT_MASKED) 391 || ((new & ~APIC_EILVT_MASKED) == old); 392 } 393 394 static unsigned int reserve_eilvt_offset(int offset, unsigned int new) 395 { 396 unsigned int rsvd, vector; 397 398 if (offset >= APIC_EILVT_NR_MAX) 399 return ~0; 400 401 rsvd = atomic_read(&eilvt_offsets[offset]); 402 do { 403 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ 404 if (vector && !eilvt_entry_is_changeable(vector, new)) 405 /* may not change if vectors are different */ 406 return rsvd; 407 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); 408 } while (rsvd != new); 409 410 rsvd &= ~APIC_EILVT_MASKED; 411 if (rsvd && rsvd != vector) 412 pr_info("LVT offset %d assigned for vector 0x%02x\n", 413 offset, rsvd); 414 415 return new; 416 } 417 418 /* 419 * If mask=1, the LVT entry does not generate interrupts while mask=0 420 * enables the vector. See also the BKDGs. Must be called with 421 * preemption disabled. 422 */ 423 424 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) 425 { 426 unsigned long reg = APIC_EILVTn(offset); 427 unsigned int new, old, reserved; 428 429 new = (mask << 16) | (msg_type << 8) | vector; 430 old = apic_read(reg); 431 reserved = reserve_eilvt_offset(offset, new); 432 433 if (reserved != new) { 434 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 435 "vector 0x%x, but the register is already in use for " 436 "vector 0x%x on another cpu\n", 437 smp_processor_id(), reg, offset, new, reserved); 438 return -EINVAL; 439 } 440 441 if (!eilvt_entry_is_changeable(old, new)) { 442 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 443 "vector 0x%x, but the register is already in use for " 444 "vector 0x%x on this cpu\n", 445 smp_processor_id(), reg, offset, new, old); 446 return -EBUSY; 447 } 448 449 apic_write(reg, new); 450 451 return 0; 452 } 453 EXPORT_SYMBOL_GPL(setup_APIC_eilvt); 454 455 /* 456 * Program the next event, relative to now 457 */ 458 static int lapic_next_event(unsigned long delta, 459 struct clock_event_device *evt) 460 { 461 apic_write(APIC_TMICT, delta); 462 return 0; 463 } 464 465 static int lapic_next_deadline(unsigned long delta, 466 struct clock_event_device *evt) 467 { 468 u64 tsc; 469 470 tsc = rdtsc(); 471 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); 472 return 0; 473 } 474 475 static int lapic_timer_shutdown(struct clock_event_device *evt) 476 { 477 unsigned int v; 478 479 /* Lapic used as dummy for broadcast ? */ 480 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 481 return 0; 482 483 v = apic_read(APIC_LVTT); 484 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 485 apic_write(APIC_LVTT, v); 486 apic_write(APIC_TMICT, 0); 487 return 0; 488 } 489 490 static inline int 491 lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot) 492 { 493 /* Lapic used as dummy for broadcast ? */ 494 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 495 return 0; 496 497 __setup_APIC_LVTT(lapic_timer_frequency, oneshot, 1); 498 return 0; 499 } 500 501 static int lapic_timer_set_periodic(struct clock_event_device *evt) 502 { 503 return lapic_timer_set_periodic_oneshot(evt, false); 504 } 505 506 static int lapic_timer_set_oneshot(struct clock_event_device *evt) 507 { 508 return lapic_timer_set_periodic_oneshot(evt, true); 509 } 510 511 /* 512 * Local APIC timer broadcast function 513 */ 514 static void lapic_timer_broadcast(const struct cpumask *mask) 515 { 516 #ifdef CONFIG_SMP 517 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 518 #endif 519 } 520 521 522 /* 523 * The local apic timer can be used for any function which is CPU local. 524 */ 525 static struct clock_event_device lapic_clockevent = { 526 .name = "lapic", 527 .features = CLOCK_EVT_FEAT_PERIODIC | 528 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP 529 | CLOCK_EVT_FEAT_DUMMY, 530 .shift = 32, 531 .set_state_shutdown = lapic_timer_shutdown, 532 .set_state_periodic = lapic_timer_set_periodic, 533 .set_state_oneshot = lapic_timer_set_oneshot, 534 .set_state_oneshot_stopped = lapic_timer_shutdown, 535 .set_next_event = lapic_next_event, 536 .broadcast = lapic_timer_broadcast, 537 .rating = 100, 538 .irq = -1, 539 }; 540 static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 541 542 #define DEADLINE_MODEL_MATCH_FUNC(model, func) \ 543 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&func } 544 545 #define DEADLINE_MODEL_MATCH_REV(model, rev) \ 546 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)rev } 547 548 static u32 hsx_deadline_rev(void) 549 { 550 switch (boot_cpu_data.x86_stepping) { 551 case 0x02: return 0x3a; /* EP */ 552 case 0x04: return 0x0f; /* EX */ 553 } 554 555 return ~0U; 556 } 557 558 static u32 bdx_deadline_rev(void) 559 { 560 switch (boot_cpu_data.x86_stepping) { 561 case 0x02: return 0x00000011; 562 case 0x03: return 0x0700000e; 563 case 0x04: return 0x0f00000c; 564 case 0x05: return 0x0e000003; 565 } 566 567 return ~0U; 568 } 569 570 static u32 skx_deadline_rev(void) 571 { 572 switch (boot_cpu_data.x86_stepping) { 573 case 0x03: return 0x01000136; 574 case 0x04: return 0x02000014; 575 } 576 577 if (boot_cpu_data.x86_stepping > 4) 578 return 0; 579 580 return ~0U; 581 } 582 583 static const struct x86_cpu_id deadline_match[] = { 584 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_HASWELL_X, hsx_deadline_rev), 585 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_X, 0x0b000020), 586 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_BROADWELL_XEON_D, bdx_deadline_rev), 587 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_SKYLAKE_X, skx_deadline_rev), 588 589 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_CORE, 0x22), 590 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_ULT, 0x20), 591 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_GT3E, 0x17), 592 593 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_CORE, 0x25), 594 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_GT3E, 0x17), 595 596 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_MOBILE, 0xb2), 597 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_DESKTOP, 0xb2), 598 599 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_MOBILE, 0x52), 600 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_DESKTOP, 0x52), 601 602 {}, 603 }; 604 605 static void apic_check_deadline_errata(void) 606 { 607 const struct x86_cpu_id *m; 608 u32 rev; 609 610 if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER) || 611 boot_cpu_has(X86_FEATURE_HYPERVISOR)) 612 return; 613 614 m = x86_match_cpu(deadline_match); 615 if (!m) 616 return; 617 618 /* 619 * Function pointers will have the MSB set due to address layout, 620 * immediate revisions will not. 621 */ 622 if ((long)m->driver_data < 0) 623 rev = ((u32 (*)(void))(m->driver_data))(); 624 else 625 rev = (u32)m->driver_data; 626 627 if (boot_cpu_data.microcode >= rev) 628 return; 629 630 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 631 pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; " 632 "please update microcode to version: 0x%x (or later)\n", rev); 633 } 634 635 /* 636 * Setup the local APIC timer for this CPU. Copy the initialized values 637 * of the boot CPU and register the clock event in the framework. 638 */ 639 static void setup_APIC_timer(void) 640 { 641 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 642 643 if (this_cpu_has(X86_FEATURE_ARAT)) { 644 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 645 /* Make LAPIC timer preferrable over percpu HPET */ 646 lapic_clockevent.rating = 150; 647 } 648 649 memcpy(levt, &lapic_clockevent, sizeof(*levt)); 650 levt->cpumask = cpumask_of(smp_processor_id()); 651 652 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 653 levt->name = "lapic-deadline"; 654 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | 655 CLOCK_EVT_FEAT_DUMMY); 656 levt->set_next_event = lapic_next_deadline; 657 clockevents_config_and_register(levt, 658 tsc_khz * (1000 / TSC_DIVISOR), 659 0xF, ~0UL); 660 } else 661 clockevents_register_device(levt); 662 } 663 664 /* 665 * Install the updated TSC frequency from recalibration at the TSC 666 * deadline clockevent devices. 667 */ 668 static void __lapic_update_tsc_freq(void *info) 669 { 670 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 671 672 if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 673 return; 674 675 clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR)); 676 } 677 678 void lapic_update_tsc_freq(void) 679 { 680 /* 681 * The clockevent device's ->mult and ->shift can both be 682 * changed. In order to avoid races, schedule the frequency 683 * update code on each CPU. 684 */ 685 on_each_cpu(__lapic_update_tsc_freq, NULL, 0); 686 } 687 688 /* 689 * In this functions we calibrate APIC bus clocks to the external timer. 690 * 691 * We want to do the calibration only once since we want to have local timer 692 * irqs syncron. CPUs connected by the same APIC bus have the very same bus 693 * frequency. 694 * 695 * This was previously done by reading the PIT/HPET and waiting for a wrap 696 * around to find out, that a tick has elapsed. I have a box, where the PIT 697 * readout is broken, so it never gets out of the wait loop again. This was 698 * also reported by others. 699 * 700 * Monitoring the jiffies value is inaccurate and the clockevents 701 * infrastructure allows us to do a simple substitution of the interrupt 702 * handler. 703 * 704 * The calibration routine also uses the pm_timer when possible, as the PIT 705 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 706 * back to normal later in the boot process). 707 */ 708 709 #define LAPIC_CAL_LOOPS (HZ/10) 710 711 static __initdata int lapic_cal_loops = -1; 712 static __initdata long lapic_cal_t1, lapic_cal_t2; 713 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 714 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 715 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 716 717 /* 718 * Temporary interrupt handler. 719 */ 720 static void __init lapic_cal_handler(struct clock_event_device *dev) 721 { 722 unsigned long long tsc = 0; 723 long tapic = apic_read(APIC_TMCCT); 724 unsigned long pm = acpi_pm_read_early(); 725 726 if (boot_cpu_has(X86_FEATURE_TSC)) 727 tsc = rdtsc(); 728 729 switch (lapic_cal_loops++) { 730 case 0: 731 lapic_cal_t1 = tapic; 732 lapic_cal_tsc1 = tsc; 733 lapic_cal_pm1 = pm; 734 lapic_cal_j1 = jiffies; 735 break; 736 737 case LAPIC_CAL_LOOPS: 738 lapic_cal_t2 = tapic; 739 lapic_cal_tsc2 = tsc; 740 if (pm < lapic_cal_pm1) 741 pm += ACPI_PM_OVRRUN; 742 lapic_cal_pm2 = pm; 743 lapic_cal_j2 = jiffies; 744 break; 745 } 746 } 747 748 static int __init 749 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 750 { 751 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 752 const long pm_thresh = pm_100ms / 100; 753 unsigned long mult; 754 u64 res; 755 756 #ifndef CONFIG_X86_PM_TIMER 757 return -1; 758 #endif 759 760 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 761 762 /* Check, if the PM timer is available */ 763 if (!deltapm) 764 return -1; 765 766 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 767 768 if (deltapm > (pm_100ms - pm_thresh) && 769 deltapm < (pm_100ms + pm_thresh)) { 770 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 771 return 0; 772 } 773 774 res = (((u64)deltapm) * mult) >> 22; 775 do_div(res, 1000000); 776 pr_warning("APIC calibration not consistent " 777 "with PM-Timer: %ldms instead of 100ms\n",(long)res); 778 779 /* Correct the lapic counter value */ 780 res = (((u64)(*delta)) * pm_100ms); 781 do_div(res, deltapm); 782 pr_info("APIC delta adjusted to PM-Timer: " 783 "%lu (%ld)\n", (unsigned long)res, *delta); 784 *delta = (long)res; 785 786 /* Correct the tsc counter value */ 787 if (boot_cpu_has(X86_FEATURE_TSC)) { 788 res = (((u64)(*deltatsc)) * pm_100ms); 789 do_div(res, deltapm); 790 apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 791 "PM-Timer: %lu (%ld)\n", 792 (unsigned long)res, *deltatsc); 793 *deltatsc = (long)res; 794 } 795 796 return 0; 797 } 798 799 static int __init calibrate_APIC_clock(void) 800 { 801 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 802 void (*real_handler)(struct clock_event_device *dev); 803 unsigned long deltaj; 804 long delta, deltatsc; 805 int pm_referenced = 0; 806 807 /** 808 * check if lapic timer has already been calibrated by platform 809 * specific routine, such as tsc calibration code. if so, we just fill 810 * in the clockevent structure and return. 811 */ 812 813 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 814 return 0; 815 } else if (lapic_timer_frequency) { 816 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", 817 lapic_timer_frequency); 818 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR, 819 TICK_NSEC, lapic_clockevent.shift); 820 lapic_clockevent.max_delta_ns = 821 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); 822 lapic_clockevent.max_delta_ticks = 0x7FFFFF; 823 lapic_clockevent.min_delta_ns = 824 clockevent_delta2ns(0xF, &lapic_clockevent); 825 lapic_clockevent.min_delta_ticks = 0xF; 826 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 827 return 0; 828 } 829 830 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 831 "calibrating APIC timer ...\n"); 832 833 local_irq_disable(); 834 835 /* Replace the global interrupt handler */ 836 real_handler = global_clock_event->event_handler; 837 global_clock_event->event_handler = lapic_cal_handler; 838 839 /* 840 * Setup the APIC counter to maximum. There is no way the lapic 841 * can underflow in the 100ms detection time frame 842 */ 843 __setup_APIC_LVTT(0xffffffff, 0, 0); 844 845 /* Let the interrupts run */ 846 local_irq_enable(); 847 848 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 849 cpu_relax(); 850 851 local_irq_disable(); 852 853 /* Restore the real event handler */ 854 global_clock_event->event_handler = real_handler; 855 856 /* Build delta t1-t2 as apic timer counts down */ 857 delta = lapic_cal_t1 - lapic_cal_t2; 858 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 859 860 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 861 862 /* we trust the PM based calibration if possible */ 863 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 864 &delta, &deltatsc); 865 866 /* Calculate the scaled math multiplication factor */ 867 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 868 lapic_clockevent.shift); 869 lapic_clockevent.max_delta_ns = 870 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); 871 lapic_clockevent.max_delta_ticks = 0x7FFFFFFF; 872 lapic_clockevent.min_delta_ns = 873 clockevent_delta2ns(0xF, &lapic_clockevent); 874 lapic_clockevent.min_delta_ticks = 0xF; 875 876 lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 877 878 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 879 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); 880 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 881 lapic_timer_frequency); 882 883 if (boot_cpu_has(X86_FEATURE_TSC)) { 884 apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 885 "%ld.%04ld MHz.\n", 886 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 887 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 888 } 889 890 apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 891 "%u.%04u MHz.\n", 892 lapic_timer_frequency / (1000000 / HZ), 893 lapic_timer_frequency % (1000000 / HZ)); 894 895 /* 896 * Do a sanity check on the APIC calibration result 897 */ 898 if (lapic_timer_frequency < (1000000 / HZ)) { 899 local_irq_enable(); 900 pr_warning("APIC frequency too slow, disabling apic timer\n"); 901 return -1; 902 } 903 904 levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 905 906 /* 907 * PM timer calibration failed or not turned on 908 * so lets try APIC timer based calibration 909 */ 910 if (!pm_referenced) { 911 apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 912 913 /* 914 * Setup the apic timer manually 915 */ 916 levt->event_handler = lapic_cal_handler; 917 lapic_timer_set_periodic(levt); 918 lapic_cal_loops = -1; 919 920 /* Let the interrupts run */ 921 local_irq_enable(); 922 923 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 924 cpu_relax(); 925 926 /* Stop the lapic timer */ 927 local_irq_disable(); 928 lapic_timer_shutdown(levt); 929 930 /* Jiffies delta */ 931 deltaj = lapic_cal_j2 - lapic_cal_j1; 932 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 933 934 /* Check, if the jiffies result is consistent */ 935 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 936 apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 937 else 938 levt->features |= CLOCK_EVT_FEAT_DUMMY; 939 } 940 local_irq_enable(); 941 942 if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 943 pr_warning("APIC timer disabled due to verification failure\n"); 944 return -1; 945 } 946 947 return 0; 948 } 949 950 /* 951 * Setup the boot APIC 952 * 953 * Calibrate and verify the result. 954 */ 955 void __init setup_boot_APIC_clock(void) 956 { 957 /* 958 * The local apic timer can be disabled via the kernel 959 * commandline or from the CPU detection code. Register the lapic 960 * timer as a dummy clock event source on SMP systems, so the 961 * broadcast mechanism is used. On UP systems simply ignore it. 962 */ 963 if (disable_apic_timer) { 964 pr_info("Disabling APIC timer\n"); 965 /* No broadcast on UP ! */ 966 if (num_possible_cpus() > 1) { 967 lapic_clockevent.mult = 1; 968 setup_APIC_timer(); 969 } 970 return; 971 } 972 973 if (calibrate_APIC_clock()) { 974 /* No broadcast on UP ! */ 975 if (num_possible_cpus() > 1) 976 setup_APIC_timer(); 977 return; 978 } 979 980 /* 981 * If nmi_watchdog is set to IO_APIC, we need the 982 * PIT/HPET going. Otherwise register lapic as a dummy 983 * device. 984 */ 985 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 986 987 /* Setup the lapic or request the broadcast */ 988 setup_APIC_timer(); 989 amd_e400_c1e_apic_setup(); 990 } 991 992 void setup_secondary_APIC_clock(void) 993 { 994 setup_APIC_timer(); 995 amd_e400_c1e_apic_setup(); 996 } 997 998 /* 999 * The guts of the apic timer interrupt 1000 */ 1001 static void local_apic_timer_interrupt(void) 1002 { 1003 struct clock_event_device *evt = this_cpu_ptr(&lapic_events); 1004 1005 /* 1006 * Normally we should not be here till LAPIC has been initialized but 1007 * in some cases like kdump, its possible that there is a pending LAPIC 1008 * timer interrupt from previous kernel's context and is delivered in 1009 * new kernel the moment interrupts are enabled. 1010 * 1011 * Interrupts are enabled early and LAPIC is setup much later, hence 1012 * its possible that when we get here evt->event_handler is NULL. 1013 * Check for event_handler being NULL and discard the interrupt as 1014 * spurious. 1015 */ 1016 if (!evt->event_handler) { 1017 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", 1018 smp_processor_id()); 1019 /* Switch it off */ 1020 lapic_timer_shutdown(evt); 1021 return; 1022 } 1023 1024 /* 1025 * the NMI deadlock-detector uses this. 1026 */ 1027 inc_irq_stat(apic_timer_irqs); 1028 1029 evt->event_handler(evt); 1030 } 1031 1032 /* 1033 * Local APIC timer interrupt. This is the most natural way for doing 1034 * local interrupts, but local timer interrupts can be emulated by 1035 * broadcast interrupts too. [in case the hw doesn't support APIC timers] 1036 * 1037 * [ if a single-CPU system runs an SMP kernel then we call the local 1038 * interrupt as well. Thus we cannot inline the local irq ... ] 1039 */ 1040 __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) 1041 { 1042 struct pt_regs *old_regs = set_irq_regs(regs); 1043 1044 /* 1045 * NOTE! We'd better ACK the irq immediately, 1046 * because timer handling can be slow. 1047 * 1048 * update_process_times() expects us to have done irq_enter(). 1049 * Besides, if we don't timer interrupts ignore the global 1050 * interrupt lock, which is the WrongThing (tm) to do. 1051 */ 1052 entering_ack_irq(); 1053 trace_local_timer_entry(LOCAL_TIMER_VECTOR); 1054 local_apic_timer_interrupt(); 1055 trace_local_timer_exit(LOCAL_TIMER_VECTOR); 1056 exiting_irq(); 1057 1058 set_irq_regs(old_regs); 1059 } 1060 1061 int setup_profiling_timer(unsigned int multiplier) 1062 { 1063 return -EINVAL; 1064 } 1065 1066 /* 1067 * Local APIC start and shutdown 1068 */ 1069 1070 /** 1071 * clear_local_APIC - shutdown the local APIC 1072 * 1073 * This is called, when a CPU is disabled and before rebooting, so the state of 1074 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 1075 * leftovers during boot. 1076 */ 1077 void clear_local_APIC(void) 1078 { 1079 int maxlvt; 1080 u32 v; 1081 1082 /* APIC hasn't been mapped yet */ 1083 if (!x2apic_mode && !apic_phys) 1084 return; 1085 1086 maxlvt = lapic_get_maxlvt(); 1087 /* 1088 * Masking an LVT entry can trigger a local APIC error 1089 * if the vector is zero. Mask LVTERR first to prevent this. 1090 */ 1091 if (maxlvt >= 3) { 1092 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 1093 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 1094 } 1095 /* 1096 * Careful: we have to set masks only first to deassert 1097 * any level-triggered sources. 1098 */ 1099 v = apic_read(APIC_LVTT); 1100 apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 1101 v = apic_read(APIC_LVT0); 1102 apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 1103 v = apic_read(APIC_LVT1); 1104 apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 1105 if (maxlvt >= 4) { 1106 v = apic_read(APIC_LVTPC); 1107 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 1108 } 1109 1110 /* lets not touch this if we didn't frob it */ 1111 #ifdef CONFIG_X86_THERMAL_VECTOR 1112 if (maxlvt >= 5) { 1113 v = apic_read(APIC_LVTTHMR); 1114 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 1115 } 1116 #endif 1117 #ifdef CONFIG_X86_MCE_INTEL 1118 if (maxlvt >= 6) { 1119 v = apic_read(APIC_LVTCMCI); 1120 if (!(v & APIC_LVT_MASKED)) 1121 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 1122 } 1123 #endif 1124 1125 /* 1126 * Clean APIC state for other OSs: 1127 */ 1128 apic_write(APIC_LVTT, APIC_LVT_MASKED); 1129 apic_write(APIC_LVT0, APIC_LVT_MASKED); 1130 apic_write(APIC_LVT1, APIC_LVT_MASKED); 1131 if (maxlvt >= 3) 1132 apic_write(APIC_LVTERR, APIC_LVT_MASKED); 1133 if (maxlvt >= 4) 1134 apic_write(APIC_LVTPC, APIC_LVT_MASKED); 1135 1136 /* Integrated APIC (!82489DX) ? */ 1137 if (lapic_is_integrated()) { 1138 if (maxlvt > 3) 1139 /* Clear ESR due to Pentium errata 3AP and 11AP */ 1140 apic_write(APIC_ESR, 0); 1141 apic_read(APIC_ESR); 1142 } 1143 } 1144 1145 /** 1146 * disable_local_APIC - clear and disable the local APIC 1147 */ 1148 void disable_local_APIC(void) 1149 { 1150 unsigned int value; 1151 1152 /* APIC hasn't been mapped yet */ 1153 if (!x2apic_mode && !apic_phys) 1154 return; 1155 1156 clear_local_APIC(); 1157 1158 /* 1159 * Disable APIC (implies clearing of registers 1160 * for 82489DX!). 1161 */ 1162 value = apic_read(APIC_SPIV); 1163 value &= ~APIC_SPIV_APIC_ENABLED; 1164 apic_write(APIC_SPIV, value); 1165 1166 #ifdef CONFIG_X86_32 1167 /* 1168 * When LAPIC was disabled by the BIOS and enabled by the kernel, 1169 * restore the disabled state. 1170 */ 1171 if (enabled_via_apicbase) { 1172 unsigned int l, h; 1173 1174 rdmsr(MSR_IA32_APICBASE, l, h); 1175 l &= ~MSR_IA32_APICBASE_ENABLE; 1176 wrmsr(MSR_IA32_APICBASE, l, h); 1177 } 1178 #endif 1179 } 1180 1181 /* 1182 * If Linux enabled the LAPIC against the BIOS default disable it down before 1183 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 1184 * not power-off. Additionally clear all LVT entries before disable_local_APIC 1185 * for the case where Linux didn't enable the LAPIC. 1186 */ 1187 void lapic_shutdown(void) 1188 { 1189 unsigned long flags; 1190 1191 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) 1192 return; 1193 1194 local_irq_save(flags); 1195 1196 #ifdef CONFIG_X86_32 1197 if (!enabled_via_apicbase) 1198 clear_local_APIC(); 1199 else 1200 #endif 1201 disable_local_APIC(); 1202 1203 1204 local_irq_restore(flags); 1205 } 1206 1207 /** 1208 * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1209 */ 1210 void __init sync_Arb_IDs(void) 1211 { 1212 /* 1213 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1214 * needed on AMD. 1215 */ 1216 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1217 return; 1218 1219 /* 1220 * Wait for idle. 1221 */ 1222 apic_wait_icr_idle(); 1223 1224 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1225 apic_write(APIC_ICR, APIC_DEST_ALLINC | 1226 APIC_INT_LEVELTRIG | APIC_DM_INIT); 1227 } 1228 1229 enum apic_intr_mode_id apic_intr_mode; 1230 1231 static int __init apic_intr_mode_select(void) 1232 { 1233 /* Check kernel option */ 1234 if (disable_apic) { 1235 pr_info("APIC disabled via kernel command line\n"); 1236 return APIC_PIC; 1237 } 1238 1239 /* Check BIOS */ 1240 #ifdef CONFIG_X86_64 1241 /* On 64-bit, the APIC must be integrated, Check local APIC only */ 1242 if (!boot_cpu_has(X86_FEATURE_APIC)) { 1243 disable_apic = 1; 1244 pr_info("APIC disabled by BIOS\n"); 1245 return APIC_PIC; 1246 } 1247 #else 1248 /* On 32-bit, the APIC may be integrated APIC or 82489DX */ 1249 1250 /* Neither 82489DX nor integrated APIC ? */ 1251 if (!boot_cpu_has(X86_FEATURE_APIC) && !smp_found_config) { 1252 disable_apic = 1; 1253 return APIC_PIC; 1254 } 1255 1256 /* If the BIOS pretends there is an integrated APIC ? */ 1257 if (!boot_cpu_has(X86_FEATURE_APIC) && 1258 APIC_INTEGRATED(boot_cpu_apic_version)) { 1259 disable_apic = 1; 1260 pr_err(FW_BUG "Local APIC %d not detected, force emulation\n", 1261 boot_cpu_physical_apicid); 1262 return APIC_PIC; 1263 } 1264 #endif 1265 1266 /* Check MP table or ACPI MADT configuration */ 1267 if (!smp_found_config) { 1268 disable_ioapic_support(); 1269 if (!acpi_lapic) { 1270 pr_info("APIC: ACPI MADT or MP tables are not detected\n"); 1271 return APIC_VIRTUAL_WIRE_NO_CONFIG; 1272 } 1273 return APIC_VIRTUAL_WIRE; 1274 } 1275 1276 #ifdef CONFIG_SMP 1277 /* If SMP should be disabled, then really disable it! */ 1278 if (!setup_max_cpus) { 1279 pr_info("APIC: SMP mode deactivated\n"); 1280 return APIC_SYMMETRIC_IO_NO_ROUTING; 1281 } 1282 1283 if (read_apic_id() != boot_cpu_physical_apicid) { 1284 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1285 read_apic_id(), boot_cpu_physical_apicid); 1286 /* Or can we switch back to PIC here? */ 1287 } 1288 #endif 1289 1290 return APIC_SYMMETRIC_IO; 1291 } 1292 1293 /* 1294 * An initial setup of the virtual wire mode. 1295 */ 1296 void __init init_bsp_APIC(void) 1297 { 1298 unsigned int value; 1299 1300 /* 1301 * Don't do the setup now if we have a SMP BIOS as the 1302 * through-I/O-APIC virtual wire mode might be active. 1303 */ 1304 if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC)) 1305 return; 1306 1307 /* 1308 * Do not trust the local APIC being empty at bootup. 1309 */ 1310 clear_local_APIC(); 1311 1312 /* 1313 * Enable APIC. 1314 */ 1315 value = apic_read(APIC_SPIV); 1316 value &= ~APIC_VECTOR_MASK; 1317 value |= APIC_SPIV_APIC_ENABLED; 1318 1319 #ifdef CONFIG_X86_32 1320 /* This bit is reserved on P4/Xeon and should be cleared */ 1321 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1322 (boot_cpu_data.x86 == 15)) 1323 value &= ~APIC_SPIV_FOCUS_DISABLED; 1324 else 1325 #endif 1326 value |= APIC_SPIV_FOCUS_DISABLED; 1327 value |= SPURIOUS_APIC_VECTOR; 1328 apic_write(APIC_SPIV, value); 1329 1330 /* 1331 * Set up the virtual wire mode. 1332 */ 1333 apic_write(APIC_LVT0, APIC_DM_EXTINT); 1334 value = APIC_DM_NMI; 1335 if (!lapic_is_integrated()) /* 82489DX */ 1336 value |= APIC_LVT_LEVEL_TRIGGER; 1337 if (apic_extnmi == APIC_EXTNMI_NONE) 1338 value |= APIC_LVT_MASKED; 1339 apic_write(APIC_LVT1, value); 1340 } 1341 1342 /* Init the interrupt delivery mode for the BSP */ 1343 void __init apic_intr_mode_init(void) 1344 { 1345 bool upmode = IS_ENABLED(CONFIG_UP_LATE_INIT); 1346 1347 apic_intr_mode = apic_intr_mode_select(); 1348 1349 switch (apic_intr_mode) { 1350 case APIC_PIC: 1351 pr_info("APIC: Keep in PIC mode(8259)\n"); 1352 return; 1353 case APIC_VIRTUAL_WIRE: 1354 pr_info("APIC: Switch to virtual wire mode setup\n"); 1355 default_setup_apic_routing(); 1356 break; 1357 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1358 pr_info("APIC: Switch to virtual wire mode setup with no configuration\n"); 1359 upmode = true; 1360 default_setup_apic_routing(); 1361 break; 1362 case APIC_SYMMETRIC_IO: 1363 pr_info("APIC: Switch to symmetric I/O mode setup\n"); 1364 default_setup_apic_routing(); 1365 break; 1366 case APIC_SYMMETRIC_IO_NO_ROUTING: 1367 pr_info("APIC: Switch to symmetric I/O mode setup in no SMP routine\n"); 1368 break; 1369 } 1370 1371 apic_bsp_setup(upmode); 1372 } 1373 1374 static void lapic_setup_esr(void) 1375 { 1376 unsigned int oldvalue, value, maxlvt; 1377 1378 if (!lapic_is_integrated()) { 1379 pr_info("No ESR for 82489DX.\n"); 1380 return; 1381 } 1382 1383 if (apic->disable_esr) { 1384 /* 1385 * Something untraceable is creating bad interrupts on 1386 * secondary quads ... for the moment, just leave the 1387 * ESR disabled - we can't do anything useful with the 1388 * errors anyway - mbligh 1389 */ 1390 pr_info("Leaving ESR disabled.\n"); 1391 return; 1392 } 1393 1394 maxlvt = lapic_get_maxlvt(); 1395 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1396 apic_write(APIC_ESR, 0); 1397 oldvalue = apic_read(APIC_ESR); 1398 1399 /* enables sending errors */ 1400 value = ERROR_APIC_VECTOR; 1401 apic_write(APIC_LVTERR, value); 1402 1403 /* 1404 * spec says clear errors after enabling vector. 1405 */ 1406 if (maxlvt > 3) 1407 apic_write(APIC_ESR, 0); 1408 value = apic_read(APIC_ESR); 1409 if (value != oldvalue) 1410 apic_printk(APIC_VERBOSE, "ESR value before enabling " 1411 "vector: 0x%08x after: 0x%08x\n", 1412 oldvalue, value); 1413 } 1414 1415 static void apic_pending_intr_clear(void) 1416 { 1417 long long max_loops = cpu_khz ? cpu_khz : 1000000; 1418 unsigned long long tsc = 0, ntsc; 1419 unsigned int queued; 1420 unsigned long value; 1421 int i, j, acked = 0; 1422 1423 if (boot_cpu_has(X86_FEATURE_TSC)) 1424 tsc = rdtsc(); 1425 /* 1426 * After a crash, we no longer service the interrupts and a pending 1427 * interrupt from previous kernel might still have ISR bit set. 1428 * 1429 * Most probably by now CPU has serviced that pending interrupt and 1430 * it might not have done the ack_APIC_irq() because it thought, 1431 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it 1432 * does not clear the ISR bit and cpu thinks it has already serivced 1433 * the interrupt. Hence a vector might get locked. It was noticed 1434 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. 1435 */ 1436 do { 1437 queued = 0; 1438 for (i = APIC_ISR_NR - 1; i >= 0; i--) 1439 queued |= apic_read(APIC_IRR + i*0x10); 1440 1441 for (i = APIC_ISR_NR - 1; i >= 0; i--) { 1442 value = apic_read(APIC_ISR + i*0x10); 1443 for_each_set_bit(j, &value, 32) { 1444 ack_APIC_irq(); 1445 acked++; 1446 } 1447 } 1448 if (acked > 256) { 1449 pr_err("LAPIC pending interrupts after %d EOI\n", acked); 1450 break; 1451 } 1452 if (queued) { 1453 if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) { 1454 ntsc = rdtsc(); 1455 max_loops = (cpu_khz << 10) - (ntsc - tsc); 1456 } else { 1457 max_loops--; 1458 } 1459 } 1460 } while (queued && max_loops > 0); 1461 WARN_ON(max_loops <= 0); 1462 } 1463 1464 /** 1465 * setup_local_APIC - setup the local APIC 1466 * 1467 * Used to setup local APIC while initializing BSP or bringing up APs. 1468 * Always called with preemption disabled. 1469 */ 1470 static void setup_local_APIC(void) 1471 { 1472 int cpu = smp_processor_id(); 1473 unsigned int value; 1474 #ifdef CONFIG_X86_32 1475 int logical_apicid, ldr_apicid; 1476 #endif 1477 1478 1479 if (disable_apic) { 1480 disable_ioapic_support(); 1481 return; 1482 } 1483 1484 #ifdef CONFIG_X86_32 1485 /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1486 if (lapic_is_integrated() && apic->disable_esr) { 1487 apic_write(APIC_ESR, 0); 1488 apic_write(APIC_ESR, 0); 1489 apic_write(APIC_ESR, 0); 1490 apic_write(APIC_ESR, 0); 1491 } 1492 #endif 1493 perf_events_lapic_init(); 1494 1495 /* 1496 * Double-check whether this APIC is really registered. 1497 * This is meaningless in clustered apic mode, so we skip it. 1498 */ 1499 BUG_ON(!apic->apic_id_registered()); 1500 1501 /* 1502 * Intel recommends to set DFR, LDR and TPR before enabling 1503 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1504 * document number 292116). So here it goes... 1505 */ 1506 apic->init_apic_ldr(); 1507 1508 #ifdef CONFIG_X86_32 1509 /* 1510 * APIC LDR is initialized. If logical_apicid mapping was 1511 * initialized during get_smp_config(), make sure it matches the 1512 * actual value. 1513 */ 1514 logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu); 1515 ldr_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 1516 WARN_ON(logical_apicid != BAD_APICID && logical_apicid != ldr_apicid); 1517 /* always use the value from LDR */ 1518 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = ldr_apicid; 1519 #endif 1520 1521 /* 1522 * Set Task Priority to 'accept all'. We never change this 1523 * later on. 1524 */ 1525 value = apic_read(APIC_TASKPRI); 1526 value &= ~APIC_TPRI_MASK; 1527 apic_write(APIC_TASKPRI, value); 1528 1529 apic_pending_intr_clear(); 1530 1531 /* 1532 * Now that we are all set up, enable the APIC 1533 */ 1534 value = apic_read(APIC_SPIV); 1535 value &= ~APIC_VECTOR_MASK; 1536 /* 1537 * Enable APIC 1538 */ 1539 value |= APIC_SPIV_APIC_ENABLED; 1540 1541 #ifdef CONFIG_X86_32 1542 /* 1543 * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1544 * certain networking cards. If high frequency interrupts are 1545 * happening on a particular IOAPIC pin, plus the IOAPIC routing 1546 * entry is masked/unmasked at a high rate as well then sooner or 1547 * later IOAPIC line gets 'stuck', no more interrupts are received 1548 * from the device. If focus CPU is disabled then the hang goes 1549 * away, oh well :-( 1550 * 1551 * [ This bug can be reproduced easily with a level-triggered 1552 * PCI Ne2000 networking cards and PII/PIII processors, dual 1553 * BX chipset. ] 1554 */ 1555 /* 1556 * Actually disabling the focus CPU check just makes the hang less 1557 * frequent as it makes the interrupt distributon model be more 1558 * like LRU than MRU (the short-term load is more even across CPUs). 1559 */ 1560 1561 /* 1562 * - enable focus processor (bit==0) 1563 * - 64bit mode always use processor focus 1564 * so no need to set it 1565 */ 1566 value &= ~APIC_SPIV_FOCUS_DISABLED; 1567 #endif 1568 1569 /* 1570 * Set spurious IRQ vector 1571 */ 1572 value |= SPURIOUS_APIC_VECTOR; 1573 apic_write(APIC_SPIV, value); 1574 1575 /* 1576 * Set up LVT0, LVT1: 1577 * 1578 * set up through-local-APIC on the boot CPU's LINT0. This is not 1579 * strictly necessary in pure symmetric-IO mode, but sometimes 1580 * we delegate interrupts to the 8259A. 1581 */ 1582 /* 1583 * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1584 */ 1585 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 1586 if (!cpu && (pic_mode || !value || skip_ioapic_setup)) { 1587 value = APIC_DM_EXTINT; 1588 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); 1589 } else { 1590 value = APIC_DM_EXTINT | APIC_LVT_MASKED; 1591 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); 1592 } 1593 apic_write(APIC_LVT0, value); 1594 1595 /* 1596 * Only the BSP sees the LINT1 NMI signal by default. This can be 1597 * modified by apic_extnmi= boot option. 1598 */ 1599 if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) || 1600 apic_extnmi == APIC_EXTNMI_ALL) 1601 value = APIC_DM_NMI; 1602 else 1603 value = APIC_DM_NMI | APIC_LVT_MASKED; 1604 1605 /* Is 82489DX ? */ 1606 if (!lapic_is_integrated()) 1607 value |= APIC_LVT_LEVEL_TRIGGER; 1608 apic_write(APIC_LVT1, value); 1609 1610 #ifdef CONFIG_X86_MCE_INTEL 1611 /* Recheck CMCI information after local APIC is up on CPU #0 */ 1612 if (!cpu) 1613 cmci_recheck(); 1614 #endif 1615 } 1616 1617 static void end_local_APIC_setup(void) 1618 { 1619 lapic_setup_esr(); 1620 1621 #ifdef CONFIG_X86_32 1622 { 1623 unsigned int value; 1624 /* Disable the local apic timer */ 1625 value = apic_read(APIC_LVTT); 1626 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1627 apic_write(APIC_LVTT, value); 1628 } 1629 #endif 1630 1631 apic_pm_activate(); 1632 } 1633 1634 /* 1635 * APIC setup function for application processors. Called from smpboot.c 1636 */ 1637 void apic_ap_setup(void) 1638 { 1639 setup_local_APIC(); 1640 end_local_APIC_setup(); 1641 } 1642 1643 #ifdef CONFIG_X86_X2APIC 1644 int x2apic_mode; 1645 1646 enum { 1647 X2APIC_OFF, 1648 X2APIC_ON, 1649 X2APIC_DISABLED, 1650 }; 1651 static int x2apic_state; 1652 1653 static void __x2apic_disable(void) 1654 { 1655 u64 msr; 1656 1657 if (!boot_cpu_has(X86_FEATURE_APIC)) 1658 return; 1659 1660 rdmsrl(MSR_IA32_APICBASE, msr); 1661 if (!(msr & X2APIC_ENABLE)) 1662 return; 1663 /* Disable xapic and x2apic first and then reenable xapic mode */ 1664 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); 1665 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); 1666 printk_once(KERN_INFO "x2apic disabled\n"); 1667 } 1668 1669 static void __x2apic_enable(void) 1670 { 1671 u64 msr; 1672 1673 rdmsrl(MSR_IA32_APICBASE, msr); 1674 if (msr & X2APIC_ENABLE) 1675 return; 1676 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); 1677 printk_once(KERN_INFO "x2apic enabled\n"); 1678 } 1679 1680 static int __init setup_nox2apic(char *str) 1681 { 1682 if (x2apic_enabled()) { 1683 int apicid = native_apic_msr_read(APIC_ID); 1684 1685 if (apicid >= 255) { 1686 pr_warning("Apicid: %08x, cannot enforce nox2apic\n", 1687 apicid); 1688 return 0; 1689 } 1690 pr_warning("x2apic already enabled.\n"); 1691 __x2apic_disable(); 1692 } 1693 setup_clear_cpu_cap(X86_FEATURE_X2APIC); 1694 x2apic_state = X2APIC_DISABLED; 1695 x2apic_mode = 0; 1696 return 0; 1697 } 1698 early_param("nox2apic", setup_nox2apic); 1699 1700 /* Called from cpu_init() to enable x2apic on (secondary) cpus */ 1701 void x2apic_setup(void) 1702 { 1703 /* 1704 * If x2apic is not in ON state, disable it if already enabled 1705 * from BIOS. 1706 */ 1707 if (x2apic_state != X2APIC_ON) { 1708 __x2apic_disable(); 1709 return; 1710 } 1711 __x2apic_enable(); 1712 } 1713 1714 static __init void x2apic_disable(void) 1715 { 1716 u32 x2apic_id, state = x2apic_state; 1717 1718 x2apic_mode = 0; 1719 x2apic_state = X2APIC_DISABLED; 1720 1721 if (state != X2APIC_ON) 1722 return; 1723 1724 x2apic_id = read_apic_id(); 1725 if (x2apic_id >= 255) 1726 panic("Cannot disable x2apic, id: %08x\n", x2apic_id); 1727 1728 __x2apic_disable(); 1729 register_lapic_address(mp_lapic_addr); 1730 } 1731 1732 static __init void x2apic_enable(void) 1733 { 1734 if (x2apic_state != X2APIC_OFF) 1735 return; 1736 1737 x2apic_mode = 1; 1738 x2apic_state = X2APIC_ON; 1739 __x2apic_enable(); 1740 } 1741 1742 static __init void try_to_enable_x2apic(int remap_mode) 1743 { 1744 if (x2apic_state == X2APIC_DISABLED) 1745 return; 1746 1747 if (remap_mode != IRQ_REMAP_X2APIC_MODE) { 1748 /* IR is required if there is APIC ID > 255 even when running 1749 * under KVM 1750 */ 1751 if (max_physical_apicid > 255 || 1752 !x86_init.hyper.x2apic_available()) { 1753 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n"); 1754 x2apic_disable(); 1755 return; 1756 } 1757 1758 /* 1759 * without IR all CPUs can be addressed by IOAPIC/MSI 1760 * only in physical mode 1761 */ 1762 x2apic_phys = 1; 1763 } 1764 x2apic_enable(); 1765 } 1766 1767 void __init check_x2apic(void) 1768 { 1769 if (x2apic_enabled()) { 1770 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n"); 1771 x2apic_mode = 1; 1772 x2apic_state = X2APIC_ON; 1773 } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) { 1774 x2apic_state = X2APIC_DISABLED; 1775 } 1776 } 1777 #else /* CONFIG_X86_X2APIC */ 1778 static int __init validate_x2apic(void) 1779 { 1780 if (!apic_is_x2apic_enabled()) 1781 return 0; 1782 /* 1783 * Checkme: Can we simply turn off x2apic here instead of panic? 1784 */ 1785 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n"); 1786 } 1787 early_initcall(validate_x2apic); 1788 1789 static inline void try_to_enable_x2apic(int remap_mode) { } 1790 static inline void __x2apic_enable(void) { } 1791 #endif /* !CONFIG_X86_X2APIC */ 1792 1793 void __init enable_IR_x2apic(void) 1794 { 1795 unsigned long flags; 1796 int ret, ir_stat; 1797 1798 if (skip_ioapic_setup) { 1799 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n"); 1800 return; 1801 } 1802 1803 ir_stat = irq_remapping_prepare(); 1804 if (ir_stat < 0 && !x2apic_supported()) 1805 return; 1806 1807 ret = save_ioapic_entries(); 1808 if (ret) { 1809 pr_info("Saving IO-APIC state failed: %d\n", ret); 1810 return; 1811 } 1812 1813 local_irq_save(flags); 1814 legacy_pic->mask_all(); 1815 mask_ioapic_entries(); 1816 1817 /* If irq_remapping_prepare() succeeded, try to enable it */ 1818 if (ir_stat >= 0) 1819 ir_stat = irq_remapping_enable(); 1820 /* ir_stat contains the remap mode or an error code */ 1821 try_to_enable_x2apic(ir_stat); 1822 1823 if (ir_stat < 0) 1824 restore_ioapic_entries(); 1825 legacy_pic->restore_mask(); 1826 local_irq_restore(flags); 1827 } 1828 1829 #ifdef CONFIG_X86_64 1830 /* 1831 * Detect and enable local APICs on non-SMP boards. 1832 * Original code written by Keir Fraser. 1833 * On AMD64 we trust the BIOS - if it says no APIC it is likely 1834 * not correctly set up (usually the APIC timer won't work etc.) 1835 */ 1836 static int __init detect_init_APIC(void) 1837 { 1838 if (!boot_cpu_has(X86_FEATURE_APIC)) { 1839 pr_info("No local APIC present\n"); 1840 return -1; 1841 } 1842 1843 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1844 return 0; 1845 } 1846 #else 1847 1848 static int __init apic_verify(void) 1849 { 1850 u32 features, h, l; 1851 1852 /* 1853 * The APIC feature bit should now be enabled 1854 * in `cpuid' 1855 */ 1856 features = cpuid_edx(1); 1857 if (!(features & (1 << X86_FEATURE_APIC))) { 1858 pr_warning("Could not enable APIC!\n"); 1859 return -1; 1860 } 1861 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 1862 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1863 1864 /* The BIOS may have set up the APIC at some other address */ 1865 if (boot_cpu_data.x86 >= 6) { 1866 rdmsr(MSR_IA32_APICBASE, l, h); 1867 if (l & MSR_IA32_APICBASE_ENABLE) 1868 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 1869 } 1870 1871 pr_info("Found and enabled local APIC!\n"); 1872 return 0; 1873 } 1874 1875 int __init apic_force_enable(unsigned long addr) 1876 { 1877 u32 h, l; 1878 1879 if (disable_apic) 1880 return -1; 1881 1882 /* 1883 * Some BIOSes disable the local APIC in the APIC_BASE 1884 * MSR. This can only be done in software for Intel P6 or later 1885 * and AMD K7 (Model > 1) or later. 1886 */ 1887 if (boot_cpu_data.x86 >= 6) { 1888 rdmsr(MSR_IA32_APICBASE, l, h); 1889 if (!(l & MSR_IA32_APICBASE_ENABLE)) { 1890 pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 1891 l &= ~MSR_IA32_APICBASE_BASE; 1892 l |= MSR_IA32_APICBASE_ENABLE | addr; 1893 wrmsr(MSR_IA32_APICBASE, l, h); 1894 enabled_via_apicbase = 1; 1895 } 1896 } 1897 return apic_verify(); 1898 } 1899 1900 /* 1901 * Detect and initialize APIC 1902 */ 1903 static int __init detect_init_APIC(void) 1904 { 1905 /* Disabled by kernel option? */ 1906 if (disable_apic) 1907 return -1; 1908 1909 switch (boot_cpu_data.x86_vendor) { 1910 case X86_VENDOR_AMD: 1911 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 1912 (boot_cpu_data.x86 >= 15)) 1913 break; 1914 goto no_apic; 1915 case X86_VENDOR_INTEL: 1916 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 1917 (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC))) 1918 break; 1919 goto no_apic; 1920 default: 1921 goto no_apic; 1922 } 1923 1924 if (!boot_cpu_has(X86_FEATURE_APIC)) { 1925 /* 1926 * Over-ride BIOS and try to enable the local APIC only if 1927 * "lapic" specified. 1928 */ 1929 if (!force_enable_local_apic) { 1930 pr_info("Local APIC disabled by BIOS -- " 1931 "you can enable it with \"lapic\"\n"); 1932 return -1; 1933 } 1934 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) 1935 return -1; 1936 } else { 1937 if (apic_verify()) 1938 return -1; 1939 } 1940 1941 apic_pm_activate(); 1942 1943 return 0; 1944 1945 no_apic: 1946 pr_info("No local APIC present or hardware disabled\n"); 1947 return -1; 1948 } 1949 #endif 1950 1951 /** 1952 * init_apic_mappings - initialize APIC mappings 1953 */ 1954 void __init init_apic_mappings(void) 1955 { 1956 unsigned int new_apicid; 1957 1958 apic_check_deadline_errata(); 1959 1960 if (x2apic_mode) { 1961 boot_cpu_physical_apicid = read_apic_id(); 1962 return; 1963 } 1964 1965 /* If no local APIC can be found return early */ 1966 if (!smp_found_config && detect_init_APIC()) { 1967 /* lets NOP'ify apic operations */ 1968 pr_info("APIC: disable apic facility\n"); 1969 apic_disable(); 1970 } else { 1971 apic_phys = mp_lapic_addr; 1972 1973 /* 1974 * If the system has ACPI MADT tables or MP info, the LAPIC 1975 * address is already registered. 1976 */ 1977 if (!acpi_lapic && !smp_found_config) 1978 register_lapic_address(apic_phys); 1979 } 1980 1981 /* 1982 * Fetch the APIC ID of the BSP in case we have a 1983 * default configuration (or the MP table is broken). 1984 */ 1985 new_apicid = read_apic_id(); 1986 if (boot_cpu_physical_apicid != new_apicid) { 1987 boot_cpu_physical_apicid = new_apicid; 1988 /* 1989 * yeah -- we lie about apic_version 1990 * in case if apic was disabled via boot option 1991 * but it's not a problem for SMP compiled kernel 1992 * since apic_intr_mode_select is prepared for such 1993 * a case and disable smp mode 1994 */ 1995 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 1996 } 1997 } 1998 1999 void __init register_lapic_address(unsigned long address) 2000 { 2001 mp_lapic_addr = address; 2002 2003 if (!x2apic_mode) { 2004 set_fixmap_nocache(FIX_APIC_BASE, address); 2005 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 2006 APIC_BASE, address); 2007 } 2008 if (boot_cpu_physical_apicid == -1U) { 2009 boot_cpu_physical_apicid = read_apic_id(); 2010 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 2011 } 2012 } 2013 2014 /* 2015 * Local APIC interrupts 2016 */ 2017 2018 /* 2019 * This interrupt should _never_ happen with our APIC/SMP architecture 2020 */ 2021 __visible void __irq_entry smp_spurious_interrupt(struct pt_regs *regs) 2022 { 2023 u8 vector = ~regs->orig_ax; 2024 u32 v; 2025 2026 entering_irq(); 2027 trace_spurious_apic_entry(vector); 2028 2029 /* 2030 * Check if this really is a spurious interrupt and ACK it 2031 * if it is a vectored one. Just in case... 2032 * Spurious interrupts should not be ACKed. 2033 */ 2034 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1)); 2035 if (v & (1 << (vector & 0x1f))) 2036 ack_APIC_irq(); 2037 2038 inc_irq_stat(irq_spurious_count); 2039 2040 /* see sw-dev-man vol 3, chapter 7.4.13.5 */ 2041 pr_info("spurious APIC interrupt through vector %02x on CPU#%d, " 2042 "should never happen.\n", vector, smp_processor_id()); 2043 2044 trace_spurious_apic_exit(vector); 2045 exiting_irq(); 2046 } 2047 2048 /* 2049 * This interrupt should never happen with our APIC/SMP architecture 2050 */ 2051 __visible void __irq_entry smp_error_interrupt(struct pt_regs *regs) 2052 { 2053 static const char * const error_interrupt_reason[] = { 2054 "Send CS error", /* APIC Error Bit 0 */ 2055 "Receive CS error", /* APIC Error Bit 1 */ 2056 "Send accept error", /* APIC Error Bit 2 */ 2057 "Receive accept error", /* APIC Error Bit 3 */ 2058 "Redirectable IPI", /* APIC Error Bit 4 */ 2059 "Send illegal vector", /* APIC Error Bit 5 */ 2060 "Received illegal vector", /* APIC Error Bit 6 */ 2061 "Illegal register address", /* APIC Error Bit 7 */ 2062 }; 2063 u32 v, i = 0; 2064 2065 entering_irq(); 2066 trace_error_apic_entry(ERROR_APIC_VECTOR); 2067 2068 /* First tickle the hardware, only then report what went on. -- REW */ 2069 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */ 2070 apic_write(APIC_ESR, 0); 2071 v = apic_read(APIC_ESR); 2072 ack_APIC_irq(); 2073 atomic_inc(&irq_err_count); 2074 2075 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x", 2076 smp_processor_id(), v); 2077 2078 v &= 0xff; 2079 while (v) { 2080 if (v & 0x1) 2081 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); 2082 i++; 2083 v >>= 1; 2084 } 2085 2086 apic_printk(APIC_DEBUG, KERN_CONT "\n"); 2087 2088 trace_error_apic_exit(ERROR_APIC_VECTOR); 2089 exiting_irq(); 2090 } 2091 2092 /** 2093 * connect_bsp_APIC - attach the APIC to the interrupt system 2094 */ 2095 static void __init connect_bsp_APIC(void) 2096 { 2097 #ifdef CONFIG_X86_32 2098 if (pic_mode) { 2099 /* 2100 * Do not trust the local APIC being empty at bootup. 2101 */ 2102 clear_local_APIC(); 2103 /* 2104 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 2105 * local APIC to INT and NMI lines. 2106 */ 2107 apic_printk(APIC_VERBOSE, "leaving PIC mode, " 2108 "enabling APIC mode.\n"); 2109 imcr_pic_to_apic(); 2110 } 2111 #endif 2112 } 2113 2114 /** 2115 * disconnect_bsp_APIC - detach the APIC from the interrupt system 2116 * @virt_wire_setup: indicates, whether virtual wire mode is selected 2117 * 2118 * Virtual wire mode is necessary to deliver legacy interrupts even when the 2119 * APIC is disabled. 2120 */ 2121 void disconnect_bsp_APIC(int virt_wire_setup) 2122 { 2123 unsigned int value; 2124 2125 #ifdef CONFIG_X86_32 2126 if (pic_mode) { 2127 /* 2128 * Put the board back into PIC mode (has an effect only on 2129 * certain older boards). Note that APIC interrupts, including 2130 * IPIs, won't work beyond this point! The only exception are 2131 * INIT IPIs. 2132 */ 2133 apic_printk(APIC_VERBOSE, "disabling APIC mode, " 2134 "entering PIC mode.\n"); 2135 imcr_apic_to_pic(); 2136 return; 2137 } 2138 #endif 2139 2140 /* Go back to Virtual Wire compatibility mode */ 2141 2142 /* For the spurious interrupt use vector F, and enable it */ 2143 value = apic_read(APIC_SPIV); 2144 value &= ~APIC_VECTOR_MASK; 2145 value |= APIC_SPIV_APIC_ENABLED; 2146 value |= 0xf; 2147 apic_write(APIC_SPIV, value); 2148 2149 if (!virt_wire_setup) { 2150 /* 2151 * For LVT0 make it edge triggered, active high, 2152 * external and enabled 2153 */ 2154 value = apic_read(APIC_LVT0); 2155 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2156 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2157 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2158 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2159 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 2160 apic_write(APIC_LVT0, value); 2161 } else { 2162 /* Disable LVT0 */ 2163 apic_write(APIC_LVT0, APIC_LVT_MASKED); 2164 } 2165 2166 /* 2167 * For LVT1 make it edge triggered, active high, 2168 * nmi and enabled 2169 */ 2170 value = apic_read(APIC_LVT1); 2171 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2172 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2173 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2174 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2175 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 2176 apic_write(APIC_LVT1, value); 2177 } 2178 2179 /* 2180 * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated 2181 * contiguously, it equals to current allocated max logical CPU ID plus 1. 2182 * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range, 2183 * so the maximum of nr_logical_cpuids is nr_cpu_ids. 2184 * 2185 * NOTE: Reserve 0 for BSP. 2186 */ 2187 static int nr_logical_cpuids = 1; 2188 2189 /* 2190 * Used to store mapping between logical CPU IDs and APIC IDs. 2191 */ 2192 static int cpuid_to_apicid[] = { 2193 [0 ... NR_CPUS - 1] = -1, 2194 }; 2195 2196 #ifdef CONFIG_SMP 2197 /** 2198 * apic_id_is_primary_thread - Check whether APIC ID belongs to a primary thread 2199 * @id: APIC ID to check 2200 */ 2201 bool apic_id_is_primary_thread(unsigned int apicid) 2202 { 2203 u32 mask; 2204 2205 if (smp_num_siblings == 1) 2206 return true; 2207 /* Isolate the SMT bit(s) in the APICID and check for 0 */ 2208 mask = (1U << (fls(smp_num_siblings) - 1)) - 1; 2209 return !(apicid & mask); 2210 } 2211 #endif 2212 2213 /* 2214 * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids 2215 * and cpuid_to_apicid[] synchronized. 2216 */ 2217 static int allocate_logical_cpuid(int apicid) 2218 { 2219 int i; 2220 2221 /* 2222 * cpuid <-> apicid mapping is persistent, so when a cpu is up, 2223 * check if the kernel has allocated a cpuid for it. 2224 */ 2225 for (i = 0; i < nr_logical_cpuids; i++) { 2226 if (cpuid_to_apicid[i] == apicid) 2227 return i; 2228 } 2229 2230 /* Allocate a new cpuid. */ 2231 if (nr_logical_cpuids >= nr_cpu_ids) { 2232 WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. " 2233 "Processor %d/0x%x and the rest are ignored.\n", 2234 nr_cpu_ids, nr_logical_cpuids, apicid); 2235 return -EINVAL; 2236 } 2237 2238 cpuid_to_apicid[nr_logical_cpuids] = apicid; 2239 return nr_logical_cpuids++; 2240 } 2241 2242 int generic_processor_info(int apicid, int version) 2243 { 2244 int cpu, max = nr_cpu_ids; 2245 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, 2246 phys_cpu_present_map); 2247 2248 /* 2249 * boot_cpu_physical_apicid is designed to have the apicid 2250 * returned by read_apic_id(), i.e, the apicid of the 2251 * currently booting-up processor. However, on some platforms, 2252 * it is temporarily modified by the apicid reported as BSP 2253 * through MP table. Concretely: 2254 * 2255 * - arch/x86/kernel/mpparse.c: MP_processor_info() 2256 * - arch/x86/mm/amdtopology.c: amd_numa_init() 2257 * 2258 * This function is executed with the modified 2259 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel 2260 * parameter doesn't work to disable APs on kdump 2nd kernel. 2261 * 2262 * Since fixing handling of boot_cpu_physical_apicid requires 2263 * another discussion and tests on each platform, we leave it 2264 * for now and here we use read_apic_id() directly in this 2265 * function, generic_processor_info(). 2266 */ 2267 if (disabled_cpu_apicid != BAD_APICID && 2268 disabled_cpu_apicid != read_apic_id() && 2269 disabled_cpu_apicid == apicid) { 2270 int thiscpu = num_processors + disabled_cpus; 2271 2272 pr_warning("APIC: Disabling requested cpu." 2273 " Processor %d/0x%x ignored.\n", 2274 thiscpu, apicid); 2275 2276 disabled_cpus++; 2277 return -ENODEV; 2278 } 2279 2280 /* 2281 * If boot cpu has not been detected yet, then only allow upto 2282 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu 2283 */ 2284 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && 2285 apicid != boot_cpu_physical_apicid) { 2286 int thiscpu = max + disabled_cpus - 1; 2287 2288 pr_warning( 2289 "APIC: NR_CPUS/possible_cpus limit of %i almost" 2290 " reached. Keeping one slot for boot cpu." 2291 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 2292 2293 disabled_cpus++; 2294 return -ENODEV; 2295 } 2296 2297 if (num_processors >= nr_cpu_ids) { 2298 int thiscpu = max + disabled_cpus; 2299 2300 pr_warning("APIC: NR_CPUS/possible_cpus limit of %i " 2301 "reached. Processor %d/0x%x ignored.\n", 2302 max, thiscpu, apicid); 2303 2304 disabled_cpus++; 2305 return -EINVAL; 2306 } 2307 2308 if (apicid == boot_cpu_physical_apicid) { 2309 /* 2310 * x86_bios_cpu_apicid is required to have processors listed 2311 * in same order as logical cpu numbers. Hence the first 2312 * entry is BSP, and so on. 2313 * boot_cpu_init() already hold bit 0 in cpu_present_mask 2314 * for BSP. 2315 */ 2316 cpu = 0; 2317 2318 /* Logical cpuid 0 is reserved for BSP. */ 2319 cpuid_to_apicid[0] = apicid; 2320 } else { 2321 cpu = allocate_logical_cpuid(apicid); 2322 if (cpu < 0) { 2323 disabled_cpus++; 2324 return -EINVAL; 2325 } 2326 } 2327 2328 /* 2329 * Validate version 2330 */ 2331 if (version == 0x0) { 2332 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", 2333 cpu, apicid); 2334 version = 0x10; 2335 } 2336 2337 if (version != boot_cpu_apic_version) { 2338 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", 2339 boot_cpu_apic_version, cpu, version); 2340 } 2341 2342 if (apicid > max_physical_apicid) 2343 max_physical_apicid = apicid; 2344 2345 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 2346 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 2347 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 2348 #endif 2349 #ifdef CONFIG_X86_32 2350 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 2351 apic->x86_32_early_logical_apicid(cpu); 2352 #endif 2353 set_cpu_possible(cpu, true); 2354 physid_set(apicid, phys_cpu_present_map); 2355 set_cpu_present(cpu, true); 2356 num_processors++; 2357 2358 return cpu; 2359 } 2360 2361 int hard_smp_processor_id(void) 2362 { 2363 return read_apic_id(); 2364 } 2365 2366 /* 2367 * Override the generic EOI implementation with an optimized version. 2368 * Only called during early boot when only one CPU is active and with 2369 * interrupts disabled, so we know this does not race with actual APIC driver 2370 * use. 2371 */ 2372 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) 2373 { 2374 struct apic **drv; 2375 2376 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { 2377 /* Should happen once for each apic */ 2378 WARN_ON((*drv)->eoi_write == eoi_write); 2379 (*drv)->native_eoi_write = (*drv)->eoi_write; 2380 (*drv)->eoi_write = eoi_write; 2381 } 2382 } 2383 2384 static void __init apic_bsp_up_setup(void) 2385 { 2386 #ifdef CONFIG_X86_64 2387 apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid)); 2388 #else 2389 /* 2390 * Hack: In case of kdump, after a crash, kernel might be booting 2391 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 2392 * might be zero if read from MP tables. Get it from LAPIC. 2393 */ 2394 # ifdef CONFIG_CRASH_DUMP 2395 boot_cpu_physical_apicid = read_apic_id(); 2396 # endif 2397 #endif 2398 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 2399 } 2400 2401 /** 2402 * apic_bsp_setup - Setup function for local apic and io-apic 2403 * @upmode: Force UP mode (for APIC_init_uniprocessor) 2404 * 2405 * Returns: 2406 * apic_id of BSP APIC 2407 */ 2408 void __init apic_bsp_setup(bool upmode) 2409 { 2410 connect_bsp_APIC(); 2411 if (upmode) 2412 apic_bsp_up_setup(); 2413 setup_local_APIC(); 2414 2415 enable_IO_APIC(); 2416 end_local_APIC_setup(); 2417 irq_remap_enable_fault_handling(); 2418 setup_IO_APIC(); 2419 } 2420 2421 #ifdef CONFIG_UP_LATE_INIT 2422 void __init up_late_init(void) 2423 { 2424 if (apic_intr_mode == APIC_PIC) 2425 return; 2426 2427 /* Setup local timer */ 2428 x86_init.timers.setup_percpu_clockev(); 2429 } 2430 #endif 2431 2432 /* 2433 * Power management 2434 */ 2435 #ifdef CONFIG_PM 2436 2437 static struct { 2438 /* 2439 * 'active' is true if the local APIC was enabled by us and 2440 * not the BIOS; this signifies that we are also responsible 2441 * for disabling it before entering apm/acpi suspend 2442 */ 2443 int active; 2444 /* r/w apic fields */ 2445 unsigned int apic_id; 2446 unsigned int apic_taskpri; 2447 unsigned int apic_ldr; 2448 unsigned int apic_dfr; 2449 unsigned int apic_spiv; 2450 unsigned int apic_lvtt; 2451 unsigned int apic_lvtpc; 2452 unsigned int apic_lvt0; 2453 unsigned int apic_lvt1; 2454 unsigned int apic_lvterr; 2455 unsigned int apic_tmict; 2456 unsigned int apic_tdcr; 2457 unsigned int apic_thmr; 2458 unsigned int apic_cmci; 2459 } apic_pm_state; 2460 2461 static int lapic_suspend(void) 2462 { 2463 unsigned long flags; 2464 int maxlvt; 2465 2466 if (!apic_pm_state.active) 2467 return 0; 2468 2469 maxlvt = lapic_get_maxlvt(); 2470 2471 apic_pm_state.apic_id = apic_read(APIC_ID); 2472 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 2473 apic_pm_state.apic_ldr = apic_read(APIC_LDR); 2474 apic_pm_state.apic_dfr = apic_read(APIC_DFR); 2475 apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2476 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2477 if (maxlvt >= 4) 2478 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2479 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2480 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2481 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2482 apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2483 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 2484 #ifdef CONFIG_X86_THERMAL_VECTOR 2485 if (maxlvt >= 5) 2486 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2487 #endif 2488 #ifdef CONFIG_X86_MCE_INTEL 2489 if (maxlvt >= 6) 2490 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI); 2491 #endif 2492 2493 local_irq_save(flags); 2494 disable_local_APIC(); 2495 2496 irq_remapping_disable(); 2497 2498 local_irq_restore(flags); 2499 return 0; 2500 } 2501 2502 static void lapic_resume(void) 2503 { 2504 unsigned int l, h; 2505 unsigned long flags; 2506 int maxlvt; 2507 2508 if (!apic_pm_state.active) 2509 return; 2510 2511 local_irq_save(flags); 2512 2513 /* 2514 * IO-APIC and PIC have their own resume routines. 2515 * We just mask them here to make sure the interrupt 2516 * subsystem is completely quiet while we enable x2apic 2517 * and interrupt-remapping. 2518 */ 2519 mask_ioapic_entries(); 2520 legacy_pic->mask_all(); 2521 2522 if (x2apic_mode) { 2523 __x2apic_enable(); 2524 } else { 2525 /* 2526 * Make sure the APICBASE points to the right address 2527 * 2528 * FIXME! This will be wrong if we ever support suspend on 2529 * SMP! We'll need to do this as part of the CPU restore! 2530 */ 2531 if (boot_cpu_data.x86 >= 6) { 2532 rdmsr(MSR_IA32_APICBASE, l, h); 2533 l &= ~MSR_IA32_APICBASE_BASE; 2534 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2535 wrmsr(MSR_IA32_APICBASE, l, h); 2536 } 2537 } 2538 2539 maxlvt = lapic_get_maxlvt(); 2540 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2541 apic_write(APIC_ID, apic_pm_state.apic_id); 2542 apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2543 apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2544 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2545 apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2546 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2547 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 2548 #ifdef CONFIG_X86_THERMAL_VECTOR 2549 if (maxlvt >= 5) 2550 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2551 #endif 2552 #ifdef CONFIG_X86_MCE_INTEL 2553 if (maxlvt >= 6) 2554 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci); 2555 #endif 2556 if (maxlvt >= 4) 2557 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2558 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2559 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2560 apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2561 apic_write(APIC_ESR, 0); 2562 apic_read(APIC_ESR); 2563 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2564 apic_write(APIC_ESR, 0); 2565 apic_read(APIC_ESR); 2566 2567 irq_remapping_reenable(x2apic_mode); 2568 2569 local_irq_restore(flags); 2570 } 2571 2572 /* 2573 * This device has no shutdown method - fully functioning local APICs 2574 * are needed on every CPU up until machine_halt/restart/poweroff. 2575 */ 2576 2577 static struct syscore_ops lapic_syscore_ops = { 2578 .resume = lapic_resume, 2579 .suspend = lapic_suspend, 2580 }; 2581 2582 static void apic_pm_activate(void) 2583 { 2584 apic_pm_state.active = 1; 2585 } 2586 2587 static int __init init_lapic_sysfs(void) 2588 { 2589 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 2590 if (boot_cpu_has(X86_FEATURE_APIC)) 2591 register_syscore_ops(&lapic_syscore_ops); 2592 2593 return 0; 2594 } 2595 2596 /* local apic needs to resume before other devices access its registers. */ 2597 core_initcall(init_lapic_sysfs); 2598 2599 #else /* CONFIG_PM */ 2600 2601 static void apic_pm_activate(void) { } 2602 2603 #endif /* CONFIG_PM */ 2604 2605 #ifdef CONFIG_X86_64 2606 2607 static int multi_checked; 2608 static int multi; 2609 2610 static int set_multi(const struct dmi_system_id *d) 2611 { 2612 if (multi) 2613 return 0; 2614 pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2615 multi = 1; 2616 return 0; 2617 } 2618 2619 static const struct dmi_system_id multi_dmi_table[] = { 2620 { 2621 .callback = set_multi, 2622 .ident = "IBM System Summit2", 2623 .matches = { 2624 DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2625 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2626 }, 2627 }, 2628 {} 2629 }; 2630 2631 static void dmi_check_multi(void) 2632 { 2633 if (multi_checked) 2634 return; 2635 2636 dmi_check_system(multi_dmi_table); 2637 multi_checked = 1; 2638 } 2639 2640 /* 2641 * apic_is_clustered_box() -- Check if we can expect good TSC 2642 * 2643 * Thus far, the major user of this is IBM's Summit2 series: 2644 * Clustered boxes may have unsynced TSC problems if they are 2645 * multi-chassis. 2646 * Use DMI to check them 2647 */ 2648 int apic_is_clustered_box(void) 2649 { 2650 dmi_check_multi(); 2651 return multi; 2652 } 2653 #endif 2654 2655 /* 2656 * APIC command line parameters 2657 */ 2658 static int __init setup_disableapic(char *arg) 2659 { 2660 disable_apic = 1; 2661 setup_clear_cpu_cap(X86_FEATURE_APIC); 2662 return 0; 2663 } 2664 early_param("disableapic", setup_disableapic); 2665 2666 /* same as disableapic, for compatibility */ 2667 static int __init setup_nolapic(char *arg) 2668 { 2669 return setup_disableapic(arg); 2670 } 2671 early_param("nolapic", setup_nolapic); 2672 2673 static int __init parse_lapic_timer_c2_ok(char *arg) 2674 { 2675 local_apic_timer_c2_ok = 1; 2676 return 0; 2677 } 2678 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2679 2680 static int __init parse_disable_apic_timer(char *arg) 2681 { 2682 disable_apic_timer = 1; 2683 return 0; 2684 } 2685 early_param("noapictimer", parse_disable_apic_timer); 2686 2687 static int __init parse_nolapic_timer(char *arg) 2688 { 2689 disable_apic_timer = 1; 2690 return 0; 2691 } 2692 early_param("nolapic_timer", parse_nolapic_timer); 2693 2694 static int __init apic_set_verbosity(char *arg) 2695 { 2696 if (!arg) { 2697 #ifdef CONFIG_X86_64 2698 skip_ioapic_setup = 0; 2699 return 0; 2700 #endif 2701 return -EINVAL; 2702 } 2703 2704 if (strcmp("debug", arg) == 0) 2705 apic_verbosity = APIC_DEBUG; 2706 else if (strcmp("verbose", arg) == 0) 2707 apic_verbosity = APIC_VERBOSE; 2708 #ifdef CONFIG_X86_64 2709 else { 2710 pr_warning("APIC Verbosity level %s not recognised" 2711 " use apic=verbose or apic=debug\n", arg); 2712 return -EINVAL; 2713 } 2714 #endif 2715 2716 return 0; 2717 } 2718 early_param("apic", apic_set_verbosity); 2719 2720 static int __init lapic_insert_resource(void) 2721 { 2722 if (!apic_phys) 2723 return -1; 2724 2725 /* Put local APIC into the resource map. */ 2726 lapic_resource.start = apic_phys; 2727 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2728 insert_resource(&iomem_resource, &lapic_resource); 2729 2730 return 0; 2731 } 2732 2733 /* 2734 * need call insert after e820__reserve_resources() 2735 * that is using request_resource 2736 */ 2737 late_initcall(lapic_insert_resource); 2738 2739 static int __init apic_set_disabled_cpu_apicid(char *arg) 2740 { 2741 if (!arg || !get_option(&arg, &disabled_cpu_apicid)) 2742 return -EINVAL; 2743 2744 return 0; 2745 } 2746 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); 2747 2748 static int __init apic_set_extnmi(char *arg) 2749 { 2750 if (!arg) 2751 return -EINVAL; 2752 2753 if (!strncmp("all", arg, 3)) 2754 apic_extnmi = APIC_EXTNMI_ALL; 2755 else if (!strncmp("none", arg, 4)) 2756 apic_extnmi = APIC_EXTNMI_NONE; 2757 else if (!strncmp("bsp", arg, 3)) 2758 apic_extnmi = APIC_EXTNMI_BSP; 2759 else { 2760 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg); 2761 return -EINVAL; 2762 } 2763 2764 return 0; 2765 } 2766 early_param("apic_extnmi", apic_set_extnmi); 2767