1 /* 2 * Local APIC handling, local APIC timers 3 * 4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 5 * 6 * Fixes 7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 8 * thanks to Eric Gilmore 9 * and Rolf G. Tews 10 * for testing these extensively. 11 * Maciej W. Rozycki : Various updates and fixes. 12 * Mikael Pettersson : Power Management for UP-APIC. 13 * Pavel Machek and 14 * Mikael Pettersson : PM converted to driver model. 15 */ 16 17 #include <linux/perf_event.h> 18 #include <linux/kernel_stat.h> 19 #include <linux/mc146818rtc.h> 20 #include <linux/acpi_pmtmr.h> 21 #include <linux/clockchips.h> 22 #include <linux/interrupt.h> 23 #include <linux/memblock.h> 24 #include <linux/ftrace.h> 25 #include <linux/ioport.h> 26 #include <linux/export.h> 27 #include <linux/syscore_ops.h> 28 #include <linux/delay.h> 29 #include <linux/timex.h> 30 #include <linux/i8253.h> 31 #include <linux/dmar.h> 32 #include <linux/init.h> 33 #include <linux/cpu.h> 34 #include <linux/dmi.h> 35 #include <linux/smp.h> 36 #include <linux/mm.h> 37 38 #include <asm/trace/irq_vectors.h> 39 #include <asm/irq_remapping.h> 40 #include <asm/perf_event.h> 41 #include <asm/x86_init.h> 42 #include <asm/pgalloc.h> 43 #include <linux/atomic.h> 44 #include <asm/mpspec.h> 45 #include <asm/i8259.h> 46 #include <asm/proto.h> 47 #include <asm/traps.h> 48 #include <asm/apic.h> 49 #include <asm/io_apic.h> 50 #include <asm/desc.h> 51 #include <asm/hpet.h> 52 #include <asm/mtrr.h> 53 #include <asm/time.h> 54 #include <asm/smp.h> 55 #include <asm/mce.h> 56 #include <asm/tsc.h> 57 #include <asm/hypervisor.h> 58 #include <asm/cpu_device_id.h> 59 #include <asm/intel-family.h> 60 #include <asm/irq_regs.h> 61 62 unsigned int num_processors; 63 64 unsigned disabled_cpus; 65 66 /* Processor that is doing the boot up */ 67 unsigned int boot_cpu_physical_apicid = -1U; 68 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); 69 70 u8 boot_cpu_apic_version; 71 72 /* 73 * The highest APIC ID seen during enumeration. 74 */ 75 static unsigned int max_physical_apicid; 76 77 /* 78 * Bitmask of physically existing CPUs: 79 */ 80 physid_mask_t phys_cpu_present_map; 81 82 /* 83 * Processor to be disabled specified by kernel parameter 84 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to 85 * avoid undefined behaviour caused by sending INIT from AP to BSP. 86 */ 87 static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID; 88 89 /* 90 * This variable controls which CPUs receive external NMIs. By default, 91 * external NMIs are delivered only to the BSP. 92 */ 93 static int apic_extnmi = APIC_EXTNMI_BSP; 94 95 /* 96 * Map cpu index to physical APIC ID 97 */ 98 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); 99 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID); 100 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX); 101 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 102 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 103 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid); 104 105 #ifdef CONFIG_X86_32 106 107 /* 108 * On x86_32, the mapping between cpu and logical apicid may vary 109 * depending on apic in use. The following early percpu variable is 110 * used for the mapping. This is where the behaviors of x86_64 and 32 111 * actually diverge. Let's keep it ugly for now. 112 */ 113 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID); 114 115 /* Local APIC was disabled by the BIOS and enabled by the kernel */ 116 static int enabled_via_apicbase; 117 118 /* 119 * Handle interrupt mode configuration register (IMCR). 120 * This register controls whether the interrupt signals 121 * that reach the BSP come from the master PIC or from the 122 * local APIC. Before entering Symmetric I/O Mode, either 123 * the BIOS or the operating system must switch out of 124 * PIC Mode by changing the IMCR. 125 */ 126 static inline void imcr_pic_to_apic(void) 127 { 128 /* select IMCR register */ 129 outb(0x70, 0x22); 130 /* NMI and 8259 INTR go through APIC */ 131 outb(0x01, 0x23); 132 } 133 134 static inline void imcr_apic_to_pic(void) 135 { 136 /* select IMCR register */ 137 outb(0x70, 0x22); 138 /* NMI and 8259 INTR go directly to BSP */ 139 outb(0x00, 0x23); 140 } 141 #endif 142 143 /* 144 * Knob to control our willingness to enable the local APIC. 145 * 146 * +1=force-enable 147 */ 148 static int force_enable_local_apic __initdata; 149 150 /* 151 * APIC command line parameters 152 */ 153 static int __init parse_lapic(char *arg) 154 { 155 if (IS_ENABLED(CONFIG_X86_32) && !arg) 156 force_enable_local_apic = 1; 157 else if (arg && !strncmp(arg, "notscdeadline", 13)) 158 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 159 return 0; 160 } 161 early_param("lapic", parse_lapic); 162 163 #ifdef CONFIG_X86_64 164 static int apic_calibrate_pmtmr __initdata; 165 static __init int setup_apicpmtimer(char *s) 166 { 167 apic_calibrate_pmtmr = 1; 168 notsc_setup(NULL); 169 return 0; 170 } 171 __setup("apicpmtimer", setup_apicpmtimer); 172 #endif 173 174 unsigned long mp_lapic_addr; 175 int disable_apic; 176 /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 177 static int disable_apic_timer __initdata; 178 /* Local APIC timer works in C2 */ 179 int local_apic_timer_c2_ok; 180 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 181 182 /* 183 * Debug level, exported for io_apic.c 184 */ 185 unsigned int apic_verbosity; 186 187 int pic_mode; 188 189 /* Have we found an MP table */ 190 int smp_found_config; 191 192 static struct resource lapic_resource = { 193 .name = "Local APIC", 194 .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 195 }; 196 197 unsigned int lapic_timer_frequency = 0; 198 199 static void apic_pm_activate(void); 200 201 static unsigned long apic_phys; 202 203 /* 204 * Get the LAPIC version 205 */ 206 static inline int lapic_get_version(void) 207 { 208 return GET_APIC_VERSION(apic_read(APIC_LVR)); 209 } 210 211 /* 212 * Check, if the APIC is integrated or a separate chip 213 */ 214 static inline int lapic_is_integrated(void) 215 { 216 return APIC_INTEGRATED(lapic_get_version()); 217 } 218 219 /* 220 * Check, whether this is a modern or a first generation APIC 221 */ 222 static int modern_apic(void) 223 { 224 /* AMD systems use old APIC versions, so check the CPU */ 225 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 226 boot_cpu_data.x86 >= 0xf) 227 return 1; 228 229 /* Hygon systems use modern APIC */ 230 if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 231 return 1; 232 233 return lapic_get_version() >= 0x14; 234 } 235 236 /* 237 * right after this call apic become NOOP driven 238 * so apic->write/read doesn't do anything 239 */ 240 static void __init apic_disable(void) 241 { 242 pr_info("APIC: switched to apic NOOP\n"); 243 apic = &apic_noop; 244 } 245 246 void native_apic_wait_icr_idle(void) 247 { 248 while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 249 cpu_relax(); 250 } 251 252 u32 native_safe_apic_wait_icr_idle(void) 253 { 254 u32 send_status; 255 int timeout; 256 257 timeout = 0; 258 do { 259 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 260 if (!send_status) 261 break; 262 inc_irq_stat(icr_read_retry_count); 263 udelay(100); 264 } while (timeout++ < 1000); 265 266 return send_status; 267 } 268 269 void native_apic_icr_write(u32 low, u32 id) 270 { 271 unsigned long flags; 272 273 local_irq_save(flags); 274 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 275 apic_write(APIC_ICR, low); 276 local_irq_restore(flags); 277 } 278 279 u64 native_apic_icr_read(void) 280 { 281 u32 icr1, icr2; 282 283 icr2 = apic_read(APIC_ICR2); 284 icr1 = apic_read(APIC_ICR); 285 286 return icr1 | ((u64)icr2 << 32); 287 } 288 289 #ifdef CONFIG_X86_32 290 /** 291 * get_physical_broadcast - Get number of physical broadcast IDs 292 */ 293 int get_physical_broadcast(void) 294 { 295 return modern_apic() ? 0xff : 0xf; 296 } 297 #endif 298 299 /** 300 * lapic_get_maxlvt - get the maximum number of local vector table entries 301 */ 302 int lapic_get_maxlvt(void) 303 { 304 /* 305 * - we always have APIC integrated on 64bit mode 306 * - 82489DXs do not report # of LVT entries 307 */ 308 return lapic_is_integrated() ? GET_APIC_MAXLVT(apic_read(APIC_LVR)) : 2; 309 } 310 311 /* 312 * Local APIC timer 313 */ 314 315 /* Clock divisor */ 316 #define APIC_DIVISOR 16 317 #define TSC_DIVISOR 8 318 319 /* 320 * This function sets up the local APIC timer, with a timeout of 321 * 'clocks' APIC bus clock. During calibration we actually call 322 * this function twice on the boot CPU, once with a bogus timeout 323 * value, second time for real. The other (noncalibrating) CPUs 324 * call this function only once, with the real, calibrated value. 325 * 326 * We do reads before writes even if unnecessary, to get around the 327 * P5 APIC double write bug. 328 */ 329 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 330 { 331 unsigned int lvtt_value, tmp_value; 332 333 lvtt_value = LOCAL_TIMER_VECTOR; 334 if (!oneshot) 335 lvtt_value |= APIC_LVT_TIMER_PERIODIC; 336 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 337 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE; 338 339 if (!lapic_is_integrated()) 340 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 341 342 if (!irqen) 343 lvtt_value |= APIC_LVT_MASKED; 344 345 apic_write(APIC_LVTT, lvtt_value); 346 347 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { 348 /* 349 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, 350 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized. 351 * According to Intel, MFENCE can do the serialization here. 352 */ 353 asm volatile("mfence" : : : "memory"); 354 355 printk_once(KERN_DEBUG "TSC deadline timer enabled\n"); 356 return; 357 } 358 359 /* 360 * Divide PICLK by 16 361 */ 362 tmp_value = apic_read(APIC_TDCR); 363 apic_write(APIC_TDCR, 364 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 365 APIC_TDR_DIV_16); 366 367 if (!oneshot) 368 apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 369 } 370 371 /* 372 * Setup extended LVT, AMD specific 373 * 374 * Software should use the LVT offsets the BIOS provides. The offsets 375 * are determined by the subsystems using it like those for MCE 376 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts 377 * are supported. Beginning with family 10h at least 4 offsets are 378 * available. 379 * 380 * Since the offsets must be consistent for all cores, we keep track 381 * of the LVT offsets in software and reserve the offset for the same 382 * vector also to be used on other cores. An offset is freed by 383 * setting the entry to APIC_EILVT_MASKED. 384 * 385 * If the BIOS is right, there should be no conflicts. Otherwise a 386 * "[Firmware Bug]: ..." error message is generated. However, if 387 * software does not properly determines the offsets, it is not 388 * necessarily a BIOS bug. 389 */ 390 391 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; 392 393 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) 394 { 395 return (old & APIC_EILVT_MASKED) 396 || (new == APIC_EILVT_MASKED) 397 || ((new & ~APIC_EILVT_MASKED) == old); 398 } 399 400 static unsigned int reserve_eilvt_offset(int offset, unsigned int new) 401 { 402 unsigned int rsvd, vector; 403 404 if (offset >= APIC_EILVT_NR_MAX) 405 return ~0; 406 407 rsvd = atomic_read(&eilvt_offsets[offset]); 408 do { 409 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ 410 if (vector && !eilvt_entry_is_changeable(vector, new)) 411 /* may not change if vectors are different */ 412 return rsvd; 413 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); 414 } while (rsvd != new); 415 416 rsvd &= ~APIC_EILVT_MASKED; 417 if (rsvd && rsvd != vector) 418 pr_info("LVT offset %d assigned for vector 0x%02x\n", 419 offset, rsvd); 420 421 return new; 422 } 423 424 /* 425 * If mask=1, the LVT entry does not generate interrupts while mask=0 426 * enables the vector. See also the BKDGs. Must be called with 427 * preemption disabled. 428 */ 429 430 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) 431 { 432 unsigned long reg = APIC_EILVTn(offset); 433 unsigned int new, old, reserved; 434 435 new = (mask << 16) | (msg_type << 8) | vector; 436 old = apic_read(reg); 437 reserved = reserve_eilvt_offset(offset, new); 438 439 if (reserved != new) { 440 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 441 "vector 0x%x, but the register is already in use for " 442 "vector 0x%x on another cpu\n", 443 smp_processor_id(), reg, offset, new, reserved); 444 return -EINVAL; 445 } 446 447 if (!eilvt_entry_is_changeable(old, new)) { 448 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 449 "vector 0x%x, but the register is already in use for " 450 "vector 0x%x on this cpu\n", 451 smp_processor_id(), reg, offset, new, old); 452 return -EBUSY; 453 } 454 455 apic_write(reg, new); 456 457 return 0; 458 } 459 EXPORT_SYMBOL_GPL(setup_APIC_eilvt); 460 461 /* 462 * Program the next event, relative to now 463 */ 464 static int lapic_next_event(unsigned long delta, 465 struct clock_event_device *evt) 466 { 467 apic_write(APIC_TMICT, delta); 468 return 0; 469 } 470 471 static int lapic_next_deadline(unsigned long delta, 472 struct clock_event_device *evt) 473 { 474 u64 tsc; 475 476 tsc = rdtsc(); 477 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); 478 return 0; 479 } 480 481 static int lapic_timer_shutdown(struct clock_event_device *evt) 482 { 483 unsigned int v; 484 485 /* Lapic used as dummy for broadcast ? */ 486 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 487 return 0; 488 489 v = apic_read(APIC_LVTT); 490 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 491 apic_write(APIC_LVTT, v); 492 apic_write(APIC_TMICT, 0); 493 return 0; 494 } 495 496 static inline int 497 lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot) 498 { 499 /* Lapic used as dummy for broadcast ? */ 500 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 501 return 0; 502 503 __setup_APIC_LVTT(lapic_timer_frequency, oneshot, 1); 504 return 0; 505 } 506 507 static int lapic_timer_set_periodic(struct clock_event_device *evt) 508 { 509 return lapic_timer_set_periodic_oneshot(evt, false); 510 } 511 512 static int lapic_timer_set_oneshot(struct clock_event_device *evt) 513 { 514 return lapic_timer_set_periodic_oneshot(evt, true); 515 } 516 517 /* 518 * Local APIC timer broadcast function 519 */ 520 static void lapic_timer_broadcast(const struct cpumask *mask) 521 { 522 #ifdef CONFIG_SMP 523 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 524 #endif 525 } 526 527 528 /* 529 * The local apic timer can be used for any function which is CPU local. 530 */ 531 static struct clock_event_device lapic_clockevent = { 532 .name = "lapic", 533 .features = CLOCK_EVT_FEAT_PERIODIC | 534 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP 535 | CLOCK_EVT_FEAT_DUMMY, 536 .shift = 32, 537 .set_state_shutdown = lapic_timer_shutdown, 538 .set_state_periodic = lapic_timer_set_periodic, 539 .set_state_oneshot = lapic_timer_set_oneshot, 540 .set_state_oneshot_stopped = lapic_timer_shutdown, 541 .set_next_event = lapic_next_event, 542 .broadcast = lapic_timer_broadcast, 543 .rating = 100, 544 .irq = -1, 545 }; 546 static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 547 548 #define DEADLINE_MODEL_MATCH_FUNC(model, func) \ 549 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&func } 550 551 #define DEADLINE_MODEL_MATCH_REV(model, rev) \ 552 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)rev } 553 554 static u32 hsx_deadline_rev(void) 555 { 556 switch (boot_cpu_data.x86_stepping) { 557 case 0x02: return 0x3a; /* EP */ 558 case 0x04: return 0x0f; /* EX */ 559 } 560 561 return ~0U; 562 } 563 564 static u32 bdx_deadline_rev(void) 565 { 566 switch (boot_cpu_data.x86_stepping) { 567 case 0x02: return 0x00000011; 568 case 0x03: return 0x0700000e; 569 case 0x04: return 0x0f00000c; 570 case 0x05: return 0x0e000003; 571 } 572 573 return ~0U; 574 } 575 576 static u32 skx_deadline_rev(void) 577 { 578 switch (boot_cpu_data.x86_stepping) { 579 case 0x03: return 0x01000136; 580 case 0x04: return 0x02000014; 581 } 582 583 if (boot_cpu_data.x86_stepping > 4) 584 return 0; 585 586 return ~0U; 587 } 588 589 static const struct x86_cpu_id deadline_match[] = { 590 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_HASWELL_X, hsx_deadline_rev), 591 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_X, 0x0b000020), 592 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_BROADWELL_XEON_D, bdx_deadline_rev), 593 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_SKYLAKE_X, skx_deadline_rev), 594 595 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_CORE, 0x22), 596 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_ULT, 0x20), 597 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_GT3E, 0x17), 598 599 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_CORE, 0x25), 600 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_GT3E, 0x17), 601 602 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_MOBILE, 0xb2), 603 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_DESKTOP, 0xb2), 604 605 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_MOBILE, 0x52), 606 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_DESKTOP, 0x52), 607 608 {}, 609 }; 610 611 static void apic_check_deadline_errata(void) 612 { 613 const struct x86_cpu_id *m; 614 u32 rev; 615 616 if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER) || 617 boot_cpu_has(X86_FEATURE_HYPERVISOR)) 618 return; 619 620 m = x86_match_cpu(deadline_match); 621 if (!m) 622 return; 623 624 /* 625 * Function pointers will have the MSB set due to address layout, 626 * immediate revisions will not. 627 */ 628 if ((long)m->driver_data < 0) 629 rev = ((u32 (*)(void))(m->driver_data))(); 630 else 631 rev = (u32)m->driver_data; 632 633 if (boot_cpu_data.microcode >= rev) 634 return; 635 636 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 637 pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; " 638 "please update microcode to version: 0x%x (or later)\n", rev); 639 } 640 641 /* 642 * Setup the local APIC timer for this CPU. Copy the initialized values 643 * of the boot CPU and register the clock event in the framework. 644 */ 645 static void setup_APIC_timer(void) 646 { 647 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 648 649 if (this_cpu_has(X86_FEATURE_ARAT)) { 650 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 651 /* Make LAPIC timer preferrable over percpu HPET */ 652 lapic_clockevent.rating = 150; 653 } 654 655 memcpy(levt, &lapic_clockevent, sizeof(*levt)); 656 levt->cpumask = cpumask_of(smp_processor_id()); 657 658 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 659 levt->name = "lapic-deadline"; 660 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | 661 CLOCK_EVT_FEAT_DUMMY); 662 levt->set_next_event = lapic_next_deadline; 663 clockevents_config_and_register(levt, 664 tsc_khz * (1000 / TSC_DIVISOR), 665 0xF, ~0UL); 666 } else 667 clockevents_register_device(levt); 668 } 669 670 /* 671 * Install the updated TSC frequency from recalibration at the TSC 672 * deadline clockevent devices. 673 */ 674 static void __lapic_update_tsc_freq(void *info) 675 { 676 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 677 678 if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 679 return; 680 681 clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR)); 682 } 683 684 void lapic_update_tsc_freq(void) 685 { 686 /* 687 * The clockevent device's ->mult and ->shift can both be 688 * changed. In order to avoid races, schedule the frequency 689 * update code on each CPU. 690 */ 691 on_each_cpu(__lapic_update_tsc_freq, NULL, 0); 692 } 693 694 /* 695 * In this functions we calibrate APIC bus clocks to the external timer. 696 * 697 * We want to do the calibration only once since we want to have local timer 698 * irqs syncron. CPUs connected by the same APIC bus have the very same bus 699 * frequency. 700 * 701 * This was previously done by reading the PIT/HPET and waiting for a wrap 702 * around to find out, that a tick has elapsed. I have a box, where the PIT 703 * readout is broken, so it never gets out of the wait loop again. This was 704 * also reported by others. 705 * 706 * Monitoring the jiffies value is inaccurate and the clockevents 707 * infrastructure allows us to do a simple substitution of the interrupt 708 * handler. 709 * 710 * The calibration routine also uses the pm_timer when possible, as the PIT 711 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 712 * back to normal later in the boot process). 713 */ 714 715 #define LAPIC_CAL_LOOPS (HZ/10) 716 717 static __initdata int lapic_cal_loops = -1; 718 static __initdata long lapic_cal_t1, lapic_cal_t2; 719 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 720 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 721 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 722 723 /* 724 * Temporary interrupt handler. 725 */ 726 static void __init lapic_cal_handler(struct clock_event_device *dev) 727 { 728 unsigned long long tsc = 0; 729 long tapic = apic_read(APIC_TMCCT); 730 unsigned long pm = acpi_pm_read_early(); 731 732 if (boot_cpu_has(X86_FEATURE_TSC)) 733 tsc = rdtsc(); 734 735 switch (lapic_cal_loops++) { 736 case 0: 737 lapic_cal_t1 = tapic; 738 lapic_cal_tsc1 = tsc; 739 lapic_cal_pm1 = pm; 740 lapic_cal_j1 = jiffies; 741 break; 742 743 case LAPIC_CAL_LOOPS: 744 lapic_cal_t2 = tapic; 745 lapic_cal_tsc2 = tsc; 746 if (pm < lapic_cal_pm1) 747 pm += ACPI_PM_OVRRUN; 748 lapic_cal_pm2 = pm; 749 lapic_cal_j2 = jiffies; 750 break; 751 } 752 } 753 754 static int __init 755 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 756 { 757 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 758 const long pm_thresh = pm_100ms / 100; 759 unsigned long mult; 760 u64 res; 761 762 #ifndef CONFIG_X86_PM_TIMER 763 return -1; 764 #endif 765 766 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 767 768 /* Check, if the PM timer is available */ 769 if (!deltapm) 770 return -1; 771 772 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 773 774 if (deltapm > (pm_100ms - pm_thresh) && 775 deltapm < (pm_100ms + pm_thresh)) { 776 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 777 return 0; 778 } 779 780 res = (((u64)deltapm) * mult) >> 22; 781 do_div(res, 1000000); 782 pr_warning("APIC calibration not consistent " 783 "with PM-Timer: %ldms instead of 100ms\n",(long)res); 784 785 /* Correct the lapic counter value */ 786 res = (((u64)(*delta)) * pm_100ms); 787 do_div(res, deltapm); 788 pr_info("APIC delta adjusted to PM-Timer: " 789 "%lu (%ld)\n", (unsigned long)res, *delta); 790 *delta = (long)res; 791 792 /* Correct the tsc counter value */ 793 if (boot_cpu_has(X86_FEATURE_TSC)) { 794 res = (((u64)(*deltatsc)) * pm_100ms); 795 do_div(res, deltapm); 796 apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 797 "PM-Timer: %lu (%ld)\n", 798 (unsigned long)res, *deltatsc); 799 *deltatsc = (long)res; 800 } 801 802 return 0; 803 } 804 805 static int __init lapic_init_clockevent(void) 806 { 807 if (!lapic_timer_frequency) 808 return -1; 809 810 /* Calculate the scaled math multiplication factor */ 811 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR, 812 TICK_NSEC, lapic_clockevent.shift); 813 lapic_clockevent.max_delta_ns = 814 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); 815 lapic_clockevent.max_delta_ticks = 0x7FFFFFFF; 816 lapic_clockevent.min_delta_ns = 817 clockevent_delta2ns(0xF, &lapic_clockevent); 818 lapic_clockevent.min_delta_ticks = 0xF; 819 820 return 0; 821 } 822 823 static int __init calibrate_APIC_clock(void) 824 { 825 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 826 void (*real_handler)(struct clock_event_device *dev); 827 unsigned long deltaj; 828 long delta, deltatsc; 829 int pm_referenced = 0; 830 831 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 832 return 0; 833 834 /* 835 * Check if lapic timer has already been calibrated by platform 836 * specific routine, such as tsc calibration code. If so just fill 837 * in the clockevent structure and return. 838 */ 839 if (!lapic_init_clockevent()) { 840 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", 841 lapic_timer_frequency); 842 /* 843 * Direct calibration methods must have an always running 844 * local APIC timer, no need for broadcast timer. 845 */ 846 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 847 return 0; 848 } 849 850 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 851 "calibrating APIC timer ...\n"); 852 853 local_irq_disable(); 854 855 /* Replace the global interrupt handler */ 856 real_handler = global_clock_event->event_handler; 857 global_clock_event->event_handler = lapic_cal_handler; 858 859 /* 860 * Setup the APIC counter to maximum. There is no way the lapic 861 * can underflow in the 100ms detection time frame 862 */ 863 __setup_APIC_LVTT(0xffffffff, 0, 0); 864 865 /* Let the interrupts run */ 866 local_irq_enable(); 867 868 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 869 cpu_relax(); 870 871 local_irq_disable(); 872 873 /* Restore the real event handler */ 874 global_clock_event->event_handler = real_handler; 875 876 /* Build delta t1-t2 as apic timer counts down */ 877 delta = lapic_cal_t1 - lapic_cal_t2; 878 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 879 880 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 881 882 /* we trust the PM based calibration if possible */ 883 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 884 &delta, &deltatsc); 885 886 lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 887 lapic_init_clockevent(); 888 889 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 890 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); 891 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 892 lapic_timer_frequency); 893 894 if (boot_cpu_has(X86_FEATURE_TSC)) { 895 apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 896 "%ld.%04ld MHz.\n", 897 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 898 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 899 } 900 901 apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 902 "%u.%04u MHz.\n", 903 lapic_timer_frequency / (1000000 / HZ), 904 lapic_timer_frequency % (1000000 / HZ)); 905 906 /* 907 * Do a sanity check on the APIC calibration result 908 */ 909 if (lapic_timer_frequency < (1000000 / HZ)) { 910 local_irq_enable(); 911 pr_warning("APIC frequency too slow, disabling apic timer\n"); 912 return -1; 913 } 914 915 levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 916 917 /* 918 * PM timer calibration failed or not turned on 919 * so lets try APIC timer based calibration 920 */ 921 if (!pm_referenced) { 922 apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 923 924 /* 925 * Setup the apic timer manually 926 */ 927 levt->event_handler = lapic_cal_handler; 928 lapic_timer_set_periodic(levt); 929 lapic_cal_loops = -1; 930 931 /* Let the interrupts run */ 932 local_irq_enable(); 933 934 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 935 cpu_relax(); 936 937 /* Stop the lapic timer */ 938 local_irq_disable(); 939 lapic_timer_shutdown(levt); 940 941 /* Jiffies delta */ 942 deltaj = lapic_cal_j2 - lapic_cal_j1; 943 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 944 945 /* Check, if the jiffies result is consistent */ 946 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 947 apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 948 else 949 levt->features |= CLOCK_EVT_FEAT_DUMMY; 950 } 951 local_irq_enable(); 952 953 if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 954 pr_warning("APIC timer disabled due to verification failure\n"); 955 return -1; 956 } 957 958 return 0; 959 } 960 961 /* 962 * Setup the boot APIC 963 * 964 * Calibrate and verify the result. 965 */ 966 void __init setup_boot_APIC_clock(void) 967 { 968 /* 969 * The local apic timer can be disabled via the kernel 970 * commandline or from the CPU detection code. Register the lapic 971 * timer as a dummy clock event source on SMP systems, so the 972 * broadcast mechanism is used. On UP systems simply ignore it. 973 */ 974 if (disable_apic_timer) { 975 pr_info("Disabling APIC timer\n"); 976 /* No broadcast on UP ! */ 977 if (num_possible_cpus() > 1) { 978 lapic_clockevent.mult = 1; 979 setup_APIC_timer(); 980 } 981 return; 982 } 983 984 if (calibrate_APIC_clock()) { 985 /* No broadcast on UP ! */ 986 if (num_possible_cpus() > 1) 987 setup_APIC_timer(); 988 return; 989 } 990 991 /* 992 * If nmi_watchdog is set to IO_APIC, we need the 993 * PIT/HPET going. Otherwise register lapic as a dummy 994 * device. 995 */ 996 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 997 998 /* Setup the lapic or request the broadcast */ 999 setup_APIC_timer(); 1000 amd_e400_c1e_apic_setup(); 1001 } 1002 1003 void setup_secondary_APIC_clock(void) 1004 { 1005 setup_APIC_timer(); 1006 amd_e400_c1e_apic_setup(); 1007 } 1008 1009 /* 1010 * The guts of the apic timer interrupt 1011 */ 1012 static void local_apic_timer_interrupt(void) 1013 { 1014 struct clock_event_device *evt = this_cpu_ptr(&lapic_events); 1015 1016 /* 1017 * Normally we should not be here till LAPIC has been initialized but 1018 * in some cases like kdump, its possible that there is a pending LAPIC 1019 * timer interrupt from previous kernel's context and is delivered in 1020 * new kernel the moment interrupts are enabled. 1021 * 1022 * Interrupts are enabled early and LAPIC is setup much later, hence 1023 * its possible that when we get here evt->event_handler is NULL. 1024 * Check for event_handler being NULL and discard the interrupt as 1025 * spurious. 1026 */ 1027 if (!evt->event_handler) { 1028 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", 1029 smp_processor_id()); 1030 /* Switch it off */ 1031 lapic_timer_shutdown(evt); 1032 return; 1033 } 1034 1035 /* 1036 * the NMI deadlock-detector uses this. 1037 */ 1038 inc_irq_stat(apic_timer_irqs); 1039 1040 evt->event_handler(evt); 1041 } 1042 1043 /* 1044 * Local APIC timer interrupt. This is the most natural way for doing 1045 * local interrupts, but local timer interrupts can be emulated by 1046 * broadcast interrupts too. [in case the hw doesn't support APIC timers] 1047 * 1048 * [ if a single-CPU system runs an SMP kernel then we call the local 1049 * interrupt as well. Thus we cannot inline the local irq ... ] 1050 */ 1051 __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) 1052 { 1053 struct pt_regs *old_regs = set_irq_regs(regs); 1054 1055 /* 1056 * NOTE! We'd better ACK the irq immediately, 1057 * because timer handling can be slow. 1058 * 1059 * update_process_times() expects us to have done irq_enter(). 1060 * Besides, if we don't timer interrupts ignore the global 1061 * interrupt lock, which is the WrongThing (tm) to do. 1062 */ 1063 entering_ack_irq(); 1064 trace_local_timer_entry(LOCAL_TIMER_VECTOR); 1065 local_apic_timer_interrupt(); 1066 trace_local_timer_exit(LOCAL_TIMER_VECTOR); 1067 exiting_irq(); 1068 1069 set_irq_regs(old_regs); 1070 } 1071 1072 int setup_profiling_timer(unsigned int multiplier) 1073 { 1074 return -EINVAL; 1075 } 1076 1077 /* 1078 * Local APIC start and shutdown 1079 */ 1080 1081 /** 1082 * clear_local_APIC - shutdown the local APIC 1083 * 1084 * This is called, when a CPU is disabled and before rebooting, so the state of 1085 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 1086 * leftovers during boot. 1087 */ 1088 void clear_local_APIC(void) 1089 { 1090 int maxlvt; 1091 u32 v; 1092 1093 /* APIC hasn't been mapped yet */ 1094 if (!x2apic_mode && !apic_phys) 1095 return; 1096 1097 maxlvt = lapic_get_maxlvt(); 1098 /* 1099 * Masking an LVT entry can trigger a local APIC error 1100 * if the vector is zero. Mask LVTERR first to prevent this. 1101 */ 1102 if (maxlvt >= 3) { 1103 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 1104 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 1105 } 1106 /* 1107 * Careful: we have to set masks only first to deassert 1108 * any level-triggered sources. 1109 */ 1110 v = apic_read(APIC_LVTT); 1111 apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 1112 v = apic_read(APIC_LVT0); 1113 apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 1114 v = apic_read(APIC_LVT1); 1115 apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 1116 if (maxlvt >= 4) { 1117 v = apic_read(APIC_LVTPC); 1118 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 1119 } 1120 1121 /* lets not touch this if we didn't frob it */ 1122 #ifdef CONFIG_X86_THERMAL_VECTOR 1123 if (maxlvt >= 5) { 1124 v = apic_read(APIC_LVTTHMR); 1125 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 1126 } 1127 #endif 1128 #ifdef CONFIG_X86_MCE_INTEL 1129 if (maxlvt >= 6) { 1130 v = apic_read(APIC_LVTCMCI); 1131 if (!(v & APIC_LVT_MASKED)) 1132 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 1133 } 1134 #endif 1135 1136 /* 1137 * Clean APIC state for other OSs: 1138 */ 1139 apic_write(APIC_LVTT, APIC_LVT_MASKED); 1140 apic_write(APIC_LVT0, APIC_LVT_MASKED); 1141 apic_write(APIC_LVT1, APIC_LVT_MASKED); 1142 if (maxlvt >= 3) 1143 apic_write(APIC_LVTERR, APIC_LVT_MASKED); 1144 if (maxlvt >= 4) 1145 apic_write(APIC_LVTPC, APIC_LVT_MASKED); 1146 1147 /* Integrated APIC (!82489DX) ? */ 1148 if (lapic_is_integrated()) { 1149 if (maxlvt > 3) 1150 /* Clear ESR due to Pentium errata 3AP and 11AP */ 1151 apic_write(APIC_ESR, 0); 1152 apic_read(APIC_ESR); 1153 } 1154 } 1155 1156 /** 1157 * disable_local_APIC - clear and disable the local APIC 1158 */ 1159 void disable_local_APIC(void) 1160 { 1161 unsigned int value; 1162 1163 /* APIC hasn't been mapped yet */ 1164 if (!x2apic_mode && !apic_phys) 1165 return; 1166 1167 clear_local_APIC(); 1168 1169 /* 1170 * Disable APIC (implies clearing of registers 1171 * for 82489DX!). 1172 */ 1173 value = apic_read(APIC_SPIV); 1174 value &= ~APIC_SPIV_APIC_ENABLED; 1175 apic_write(APIC_SPIV, value); 1176 1177 #ifdef CONFIG_X86_32 1178 /* 1179 * When LAPIC was disabled by the BIOS and enabled by the kernel, 1180 * restore the disabled state. 1181 */ 1182 if (enabled_via_apicbase) { 1183 unsigned int l, h; 1184 1185 rdmsr(MSR_IA32_APICBASE, l, h); 1186 l &= ~MSR_IA32_APICBASE_ENABLE; 1187 wrmsr(MSR_IA32_APICBASE, l, h); 1188 } 1189 #endif 1190 } 1191 1192 /* 1193 * If Linux enabled the LAPIC against the BIOS default disable it down before 1194 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 1195 * not power-off. Additionally clear all LVT entries before disable_local_APIC 1196 * for the case where Linux didn't enable the LAPIC. 1197 */ 1198 void lapic_shutdown(void) 1199 { 1200 unsigned long flags; 1201 1202 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) 1203 return; 1204 1205 local_irq_save(flags); 1206 1207 #ifdef CONFIG_X86_32 1208 if (!enabled_via_apicbase) 1209 clear_local_APIC(); 1210 else 1211 #endif 1212 disable_local_APIC(); 1213 1214 1215 local_irq_restore(flags); 1216 } 1217 1218 /** 1219 * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1220 */ 1221 void __init sync_Arb_IDs(void) 1222 { 1223 /* 1224 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1225 * needed on AMD. 1226 */ 1227 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1228 return; 1229 1230 /* 1231 * Wait for idle. 1232 */ 1233 apic_wait_icr_idle(); 1234 1235 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1236 apic_write(APIC_ICR, APIC_DEST_ALLINC | 1237 APIC_INT_LEVELTRIG | APIC_DM_INIT); 1238 } 1239 1240 enum apic_intr_mode_id apic_intr_mode; 1241 1242 static int __init apic_intr_mode_select(void) 1243 { 1244 /* Check kernel option */ 1245 if (disable_apic) { 1246 pr_info("APIC disabled via kernel command line\n"); 1247 return APIC_PIC; 1248 } 1249 1250 /* Check BIOS */ 1251 #ifdef CONFIG_X86_64 1252 /* On 64-bit, the APIC must be integrated, Check local APIC only */ 1253 if (!boot_cpu_has(X86_FEATURE_APIC)) { 1254 disable_apic = 1; 1255 pr_info("APIC disabled by BIOS\n"); 1256 return APIC_PIC; 1257 } 1258 #else 1259 /* On 32-bit, the APIC may be integrated APIC or 82489DX */ 1260 1261 /* Neither 82489DX nor integrated APIC ? */ 1262 if (!boot_cpu_has(X86_FEATURE_APIC) && !smp_found_config) { 1263 disable_apic = 1; 1264 return APIC_PIC; 1265 } 1266 1267 /* If the BIOS pretends there is an integrated APIC ? */ 1268 if (!boot_cpu_has(X86_FEATURE_APIC) && 1269 APIC_INTEGRATED(boot_cpu_apic_version)) { 1270 disable_apic = 1; 1271 pr_err(FW_BUG "Local APIC %d not detected, force emulation\n", 1272 boot_cpu_physical_apicid); 1273 return APIC_PIC; 1274 } 1275 #endif 1276 1277 /* Check MP table or ACPI MADT configuration */ 1278 if (!smp_found_config) { 1279 disable_ioapic_support(); 1280 if (!acpi_lapic) { 1281 pr_info("APIC: ACPI MADT or MP tables are not detected\n"); 1282 return APIC_VIRTUAL_WIRE_NO_CONFIG; 1283 } 1284 return APIC_VIRTUAL_WIRE; 1285 } 1286 1287 #ifdef CONFIG_SMP 1288 /* If SMP should be disabled, then really disable it! */ 1289 if (!setup_max_cpus) { 1290 pr_info("APIC: SMP mode deactivated\n"); 1291 return APIC_SYMMETRIC_IO_NO_ROUTING; 1292 } 1293 1294 if (read_apic_id() != boot_cpu_physical_apicid) { 1295 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1296 read_apic_id(), boot_cpu_physical_apicid); 1297 /* Or can we switch back to PIC here? */ 1298 } 1299 #endif 1300 1301 return APIC_SYMMETRIC_IO; 1302 } 1303 1304 /* 1305 * An initial setup of the virtual wire mode. 1306 */ 1307 void __init init_bsp_APIC(void) 1308 { 1309 unsigned int value; 1310 1311 /* 1312 * Don't do the setup now if we have a SMP BIOS as the 1313 * through-I/O-APIC virtual wire mode might be active. 1314 */ 1315 if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC)) 1316 return; 1317 1318 /* 1319 * Do not trust the local APIC being empty at bootup. 1320 */ 1321 clear_local_APIC(); 1322 1323 /* 1324 * Enable APIC. 1325 */ 1326 value = apic_read(APIC_SPIV); 1327 value &= ~APIC_VECTOR_MASK; 1328 value |= APIC_SPIV_APIC_ENABLED; 1329 1330 #ifdef CONFIG_X86_32 1331 /* This bit is reserved on P4/Xeon and should be cleared */ 1332 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1333 (boot_cpu_data.x86 == 15)) 1334 value &= ~APIC_SPIV_FOCUS_DISABLED; 1335 else 1336 #endif 1337 value |= APIC_SPIV_FOCUS_DISABLED; 1338 value |= SPURIOUS_APIC_VECTOR; 1339 apic_write(APIC_SPIV, value); 1340 1341 /* 1342 * Set up the virtual wire mode. 1343 */ 1344 apic_write(APIC_LVT0, APIC_DM_EXTINT); 1345 value = APIC_DM_NMI; 1346 if (!lapic_is_integrated()) /* 82489DX */ 1347 value |= APIC_LVT_LEVEL_TRIGGER; 1348 if (apic_extnmi == APIC_EXTNMI_NONE) 1349 value |= APIC_LVT_MASKED; 1350 apic_write(APIC_LVT1, value); 1351 } 1352 1353 /* Init the interrupt delivery mode for the BSP */ 1354 void __init apic_intr_mode_init(void) 1355 { 1356 bool upmode = IS_ENABLED(CONFIG_UP_LATE_INIT); 1357 1358 apic_intr_mode = apic_intr_mode_select(); 1359 1360 switch (apic_intr_mode) { 1361 case APIC_PIC: 1362 pr_info("APIC: Keep in PIC mode(8259)\n"); 1363 return; 1364 case APIC_VIRTUAL_WIRE: 1365 pr_info("APIC: Switch to virtual wire mode setup\n"); 1366 default_setup_apic_routing(); 1367 break; 1368 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1369 pr_info("APIC: Switch to virtual wire mode setup with no configuration\n"); 1370 upmode = true; 1371 default_setup_apic_routing(); 1372 break; 1373 case APIC_SYMMETRIC_IO: 1374 pr_info("APIC: Switch to symmetric I/O mode setup\n"); 1375 default_setup_apic_routing(); 1376 break; 1377 case APIC_SYMMETRIC_IO_NO_ROUTING: 1378 pr_info("APIC: Switch to symmetric I/O mode setup in no SMP routine\n"); 1379 break; 1380 } 1381 1382 apic_bsp_setup(upmode); 1383 } 1384 1385 static void lapic_setup_esr(void) 1386 { 1387 unsigned int oldvalue, value, maxlvt; 1388 1389 if (!lapic_is_integrated()) { 1390 pr_info("No ESR for 82489DX.\n"); 1391 return; 1392 } 1393 1394 if (apic->disable_esr) { 1395 /* 1396 * Something untraceable is creating bad interrupts on 1397 * secondary quads ... for the moment, just leave the 1398 * ESR disabled - we can't do anything useful with the 1399 * errors anyway - mbligh 1400 */ 1401 pr_info("Leaving ESR disabled.\n"); 1402 return; 1403 } 1404 1405 maxlvt = lapic_get_maxlvt(); 1406 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1407 apic_write(APIC_ESR, 0); 1408 oldvalue = apic_read(APIC_ESR); 1409 1410 /* enables sending errors */ 1411 value = ERROR_APIC_VECTOR; 1412 apic_write(APIC_LVTERR, value); 1413 1414 /* 1415 * spec says clear errors after enabling vector. 1416 */ 1417 if (maxlvt > 3) 1418 apic_write(APIC_ESR, 0); 1419 value = apic_read(APIC_ESR); 1420 if (value != oldvalue) 1421 apic_printk(APIC_VERBOSE, "ESR value before enabling " 1422 "vector: 0x%08x after: 0x%08x\n", 1423 oldvalue, value); 1424 } 1425 1426 static void apic_pending_intr_clear(void) 1427 { 1428 long long max_loops = cpu_khz ? cpu_khz : 1000000; 1429 unsigned long long tsc = 0, ntsc; 1430 unsigned int queued; 1431 unsigned long value; 1432 int i, j, acked = 0; 1433 1434 if (boot_cpu_has(X86_FEATURE_TSC)) 1435 tsc = rdtsc(); 1436 /* 1437 * After a crash, we no longer service the interrupts and a pending 1438 * interrupt from previous kernel might still have ISR bit set. 1439 * 1440 * Most probably by now CPU has serviced that pending interrupt and 1441 * it might not have done the ack_APIC_irq() because it thought, 1442 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it 1443 * does not clear the ISR bit and cpu thinks it has already serivced 1444 * the interrupt. Hence a vector might get locked. It was noticed 1445 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. 1446 */ 1447 do { 1448 queued = 0; 1449 for (i = APIC_ISR_NR - 1; i >= 0; i--) 1450 queued |= apic_read(APIC_IRR + i*0x10); 1451 1452 for (i = APIC_ISR_NR - 1; i >= 0; i--) { 1453 value = apic_read(APIC_ISR + i*0x10); 1454 for_each_set_bit(j, &value, 32) { 1455 ack_APIC_irq(); 1456 acked++; 1457 } 1458 } 1459 if (acked > 256) { 1460 pr_err("LAPIC pending interrupts after %d EOI\n", acked); 1461 break; 1462 } 1463 if (queued) { 1464 if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) { 1465 ntsc = rdtsc(); 1466 max_loops = (cpu_khz << 10) - (ntsc - tsc); 1467 } else { 1468 max_loops--; 1469 } 1470 } 1471 } while (queued && max_loops > 0); 1472 WARN_ON(max_loops <= 0); 1473 } 1474 1475 /** 1476 * setup_local_APIC - setup the local APIC 1477 * 1478 * Used to setup local APIC while initializing BSP or bringing up APs. 1479 * Always called with preemption disabled. 1480 */ 1481 static void setup_local_APIC(void) 1482 { 1483 int cpu = smp_processor_id(); 1484 unsigned int value; 1485 #ifdef CONFIG_X86_32 1486 int logical_apicid, ldr_apicid; 1487 #endif 1488 1489 1490 if (disable_apic) { 1491 disable_ioapic_support(); 1492 return; 1493 } 1494 1495 #ifdef CONFIG_X86_32 1496 /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1497 if (lapic_is_integrated() && apic->disable_esr) { 1498 apic_write(APIC_ESR, 0); 1499 apic_write(APIC_ESR, 0); 1500 apic_write(APIC_ESR, 0); 1501 apic_write(APIC_ESR, 0); 1502 } 1503 #endif 1504 perf_events_lapic_init(); 1505 1506 /* 1507 * Double-check whether this APIC is really registered. 1508 * This is meaningless in clustered apic mode, so we skip it. 1509 */ 1510 BUG_ON(!apic->apic_id_registered()); 1511 1512 /* 1513 * Intel recommends to set DFR, LDR and TPR before enabling 1514 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1515 * document number 292116). So here it goes... 1516 */ 1517 apic->init_apic_ldr(); 1518 1519 #ifdef CONFIG_X86_32 1520 /* 1521 * APIC LDR is initialized. If logical_apicid mapping was 1522 * initialized during get_smp_config(), make sure it matches the 1523 * actual value. 1524 */ 1525 logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu); 1526 ldr_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 1527 WARN_ON(logical_apicid != BAD_APICID && logical_apicid != ldr_apicid); 1528 /* always use the value from LDR */ 1529 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = ldr_apicid; 1530 #endif 1531 1532 /* 1533 * Set Task Priority to 'accept all'. We never change this 1534 * later on. 1535 */ 1536 value = apic_read(APIC_TASKPRI); 1537 value &= ~APIC_TPRI_MASK; 1538 apic_write(APIC_TASKPRI, value); 1539 1540 apic_pending_intr_clear(); 1541 1542 /* 1543 * Now that we are all set up, enable the APIC 1544 */ 1545 value = apic_read(APIC_SPIV); 1546 value &= ~APIC_VECTOR_MASK; 1547 /* 1548 * Enable APIC 1549 */ 1550 value |= APIC_SPIV_APIC_ENABLED; 1551 1552 #ifdef CONFIG_X86_32 1553 /* 1554 * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1555 * certain networking cards. If high frequency interrupts are 1556 * happening on a particular IOAPIC pin, plus the IOAPIC routing 1557 * entry is masked/unmasked at a high rate as well then sooner or 1558 * later IOAPIC line gets 'stuck', no more interrupts are received 1559 * from the device. If focus CPU is disabled then the hang goes 1560 * away, oh well :-( 1561 * 1562 * [ This bug can be reproduced easily with a level-triggered 1563 * PCI Ne2000 networking cards and PII/PIII processors, dual 1564 * BX chipset. ] 1565 */ 1566 /* 1567 * Actually disabling the focus CPU check just makes the hang less 1568 * frequent as it makes the interrupt distributon model be more 1569 * like LRU than MRU (the short-term load is more even across CPUs). 1570 */ 1571 1572 /* 1573 * - enable focus processor (bit==0) 1574 * - 64bit mode always use processor focus 1575 * so no need to set it 1576 */ 1577 value &= ~APIC_SPIV_FOCUS_DISABLED; 1578 #endif 1579 1580 /* 1581 * Set spurious IRQ vector 1582 */ 1583 value |= SPURIOUS_APIC_VECTOR; 1584 apic_write(APIC_SPIV, value); 1585 1586 /* 1587 * Set up LVT0, LVT1: 1588 * 1589 * set up through-local-APIC on the boot CPU's LINT0. This is not 1590 * strictly necessary in pure symmetric-IO mode, but sometimes 1591 * we delegate interrupts to the 8259A. 1592 */ 1593 /* 1594 * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1595 */ 1596 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 1597 if (!cpu && (pic_mode || !value || skip_ioapic_setup)) { 1598 value = APIC_DM_EXTINT; 1599 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); 1600 } else { 1601 value = APIC_DM_EXTINT | APIC_LVT_MASKED; 1602 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); 1603 } 1604 apic_write(APIC_LVT0, value); 1605 1606 /* 1607 * Only the BSP sees the LINT1 NMI signal by default. This can be 1608 * modified by apic_extnmi= boot option. 1609 */ 1610 if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) || 1611 apic_extnmi == APIC_EXTNMI_ALL) 1612 value = APIC_DM_NMI; 1613 else 1614 value = APIC_DM_NMI | APIC_LVT_MASKED; 1615 1616 /* Is 82489DX ? */ 1617 if (!lapic_is_integrated()) 1618 value |= APIC_LVT_LEVEL_TRIGGER; 1619 apic_write(APIC_LVT1, value); 1620 1621 #ifdef CONFIG_X86_MCE_INTEL 1622 /* Recheck CMCI information after local APIC is up on CPU #0 */ 1623 if (!cpu) 1624 cmci_recheck(); 1625 #endif 1626 } 1627 1628 static void end_local_APIC_setup(void) 1629 { 1630 lapic_setup_esr(); 1631 1632 #ifdef CONFIG_X86_32 1633 { 1634 unsigned int value; 1635 /* Disable the local apic timer */ 1636 value = apic_read(APIC_LVTT); 1637 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1638 apic_write(APIC_LVTT, value); 1639 } 1640 #endif 1641 1642 apic_pm_activate(); 1643 } 1644 1645 /* 1646 * APIC setup function for application processors. Called from smpboot.c 1647 */ 1648 void apic_ap_setup(void) 1649 { 1650 setup_local_APIC(); 1651 end_local_APIC_setup(); 1652 } 1653 1654 #ifdef CONFIG_X86_X2APIC 1655 int x2apic_mode; 1656 1657 enum { 1658 X2APIC_OFF, 1659 X2APIC_ON, 1660 X2APIC_DISABLED, 1661 }; 1662 static int x2apic_state; 1663 1664 static void __x2apic_disable(void) 1665 { 1666 u64 msr; 1667 1668 if (!boot_cpu_has(X86_FEATURE_APIC)) 1669 return; 1670 1671 rdmsrl(MSR_IA32_APICBASE, msr); 1672 if (!(msr & X2APIC_ENABLE)) 1673 return; 1674 /* Disable xapic and x2apic first and then reenable xapic mode */ 1675 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); 1676 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); 1677 printk_once(KERN_INFO "x2apic disabled\n"); 1678 } 1679 1680 static void __x2apic_enable(void) 1681 { 1682 u64 msr; 1683 1684 rdmsrl(MSR_IA32_APICBASE, msr); 1685 if (msr & X2APIC_ENABLE) 1686 return; 1687 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); 1688 printk_once(KERN_INFO "x2apic enabled\n"); 1689 } 1690 1691 static int __init setup_nox2apic(char *str) 1692 { 1693 if (x2apic_enabled()) { 1694 int apicid = native_apic_msr_read(APIC_ID); 1695 1696 if (apicid >= 255) { 1697 pr_warning("Apicid: %08x, cannot enforce nox2apic\n", 1698 apicid); 1699 return 0; 1700 } 1701 pr_warning("x2apic already enabled.\n"); 1702 __x2apic_disable(); 1703 } 1704 setup_clear_cpu_cap(X86_FEATURE_X2APIC); 1705 x2apic_state = X2APIC_DISABLED; 1706 x2apic_mode = 0; 1707 return 0; 1708 } 1709 early_param("nox2apic", setup_nox2apic); 1710 1711 /* Called from cpu_init() to enable x2apic on (secondary) cpus */ 1712 void x2apic_setup(void) 1713 { 1714 /* 1715 * If x2apic is not in ON state, disable it if already enabled 1716 * from BIOS. 1717 */ 1718 if (x2apic_state != X2APIC_ON) { 1719 __x2apic_disable(); 1720 return; 1721 } 1722 __x2apic_enable(); 1723 } 1724 1725 static __init void x2apic_disable(void) 1726 { 1727 u32 x2apic_id, state = x2apic_state; 1728 1729 x2apic_mode = 0; 1730 x2apic_state = X2APIC_DISABLED; 1731 1732 if (state != X2APIC_ON) 1733 return; 1734 1735 x2apic_id = read_apic_id(); 1736 if (x2apic_id >= 255) 1737 panic("Cannot disable x2apic, id: %08x\n", x2apic_id); 1738 1739 __x2apic_disable(); 1740 register_lapic_address(mp_lapic_addr); 1741 } 1742 1743 static __init void x2apic_enable(void) 1744 { 1745 if (x2apic_state != X2APIC_OFF) 1746 return; 1747 1748 x2apic_mode = 1; 1749 x2apic_state = X2APIC_ON; 1750 __x2apic_enable(); 1751 } 1752 1753 static __init void try_to_enable_x2apic(int remap_mode) 1754 { 1755 if (x2apic_state == X2APIC_DISABLED) 1756 return; 1757 1758 if (remap_mode != IRQ_REMAP_X2APIC_MODE) { 1759 /* IR is required if there is APIC ID > 255 even when running 1760 * under KVM 1761 */ 1762 if (max_physical_apicid > 255 || 1763 !x86_init.hyper.x2apic_available()) { 1764 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n"); 1765 x2apic_disable(); 1766 return; 1767 } 1768 1769 /* 1770 * without IR all CPUs can be addressed by IOAPIC/MSI 1771 * only in physical mode 1772 */ 1773 x2apic_phys = 1; 1774 } 1775 x2apic_enable(); 1776 } 1777 1778 void __init check_x2apic(void) 1779 { 1780 if (x2apic_enabled()) { 1781 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n"); 1782 x2apic_mode = 1; 1783 x2apic_state = X2APIC_ON; 1784 } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) { 1785 x2apic_state = X2APIC_DISABLED; 1786 } 1787 } 1788 #else /* CONFIG_X86_X2APIC */ 1789 static int __init validate_x2apic(void) 1790 { 1791 if (!apic_is_x2apic_enabled()) 1792 return 0; 1793 /* 1794 * Checkme: Can we simply turn off x2apic here instead of panic? 1795 */ 1796 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n"); 1797 } 1798 early_initcall(validate_x2apic); 1799 1800 static inline void try_to_enable_x2apic(int remap_mode) { } 1801 static inline void __x2apic_enable(void) { } 1802 #endif /* !CONFIG_X86_X2APIC */ 1803 1804 void __init enable_IR_x2apic(void) 1805 { 1806 unsigned long flags; 1807 int ret, ir_stat; 1808 1809 if (skip_ioapic_setup) { 1810 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n"); 1811 return; 1812 } 1813 1814 ir_stat = irq_remapping_prepare(); 1815 if (ir_stat < 0 && !x2apic_supported()) 1816 return; 1817 1818 ret = save_ioapic_entries(); 1819 if (ret) { 1820 pr_info("Saving IO-APIC state failed: %d\n", ret); 1821 return; 1822 } 1823 1824 local_irq_save(flags); 1825 legacy_pic->mask_all(); 1826 mask_ioapic_entries(); 1827 1828 /* If irq_remapping_prepare() succeeded, try to enable it */ 1829 if (ir_stat >= 0) 1830 ir_stat = irq_remapping_enable(); 1831 /* ir_stat contains the remap mode or an error code */ 1832 try_to_enable_x2apic(ir_stat); 1833 1834 if (ir_stat < 0) 1835 restore_ioapic_entries(); 1836 legacy_pic->restore_mask(); 1837 local_irq_restore(flags); 1838 } 1839 1840 #ifdef CONFIG_X86_64 1841 /* 1842 * Detect and enable local APICs on non-SMP boards. 1843 * Original code written by Keir Fraser. 1844 * On AMD64 we trust the BIOS - if it says no APIC it is likely 1845 * not correctly set up (usually the APIC timer won't work etc.) 1846 */ 1847 static int __init detect_init_APIC(void) 1848 { 1849 if (!boot_cpu_has(X86_FEATURE_APIC)) { 1850 pr_info("No local APIC present\n"); 1851 return -1; 1852 } 1853 1854 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1855 return 0; 1856 } 1857 #else 1858 1859 static int __init apic_verify(void) 1860 { 1861 u32 features, h, l; 1862 1863 /* 1864 * The APIC feature bit should now be enabled 1865 * in `cpuid' 1866 */ 1867 features = cpuid_edx(1); 1868 if (!(features & (1 << X86_FEATURE_APIC))) { 1869 pr_warning("Could not enable APIC!\n"); 1870 return -1; 1871 } 1872 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 1873 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1874 1875 /* The BIOS may have set up the APIC at some other address */ 1876 if (boot_cpu_data.x86 >= 6) { 1877 rdmsr(MSR_IA32_APICBASE, l, h); 1878 if (l & MSR_IA32_APICBASE_ENABLE) 1879 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 1880 } 1881 1882 pr_info("Found and enabled local APIC!\n"); 1883 return 0; 1884 } 1885 1886 int __init apic_force_enable(unsigned long addr) 1887 { 1888 u32 h, l; 1889 1890 if (disable_apic) 1891 return -1; 1892 1893 /* 1894 * Some BIOSes disable the local APIC in the APIC_BASE 1895 * MSR. This can only be done in software for Intel P6 or later 1896 * and AMD K7 (Model > 1) or later. 1897 */ 1898 if (boot_cpu_data.x86 >= 6) { 1899 rdmsr(MSR_IA32_APICBASE, l, h); 1900 if (!(l & MSR_IA32_APICBASE_ENABLE)) { 1901 pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 1902 l &= ~MSR_IA32_APICBASE_BASE; 1903 l |= MSR_IA32_APICBASE_ENABLE | addr; 1904 wrmsr(MSR_IA32_APICBASE, l, h); 1905 enabled_via_apicbase = 1; 1906 } 1907 } 1908 return apic_verify(); 1909 } 1910 1911 /* 1912 * Detect and initialize APIC 1913 */ 1914 static int __init detect_init_APIC(void) 1915 { 1916 /* Disabled by kernel option? */ 1917 if (disable_apic) 1918 return -1; 1919 1920 switch (boot_cpu_data.x86_vendor) { 1921 case X86_VENDOR_AMD: 1922 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 1923 (boot_cpu_data.x86 >= 15)) 1924 break; 1925 goto no_apic; 1926 case X86_VENDOR_HYGON: 1927 break; 1928 case X86_VENDOR_INTEL: 1929 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 1930 (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC))) 1931 break; 1932 goto no_apic; 1933 default: 1934 goto no_apic; 1935 } 1936 1937 if (!boot_cpu_has(X86_FEATURE_APIC)) { 1938 /* 1939 * Over-ride BIOS and try to enable the local APIC only if 1940 * "lapic" specified. 1941 */ 1942 if (!force_enable_local_apic) { 1943 pr_info("Local APIC disabled by BIOS -- " 1944 "you can enable it with \"lapic\"\n"); 1945 return -1; 1946 } 1947 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) 1948 return -1; 1949 } else { 1950 if (apic_verify()) 1951 return -1; 1952 } 1953 1954 apic_pm_activate(); 1955 1956 return 0; 1957 1958 no_apic: 1959 pr_info("No local APIC present or hardware disabled\n"); 1960 return -1; 1961 } 1962 #endif 1963 1964 /** 1965 * init_apic_mappings - initialize APIC mappings 1966 */ 1967 void __init init_apic_mappings(void) 1968 { 1969 unsigned int new_apicid; 1970 1971 apic_check_deadline_errata(); 1972 1973 if (x2apic_mode) { 1974 boot_cpu_physical_apicid = read_apic_id(); 1975 return; 1976 } 1977 1978 /* If no local APIC can be found return early */ 1979 if (!smp_found_config && detect_init_APIC()) { 1980 /* lets NOP'ify apic operations */ 1981 pr_info("APIC: disable apic facility\n"); 1982 apic_disable(); 1983 } else { 1984 apic_phys = mp_lapic_addr; 1985 1986 /* 1987 * If the system has ACPI MADT tables or MP info, the LAPIC 1988 * address is already registered. 1989 */ 1990 if (!acpi_lapic && !smp_found_config) 1991 register_lapic_address(apic_phys); 1992 } 1993 1994 /* 1995 * Fetch the APIC ID of the BSP in case we have a 1996 * default configuration (or the MP table is broken). 1997 */ 1998 new_apicid = read_apic_id(); 1999 if (boot_cpu_physical_apicid != new_apicid) { 2000 boot_cpu_physical_apicid = new_apicid; 2001 /* 2002 * yeah -- we lie about apic_version 2003 * in case if apic was disabled via boot option 2004 * but it's not a problem for SMP compiled kernel 2005 * since apic_intr_mode_select is prepared for such 2006 * a case and disable smp mode 2007 */ 2008 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 2009 } 2010 } 2011 2012 void __init register_lapic_address(unsigned long address) 2013 { 2014 mp_lapic_addr = address; 2015 2016 if (!x2apic_mode) { 2017 set_fixmap_nocache(FIX_APIC_BASE, address); 2018 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 2019 APIC_BASE, address); 2020 } 2021 if (boot_cpu_physical_apicid == -1U) { 2022 boot_cpu_physical_apicid = read_apic_id(); 2023 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 2024 } 2025 } 2026 2027 /* 2028 * Local APIC interrupts 2029 */ 2030 2031 /* 2032 * This interrupt should _never_ happen with our APIC/SMP architecture 2033 */ 2034 __visible void __irq_entry smp_spurious_interrupt(struct pt_regs *regs) 2035 { 2036 u8 vector = ~regs->orig_ax; 2037 u32 v; 2038 2039 entering_irq(); 2040 trace_spurious_apic_entry(vector); 2041 2042 /* 2043 * Check if this really is a spurious interrupt and ACK it 2044 * if it is a vectored one. Just in case... 2045 * Spurious interrupts should not be ACKed. 2046 */ 2047 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1)); 2048 if (v & (1 << (vector & 0x1f))) 2049 ack_APIC_irq(); 2050 2051 inc_irq_stat(irq_spurious_count); 2052 2053 /* see sw-dev-man vol 3, chapter 7.4.13.5 */ 2054 pr_info("spurious APIC interrupt through vector %02x on CPU#%d, " 2055 "should never happen.\n", vector, smp_processor_id()); 2056 2057 trace_spurious_apic_exit(vector); 2058 exiting_irq(); 2059 } 2060 2061 /* 2062 * This interrupt should never happen with our APIC/SMP architecture 2063 */ 2064 __visible void __irq_entry smp_error_interrupt(struct pt_regs *regs) 2065 { 2066 static const char * const error_interrupt_reason[] = { 2067 "Send CS error", /* APIC Error Bit 0 */ 2068 "Receive CS error", /* APIC Error Bit 1 */ 2069 "Send accept error", /* APIC Error Bit 2 */ 2070 "Receive accept error", /* APIC Error Bit 3 */ 2071 "Redirectable IPI", /* APIC Error Bit 4 */ 2072 "Send illegal vector", /* APIC Error Bit 5 */ 2073 "Received illegal vector", /* APIC Error Bit 6 */ 2074 "Illegal register address", /* APIC Error Bit 7 */ 2075 }; 2076 u32 v, i = 0; 2077 2078 entering_irq(); 2079 trace_error_apic_entry(ERROR_APIC_VECTOR); 2080 2081 /* First tickle the hardware, only then report what went on. -- REW */ 2082 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */ 2083 apic_write(APIC_ESR, 0); 2084 v = apic_read(APIC_ESR); 2085 ack_APIC_irq(); 2086 atomic_inc(&irq_err_count); 2087 2088 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x", 2089 smp_processor_id(), v); 2090 2091 v &= 0xff; 2092 while (v) { 2093 if (v & 0x1) 2094 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); 2095 i++; 2096 v >>= 1; 2097 } 2098 2099 apic_printk(APIC_DEBUG, KERN_CONT "\n"); 2100 2101 trace_error_apic_exit(ERROR_APIC_VECTOR); 2102 exiting_irq(); 2103 } 2104 2105 /** 2106 * connect_bsp_APIC - attach the APIC to the interrupt system 2107 */ 2108 static void __init connect_bsp_APIC(void) 2109 { 2110 #ifdef CONFIG_X86_32 2111 if (pic_mode) { 2112 /* 2113 * Do not trust the local APIC being empty at bootup. 2114 */ 2115 clear_local_APIC(); 2116 /* 2117 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 2118 * local APIC to INT and NMI lines. 2119 */ 2120 apic_printk(APIC_VERBOSE, "leaving PIC mode, " 2121 "enabling APIC mode.\n"); 2122 imcr_pic_to_apic(); 2123 } 2124 #endif 2125 } 2126 2127 /** 2128 * disconnect_bsp_APIC - detach the APIC from the interrupt system 2129 * @virt_wire_setup: indicates, whether virtual wire mode is selected 2130 * 2131 * Virtual wire mode is necessary to deliver legacy interrupts even when the 2132 * APIC is disabled. 2133 */ 2134 void disconnect_bsp_APIC(int virt_wire_setup) 2135 { 2136 unsigned int value; 2137 2138 #ifdef CONFIG_X86_32 2139 if (pic_mode) { 2140 /* 2141 * Put the board back into PIC mode (has an effect only on 2142 * certain older boards). Note that APIC interrupts, including 2143 * IPIs, won't work beyond this point! The only exception are 2144 * INIT IPIs. 2145 */ 2146 apic_printk(APIC_VERBOSE, "disabling APIC mode, " 2147 "entering PIC mode.\n"); 2148 imcr_apic_to_pic(); 2149 return; 2150 } 2151 #endif 2152 2153 /* Go back to Virtual Wire compatibility mode */ 2154 2155 /* For the spurious interrupt use vector F, and enable it */ 2156 value = apic_read(APIC_SPIV); 2157 value &= ~APIC_VECTOR_MASK; 2158 value |= APIC_SPIV_APIC_ENABLED; 2159 value |= 0xf; 2160 apic_write(APIC_SPIV, value); 2161 2162 if (!virt_wire_setup) { 2163 /* 2164 * For LVT0 make it edge triggered, active high, 2165 * external and enabled 2166 */ 2167 value = apic_read(APIC_LVT0); 2168 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2169 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2170 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2171 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2172 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 2173 apic_write(APIC_LVT0, value); 2174 } else { 2175 /* Disable LVT0 */ 2176 apic_write(APIC_LVT0, APIC_LVT_MASKED); 2177 } 2178 2179 /* 2180 * For LVT1 make it edge triggered, active high, 2181 * nmi and enabled 2182 */ 2183 value = apic_read(APIC_LVT1); 2184 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2185 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2186 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2187 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2188 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 2189 apic_write(APIC_LVT1, value); 2190 } 2191 2192 /* 2193 * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated 2194 * contiguously, it equals to current allocated max logical CPU ID plus 1. 2195 * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range, 2196 * so the maximum of nr_logical_cpuids is nr_cpu_ids. 2197 * 2198 * NOTE: Reserve 0 for BSP. 2199 */ 2200 static int nr_logical_cpuids = 1; 2201 2202 /* 2203 * Used to store mapping between logical CPU IDs and APIC IDs. 2204 */ 2205 static int cpuid_to_apicid[] = { 2206 [0 ... NR_CPUS - 1] = -1, 2207 }; 2208 2209 #ifdef CONFIG_SMP 2210 /** 2211 * apic_id_is_primary_thread - Check whether APIC ID belongs to a primary thread 2212 * @id: APIC ID to check 2213 */ 2214 bool apic_id_is_primary_thread(unsigned int apicid) 2215 { 2216 u32 mask; 2217 2218 if (smp_num_siblings == 1) 2219 return true; 2220 /* Isolate the SMT bit(s) in the APICID and check for 0 */ 2221 mask = (1U << (fls(smp_num_siblings) - 1)) - 1; 2222 return !(apicid & mask); 2223 } 2224 #endif 2225 2226 /* 2227 * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids 2228 * and cpuid_to_apicid[] synchronized. 2229 */ 2230 static int allocate_logical_cpuid(int apicid) 2231 { 2232 int i; 2233 2234 /* 2235 * cpuid <-> apicid mapping is persistent, so when a cpu is up, 2236 * check if the kernel has allocated a cpuid for it. 2237 */ 2238 for (i = 0; i < nr_logical_cpuids; i++) { 2239 if (cpuid_to_apicid[i] == apicid) 2240 return i; 2241 } 2242 2243 /* Allocate a new cpuid. */ 2244 if (nr_logical_cpuids >= nr_cpu_ids) { 2245 WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. " 2246 "Processor %d/0x%x and the rest are ignored.\n", 2247 nr_cpu_ids, nr_logical_cpuids, apicid); 2248 return -EINVAL; 2249 } 2250 2251 cpuid_to_apicid[nr_logical_cpuids] = apicid; 2252 return nr_logical_cpuids++; 2253 } 2254 2255 int generic_processor_info(int apicid, int version) 2256 { 2257 int cpu, max = nr_cpu_ids; 2258 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, 2259 phys_cpu_present_map); 2260 2261 /* 2262 * boot_cpu_physical_apicid is designed to have the apicid 2263 * returned by read_apic_id(), i.e, the apicid of the 2264 * currently booting-up processor. However, on some platforms, 2265 * it is temporarily modified by the apicid reported as BSP 2266 * through MP table. Concretely: 2267 * 2268 * - arch/x86/kernel/mpparse.c: MP_processor_info() 2269 * - arch/x86/mm/amdtopology.c: amd_numa_init() 2270 * 2271 * This function is executed with the modified 2272 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel 2273 * parameter doesn't work to disable APs on kdump 2nd kernel. 2274 * 2275 * Since fixing handling of boot_cpu_physical_apicid requires 2276 * another discussion and tests on each platform, we leave it 2277 * for now and here we use read_apic_id() directly in this 2278 * function, generic_processor_info(). 2279 */ 2280 if (disabled_cpu_apicid != BAD_APICID && 2281 disabled_cpu_apicid != read_apic_id() && 2282 disabled_cpu_apicid == apicid) { 2283 int thiscpu = num_processors + disabled_cpus; 2284 2285 pr_warning("APIC: Disabling requested cpu." 2286 " Processor %d/0x%x ignored.\n", 2287 thiscpu, apicid); 2288 2289 disabled_cpus++; 2290 return -ENODEV; 2291 } 2292 2293 /* 2294 * If boot cpu has not been detected yet, then only allow upto 2295 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu 2296 */ 2297 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && 2298 apicid != boot_cpu_physical_apicid) { 2299 int thiscpu = max + disabled_cpus - 1; 2300 2301 pr_warning( 2302 "APIC: NR_CPUS/possible_cpus limit of %i almost" 2303 " reached. Keeping one slot for boot cpu." 2304 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 2305 2306 disabled_cpus++; 2307 return -ENODEV; 2308 } 2309 2310 if (num_processors >= nr_cpu_ids) { 2311 int thiscpu = max + disabled_cpus; 2312 2313 pr_warning("APIC: NR_CPUS/possible_cpus limit of %i " 2314 "reached. Processor %d/0x%x ignored.\n", 2315 max, thiscpu, apicid); 2316 2317 disabled_cpus++; 2318 return -EINVAL; 2319 } 2320 2321 if (apicid == boot_cpu_physical_apicid) { 2322 /* 2323 * x86_bios_cpu_apicid is required to have processors listed 2324 * in same order as logical cpu numbers. Hence the first 2325 * entry is BSP, and so on. 2326 * boot_cpu_init() already hold bit 0 in cpu_present_mask 2327 * for BSP. 2328 */ 2329 cpu = 0; 2330 2331 /* Logical cpuid 0 is reserved for BSP. */ 2332 cpuid_to_apicid[0] = apicid; 2333 } else { 2334 cpu = allocate_logical_cpuid(apicid); 2335 if (cpu < 0) { 2336 disabled_cpus++; 2337 return -EINVAL; 2338 } 2339 } 2340 2341 /* 2342 * Validate version 2343 */ 2344 if (version == 0x0) { 2345 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", 2346 cpu, apicid); 2347 version = 0x10; 2348 } 2349 2350 if (version != boot_cpu_apic_version) { 2351 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", 2352 boot_cpu_apic_version, cpu, version); 2353 } 2354 2355 if (apicid > max_physical_apicid) 2356 max_physical_apicid = apicid; 2357 2358 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 2359 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 2360 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 2361 #endif 2362 #ifdef CONFIG_X86_32 2363 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 2364 apic->x86_32_early_logical_apicid(cpu); 2365 #endif 2366 set_cpu_possible(cpu, true); 2367 physid_set(apicid, phys_cpu_present_map); 2368 set_cpu_present(cpu, true); 2369 num_processors++; 2370 2371 return cpu; 2372 } 2373 2374 int hard_smp_processor_id(void) 2375 { 2376 return read_apic_id(); 2377 } 2378 2379 /* 2380 * Override the generic EOI implementation with an optimized version. 2381 * Only called during early boot when only one CPU is active and with 2382 * interrupts disabled, so we know this does not race with actual APIC driver 2383 * use. 2384 */ 2385 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) 2386 { 2387 struct apic **drv; 2388 2389 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { 2390 /* Should happen once for each apic */ 2391 WARN_ON((*drv)->eoi_write == eoi_write); 2392 (*drv)->native_eoi_write = (*drv)->eoi_write; 2393 (*drv)->eoi_write = eoi_write; 2394 } 2395 } 2396 2397 static void __init apic_bsp_up_setup(void) 2398 { 2399 #ifdef CONFIG_X86_64 2400 apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid)); 2401 #else 2402 /* 2403 * Hack: In case of kdump, after a crash, kernel might be booting 2404 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 2405 * might be zero if read from MP tables. Get it from LAPIC. 2406 */ 2407 # ifdef CONFIG_CRASH_DUMP 2408 boot_cpu_physical_apicid = read_apic_id(); 2409 # endif 2410 #endif 2411 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 2412 } 2413 2414 /** 2415 * apic_bsp_setup - Setup function for local apic and io-apic 2416 * @upmode: Force UP mode (for APIC_init_uniprocessor) 2417 * 2418 * Returns: 2419 * apic_id of BSP APIC 2420 */ 2421 void __init apic_bsp_setup(bool upmode) 2422 { 2423 connect_bsp_APIC(); 2424 if (upmode) 2425 apic_bsp_up_setup(); 2426 setup_local_APIC(); 2427 2428 enable_IO_APIC(); 2429 end_local_APIC_setup(); 2430 irq_remap_enable_fault_handling(); 2431 setup_IO_APIC(); 2432 } 2433 2434 #ifdef CONFIG_UP_LATE_INIT 2435 void __init up_late_init(void) 2436 { 2437 if (apic_intr_mode == APIC_PIC) 2438 return; 2439 2440 /* Setup local timer */ 2441 x86_init.timers.setup_percpu_clockev(); 2442 } 2443 #endif 2444 2445 /* 2446 * Power management 2447 */ 2448 #ifdef CONFIG_PM 2449 2450 static struct { 2451 /* 2452 * 'active' is true if the local APIC was enabled by us and 2453 * not the BIOS; this signifies that we are also responsible 2454 * for disabling it before entering apm/acpi suspend 2455 */ 2456 int active; 2457 /* r/w apic fields */ 2458 unsigned int apic_id; 2459 unsigned int apic_taskpri; 2460 unsigned int apic_ldr; 2461 unsigned int apic_dfr; 2462 unsigned int apic_spiv; 2463 unsigned int apic_lvtt; 2464 unsigned int apic_lvtpc; 2465 unsigned int apic_lvt0; 2466 unsigned int apic_lvt1; 2467 unsigned int apic_lvterr; 2468 unsigned int apic_tmict; 2469 unsigned int apic_tdcr; 2470 unsigned int apic_thmr; 2471 unsigned int apic_cmci; 2472 } apic_pm_state; 2473 2474 static int lapic_suspend(void) 2475 { 2476 unsigned long flags; 2477 int maxlvt; 2478 2479 if (!apic_pm_state.active) 2480 return 0; 2481 2482 maxlvt = lapic_get_maxlvt(); 2483 2484 apic_pm_state.apic_id = apic_read(APIC_ID); 2485 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 2486 apic_pm_state.apic_ldr = apic_read(APIC_LDR); 2487 apic_pm_state.apic_dfr = apic_read(APIC_DFR); 2488 apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2489 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2490 if (maxlvt >= 4) 2491 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2492 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2493 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2494 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2495 apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2496 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 2497 #ifdef CONFIG_X86_THERMAL_VECTOR 2498 if (maxlvt >= 5) 2499 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2500 #endif 2501 #ifdef CONFIG_X86_MCE_INTEL 2502 if (maxlvt >= 6) 2503 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI); 2504 #endif 2505 2506 local_irq_save(flags); 2507 disable_local_APIC(); 2508 2509 irq_remapping_disable(); 2510 2511 local_irq_restore(flags); 2512 return 0; 2513 } 2514 2515 static void lapic_resume(void) 2516 { 2517 unsigned int l, h; 2518 unsigned long flags; 2519 int maxlvt; 2520 2521 if (!apic_pm_state.active) 2522 return; 2523 2524 local_irq_save(flags); 2525 2526 /* 2527 * IO-APIC and PIC have their own resume routines. 2528 * We just mask them here to make sure the interrupt 2529 * subsystem is completely quiet while we enable x2apic 2530 * and interrupt-remapping. 2531 */ 2532 mask_ioapic_entries(); 2533 legacy_pic->mask_all(); 2534 2535 if (x2apic_mode) { 2536 __x2apic_enable(); 2537 } else { 2538 /* 2539 * Make sure the APICBASE points to the right address 2540 * 2541 * FIXME! This will be wrong if we ever support suspend on 2542 * SMP! We'll need to do this as part of the CPU restore! 2543 */ 2544 if (boot_cpu_data.x86 >= 6) { 2545 rdmsr(MSR_IA32_APICBASE, l, h); 2546 l &= ~MSR_IA32_APICBASE_BASE; 2547 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2548 wrmsr(MSR_IA32_APICBASE, l, h); 2549 } 2550 } 2551 2552 maxlvt = lapic_get_maxlvt(); 2553 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2554 apic_write(APIC_ID, apic_pm_state.apic_id); 2555 apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2556 apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2557 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2558 apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2559 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2560 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 2561 #ifdef CONFIG_X86_THERMAL_VECTOR 2562 if (maxlvt >= 5) 2563 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2564 #endif 2565 #ifdef CONFIG_X86_MCE_INTEL 2566 if (maxlvt >= 6) 2567 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci); 2568 #endif 2569 if (maxlvt >= 4) 2570 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2571 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2572 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2573 apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2574 apic_write(APIC_ESR, 0); 2575 apic_read(APIC_ESR); 2576 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2577 apic_write(APIC_ESR, 0); 2578 apic_read(APIC_ESR); 2579 2580 irq_remapping_reenable(x2apic_mode); 2581 2582 local_irq_restore(flags); 2583 } 2584 2585 /* 2586 * This device has no shutdown method - fully functioning local APICs 2587 * are needed on every CPU up until machine_halt/restart/poweroff. 2588 */ 2589 2590 static struct syscore_ops lapic_syscore_ops = { 2591 .resume = lapic_resume, 2592 .suspend = lapic_suspend, 2593 }; 2594 2595 static void apic_pm_activate(void) 2596 { 2597 apic_pm_state.active = 1; 2598 } 2599 2600 static int __init init_lapic_sysfs(void) 2601 { 2602 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 2603 if (boot_cpu_has(X86_FEATURE_APIC)) 2604 register_syscore_ops(&lapic_syscore_ops); 2605 2606 return 0; 2607 } 2608 2609 /* local apic needs to resume before other devices access its registers. */ 2610 core_initcall(init_lapic_sysfs); 2611 2612 #else /* CONFIG_PM */ 2613 2614 static void apic_pm_activate(void) { } 2615 2616 #endif /* CONFIG_PM */ 2617 2618 #ifdef CONFIG_X86_64 2619 2620 static int multi_checked; 2621 static int multi; 2622 2623 static int set_multi(const struct dmi_system_id *d) 2624 { 2625 if (multi) 2626 return 0; 2627 pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2628 multi = 1; 2629 return 0; 2630 } 2631 2632 static const struct dmi_system_id multi_dmi_table[] = { 2633 { 2634 .callback = set_multi, 2635 .ident = "IBM System Summit2", 2636 .matches = { 2637 DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2638 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2639 }, 2640 }, 2641 {} 2642 }; 2643 2644 static void dmi_check_multi(void) 2645 { 2646 if (multi_checked) 2647 return; 2648 2649 dmi_check_system(multi_dmi_table); 2650 multi_checked = 1; 2651 } 2652 2653 /* 2654 * apic_is_clustered_box() -- Check if we can expect good TSC 2655 * 2656 * Thus far, the major user of this is IBM's Summit2 series: 2657 * Clustered boxes may have unsynced TSC problems if they are 2658 * multi-chassis. 2659 * Use DMI to check them 2660 */ 2661 int apic_is_clustered_box(void) 2662 { 2663 dmi_check_multi(); 2664 return multi; 2665 } 2666 #endif 2667 2668 /* 2669 * APIC command line parameters 2670 */ 2671 static int __init setup_disableapic(char *arg) 2672 { 2673 disable_apic = 1; 2674 setup_clear_cpu_cap(X86_FEATURE_APIC); 2675 return 0; 2676 } 2677 early_param("disableapic", setup_disableapic); 2678 2679 /* same as disableapic, for compatibility */ 2680 static int __init setup_nolapic(char *arg) 2681 { 2682 return setup_disableapic(arg); 2683 } 2684 early_param("nolapic", setup_nolapic); 2685 2686 static int __init parse_lapic_timer_c2_ok(char *arg) 2687 { 2688 local_apic_timer_c2_ok = 1; 2689 return 0; 2690 } 2691 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2692 2693 static int __init parse_disable_apic_timer(char *arg) 2694 { 2695 disable_apic_timer = 1; 2696 return 0; 2697 } 2698 early_param("noapictimer", parse_disable_apic_timer); 2699 2700 static int __init parse_nolapic_timer(char *arg) 2701 { 2702 disable_apic_timer = 1; 2703 return 0; 2704 } 2705 early_param("nolapic_timer", parse_nolapic_timer); 2706 2707 static int __init apic_set_verbosity(char *arg) 2708 { 2709 if (!arg) { 2710 #ifdef CONFIG_X86_64 2711 skip_ioapic_setup = 0; 2712 return 0; 2713 #endif 2714 return -EINVAL; 2715 } 2716 2717 if (strcmp("debug", arg) == 0) 2718 apic_verbosity = APIC_DEBUG; 2719 else if (strcmp("verbose", arg) == 0) 2720 apic_verbosity = APIC_VERBOSE; 2721 #ifdef CONFIG_X86_64 2722 else { 2723 pr_warning("APIC Verbosity level %s not recognised" 2724 " use apic=verbose or apic=debug\n", arg); 2725 return -EINVAL; 2726 } 2727 #endif 2728 2729 return 0; 2730 } 2731 early_param("apic", apic_set_verbosity); 2732 2733 static int __init lapic_insert_resource(void) 2734 { 2735 if (!apic_phys) 2736 return -1; 2737 2738 /* Put local APIC into the resource map. */ 2739 lapic_resource.start = apic_phys; 2740 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2741 insert_resource(&iomem_resource, &lapic_resource); 2742 2743 return 0; 2744 } 2745 2746 /* 2747 * need call insert after e820__reserve_resources() 2748 * that is using request_resource 2749 */ 2750 late_initcall(lapic_insert_resource); 2751 2752 static int __init apic_set_disabled_cpu_apicid(char *arg) 2753 { 2754 if (!arg || !get_option(&arg, &disabled_cpu_apicid)) 2755 return -EINVAL; 2756 2757 return 0; 2758 } 2759 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); 2760 2761 static int __init apic_set_extnmi(char *arg) 2762 { 2763 if (!arg) 2764 return -EINVAL; 2765 2766 if (!strncmp("all", arg, 3)) 2767 apic_extnmi = APIC_EXTNMI_ALL; 2768 else if (!strncmp("none", arg, 4)) 2769 apic_extnmi = APIC_EXTNMI_NONE; 2770 else if (!strncmp("bsp", arg, 3)) 2771 apic_extnmi = APIC_EXTNMI_BSP; 2772 else { 2773 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg); 2774 return -EINVAL; 2775 } 2776 2777 return 0; 2778 } 2779 early_param("apic_extnmi", apic_set_extnmi); 2780