1 /* 2 * Local APIC handling, local APIC timers 3 * 4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 5 * 6 * Fixes 7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 8 * thanks to Eric Gilmore 9 * and Rolf G. Tews 10 * for testing these extensively. 11 * Maciej W. Rozycki : Various updates and fixes. 12 * Mikael Pettersson : Power Management for UP-APIC. 13 * Pavel Machek and 14 * Mikael Pettersson : PM converted to driver model. 15 */ 16 17 #include <linux/kernel_stat.h> 18 #include <linux/mc146818rtc.h> 19 #include <linux/acpi_pmtmr.h> 20 #include <linux/clockchips.h> 21 #include <linux/interrupt.h> 22 #include <linux/bootmem.h> 23 #include <linux/ftrace.h> 24 #include <linux/ioport.h> 25 #include <linux/module.h> 26 #include <linux/sysdev.h> 27 #include <linux/delay.h> 28 #include <linux/timex.h> 29 #include <linux/dmar.h> 30 #include <linux/init.h> 31 #include <linux/cpu.h> 32 #include <linux/dmi.h> 33 #include <linux/nmi.h> 34 #include <linux/smp.h> 35 #include <linux/mm.h> 36 37 #include <asm/pgalloc.h> 38 #include <asm/atomic.h> 39 #include <asm/mpspec.h> 40 #include <asm/i8253.h> 41 #include <asm/i8259.h> 42 #include <asm/proto.h> 43 #include <asm/apic.h> 44 #include <asm/desc.h> 45 #include <asm/hpet.h> 46 #include <asm/idle.h> 47 #include <asm/mtrr.h> 48 #include <asm/smp.h> 49 #include <asm/mce.h> 50 51 unsigned int num_processors; 52 53 unsigned disabled_cpus __cpuinitdata; 54 55 /* Processor that is doing the boot up */ 56 unsigned int boot_cpu_physical_apicid = -1U; 57 58 /* 59 * The highest APIC ID seen during enumeration. 60 * 61 * This determines the messaging protocol we can use: if all APIC IDs 62 * are in the 0 ... 7 range, then we can use logical addressing which 63 * has some performance advantages (better broadcasting). 64 * 65 * If there's an APIC ID above 8, we use physical addressing. 66 */ 67 unsigned int max_physical_apicid; 68 69 /* 70 * Bitmask of physically existing CPUs: 71 */ 72 physid_mask_t phys_cpu_present_map; 73 74 /* 75 * Map cpu index to physical APIC ID 76 */ 77 DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID); 78 DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID); 79 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 80 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 81 82 #ifdef CONFIG_X86_32 83 /* 84 * Knob to control our willingness to enable the local APIC. 85 * 86 * +1=force-enable 87 */ 88 static int force_enable_local_apic; 89 /* 90 * APIC command line parameters 91 */ 92 static int __init parse_lapic(char *arg) 93 { 94 force_enable_local_apic = 1; 95 return 0; 96 } 97 early_param("lapic", parse_lapic); 98 /* Local APIC was disabled by the BIOS and enabled by the kernel */ 99 static int enabled_via_apicbase; 100 101 #endif 102 103 #ifdef CONFIG_X86_64 104 static int apic_calibrate_pmtmr __initdata; 105 static __init int setup_apicpmtimer(char *s) 106 { 107 apic_calibrate_pmtmr = 1; 108 notsc_setup(NULL); 109 return 0; 110 } 111 __setup("apicpmtimer", setup_apicpmtimer); 112 #endif 113 114 #ifdef CONFIG_X86_X2APIC 115 int x2apic; 116 /* x2apic enabled before OS handover */ 117 static int x2apic_preenabled; 118 static int disable_x2apic; 119 static __init int setup_nox2apic(char *str) 120 { 121 disable_x2apic = 1; 122 setup_clear_cpu_cap(X86_FEATURE_X2APIC); 123 return 0; 124 } 125 early_param("nox2apic", setup_nox2apic); 126 #endif 127 128 unsigned long mp_lapic_addr; 129 int disable_apic; 130 /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 131 static int disable_apic_timer __cpuinitdata; 132 /* Local APIC timer works in C2 */ 133 int local_apic_timer_c2_ok; 134 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 135 136 int first_system_vector = 0xfe; 137 138 /* 139 * Debug level, exported for io_apic.c 140 */ 141 unsigned int apic_verbosity; 142 143 int pic_mode; 144 145 /* Have we found an MP table */ 146 int smp_found_config; 147 148 static struct resource lapic_resource = { 149 .name = "Local APIC", 150 .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 151 }; 152 153 static unsigned int calibration_result; 154 155 static int lapic_next_event(unsigned long delta, 156 struct clock_event_device *evt); 157 static void lapic_timer_setup(enum clock_event_mode mode, 158 struct clock_event_device *evt); 159 static void lapic_timer_broadcast(const struct cpumask *mask); 160 static void apic_pm_activate(void); 161 162 /* 163 * The local apic timer can be used for any function which is CPU local. 164 */ 165 static struct clock_event_device lapic_clockevent = { 166 .name = "lapic", 167 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT 168 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, 169 .shift = 32, 170 .set_mode = lapic_timer_setup, 171 .set_next_event = lapic_next_event, 172 .broadcast = lapic_timer_broadcast, 173 .rating = 100, 174 .irq = -1, 175 }; 176 static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 177 178 static unsigned long apic_phys; 179 180 /* 181 * Get the LAPIC version 182 */ 183 static inline int lapic_get_version(void) 184 { 185 return GET_APIC_VERSION(apic_read(APIC_LVR)); 186 } 187 188 /* 189 * Check, if the APIC is integrated or a separate chip 190 */ 191 static inline int lapic_is_integrated(void) 192 { 193 #ifdef CONFIG_X86_64 194 return 1; 195 #else 196 return APIC_INTEGRATED(lapic_get_version()); 197 #endif 198 } 199 200 /* 201 * Check, whether this is a modern or a first generation APIC 202 */ 203 static int modern_apic(void) 204 { 205 /* AMD systems use old APIC versions, so check the CPU */ 206 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 207 boot_cpu_data.x86 >= 0xf) 208 return 1; 209 return lapic_get_version() >= 0x14; 210 } 211 212 void native_apic_wait_icr_idle(void) 213 { 214 while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 215 cpu_relax(); 216 } 217 218 u32 native_safe_apic_wait_icr_idle(void) 219 { 220 u32 send_status; 221 int timeout; 222 223 timeout = 0; 224 do { 225 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 226 if (!send_status) 227 break; 228 udelay(100); 229 } while (timeout++ < 1000); 230 231 return send_status; 232 } 233 234 void native_apic_icr_write(u32 low, u32 id) 235 { 236 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 237 apic_write(APIC_ICR, low); 238 } 239 240 u64 native_apic_icr_read(void) 241 { 242 u32 icr1, icr2; 243 244 icr2 = apic_read(APIC_ICR2); 245 icr1 = apic_read(APIC_ICR); 246 247 return icr1 | ((u64)icr2 << 32); 248 } 249 250 /** 251 * enable_NMI_through_LVT0 - enable NMI through local vector table 0 252 */ 253 void __cpuinit enable_NMI_through_LVT0(void) 254 { 255 unsigned int v; 256 257 /* unmask and set to NMI */ 258 v = APIC_DM_NMI; 259 260 /* Level triggered for 82489DX (32bit mode) */ 261 if (!lapic_is_integrated()) 262 v |= APIC_LVT_LEVEL_TRIGGER; 263 264 apic_write(APIC_LVT0, v); 265 } 266 267 #ifdef CONFIG_X86_32 268 /** 269 * get_physical_broadcast - Get number of physical broadcast IDs 270 */ 271 int get_physical_broadcast(void) 272 { 273 return modern_apic() ? 0xff : 0xf; 274 } 275 #endif 276 277 /** 278 * lapic_get_maxlvt - get the maximum number of local vector table entries 279 */ 280 int lapic_get_maxlvt(void) 281 { 282 unsigned int v; 283 284 v = apic_read(APIC_LVR); 285 /* 286 * - we always have APIC integrated on 64bit mode 287 * - 82489DXs do not report # of LVT entries 288 */ 289 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; 290 } 291 292 /* 293 * Local APIC timer 294 */ 295 296 /* Clock divisor */ 297 #define APIC_DIVISOR 16 298 299 /* 300 * This function sets up the local APIC timer, with a timeout of 301 * 'clocks' APIC bus clock. During calibration we actually call 302 * this function twice on the boot CPU, once with a bogus timeout 303 * value, second time for real. The other (noncalibrating) CPUs 304 * call this function only once, with the real, calibrated value. 305 * 306 * We do reads before writes even if unnecessary, to get around the 307 * P5 APIC double write bug. 308 */ 309 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 310 { 311 unsigned int lvtt_value, tmp_value; 312 313 lvtt_value = LOCAL_TIMER_VECTOR; 314 if (!oneshot) 315 lvtt_value |= APIC_LVT_TIMER_PERIODIC; 316 if (!lapic_is_integrated()) 317 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 318 319 if (!irqen) 320 lvtt_value |= APIC_LVT_MASKED; 321 322 apic_write(APIC_LVTT, lvtt_value); 323 324 /* 325 * Divide PICLK by 16 326 */ 327 tmp_value = apic_read(APIC_TDCR); 328 apic_write(APIC_TDCR, 329 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 330 APIC_TDR_DIV_16); 331 332 if (!oneshot) 333 apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 334 } 335 336 /* 337 * Setup extended LVT, AMD specific (K8, family 10h) 338 * 339 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and 340 * MCE interrupts are supported. Thus MCE offset must be set to 0. 341 * 342 * If mask=1, the LVT entry does not generate interrupts while mask=0 343 * enables the vector. See also the BKDGs. 344 */ 345 346 #define APIC_EILVT_LVTOFF_MCE 0 347 #define APIC_EILVT_LVTOFF_IBS 1 348 349 static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) 350 { 351 unsigned long reg = (lvt_off << 4) + APIC_EILVT0; 352 unsigned int v = (mask << 16) | (msg_type << 8) | vector; 353 354 apic_write(reg, v); 355 } 356 357 u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) 358 { 359 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); 360 return APIC_EILVT_LVTOFF_MCE; 361 } 362 363 u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) 364 { 365 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); 366 return APIC_EILVT_LVTOFF_IBS; 367 } 368 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs); 369 370 /* 371 * Program the next event, relative to now 372 */ 373 static int lapic_next_event(unsigned long delta, 374 struct clock_event_device *evt) 375 { 376 apic_write(APIC_TMICT, delta); 377 return 0; 378 } 379 380 /* 381 * Setup the lapic timer in periodic or oneshot mode 382 */ 383 static void lapic_timer_setup(enum clock_event_mode mode, 384 struct clock_event_device *evt) 385 { 386 unsigned long flags; 387 unsigned int v; 388 389 /* Lapic used as dummy for broadcast ? */ 390 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 391 return; 392 393 local_irq_save(flags); 394 395 switch (mode) { 396 case CLOCK_EVT_MODE_PERIODIC: 397 case CLOCK_EVT_MODE_ONESHOT: 398 __setup_APIC_LVTT(calibration_result, 399 mode != CLOCK_EVT_MODE_PERIODIC, 1); 400 break; 401 case CLOCK_EVT_MODE_UNUSED: 402 case CLOCK_EVT_MODE_SHUTDOWN: 403 v = apic_read(APIC_LVTT); 404 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 405 apic_write(APIC_LVTT, v); 406 apic_write(APIC_TMICT, 0xffffffff); 407 break; 408 case CLOCK_EVT_MODE_RESUME: 409 /* Nothing to do here */ 410 break; 411 } 412 413 local_irq_restore(flags); 414 } 415 416 /* 417 * Local APIC timer broadcast function 418 */ 419 static void lapic_timer_broadcast(const struct cpumask *mask) 420 { 421 #ifdef CONFIG_SMP 422 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 423 #endif 424 } 425 426 /* 427 * Setup the local APIC timer for this CPU. Copy the initilized values 428 * of the boot CPU and register the clock event in the framework. 429 */ 430 static void __cpuinit setup_APIC_timer(void) 431 { 432 struct clock_event_device *levt = &__get_cpu_var(lapic_events); 433 434 if (cpu_has(¤t_cpu_data, X86_FEATURE_ARAT)) { 435 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 436 /* Make LAPIC timer preferrable over percpu HPET */ 437 lapic_clockevent.rating = 150; 438 } 439 440 memcpy(levt, &lapic_clockevent, sizeof(*levt)); 441 levt->cpumask = cpumask_of(smp_processor_id()); 442 443 clockevents_register_device(levt); 444 } 445 446 /* 447 * In this functions we calibrate APIC bus clocks to the external timer. 448 * 449 * We want to do the calibration only once since we want to have local timer 450 * irqs syncron. CPUs connected by the same APIC bus have the very same bus 451 * frequency. 452 * 453 * This was previously done by reading the PIT/HPET and waiting for a wrap 454 * around to find out, that a tick has elapsed. I have a box, where the PIT 455 * readout is broken, so it never gets out of the wait loop again. This was 456 * also reported by others. 457 * 458 * Monitoring the jiffies value is inaccurate and the clockevents 459 * infrastructure allows us to do a simple substitution of the interrupt 460 * handler. 461 * 462 * The calibration routine also uses the pm_timer when possible, as the PIT 463 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 464 * back to normal later in the boot process). 465 */ 466 467 #define LAPIC_CAL_LOOPS (HZ/10) 468 469 static __initdata int lapic_cal_loops = -1; 470 static __initdata long lapic_cal_t1, lapic_cal_t2; 471 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 472 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 473 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 474 475 /* 476 * Temporary interrupt handler. 477 */ 478 static void __init lapic_cal_handler(struct clock_event_device *dev) 479 { 480 unsigned long long tsc = 0; 481 long tapic = apic_read(APIC_TMCCT); 482 unsigned long pm = acpi_pm_read_early(); 483 484 if (cpu_has_tsc) 485 rdtscll(tsc); 486 487 switch (lapic_cal_loops++) { 488 case 0: 489 lapic_cal_t1 = tapic; 490 lapic_cal_tsc1 = tsc; 491 lapic_cal_pm1 = pm; 492 lapic_cal_j1 = jiffies; 493 break; 494 495 case LAPIC_CAL_LOOPS: 496 lapic_cal_t2 = tapic; 497 lapic_cal_tsc2 = tsc; 498 if (pm < lapic_cal_pm1) 499 pm += ACPI_PM_OVRRUN; 500 lapic_cal_pm2 = pm; 501 lapic_cal_j2 = jiffies; 502 break; 503 } 504 } 505 506 static int __init 507 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 508 { 509 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 510 const long pm_thresh = pm_100ms / 100; 511 unsigned long mult; 512 u64 res; 513 514 #ifndef CONFIG_X86_PM_TIMER 515 return -1; 516 #endif 517 518 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 519 520 /* Check, if the PM timer is available */ 521 if (!deltapm) 522 return -1; 523 524 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 525 526 if (deltapm > (pm_100ms - pm_thresh) && 527 deltapm < (pm_100ms + pm_thresh)) { 528 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 529 return 0; 530 } 531 532 res = (((u64)deltapm) * mult) >> 22; 533 do_div(res, 1000000); 534 pr_warning("APIC calibration not consistent " 535 "with PM-Timer: %ldms instead of 100ms\n",(long)res); 536 537 /* Correct the lapic counter value */ 538 res = (((u64)(*delta)) * pm_100ms); 539 do_div(res, deltapm); 540 pr_info("APIC delta adjusted to PM-Timer: " 541 "%lu (%ld)\n", (unsigned long)res, *delta); 542 *delta = (long)res; 543 544 /* Correct the tsc counter value */ 545 if (cpu_has_tsc) { 546 res = (((u64)(*deltatsc)) * pm_100ms); 547 do_div(res, deltapm); 548 apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 549 "PM-Timer: %lu (%ld) \n", 550 (unsigned long)res, *deltatsc); 551 *deltatsc = (long)res; 552 } 553 554 return 0; 555 } 556 557 static int __init calibrate_APIC_clock(void) 558 { 559 struct clock_event_device *levt = &__get_cpu_var(lapic_events); 560 void (*real_handler)(struct clock_event_device *dev); 561 unsigned long deltaj; 562 long delta, deltatsc; 563 int pm_referenced = 0; 564 565 local_irq_disable(); 566 567 /* Replace the global interrupt handler */ 568 real_handler = global_clock_event->event_handler; 569 global_clock_event->event_handler = lapic_cal_handler; 570 571 /* 572 * Setup the APIC counter to maximum. There is no way the lapic 573 * can underflow in the 100ms detection time frame 574 */ 575 __setup_APIC_LVTT(0xffffffff, 0, 0); 576 577 /* Let the interrupts run */ 578 local_irq_enable(); 579 580 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 581 cpu_relax(); 582 583 local_irq_disable(); 584 585 /* Restore the real event handler */ 586 global_clock_event->event_handler = real_handler; 587 588 /* Build delta t1-t2 as apic timer counts down */ 589 delta = lapic_cal_t1 - lapic_cal_t2; 590 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 591 592 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 593 594 /* we trust the PM based calibration if possible */ 595 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 596 &delta, &deltatsc); 597 598 /* Calculate the scaled math multiplication factor */ 599 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 600 lapic_clockevent.shift); 601 lapic_clockevent.max_delta_ns = 602 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); 603 lapic_clockevent.min_delta_ns = 604 clockevent_delta2ns(0xF, &lapic_clockevent); 605 606 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 607 608 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 609 apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult); 610 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 611 calibration_result); 612 613 if (cpu_has_tsc) { 614 apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 615 "%ld.%04ld MHz.\n", 616 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 617 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 618 } 619 620 apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 621 "%u.%04u MHz.\n", 622 calibration_result / (1000000 / HZ), 623 calibration_result % (1000000 / HZ)); 624 625 /* 626 * Do a sanity check on the APIC calibration result 627 */ 628 if (calibration_result < (1000000 / HZ)) { 629 local_irq_enable(); 630 pr_warning("APIC frequency too slow, disabling apic timer\n"); 631 return -1; 632 } 633 634 levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 635 636 /* 637 * PM timer calibration failed or not turned on 638 * so lets try APIC timer based calibration 639 */ 640 if (!pm_referenced) { 641 apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 642 643 /* 644 * Setup the apic timer manually 645 */ 646 levt->event_handler = lapic_cal_handler; 647 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); 648 lapic_cal_loops = -1; 649 650 /* Let the interrupts run */ 651 local_irq_enable(); 652 653 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 654 cpu_relax(); 655 656 /* Stop the lapic timer */ 657 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); 658 659 /* Jiffies delta */ 660 deltaj = lapic_cal_j2 - lapic_cal_j1; 661 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 662 663 /* Check, if the jiffies result is consistent */ 664 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 665 apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 666 else 667 levt->features |= CLOCK_EVT_FEAT_DUMMY; 668 } else 669 local_irq_enable(); 670 671 if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 672 pr_warning("APIC timer disabled due to verification failure\n"); 673 return -1; 674 } 675 676 return 0; 677 } 678 679 /* 680 * Setup the boot APIC 681 * 682 * Calibrate and verify the result. 683 */ 684 void __init setup_boot_APIC_clock(void) 685 { 686 /* 687 * The local apic timer can be disabled via the kernel 688 * commandline or from the CPU detection code. Register the lapic 689 * timer as a dummy clock event source on SMP systems, so the 690 * broadcast mechanism is used. On UP systems simply ignore it. 691 */ 692 if (disable_apic_timer) { 693 pr_info("Disabling APIC timer\n"); 694 /* No broadcast on UP ! */ 695 if (num_possible_cpus() > 1) { 696 lapic_clockevent.mult = 1; 697 setup_APIC_timer(); 698 } 699 return; 700 } 701 702 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 703 "calibrating APIC timer ...\n"); 704 705 if (calibrate_APIC_clock()) { 706 /* No broadcast on UP ! */ 707 if (num_possible_cpus() > 1) 708 setup_APIC_timer(); 709 return; 710 } 711 712 /* 713 * If nmi_watchdog is set to IO_APIC, we need the 714 * PIT/HPET going. Otherwise register lapic as a dummy 715 * device. 716 */ 717 if (nmi_watchdog != NMI_IO_APIC) 718 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 719 else 720 pr_warning("APIC timer registered as dummy," 721 " due to nmi_watchdog=%d!\n", nmi_watchdog); 722 723 /* Setup the lapic or request the broadcast */ 724 setup_APIC_timer(); 725 } 726 727 void __cpuinit setup_secondary_APIC_clock(void) 728 { 729 setup_APIC_timer(); 730 } 731 732 /* 733 * The guts of the apic timer interrupt 734 */ 735 static void local_apic_timer_interrupt(void) 736 { 737 int cpu = smp_processor_id(); 738 struct clock_event_device *evt = &per_cpu(lapic_events, cpu); 739 740 /* 741 * Normally we should not be here till LAPIC has been initialized but 742 * in some cases like kdump, its possible that there is a pending LAPIC 743 * timer interrupt from previous kernel's context and is delivered in 744 * new kernel the moment interrupts are enabled. 745 * 746 * Interrupts are enabled early and LAPIC is setup much later, hence 747 * its possible that when we get here evt->event_handler is NULL. 748 * Check for event_handler being NULL and discard the interrupt as 749 * spurious. 750 */ 751 if (!evt->event_handler) { 752 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); 753 /* Switch it off */ 754 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); 755 return; 756 } 757 758 /* 759 * the NMI deadlock-detector uses this. 760 */ 761 inc_irq_stat(apic_timer_irqs); 762 763 evt->event_handler(evt); 764 } 765 766 /* 767 * Local APIC timer interrupt. This is the most natural way for doing 768 * local interrupts, but local timer interrupts can be emulated by 769 * broadcast interrupts too. [in case the hw doesn't support APIC timers] 770 * 771 * [ if a single-CPU system runs an SMP kernel then we call the local 772 * interrupt as well. Thus we cannot inline the local irq ... ] 773 */ 774 void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) 775 { 776 struct pt_regs *old_regs = set_irq_regs(regs); 777 778 /* 779 * NOTE! We'd better ACK the irq immediately, 780 * because timer handling can be slow. 781 */ 782 ack_APIC_irq(); 783 /* 784 * update_process_times() expects us to have done irq_enter(). 785 * Besides, if we don't timer interrupts ignore the global 786 * interrupt lock, which is the WrongThing (tm) to do. 787 */ 788 exit_idle(); 789 irq_enter(); 790 local_apic_timer_interrupt(); 791 irq_exit(); 792 793 set_irq_regs(old_regs); 794 } 795 796 int setup_profiling_timer(unsigned int multiplier) 797 { 798 return -EINVAL; 799 } 800 801 /* 802 * Local APIC start and shutdown 803 */ 804 805 /** 806 * clear_local_APIC - shutdown the local APIC 807 * 808 * This is called, when a CPU is disabled and before rebooting, so the state of 809 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 810 * leftovers during boot. 811 */ 812 void clear_local_APIC(void) 813 { 814 int maxlvt; 815 u32 v; 816 817 /* APIC hasn't been mapped yet */ 818 if (!x2apic && !apic_phys) 819 return; 820 821 maxlvt = lapic_get_maxlvt(); 822 /* 823 * Masking an LVT entry can trigger a local APIC error 824 * if the vector is zero. Mask LVTERR first to prevent this. 825 */ 826 if (maxlvt >= 3) { 827 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 828 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 829 } 830 /* 831 * Careful: we have to set masks only first to deassert 832 * any level-triggered sources. 833 */ 834 v = apic_read(APIC_LVTT); 835 apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 836 v = apic_read(APIC_LVT0); 837 apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 838 v = apic_read(APIC_LVT1); 839 apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 840 if (maxlvt >= 4) { 841 v = apic_read(APIC_LVTPC); 842 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 843 } 844 845 /* lets not touch this if we didn't frob it */ 846 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) 847 if (maxlvt >= 5) { 848 v = apic_read(APIC_LVTTHMR); 849 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 850 } 851 #endif 852 #ifdef CONFIG_X86_MCE_INTEL 853 if (maxlvt >= 6) { 854 v = apic_read(APIC_LVTCMCI); 855 if (!(v & APIC_LVT_MASKED)) 856 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 857 } 858 #endif 859 860 /* 861 * Clean APIC state for other OSs: 862 */ 863 apic_write(APIC_LVTT, APIC_LVT_MASKED); 864 apic_write(APIC_LVT0, APIC_LVT_MASKED); 865 apic_write(APIC_LVT1, APIC_LVT_MASKED); 866 if (maxlvt >= 3) 867 apic_write(APIC_LVTERR, APIC_LVT_MASKED); 868 if (maxlvt >= 4) 869 apic_write(APIC_LVTPC, APIC_LVT_MASKED); 870 871 /* Integrated APIC (!82489DX) ? */ 872 if (lapic_is_integrated()) { 873 if (maxlvt > 3) 874 /* Clear ESR due to Pentium errata 3AP and 11AP */ 875 apic_write(APIC_ESR, 0); 876 apic_read(APIC_ESR); 877 } 878 } 879 880 /** 881 * disable_local_APIC - clear and disable the local APIC 882 */ 883 void disable_local_APIC(void) 884 { 885 unsigned int value; 886 887 /* APIC hasn't been mapped yet */ 888 if (!apic_phys) 889 return; 890 891 clear_local_APIC(); 892 893 /* 894 * Disable APIC (implies clearing of registers 895 * for 82489DX!). 896 */ 897 value = apic_read(APIC_SPIV); 898 value &= ~APIC_SPIV_APIC_ENABLED; 899 apic_write(APIC_SPIV, value); 900 901 #ifdef CONFIG_X86_32 902 /* 903 * When LAPIC was disabled by the BIOS and enabled by the kernel, 904 * restore the disabled state. 905 */ 906 if (enabled_via_apicbase) { 907 unsigned int l, h; 908 909 rdmsr(MSR_IA32_APICBASE, l, h); 910 l &= ~MSR_IA32_APICBASE_ENABLE; 911 wrmsr(MSR_IA32_APICBASE, l, h); 912 } 913 #endif 914 } 915 916 /* 917 * If Linux enabled the LAPIC against the BIOS default disable it down before 918 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 919 * not power-off. Additionally clear all LVT entries before disable_local_APIC 920 * for the case where Linux didn't enable the LAPIC. 921 */ 922 void lapic_shutdown(void) 923 { 924 unsigned long flags; 925 926 if (!cpu_has_apic) 927 return; 928 929 local_irq_save(flags); 930 931 #ifdef CONFIG_X86_32 932 if (!enabled_via_apicbase) 933 clear_local_APIC(); 934 else 935 #endif 936 disable_local_APIC(); 937 938 939 local_irq_restore(flags); 940 } 941 942 /* 943 * This is to verify that we're looking at a real local APIC. 944 * Check these against your board if the CPUs aren't getting 945 * started for no apparent reason. 946 */ 947 int __init verify_local_APIC(void) 948 { 949 unsigned int reg0, reg1; 950 951 /* 952 * The version register is read-only in a real APIC. 953 */ 954 reg0 = apic_read(APIC_LVR); 955 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); 956 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); 957 reg1 = apic_read(APIC_LVR); 958 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); 959 960 /* 961 * The two version reads above should print the same 962 * numbers. If the second one is different, then we 963 * poke at a non-APIC. 964 */ 965 if (reg1 != reg0) 966 return 0; 967 968 /* 969 * Check if the version looks reasonably. 970 */ 971 reg1 = GET_APIC_VERSION(reg0); 972 if (reg1 == 0x00 || reg1 == 0xff) 973 return 0; 974 reg1 = lapic_get_maxlvt(); 975 if (reg1 < 0x02 || reg1 == 0xff) 976 return 0; 977 978 /* 979 * The ID register is read/write in a real APIC. 980 */ 981 reg0 = apic_read(APIC_ID); 982 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); 983 apic_write(APIC_ID, reg0 ^ apic->apic_id_mask); 984 reg1 = apic_read(APIC_ID); 985 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); 986 apic_write(APIC_ID, reg0); 987 if (reg1 != (reg0 ^ apic->apic_id_mask)) 988 return 0; 989 990 /* 991 * The next two are just to see if we have sane values. 992 * They're only really relevant if we're in Virtual Wire 993 * compatibility mode, but most boxes are anymore. 994 */ 995 reg0 = apic_read(APIC_LVT0); 996 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); 997 reg1 = apic_read(APIC_LVT1); 998 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); 999 1000 return 1; 1001 } 1002 1003 /** 1004 * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1005 */ 1006 void __init sync_Arb_IDs(void) 1007 { 1008 /* 1009 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1010 * needed on AMD. 1011 */ 1012 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1013 return; 1014 1015 /* 1016 * Wait for idle. 1017 */ 1018 apic_wait_icr_idle(); 1019 1020 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1021 apic_write(APIC_ICR, APIC_DEST_ALLINC | 1022 APIC_INT_LEVELTRIG | APIC_DM_INIT); 1023 } 1024 1025 /* 1026 * An initial setup of the virtual wire mode. 1027 */ 1028 void __init init_bsp_APIC(void) 1029 { 1030 unsigned int value; 1031 1032 /* 1033 * Don't do the setup now if we have a SMP BIOS as the 1034 * through-I/O-APIC virtual wire mode might be active. 1035 */ 1036 if (smp_found_config || !cpu_has_apic) 1037 return; 1038 1039 /* 1040 * Do not trust the local APIC being empty at bootup. 1041 */ 1042 clear_local_APIC(); 1043 1044 /* 1045 * Enable APIC. 1046 */ 1047 value = apic_read(APIC_SPIV); 1048 value &= ~APIC_VECTOR_MASK; 1049 value |= APIC_SPIV_APIC_ENABLED; 1050 1051 #ifdef CONFIG_X86_32 1052 /* This bit is reserved on P4/Xeon and should be cleared */ 1053 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1054 (boot_cpu_data.x86 == 15)) 1055 value &= ~APIC_SPIV_FOCUS_DISABLED; 1056 else 1057 #endif 1058 value |= APIC_SPIV_FOCUS_DISABLED; 1059 value |= SPURIOUS_APIC_VECTOR; 1060 apic_write(APIC_SPIV, value); 1061 1062 /* 1063 * Set up the virtual wire mode. 1064 */ 1065 apic_write(APIC_LVT0, APIC_DM_EXTINT); 1066 value = APIC_DM_NMI; 1067 if (!lapic_is_integrated()) /* 82489DX */ 1068 value |= APIC_LVT_LEVEL_TRIGGER; 1069 apic_write(APIC_LVT1, value); 1070 } 1071 1072 static void __cpuinit lapic_setup_esr(void) 1073 { 1074 unsigned int oldvalue, value, maxlvt; 1075 1076 if (!lapic_is_integrated()) { 1077 pr_info("No ESR for 82489DX.\n"); 1078 return; 1079 } 1080 1081 if (apic->disable_esr) { 1082 /* 1083 * Something untraceable is creating bad interrupts on 1084 * secondary quads ... for the moment, just leave the 1085 * ESR disabled - we can't do anything useful with the 1086 * errors anyway - mbligh 1087 */ 1088 pr_info("Leaving ESR disabled.\n"); 1089 return; 1090 } 1091 1092 maxlvt = lapic_get_maxlvt(); 1093 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1094 apic_write(APIC_ESR, 0); 1095 oldvalue = apic_read(APIC_ESR); 1096 1097 /* enables sending errors */ 1098 value = ERROR_APIC_VECTOR; 1099 apic_write(APIC_LVTERR, value); 1100 1101 /* 1102 * spec says clear errors after enabling vector. 1103 */ 1104 if (maxlvt > 3) 1105 apic_write(APIC_ESR, 0); 1106 value = apic_read(APIC_ESR); 1107 if (value != oldvalue) 1108 apic_printk(APIC_VERBOSE, "ESR value before enabling " 1109 "vector: 0x%08x after: 0x%08x\n", 1110 oldvalue, value); 1111 } 1112 1113 1114 /** 1115 * setup_local_APIC - setup the local APIC 1116 */ 1117 void __cpuinit setup_local_APIC(void) 1118 { 1119 unsigned int value; 1120 int i, j; 1121 1122 if (disable_apic) { 1123 arch_disable_smp_support(); 1124 return; 1125 } 1126 1127 #ifdef CONFIG_X86_32 1128 /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1129 if (lapic_is_integrated() && apic->disable_esr) { 1130 apic_write(APIC_ESR, 0); 1131 apic_write(APIC_ESR, 0); 1132 apic_write(APIC_ESR, 0); 1133 apic_write(APIC_ESR, 0); 1134 } 1135 #endif 1136 1137 preempt_disable(); 1138 1139 /* 1140 * Double-check whether this APIC is really registered. 1141 * This is meaningless in clustered apic mode, so we skip it. 1142 */ 1143 if (!apic->apic_id_registered()) 1144 BUG(); 1145 1146 /* 1147 * Intel recommends to set DFR, LDR and TPR before enabling 1148 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1149 * document number 292116). So here it goes... 1150 */ 1151 apic->init_apic_ldr(); 1152 1153 /* 1154 * Set Task Priority to 'accept all'. We never change this 1155 * later on. 1156 */ 1157 value = apic_read(APIC_TASKPRI); 1158 value &= ~APIC_TPRI_MASK; 1159 apic_write(APIC_TASKPRI, value); 1160 1161 /* 1162 * After a crash, we no longer service the interrupts and a pending 1163 * interrupt from previous kernel might still have ISR bit set. 1164 * 1165 * Most probably by now CPU has serviced that pending interrupt and 1166 * it might not have done the ack_APIC_irq() because it thought, 1167 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it 1168 * does not clear the ISR bit and cpu thinks it has already serivced 1169 * the interrupt. Hence a vector might get locked. It was noticed 1170 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. 1171 */ 1172 for (i = APIC_ISR_NR - 1; i >= 0; i--) { 1173 value = apic_read(APIC_ISR + i*0x10); 1174 for (j = 31; j >= 0; j--) { 1175 if (value & (1<<j)) 1176 ack_APIC_irq(); 1177 } 1178 } 1179 1180 /* 1181 * Now that we are all set up, enable the APIC 1182 */ 1183 value = apic_read(APIC_SPIV); 1184 value &= ~APIC_VECTOR_MASK; 1185 /* 1186 * Enable APIC 1187 */ 1188 value |= APIC_SPIV_APIC_ENABLED; 1189 1190 #ifdef CONFIG_X86_32 1191 /* 1192 * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1193 * certain networking cards. If high frequency interrupts are 1194 * happening on a particular IOAPIC pin, plus the IOAPIC routing 1195 * entry is masked/unmasked at a high rate as well then sooner or 1196 * later IOAPIC line gets 'stuck', no more interrupts are received 1197 * from the device. If focus CPU is disabled then the hang goes 1198 * away, oh well :-( 1199 * 1200 * [ This bug can be reproduced easily with a level-triggered 1201 * PCI Ne2000 networking cards and PII/PIII processors, dual 1202 * BX chipset. ] 1203 */ 1204 /* 1205 * Actually disabling the focus CPU check just makes the hang less 1206 * frequent as it makes the interrupt distributon model be more 1207 * like LRU than MRU (the short-term load is more even across CPUs). 1208 * See also the comment in end_level_ioapic_irq(). --macro 1209 */ 1210 1211 /* 1212 * - enable focus processor (bit==0) 1213 * - 64bit mode always use processor focus 1214 * so no need to set it 1215 */ 1216 value &= ~APIC_SPIV_FOCUS_DISABLED; 1217 #endif 1218 1219 /* 1220 * Set spurious IRQ vector 1221 */ 1222 value |= SPURIOUS_APIC_VECTOR; 1223 apic_write(APIC_SPIV, value); 1224 1225 /* 1226 * Set up LVT0, LVT1: 1227 * 1228 * set up through-local-APIC on the BP's LINT0. This is not 1229 * strictly necessary in pure symmetric-IO mode, but sometimes 1230 * we delegate interrupts to the 8259A. 1231 */ 1232 /* 1233 * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1234 */ 1235 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 1236 if (!smp_processor_id() && (pic_mode || !value)) { 1237 value = APIC_DM_EXTINT; 1238 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", 1239 smp_processor_id()); 1240 } else { 1241 value = APIC_DM_EXTINT | APIC_LVT_MASKED; 1242 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", 1243 smp_processor_id()); 1244 } 1245 apic_write(APIC_LVT0, value); 1246 1247 /* 1248 * only the BP should see the LINT1 NMI signal, obviously. 1249 */ 1250 if (!smp_processor_id()) 1251 value = APIC_DM_NMI; 1252 else 1253 value = APIC_DM_NMI | APIC_LVT_MASKED; 1254 if (!lapic_is_integrated()) /* 82489DX */ 1255 value |= APIC_LVT_LEVEL_TRIGGER; 1256 apic_write(APIC_LVT1, value); 1257 1258 preempt_enable(); 1259 1260 #ifdef CONFIG_X86_MCE_INTEL 1261 /* Recheck CMCI information after local APIC is up on CPU #0 */ 1262 if (smp_processor_id() == 0) 1263 cmci_recheck(); 1264 #endif 1265 } 1266 1267 void __cpuinit end_local_APIC_setup(void) 1268 { 1269 lapic_setup_esr(); 1270 1271 #ifdef CONFIG_X86_32 1272 { 1273 unsigned int value; 1274 /* Disable the local apic timer */ 1275 value = apic_read(APIC_LVTT); 1276 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1277 apic_write(APIC_LVTT, value); 1278 } 1279 #endif 1280 1281 setup_apic_nmi_watchdog(NULL); 1282 apic_pm_activate(); 1283 } 1284 1285 #ifdef CONFIG_X86_X2APIC 1286 void check_x2apic(void) 1287 { 1288 if (x2apic_enabled()) { 1289 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n"); 1290 x2apic_preenabled = x2apic = 1; 1291 } 1292 } 1293 1294 void enable_x2apic(void) 1295 { 1296 int msr, msr2; 1297 1298 if (!x2apic) 1299 return; 1300 1301 rdmsr(MSR_IA32_APICBASE, msr, msr2); 1302 if (!(msr & X2APIC_ENABLE)) { 1303 pr_info("Enabling x2apic\n"); 1304 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); 1305 } 1306 } 1307 1308 void __init enable_IR_x2apic(void) 1309 { 1310 #ifdef CONFIG_INTR_REMAP 1311 int ret; 1312 unsigned long flags; 1313 struct IO_APIC_route_entry **ioapic_entries = NULL; 1314 1315 if (!cpu_has_x2apic) 1316 return; 1317 1318 if (!x2apic_preenabled && disable_x2apic) { 1319 pr_info("Skipped enabling x2apic and Interrupt-remapping " 1320 "because of nox2apic\n"); 1321 return; 1322 } 1323 1324 if (x2apic_preenabled && disable_x2apic) 1325 panic("Bios already enabled x2apic, can't enforce nox2apic"); 1326 1327 if (!x2apic_preenabled && skip_ioapic_setup) { 1328 pr_info("Skipped enabling x2apic and Interrupt-remapping " 1329 "because of skipping io-apic setup\n"); 1330 return; 1331 } 1332 1333 ret = dmar_table_init(); 1334 if (ret) { 1335 pr_info("dmar_table_init() failed with %d:\n", ret); 1336 1337 if (x2apic_preenabled) 1338 panic("x2apic enabled by bios. But IR enabling failed"); 1339 else 1340 pr_info("Not enabling x2apic,Intr-remapping\n"); 1341 return; 1342 } 1343 1344 ioapic_entries = alloc_ioapic_entries(); 1345 if (!ioapic_entries) { 1346 pr_info("Allocate ioapic_entries failed: %d\n", ret); 1347 goto end; 1348 } 1349 1350 ret = save_IO_APIC_setup(ioapic_entries); 1351 if (ret) { 1352 pr_info("Saving IO-APIC state failed: %d\n", ret); 1353 goto end; 1354 } 1355 1356 local_irq_save(flags); 1357 mask_IO_APIC_setup(ioapic_entries); 1358 mask_8259A(); 1359 1360 ret = enable_intr_remapping(EIM_32BIT_APIC_ID); 1361 1362 if (ret && x2apic_preenabled) { 1363 local_irq_restore(flags); 1364 panic("x2apic enabled by bios. But IR enabling failed"); 1365 } 1366 1367 if (ret) 1368 goto end_restore; 1369 1370 if (!x2apic) { 1371 x2apic = 1; 1372 enable_x2apic(); 1373 } 1374 1375 end_restore: 1376 if (ret) 1377 /* 1378 * IR enabling failed 1379 */ 1380 restore_IO_APIC_setup(ioapic_entries); 1381 else 1382 reinit_intr_remapped_IO_APIC(x2apic_preenabled, ioapic_entries); 1383 1384 unmask_8259A(); 1385 local_irq_restore(flags); 1386 1387 end: 1388 if (!ret) { 1389 if (!x2apic_preenabled) 1390 pr_info("Enabled x2apic and interrupt-remapping\n"); 1391 else 1392 pr_info("Enabled Interrupt-remapping\n"); 1393 } else 1394 pr_err("Failed to enable Interrupt-remapping and x2apic\n"); 1395 if (ioapic_entries) 1396 free_ioapic_entries(ioapic_entries); 1397 #else 1398 if (!cpu_has_x2apic) 1399 return; 1400 1401 if (x2apic_preenabled) 1402 panic("x2apic enabled prior OS handover," 1403 " enable CONFIG_INTR_REMAP"); 1404 1405 pr_info("Enable CONFIG_INTR_REMAP for enabling intr-remapping " 1406 " and x2apic\n"); 1407 #endif 1408 1409 return; 1410 } 1411 #endif /* CONFIG_X86_X2APIC */ 1412 1413 #ifdef CONFIG_X86_64 1414 /* 1415 * Detect and enable local APICs on non-SMP boards. 1416 * Original code written by Keir Fraser. 1417 * On AMD64 we trust the BIOS - if it says no APIC it is likely 1418 * not correctly set up (usually the APIC timer won't work etc.) 1419 */ 1420 static int __init detect_init_APIC(void) 1421 { 1422 if (!cpu_has_apic) { 1423 pr_info("No local APIC present\n"); 1424 return -1; 1425 } 1426 1427 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1428 boot_cpu_physical_apicid = 0; 1429 return 0; 1430 } 1431 #else 1432 /* 1433 * Detect and initialize APIC 1434 */ 1435 static int __init detect_init_APIC(void) 1436 { 1437 u32 h, l, features; 1438 1439 /* Disabled by kernel option? */ 1440 if (disable_apic) 1441 return -1; 1442 1443 switch (boot_cpu_data.x86_vendor) { 1444 case X86_VENDOR_AMD: 1445 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 1446 (boot_cpu_data.x86 >= 15)) 1447 break; 1448 goto no_apic; 1449 case X86_VENDOR_INTEL: 1450 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 1451 (boot_cpu_data.x86 == 5 && cpu_has_apic)) 1452 break; 1453 goto no_apic; 1454 default: 1455 goto no_apic; 1456 } 1457 1458 if (!cpu_has_apic) { 1459 /* 1460 * Over-ride BIOS and try to enable the local APIC only if 1461 * "lapic" specified. 1462 */ 1463 if (!force_enable_local_apic) { 1464 pr_info("Local APIC disabled by BIOS -- " 1465 "you can enable it with \"lapic\"\n"); 1466 return -1; 1467 } 1468 /* 1469 * Some BIOSes disable the local APIC in the APIC_BASE 1470 * MSR. This can only be done in software for Intel P6 or later 1471 * and AMD K7 (Model > 1) or later. 1472 */ 1473 rdmsr(MSR_IA32_APICBASE, l, h); 1474 if (!(l & MSR_IA32_APICBASE_ENABLE)) { 1475 pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 1476 l &= ~MSR_IA32_APICBASE_BASE; 1477 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; 1478 wrmsr(MSR_IA32_APICBASE, l, h); 1479 enabled_via_apicbase = 1; 1480 } 1481 } 1482 /* 1483 * The APIC feature bit should now be enabled 1484 * in `cpuid' 1485 */ 1486 features = cpuid_edx(1); 1487 if (!(features & (1 << X86_FEATURE_APIC))) { 1488 pr_warning("Could not enable APIC!\n"); 1489 return -1; 1490 } 1491 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 1492 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1493 1494 /* The BIOS may have set up the APIC at some other address */ 1495 rdmsr(MSR_IA32_APICBASE, l, h); 1496 if (l & MSR_IA32_APICBASE_ENABLE) 1497 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 1498 1499 pr_info("Found and enabled local APIC!\n"); 1500 1501 apic_pm_activate(); 1502 1503 return 0; 1504 1505 no_apic: 1506 pr_info("No local APIC present or hardware disabled\n"); 1507 return -1; 1508 } 1509 #endif 1510 1511 #ifdef CONFIG_X86_64 1512 void __init early_init_lapic_mapping(void) 1513 { 1514 unsigned long phys_addr; 1515 1516 /* 1517 * If no local APIC can be found then go out 1518 * : it means there is no mpatable and MADT 1519 */ 1520 if (!smp_found_config) 1521 return; 1522 1523 phys_addr = mp_lapic_addr; 1524 1525 set_fixmap_nocache(FIX_APIC_BASE, phys_addr); 1526 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 1527 APIC_BASE, phys_addr); 1528 1529 /* 1530 * Fetch the APIC ID of the BSP in case we have a 1531 * default configuration (or the MP table is broken). 1532 */ 1533 boot_cpu_physical_apicid = read_apic_id(); 1534 } 1535 #endif 1536 1537 /** 1538 * init_apic_mappings - initialize APIC mappings 1539 */ 1540 void __init init_apic_mappings(void) 1541 { 1542 if (x2apic) { 1543 boot_cpu_physical_apicid = read_apic_id(); 1544 return; 1545 } 1546 1547 /* 1548 * If no local APIC can be found then set up a fake all 1549 * zeroes page to simulate the local APIC and another 1550 * one for the IO-APIC. 1551 */ 1552 if (!smp_found_config && detect_init_APIC()) { 1553 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE); 1554 apic_phys = __pa(apic_phys); 1555 } else 1556 apic_phys = mp_lapic_addr; 1557 1558 set_fixmap_nocache(FIX_APIC_BASE, apic_phys); 1559 apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n", 1560 APIC_BASE, apic_phys); 1561 1562 /* 1563 * Fetch the APIC ID of the BSP in case we have a 1564 * default configuration (or the MP table is broken). 1565 */ 1566 if (boot_cpu_physical_apicid == -1U) 1567 boot_cpu_physical_apicid = read_apic_id(); 1568 } 1569 1570 /* 1571 * This initializes the IO-APIC and APIC hardware if this is 1572 * a UP kernel. 1573 */ 1574 int apic_version[MAX_APICS]; 1575 1576 int __init APIC_init_uniprocessor(void) 1577 { 1578 if (disable_apic) { 1579 pr_info("Apic disabled\n"); 1580 return -1; 1581 } 1582 #ifdef CONFIG_X86_64 1583 if (!cpu_has_apic) { 1584 disable_apic = 1; 1585 pr_info("Apic disabled by BIOS\n"); 1586 return -1; 1587 } 1588 #else 1589 if (!smp_found_config && !cpu_has_apic) 1590 return -1; 1591 1592 /* 1593 * Complain if the BIOS pretends there is one. 1594 */ 1595 if (!cpu_has_apic && 1596 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 1597 pr_err("BIOS bug, local APIC 0x%x not detected!...\n", 1598 boot_cpu_physical_apicid); 1599 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 1600 return -1; 1601 } 1602 #endif 1603 1604 enable_IR_x2apic(); 1605 #ifdef CONFIG_X86_64 1606 default_setup_apic_routing(); 1607 #endif 1608 1609 verify_local_APIC(); 1610 connect_bsp_APIC(); 1611 1612 #ifdef CONFIG_X86_64 1613 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); 1614 #else 1615 /* 1616 * Hack: In case of kdump, after a crash, kernel might be booting 1617 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 1618 * might be zero if read from MP tables. Get it from LAPIC. 1619 */ 1620 # ifdef CONFIG_CRASH_DUMP 1621 boot_cpu_physical_apicid = read_apic_id(); 1622 # endif 1623 #endif 1624 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1625 setup_local_APIC(); 1626 1627 #ifdef CONFIG_X86_IO_APIC 1628 /* 1629 * Now enable IO-APICs, actually call clear_IO_APIC 1630 * We need clear_IO_APIC before enabling error vector 1631 */ 1632 if (!skip_ioapic_setup && nr_ioapics) 1633 enable_IO_APIC(); 1634 #endif 1635 1636 end_local_APIC_setup(); 1637 1638 #ifdef CONFIG_X86_IO_APIC 1639 if (smp_found_config && !skip_ioapic_setup && nr_ioapics) 1640 setup_IO_APIC(); 1641 else { 1642 nr_ioapics = 0; 1643 localise_nmi_watchdog(); 1644 } 1645 #else 1646 localise_nmi_watchdog(); 1647 #endif 1648 1649 setup_boot_clock(); 1650 #ifdef CONFIG_X86_64 1651 check_nmi_watchdog(); 1652 #endif 1653 1654 return 0; 1655 } 1656 1657 /* 1658 * Local APIC interrupts 1659 */ 1660 1661 /* 1662 * This interrupt should _never_ happen with our APIC/SMP architecture 1663 */ 1664 void smp_spurious_interrupt(struct pt_regs *regs) 1665 { 1666 u32 v; 1667 1668 exit_idle(); 1669 irq_enter(); 1670 /* 1671 * Check if this really is a spurious interrupt and ACK it 1672 * if it is a vectored one. Just in case... 1673 * Spurious interrupts should not be ACKed. 1674 */ 1675 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); 1676 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) 1677 ack_APIC_irq(); 1678 1679 inc_irq_stat(irq_spurious_count); 1680 1681 /* see sw-dev-man vol 3, chapter 7.4.13.5 */ 1682 pr_info("spurious APIC interrupt on CPU#%d, " 1683 "should never happen.\n", smp_processor_id()); 1684 irq_exit(); 1685 } 1686 1687 /* 1688 * This interrupt should never happen with our APIC/SMP architecture 1689 */ 1690 void smp_error_interrupt(struct pt_regs *regs) 1691 { 1692 u32 v, v1; 1693 1694 exit_idle(); 1695 irq_enter(); 1696 /* First tickle the hardware, only then report what went on. -- REW */ 1697 v = apic_read(APIC_ESR); 1698 apic_write(APIC_ESR, 0); 1699 v1 = apic_read(APIC_ESR); 1700 ack_APIC_irq(); 1701 atomic_inc(&irq_err_count); 1702 1703 /* 1704 * Here is what the APIC error bits mean: 1705 * 0: Send CS error 1706 * 1: Receive CS error 1707 * 2: Send accept error 1708 * 3: Receive accept error 1709 * 4: Reserved 1710 * 5: Send illegal vector 1711 * 6: Received illegal vector 1712 * 7: Illegal register address 1713 */ 1714 pr_debug("APIC error on CPU%d: %02x(%02x)\n", 1715 smp_processor_id(), v , v1); 1716 irq_exit(); 1717 } 1718 1719 /** 1720 * connect_bsp_APIC - attach the APIC to the interrupt system 1721 */ 1722 void __init connect_bsp_APIC(void) 1723 { 1724 #ifdef CONFIG_X86_32 1725 if (pic_mode) { 1726 /* 1727 * Do not trust the local APIC being empty at bootup. 1728 */ 1729 clear_local_APIC(); 1730 /* 1731 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 1732 * local APIC to INT and NMI lines. 1733 */ 1734 apic_printk(APIC_VERBOSE, "leaving PIC mode, " 1735 "enabling APIC mode.\n"); 1736 outb(0x70, 0x22); 1737 outb(0x01, 0x23); 1738 } 1739 #endif 1740 if (apic->enable_apic_mode) 1741 apic->enable_apic_mode(); 1742 } 1743 1744 /** 1745 * disconnect_bsp_APIC - detach the APIC from the interrupt system 1746 * @virt_wire_setup: indicates, whether virtual wire mode is selected 1747 * 1748 * Virtual wire mode is necessary to deliver legacy interrupts even when the 1749 * APIC is disabled. 1750 */ 1751 void disconnect_bsp_APIC(int virt_wire_setup) 1752 { 1753 unsigned int value; 1754 1755 #ifdef CONFIG_X86_32 1756 if (pic_mode) { 1757 /* 1758 * Put the board back into PIC mode (has an effect only on 1759 * certain older boards). Note that APIC interrupts, including 1760 * IPIs, won't work beyond this point! The only exception are 1761 * INIT IPIs. 1762 */ 1763 apic_printk(APIC_VERBOSE, "disabling APIC mode, " 1764 "entering PIC mode.\n"); 1765 outb(0x70, 0x22); 1766 outb(0x00, 0x23); 1767 return; 1768 } 1769 #endif 1770 1771 /* Go back to Virtual Wire compatibility mode */ 1772 1773 /* For the spurious interrupt use vector F, and enable it */ 1774 value = apic_read(APIC_SPIV); 1775 value &= ~APIC_VECTOR_MASK; 1776 value |= APIC_SPIV_APIC_ENABLED; 1777 value |= 0xf; 1778 apic_write(APIC_SPIV, value); 1779 1780 if (!virt_wire_setup) { 1781 /* 1782 * For LVT0 make it edge triggered, active high, 1783 * external and enabled 1784 */ 1785 value = apic_read(APIC_LVT0); 1786 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 1787 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 1788 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 1789 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 1790 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 1791 apic_write(APIC_LVT0, value); 1792 } else { 1793 /* Disable LVT0 */ 1794 apic_write(APIC_LVT0, APIC_LVT_MASKED); 1795 } 1796 1797 /* 1798 * For LVT1 make it edge triggered, active high, 1799 * nmi and enabled 1800 */ 1801 value = apic_read(APIC_LVT1); 1802 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 1803 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 1804 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 1805 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 1806 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 1807 apic_write(APIC_LVT1, value); 1808 } 1809 1810 void __cpuinit generic_processor_info(int apicid, int version) 1811 { 1812 int cpu; 1813 1814 /* 1815 * Validate version 1816 */ 1817 if (version == 0x0) { 1818 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! " 1819 "fixing up to 0x10. (tell your hw vendor)\n", 1820 version); 1821 version = 0x10; 1822 } 1823 apic_version[apicid] = version; 1824 1825 if (num_processors >= nr_cpu_ids) { 1826 int max = nr_cpu_ids; 1827 int thiscpu = max + disabled_cpus; 1828 1829 pr_warning( 1830 "ACPI: NR_CPUS/possible_cpus limit of %i reached." 1831 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 1832 1833 disabled_cpus++; 1834 return; 1835 } 1836 1837 num_processors++; 1838 cpu = cpumask_next_zero(-1, cpu_present_mask); 1839 1840 if (version != apic_version[boot_cpu_physical_apicid]) 1841 WARN_ONCE(1, 1842 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n", 1843 apic_version[boot_cpu_physical_apicid], cpu, version); 1844 1845 physid_set(apicid, phys_cpu_present_map); 1846 if (apicid == boot_cpu_physical_apicid) { 1847 /* 1848 * x86_bios_cpu_apicid is required to have processors listed 1849 * in same order as logical cpu numbers. Hence the first 1850 * entry is BSP, and so on. 1851 */ 1852 cpu = 0; 1853 } 1854 if (apicid > max_physical_apicid) 1855 max_physical_apicid = apicid; 1856 1857 #ifdef CONFIG_X86_32 1858 /* 1859 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y 1860 * but we need to work other dependencies like SMP_SUSPEND etc 1861 * before this can be done without some confusion. 1862 * if (CPU_HOTPLUG_ENABLED || num_processors > 8) 1863 * - Ashok Raj <ashok.raj@intel.com> 1864 */ 1865 if (max_physical_apicid >= 8) { 1866 switch (boot_cpu_data.x86_vendor) { 1867 case X86_VENDOR_INTEL: 1868 if (!APIC_XAPIC(version)) { 1869 def_to_bigsmp = 0; 1870 break; 1871 } 1872 /* If P4 and above fall through */ 1873 case X86_VENDOR_AMD: 1874 def_to_bigsmp = 1; 1875 } 1876 } 1877 #endif 1878 1879 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 1880 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 1881 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 1882 #endif 1883 1884 set_cpu_possible(cpu, true); 1885 set_cpu_present(cpu, true); 1886 } 1887 1888 int hard_smp_processor_id(void) 1889 { 1890 return read_apic_id(); 1891 } 1892 1893 void default_init_apic_ldr(void) 1894 { 1895 unsigned long val; 1896 1897 apic_write(APIC_DFR, APIC_DFR_VALUE); 1898 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; 1899 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); 1900 apic_write(APIC_LDR, val); 1901 } 1902 1903 #ifdef CONFIG_X86_32 1904 int default_apicid_to_node(int logical_apicid) 1905 { 1906 #ifdef CONFIG_SMP 1907 return apicid_2_node[hard_smp_processor_id()]; 1908 #else 1909 return 0; 1910 #endif 1911 } 1912 #endif 1913 1914 /* 1915 * Power management 1916 */ 1917 #ifdef CONFIG_PM 1918 1919 static struct { 1920 /* 1921 * 'active' is true if the local APIC was enabled by us and 1922 * not the BIOS; this signifies that we are also responsible 1923 * for disabling it before entering apm/acpi suspend 1924 */ 1925 int active; 1926 /* r/w apic fields */ 1927 unsigned int apic_id; 1928 unsigned int apic_taskpri; 1929 unsigned int apic_ldr; 1930 unsigned int apic_dfr; 1931 unsigned int apic_spiv; 1932 unsigned int apic_lvtt; 1933 unsigned int apic_lvtpc; 1934 unsigned int apic_lvt0; 1935 unsigned int apic_lvt1; 1936 unsigned int apic_lvterr; 1937 unsigned int apic_tmict; 1938 unsigned int apic_tdcr; 1939 unsigned int apic_thmr; 1940 } apic_pm_state; 1941 1942 static int lapic_suspend(struct sys_device *dev, pm_message_t state) 1943 { 1944 unsigned long flags; 1945 int maxlvt; 1946 1947 if (!apic_pm_state.active) 1948 return 0; 1949 1950 maxlvt = lapic_get_maxlvt(); 1951 1952 apic_pm_state.apic_id = apic_read(APIC_ID); 1953 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 1954 apic_pm_state.apic_ldr = apic_read(APIC_LDR); 1955 apic_pm_state.apic_dfr = apic_read(APIC_DFR); 1956 apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 1957 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 1958 if (maxlvt >= 4) 1959 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 1960 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 1961 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 1962 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 1963 apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 1964 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 1965 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) 1966 if (maxlvt >= 5) 1967 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 1968 #endif 1969 1970 local_irq_save(flags); 1971 disable_local_APIC(); 1972 #ifdef CONFIG_INTR_REMAP 1973 if (intr_remapping_enabled) 1974 disable_intr_remapping(); 1975 #endif 1976 local_irq_restore(flags); 1977 return 0; 1978 } 1979 1980 static int lapic_resume(struct sys_device *dev) 1981 { 1982 unsigned int l, h; 1983 unsigned long flags; 1984 int maxlvt; 1985 1986 #ifdef CONFIG_INTR_REMAP 1987 int ret; 1988 struct IO_APIC_route_entry **ioapic_entries = NULL; 1989 1990 if (!apic_pm_state.active) 1991 return 0; 1992 1993 local_irq_save(flags); 1994 if (x2apic) { 1995 ioapic_entries = alloc_ioapic_entries(); 1996 if (!ioapic_entries) { 1997 WARN(1, "Alloc ioapic_entries in lapic resume failed."); 1998 return -ENOMEM; 1999 } 2000 2001 ret = save_IO_APIC_setup(ioapic_entries); 2002 if (ret) { 2003 WARN(1, "Saving IO-APIC state failed: %d\n", ret); 2004 free_ioapic_entries(ioapic_entries); 2005 return ret; 2006 } 2007 2008 mask_IO_APIC_setup(ioapic_entries); 2009 mask_8259A(); 2010 enable_x2apic(); 2011 } 2012 #else 2013 if (!apic_pm_state.active) 2014 return 0; 2015 2016 local_irq_save(flags); 2017 if (x2apic) 2018 enable_x2apic(); 2019 #endif 2020 2021 else { 2022 /* 2023 * Make sure the APICBASE points to the right address 2024 * 2025 * FIXME! This will be wrong if we ever support suspend on 2026 * SMP! We'll need to do this as part of the CPU restore! 2027 */ 2028 rdmsr(MSR_IA32_APICBASE, l, h); 2029 l &= ~MSR_IA32_APICBASE_BASE; 2030 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2031 wrmsr(MSR_IA32_APICBASE, l, h); 2032 } 2033 2034 maxlvt = lapic_get_maxlvt(); 2035 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2036 apic_write(APIC_ID, apic_pm_state.apic_id); 2037 apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2038 apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2039 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2040 apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2041 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2042 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 2043 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) 2044 if (maxlvt >= 5) 2045 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2046 #endif 2047 if (maxlvt >= 4) 2048 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2049 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2050 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2051 apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2052 apic_write(APIC_ESR, 0); 2053 apic_read(APIC_ESR); 2054 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2055 apic_write(APIC_ESR, 0); 2056 apic_read(APIC_ESR); 2057 2058 #ifdef CONFIG_INTR_REMAP 2059 if (intr_remapping_enabled) 2060 reenable_intr_remapping(EIM_32BIT_APIC_ID); 2061 2062 if (x2apic) { 2063 unmask_8259A(); 2064 restore_IO_APIC_setup(ioapic_entries); 2065 free_ioapic_entries(ioapic_entries); 2066 } 2067 #endif 2068 2069 local_irq_restore(flags); 2070 2071 2072 return 0; 2073 } 2074 2075 /* 2076 * This device has no shutdown method - fully functioning local APICs 2077 * are needed on every CPU up until machine_halt/restart/poweroff. 2078 */ 2079 2080 static struct sysdev_class lapic_sysclass = { 2081 .name = "lapic", 2082 .resume = lapic_resume, 2083 .suspend = lapic_suspend, 2084 }; 2085 2086 static struct sys_device device_lapic = { 2087 .id = 0, 2088 .cls = &lapic_sysclass, 2089 }; 2090 2091 static void __cpuinit apic_pm_activate(void) 2092 { 2093 apic_pm_state.active = 1; 2094 } 2095 2096 static int __init init_lapic_sysfs(void) 2097 { 2098 int error; 2099 2100 if (!cpu_has_apic) 2101 return 0; 2102 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 2103 2104 error = sysdev_class_register(&lapic_sysclass); 2105 if (!error) 2106 error = sysdev_register(&device_lapic); 2107 return error; 2108 } 2109 2110 /* local apic needs to resume before other devices access its registers. */ 2111 core_initcall(init_lapic_sysfs); 2112 2113 #else /* CONFIG_PM */ 2114 2115 static void apic_pm_activate(void) { } 2116 2117 #endif /* CONFIG_PM */ 2118 2119 #ifdef CONFIG_X86_64 2120 /* 2121 * apic_is_clustered_box() -- Check if we can expect good TSC 2122 * 2123 * Thus far, the major user of this is IBM's Summit2 series: 2124 * 2125 * Clustered boxes may have unsynced TSC problems if they are 2126 * multi-chassis. Use available data to take a good guess. 2127 * If in doubt, go HPET. 2128 */ 2129 __cpuinit int apic_is_clustered_box(void) 2130 { 2131 int i, clusters, zeros; 2132 unsigned id; 2133 u16 *bios_cpu_apicid; 2134 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); 2135 2136 /* 2137 * there is not this kind of box with AMD CPU yet. 2138 * Some AMD box with quadcore cpu and 8 sockets apicid 2139 * will be [4, 0x23] or [8, 0x27] could be thought to 2140 * vsmp box still need checking... 2141 */ 2142 if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box()) 2143 return 0; 2144 2145 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); 2146 bitmap_zero(clustermap, NUM_APIC_CLUSTERS); 2147 2148 for (i = 0; i < nr_cpu_ids; i++) { 2149 /* are we being called early in kernel startup? */ 2150 if (bios_cpu_apicid) { 2151 id = bios_cpu_apicid[i]; 2152 } else if (i < nr_cpu_ids) { 2153 if (cpu_present(i)) 2154 id = per_cpu(x86_bios_cpu_apicid, i); 2155 else 2156 continue; 2157 } else 2158 break; 2159 2160 if (id != BAD_APICID) 2161 __set_bit(APIC_CLUSTERID(id), clustermap); 2162 } 2163 2164 /* Problem: Partially populated chassis may not have CPUs in some of 2165 * the APIC clusters they have been allocated. Only present CPUs have 2166 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. 2167 * Since clusters are allocated sequentially, count zeros only if 2168 * they are bounded by ones. 2169 */ 2170 clusters = 0; 2171 zeros = 0; 2172 for (i = 0; i < NUM_APIC_CLUSTERS; i++) { 2173 if (test_bit(i, clustermap)) { 2174 clusters += 1 + zeros; 2175 zeros = 0; 2176 } else 2177 ++zeros; 2178 } 2179 2180 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are 2181 * not guaranteed to be synced between boards 2182 */ 2183 if (is_vsmp_box() && clusters > 1) 2184 return 1; 2185 2186 /* 2187 * If clusters > 2, then should be multi-chassis. 2188 * May have to revisit this when multi-core + hyperthreaded CPUs come 2189 * out, but AFAIK this will work even for them. 2190 */ 2191 return (clusters > 2); 2192 } 2193 #endif 2194 2195 /* 2196 * APIC command line parameters 2197 */ 2198 static int __init setup_disableapic(char *arg) 2199 { 2200 disable_apic = 1; 2201 setup_clear_cpu_cap(X86_FEATURE_APIC); 2202 return 0; 2203 } 2204 early_param("disableapic", setup_disableapic); 2205 2206 /* same as disableapic, for compatibility */ 2207 static int __init setup_nolapic(char *arg) 2208 { 2209 return setup_disableapic(arg); 2210 } 2211 early_param("nolapic", setup_nolapic); 2212 2213 static int __init parse_lapic_timer_c2_ok(char *arg) 2214 { 2215 local_apic_timer_c2_ok = 1; 2216 return 0; 2217 } 2218 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2219 2220 static int __init parse_disable_apic_timer(char *arg) 2221 { 2222 disable_apic_timer = 1; 2223 return 0; 2224 } 2225 early_param("noapictimer", parse_disable_apic_timer); 2226 2227 static int __init parse_nolapic_timer(char *arg) 2228 { 2229 disable_apic_timer = 1; 2230 return 0; 2231 } 2232 early_param("nolapic_timer", parse_nolapic_timer); 2233 2234 static int __init apic_set_verbosity(char *arg) 2235 { 2236 if (!arg) { 2237 #ifdef CONFIG_X86_64 2238 skip_ioapic_setup = 0; 2239 return 0; 2240 #endif 2241 return -EINVAL; 2242 } 2243 2244 if (strcmp("debug", arg) == 0) 2245 apic_verbosity = APIC_DEBUG; 2246 else if (strcmp("verbose", arg) == 0) 2247 apic_verbosity = APIC_VERBOSE; 2248 else { 2249 pr_warning("APIC Verbosity level %s not recognised" 2250 " use apic=verbose or apic=debug\n", arg); 2251 return -EINVAL; 2252 } 2253 2254 return 0; 2255 } 2256 early_param("apic", apic_set_verbosity); 2257 2258 static int __init lapic_insert_resource(void) 2259 { 2260 if (!apic_phys) 2261 return -1; 2262 2263 /* Put local APIC into the resource map. */ 2264 lapic_resource.start = apic_phys; 2265 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2266 insert_resource(&iomem_resource, &lapic_resource); 2267 2268 return 0; 2269 } 2270 2271 /* 2272 * need call insert after e820_reserve_resources() 2273 * that is using request_resource 2274 */ 2275 late_initcall(lapic_insert_resource); 2276