xref: /openbmc/linux/arch/x86/kernel/apic/apic.c (revision 82003e04)
1 /*
2  *	Local APIC handling, local APIC timers
3  *
4  *	(c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
5  *
6  *	Fixes
7  *	Maciej W. Rozycki	:	Bits for genuine 82489DX APICs;
8  *					thanks to Eric Gilmore
9  *					and Rolf G. Tews
10  *					for testing these extensively.
11  *	Maciej W. Rozycki	:	Various updates and fixes.
12  *	Mikael Pettersson	:	Power Management for UP-APIC.
13  *	Pavel Machek and
14  *	Mikael Pettersson	:	PM converted to driver model.
15  */
16 
17 #include <linux/perf_event.h>
18 #include <linux/kernel_stat.h>
19 #include <linux/mc146818rtc.h>
20 #include <linux/acpi_pmtmr.h>
21 #include <linux/clockchips.h>
22 #include <linux/interrupt.h>
23 #include <linux/bootmem.h>
24 #include <linux/ftrace.h>
25 #include <linux/ioport.h>
26 #include <linux/export.h>
27 #include <linux/syscore_ops.h>
28 #include <linux/delay.h>
29 #include <linux/timex.h>
30 #include <linux/i8253.h>
31 #include <linux/dmar.h>
32 #include <linux/init.h>
33 #include <linux/cpu.h>
34 #include <linux/dmi.h>
35 #include <linux/smp.h>
36 #include <linux/mm.h>
37 
38 #include <asm/trace/irq_vectors.h>
39 #include <asm/irq_remapping.h>
40 #include <asm/perf_event.h>
41 #include <asm/x86_init.h>
42 #include <asm/pgalloc.h>
43 #include <linux/atomic.h>
44 #include <asm/mpspec.h>
45 #include <asm/i8259.h>
46 #include <asm/proto.h>
47 #include <asm/apic.h>
48 #include <asm/io_apic.h>
49 #include <asm/desc.h>
50 #include <asm/hpet.h>
51 #include <asm/idle.h>
52 #include <asm/mtrr.h>
53 #include <asm/time.h>
54 #include <asm/smp.h>
55 #include <asm/mce.h>
56 #include <asm/tsc.h>
57 #include <asm/hypervisor.h>
58 
59 unsigned int num_processors;
60 
61 unsigned disabled_cpus;
62 
63 /* Processor that is doing the boot up */
64 unsigned int boot_cpu_physical_apicid = -1U;
65 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid);
66 
67 u8 boot_cpu_apic_version;
68 
69 /*
70  * The highest APIC ID seen during enumeration.
71  */
72 static unsigned int max_physical_apicid;
73 
74 /*
75  * Bitmask of physically existing CPUs:
76  */
77 physid_mask_t phys_cpu_present_map;
78 
79 /*
80  * Processor to be disabled specified by kernel parameter
81  * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to
82  * avoid undefined behaviour caused by sending INIT from AP to BSP.
83  */
84 static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID;
85 
86 /*
87  * This variable controls which CPUs receive external NMIs.  By default,
88  * external NMIs are delivered only to the BSP.
89  */
90 static int apic_extnmi = APIC_EXTNMI_BSP;
91 
92 /*
93  * Map cpu index to physical APIC ID
94  */
95 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID);
96 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID);
97 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX);
98 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid);
99 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid);
100 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid);
101 
102 #ifdef CONFIG_X86_32
103 
104 /*
105  * On x86_32, the mapping between cpu and logical apicid may vary
106  * depending on apic in use.  The following early percpu variable is
107  * used for the mapping.  This is where the behaviors of x86_64 and 32
108  * actually diverge.  Let's keep it ugly for now.
109  */
110 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID);
111 
112 /* Local APIC was disabled by the BIOS and enabled by the kernel */
113 static int enabled_via_apicbase;
114 
115 /*
116  * Handle interrupt mode configuration register (IMCR).
117  * This register controls whether the interrupt signals
118  * that reach the BSP come from the master PIC or from the
119  * local APIC. Before entering Symmetric I/O Mode, either
120  * the BIOS or the operating system must switch out of
121  * PIC Mode by changing the IMCR.
122  */
123 static inline void imcr_pic_to_apic(void)
124 {
125 	/* select IMCR register */
126 	outb(0x70, 0x22);
127 	/* NMI and 8259 INTR go through APIC */
128 	outb(0x01, 0x23);
129 }
130 
131 static inline void imcr_apic_to_pic(void)
132 {
133 	/* select IMCR register */
134 	outb(0x70, 0x22);
135 	/* NMI and 8259 INTR go directly to BSP */
136 	outb(0x00, 0x23);
137 }
138 #endif
139 
140 /*
141  * Knob to control our willingness to enable the local APIC.
142  *
143  * +1=force-enable
144  */
145 static int force_enable_local_apic __initdata;
146 
147 /*
148  * APIC command line parameters
149  */
150 static int __init parse_lapic(char *arg)
151 {
152 	if (IS_ENABLED(CONFIG_X86_32) && !arg)
153 		force_enable_local_apic = 1;
154 	else if (arg && !strncmp(arg, "notscdeadline", 13))
155 		setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
156 	return 0;
157 }
158 early_param("lapic", parse_lapic);
159 
160 #ifdef CONFIG_X86_64
161 static int apic_calibrate_pmtmr __initdata;
162 static __init int setup_apicpmtimer(char *s)
163 {
164 	apic_calibrate_pmtmr = 1;
165 	notsc_setup(NULL);
166 	return 0;
167 }
168 __setup("apicpmtimer", setup_apicpmtimer);
169 #endif
170 
171 unsigned long mp_lapic_addr;
172 int disable_apic;
173 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
174 static int disable_apic_timer __initdata;
175 /* Local APIC timer works in C2 */
176 int local_apic_timer_c2_ok;
177 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
178 
179 int first_system_vector = FIRST_SYSTEM_VECTOR;
180 
181 /*
182  * Debug level, exported for io_apic.c
183  */
184 unsigned int apic_verbosity;
185 
186 int pic_mode;
187 
188 /* Have we found an MP table */
189 int smp_found_config;
190 
191 static struct resource lapic_resource = {
192 	.name = "Local APIC",
193 	.flags = IORESOURCE_MEM | IORESOURCE_BUSY,
194 };
195 
196 unsigned int lapic_timer_frequency = 0;
197 
198 static void apic_pm_activate(void);
199 
200 static unsigned long apic_phys;
201 
202 /*
203  * Get the LAPIC version
204  */
205 static inline int lapic_get_version(void)
206 {
207 	return GET_APIC_VERSION(apic_read(APIC_LVR));
208 }
209 
210 /*
211  * Check, if the APIC is integrated or a separate chip
212  */
213 static inline int lapic_is_integrated(void)
214 {
215 #ifdef CONFIG_X86_64
216 	return 1;
217 #else
218 	return APIC_INTEGRATED(lapic_get_version());
219 #endif
220 }
221 
222 /*
223  * Check, whether this is a modern or a first generation APIC
224  */
225 static int modern_apic(void)
226 {
227 	/* AMD systems use old APIC versions, so check the CPU */
228 	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
229 	    boot_cpu_data.x86 >= 0xf)
230 		return 1;
231 	return lapic_get_version() >= 0x14;
232 }
233 
234 /*
235  * right after this call apic become NOOP driven
236  * so apic->write/read doesn't do anything
237  */
238 static void __init apic_disable(void)
239 {
240 	pr_info("APIC: switched to apic NOOP\n");
241 	apic = &apic_noop;
242 }
243 
244 void native_apic_wait_icr_idle(void)
245 {
246 	while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
247 		cpu_relax();
248 }
249 
250 u32 native_safe_apic_wait_icr_idle(void)
251 {
252 	u32 send_status;
253 	int timeout;
254 
255 	timeout = 0;
256 	do {
257 		send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
258 		if (!send_status)
259 			break;
260 		inc_irq_stat(icr_read_retry_count);
261 		udelay(100);
262 	} while (timeout++ < 1000);
263 
264 	return send_status;
265 }
266 
267 void native_apic_icr_write(u32 low, u32 id)
268 {
269 	unsigned long flags;
270 
271 	local_irq_save(flags);
272 	apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
273 	apic_write(APIC_ICR, low);
274 	local_irq_restore(flags);
275 }
276 
277 u64 native_apic_icr_read(void)
278 {
279 	u32 icr1, icr2;
280 
281 	icr2 = apic_read(APIC_ICR2);
282 	icr1 = apic_read(APIC_ICR);
283 
284 	return icr1 | ((u64)icr2 << 32);
285 }
286 
287 #ifdef CONFIG_X86_32
288 /**
289  * get_physical_broadcast - Get number of physical broadcast IDs
290  */
291 int get_physical_broadcast(void)
292 {
293 	return modern_apic() ? 0xff : 0xf;
294 }
295 #endif
296 
297 /**
298  * lapic_get_maxlvt - get the maximum number of local vector table entries
299  */
300 int lapic_get_maxlvt(void)
301 {
302 	unsigned int v;
303 
304 	v = apic_read(APIC_LVR);
305 	/*
306 	 * - we always have APIC integrated on 64bit mode
307 	 * - 82489DXs do not report # of LVT entries
308 	 */
309 	return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
310 }
311 
312 /*
313  * Local APIC timer
314  */
315 
316 /* Clock divisor */
317 #define APIC_DIVISOR 16
318 #define TSC_DIVISOR  8
319 
320 /*
321  * This function sets up the local APIC timer, with a timeout of
322  * 'clocks' APIC bus clock. During calibration we actually call
323  * this function twice on the boot CPU, once with a bogus timeout
324  * value, second time for real. The other (noncalibrating) CPUs
325  * call this function only once, with the real, calibrated value.
326  *
327  * We do reads before writes even if unnecessary, to get around the
328  * P5 APIC double write bug.
329  */
330 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
331 {
332 	unsigned int lvtt_value, tmp_value;
333 
334 	lvtt_value = LOCAL_TIMER_VECTOR;
335 	if (!oneshot)
336 		lvtt_value |= APIC_LVT_TIMER_PERIODIC;
337 	else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
338 		lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE;
339 
340 	if (!lapic_is_integrated())
341 		lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
342 
343 	if (!irqen)
344 		lvtt_value |= APIC_LVT_MASKED;
345 
346 	apic_write(APIC_LVTT, lvtt_value);
347 
348 	if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) {
349 		/*
350 		 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode,
351 		 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized.
352 		 * According to Intel, MFENCE can do the serialization here.
353 		 */
354 		asm volatile("mfence" : : : "memory");
355 
356 		printk_once(KERN_DEBUG "TSC deadline timer enabled\n");
357 		return;
358 	}
359 
360 	/*
361 	 * Divide PICLK by 16
362 	 */
363 	tmp_value = apic_read(APIC_TDCR);
364 	apic_write(APIC_TDCR,
365 		(tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
366 		APIC_TDR_DIV_16);
367 
368 	if (!oneshot)
369 		apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
370 }
371 
372 /*
373  * Setup extended LVT, AMD specific
374  *
375  * Software should use the LVT offsets the BIOS provides.  The offsets
376  * are determined by the subsystems using it like those for MCE
377  * threshold or IBS.  On K8 only offset 0 (APIC500) and MCE interrupts
378  * are supported. Beginning with family 10h at least 4 offsets are
379  * available.
380  *
381  * Since the offsets must be consistent for all cores, we keep track
382  * of the LVT offsets in software and reserve the offset for the same
383  * vector also to be used on other cores. An offset is freed by
384  * setting the entry to APIC_EILVT_MASKED.
385  *
386  * If the BIOS is right, there should be no conflicts. Otherwise a
387  * "[Firmware Bug]: ..." error message is generated. However, if
388  * software does not properly determines the offsets, it is not
389  * necessarily a BIOS bug.
390  */
391 
392 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX];
393 
394 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new)
395 {
396 	return (old & APIC_EILVT_MASKED)
397 		|| (new == APIC_EILVT_MASKED)
398 		|| ((new & ~APIC_EILVT_MASKED) == old);
399 }
400 
401 static unsigned int reserve_eilvt_offset(int offset, unsigned int new)
402 {
403 	unsigned int rsvd, vector;
404 
405 	if (offset >= APIC_EILVT_NR_MAX)
406 		return ~0;
407 
408 	rsvd = atomic_read(&eilvt_offsets[offset]);
409 	do {
410 		vector = rsvd & ~APIC_EILVT_MASKED;	/* 0: unassigned */
411 		if (vector && !eilvt_entry_is_changeable(vector, new))
412 			/* may not change if vectors are different */
413 			return rsvd;
414 		rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new);
415 	} while (rsvd != new);
416 
417 	rsvd &= ~APIC_EILVT_MASKED;
418 	if (rsvd && rsvd != vector)
419 		pr_info("LVT offset %d assigned for vector 0x%02x\n",
420 			offset, rsvd);
421 
422 	return new;
423 }
424 
425 /*
426  * If mask=1, the LVT entry does not generate interrupts while mask=0
427  * enables the vector. See also the BKDGs. Must be called with
428  * preemption disabled.
429  */
430 
431 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask)
432 {
433 	unsigned long reg = APIC_EILVTn(offset);
434 	unsigned int new, old, reserved;
435 
436 	new = (mask << 16) | (msg_type << 8) | vector;
437 	old = apic_read(reg);
438 	reserved = reserve_eilvt_offset(offset, new);
439 
440 	if (reserved != new) {
441 		pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
442 		       "vector 0x%x, but the register is already in use for "
443 		       "vector 0x%x on another cpu\n",
444 		       smp_processor_id(), reg, offset, new, reserved);
445 		return -EINVAL;
446 	}
447 
448 	if (!eilvt_entry_is_changeable(old, new)) {
449 		pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for "
450 		       "vector 0x%x, but the register is already in use for "
451 		       "vector 0x%x on this cpu\n",
452 		       smp_processor_id(), reg, offset, new, old);
453 		return -EBUSY;
454 	}
455 
456 	apic_write(reg, new);
457 
458 	return 0;
459 }
460 EXPORT_SYMBOL_GPL(setup_APIC_eilvt);
461 
462 /*
463  * Program the next event, relative to now
464  */
465 static int lapic_next_event(unsigned long delta,
466 			    struct clock_event_device *evt)
467 {
468 	apic_write(APIC_TMICT, delta);
469 	return 0;
470 }
471 
472 static int lapic_next_deadline(unsigned long delta,
473 			       struct clock_event_device *evt)
474 {
475 	u64 tsc;
476 
477 	tsc = rdtsc();
478 	wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR));
479 	return 0;
480 }
481 
482 static int lapic_timer_shutdown(struct clock_event_device *evt)
483 {
484 	unsigned int v;
485 
486 	/* Lapic used as dummy for broadcast ? */
487 	if (evt->features & CLOCK_EVT_FEAT_DUMMY)
488 		return 0;
489 
490 	v = apic_read(APIC_LVTT);
491 	v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
492 	apic_write(APIC_LVTT, v);
493 	apic_write(APIC_TMICT, 0);
494 	return 0;
495 }
496 
497 static inline int
498 lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot)
499 {
500 	/* Lapic used as dummy for broadcast ? */
501 	if (evt->features & CLOCK_EVT_FEAT_DUMMY)
502 		return 0;
503 
504 	__setup_APIC_LVTT(lapic_timer_frequency, oneshot, 1);
505 	return 0;
506 }
507 
508 static int lapic_timer_set_periodic(struct clock_event_device *evt)
509 {
510 	return lapic_timer_set_periodic_oneshot(evt, false);
511 }
512 
513 static int lapic_timer_set_oneshot(struct clock_event_device *evt)
514 {
515 	return lapic_timer_set_periodic_oneshot(evt, true);
516 }
517 
518 /*
519  * Local APIC timer broadcast function
520  */
521 static void lapic_timer_broadcast(const struct cpumask *mask)
522 {
523 #ifdef CONFIG_SMP
524 	apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
525 #endif
526 }
527 
528 
529 /*
530  * The local apic timer can be used for any function which is CPU local.
531  */
532 static struct clock_event_device lapic_clockevent = {
533 	.name			= "lapic",
534 	.features		= CLOCK_EVT_FEAT_PERIODIC |
535 				  CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP
536 				  | CLOCK_EVT_FEAT_DUMMY,
537 	.shift			= 32,
538 	.set_state_shutdown	= lapic_timer_shutdown,
539 	.set_state_periodic	= lapic_timer_set_periodic,
540 	.set_state_oneshot	= lapic_timer_set_oneshot,
541 	.set_next_event		= lapic_next_event,
542 	.broadcast		= lapic_timer_broadcast,
543 	.rating			= 100,
544 	.irq			= -1,
545 };
546 static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
547 
548 /*
549  * Setup the local APIC timer for this CPU. Copy the initialized values
550  * of the boot CPU and register the clock event in the framework.
551  */
552 static void setup_APIC_timer(void)
553 {
554 	struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
555 
556 	if (this_cpu_has(X86_FEATURE_ARAT)) {
557 		lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP;
558 		/* Make LAPIC timer preferrable over percpu HPET */
559 		lapic_clockevent.rating = 150;
560 	}
561 
562 	memcpy(levt, &lapic_clockevent, sizeof(*levt));
563 	levt->cpumask = cpumask_of(smp_processor_id());
564 
565 	if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
566 		levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC |
567 				    CLOCK_EVT_FEAT_DUMMY);
568 		levt->set_next_event = lapic_next_deadline;
569 		clockevents_config_and_register(levt,
570 						tsc_khz * (1000 / TSC_DIVISOR),
571 						0xF, ~0UL);
572 	} else
573 		clockevents_register_device(levt);
574 }
575 
576 /*
577  * Install the updated TSC frequency from recalibration at the TSC
578  * deadline clockevent devices.
579  */
580 static void __lapic_update_tsc_freq(void *info)
581 {
582 	struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
583 
584 	if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER))
585 		return;
586 
587 	clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR));
588 }
589 
590 void lapic_update_tsc_freq(void)
591 {
592 	/*
593 	 * The clockevent device's ->mult and ->shift can both be
594 	 * changed. In order to avoid races, schedule the frequency
595 	 * update code on each CPU.
596 	 */
597 	on_each_cpu(__lapic_update_tsc_freq, NULL, 0);
598 }
599 
600 /*
601  * In this functions we calibrate APIC bus clocks to the external timer.
602  *
603  * We want to do the calibration only once since we want to have local timer
604  * irqs syncron. CPUs connected by the same APIC bus have the very same bus
605  * frequency.
606  *
607  * This was previously done by reading the PIT/HPET and waiting for a wrap
608  * around to find out, that a tick has elapsed. I have a box, where the PIT
609  * readout is broken, so it never gets out of the wait loop again. This was
610  * also reported by others.
611  *
612  * Monitoring the jiffies value is inaccurate and the clockevents
613  * infrastructure allows us to do a simple substitution of the interrupt
614  * handler.
615  *
616  * The calibration routine also uses the pm_timer when possible, as the PIT
617  * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
618  * back to normal later in the boot process).
619  */
620 
621 #define LAPIC_CAL_LOOPS		(HZ/10)
622 
623 static __initdata int lapic_cal_loops = -1;
624 static __initdata long lapic_cal_t1, lapic_cal_t2;
625 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
626 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
627 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
628 
629 /*
630  * Temporary interrupt handler.
631  */
632 static void __init lapic_cal_handler(struct clock_event_device *dev)
633 {
634 	unsigned long long tsc = 0;
635 	long tapic = apic_read(APIC_TMCCT);
636 	unsigned long pm = acpi_pm_read_early();
637 
638 	if (boot_cpu_has(X86_FEATURE_TSC))
639 		tsc = rdtsc();
640 
641 	switch (lapic_cal_loops++) {
642 	case 0:
643 		lapic_cal_t1 = tapic;
644 		lapic_cal_tsc1 = tsc;
645 		lapic_cal_pm1 = pm;
646 		lapic_cal_j1 = jiffies;
647 		break;
648 
649 	case LAPIC_CAL_LOOPS:
650 		lapic_cal_t2 = tapic;
651 		lapic_cal_tsc2 = tsc;
652 		if (pm < lapic_cal_pm1)
653 			pm += ACPI_PM_OVRRUN;
654 		lapic_cal_pm2 = pm;
655 		lapic_cal_j2 = jiffies;
656 		break;
657 	}
658 }
659 
660 static int __init
661 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc)
662 {
663 	const long pm_100ms = PMTMR_TICKS_PER_SEC / 10;
664 	const long pm_thresh = pm_100ms / 100;
665 	unsigned long mult;
666 	u64 res;
667 
668 #ifndef CONFIG_X86_PM_TIMER
669 	return -1;
670 #endif
671 
672 	apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm);
673 
674 	/* Check, if the PM timer is available */
675 	if (!deltapm)
676 		return -1;
677 
678 	mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
679 
680 	if (deltapm > (pm_100ms - pm_thresh) &&
681 	    deltapm < (pm_100ms + pm_thresh)) {
682 		apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n");
683 		return 0;
684 	}
685 
686 	res = (((u64)deltapm) *  mult) >> 22;
687 	do_div(res, 1000000);
688 	pr_warning("APIC calibration not consistent "
689 		   "with PM-Timer: %ldms instead of 100ms\n",(long)res);
690 
691 	/* Correct the lapic counter value */
692 	res = (((u64)(*delta)) * pm_100ms);
693 	do_div(res, deltapm);
694 	pr_info("APIC delta adjusted to PM-Timer: "
695 		"%lu (%ld)\n", (unsigned long)res, *delta);
696 	*delta = (long)res;
697 
698 	/* Correct the tsc counter value */
699 	if (boot_cpu_has(X86_FEATURE_TSC)) {
700 		res = (((u64)(*deltatsc)) * pm_100ms);
701 		do_div(res, deltapm);
702 		apic_printk(APIC_VERBOSE, "TSC delta adjusted to "
703 					  "PM-Timer: %lu (%ld)\n",
704 					(unsigned long)res, *deltatsc);
705 		*deltatsc = (long)res;
706 	}
707 
708 	return 0;
709 }
710 
711 static int __init calibrate_APIC_clock(void)
712 {
713 	struct clock_event_device *levt = this_cpu_ptr(&lapic_events);
714 	void (*real_handler)(struct clock_event_device *dev);
715 	unsigned long deltaj;
716 	long delta, deltatsc;
717 	int pm_referenced = 0;
718 
719 	/**
720 	 * check if lapic timer has already been calibrated by platform
721 	 * specific routine, such as tsc calibration code. if so, we just fill
722 	 * in the clockevent structure and return.
723 	 */
724 
725 	if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) {
726 		return 0;
727 	} else if (lapic_timer_frequency) {
728 		apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n",
729 				lapic_timer_frequency);
730 		lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR,
731 					TICK_NSEC, lapic_clockevent.shift);
732 		lapic_clockevent.max_delta_ns =
733 			clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
734 		lapic_clockevent.min_delta_ns =
735 			clockevent_delta2ns(0xF, &lapic_clockevent);
736 		lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
737 		return 0;
738 	}
739 
740 	apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
741 		    "calibrating APIC timer ...\n");
742 
743 	local_irq_disable();
744 
745 	/* Replace the global interrupt handler */
746 	real_handler = global_clock_event->event_handler;
747 	global_clock_event->event_handler = lapic_cal_handler;
748 
749 	/*
750 	 * Setup the APIC counter to maximum. There is no way the lapic
751 	 * can underflow in the 100ms detection time frame
752 	 */
753 	__setup_APIC_LVTT(0xffffffff, 0, 0);
754 
755 	/* Let the interrupts run */
756 	local_irq_enable();
757 
758 	while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
759 		cpu_relax();
760 
761 	local_irq_disable();
762 
763 	/* Restore the real event handler */
764 	global_clock_event->event_handler = real_handler;
765 
766 	/* Build delta t1-t2 as apic timer counts down */
767 	delta = lapic_cal_t1 - lapic_cal_t2;
768 	apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
769 
770 	deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
771 
772 	/* we trust the PM based calibration if possible */
773 	pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1,
774 					&delta, &deltatsc);
775 
776 	/* Calculate the scaled math multiplication factor */
777 	lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
778 				       lapic_clockevent.shift);
779 	lapic_clockevent.max_delta_ns =
780 		clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent);
781 	lapic_clockevent.min_delta_ns =
782 		clockevent_delta2ns(0xF, &lapic_clockevent);
783 
784 	lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
785 
786 	apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
787 	apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult);
788 	apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
789 		    lapic_timer_frequency);
790 
791 	if (boot_cpu_has(X86_FEATURE_TSC)) {
792 		apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
793 			    "%ld.%04ld MHz.\n",
794 			    (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ),
795 			    (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ));
796 	}
797 
798 	apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
799 		    "%u.%04u MHz.\n",
800 		    lapic_timer_frequency / (1000000 / HZ),
801 		    lapic_timer_frequency % (1000000 / HZ));
802 
803 	/*
804 	 * Do a sanity check on the APIC calibration result
805 	 */
806 	if (lapic_timer_frequency < (1000000 / HZ)) {
807 		local_irq_enable();
808 		pr_warning("APIC frequency too slow, disabling apic timer\n");
809 		return -1;
810 	}
811 
812 	levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
813 
814 	/*
815 	 * PM timer calibration failed or not turned on
816 	 * so lets try APIC timer based calibration
817 	 */
818 	if (!pm_referenced) {
819 		apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
820 
821 		/*
822 		 * Setup the apic timer manually
823 		 */
824 		levt->event_handler = lapic_cal_handler;
825 		lapic_timer_set_periodic(levt);
826 		lapic_cal_loops = -1;
827 
828 		/* Let the interrupts run */
829 		local_irq_enable();
830 
831 		while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
832 			cpu_relax();
833 
834 		/* Stop the lapic timer */
835 		local_irq_disable();
836 		lapic_timer_shutdown(levt);
837 
838 		/* Jiffies delta */
839 		deltaj = lapic_cal_j2 - lapic_cal_j1;
840 		apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
841 
842 		/* Check, if the jiffies result is consistent */
843 		if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
844 			apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
845 		else
846 			levt->features |= CLOCK_EVT_FEAT_DUMMY;
847 	}
848 	local_irq_enable();
849 
850 	if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
851 		pr_warning("APIC timer disabled due to verification failure\n");
852 			return -1;
853 	}
854 
855 	return 0;
856 }
857 
858 /*
859  * Setup the boot APIC
860  *
861  * Calibrate and verify the result.
862  */
863 void __init setup_boot_APIC_clock(void)
864 {
865 	/*
866 	 * The local apic timer can be disabled via the kernel
867 	 * commandline or from the CPU detection code. Register the lapic
868 	 * timer as a dummy clock event source on SMP systems, so the
869 	 * broadcast mechanism is used. On UP systems simply ignore it.
870 	 */
871 	if (disable_apic_timer) {
872 		pr_info("Disabling APIC timer\n");
873 		/* No broadcast on UP ! */
874 		if (num_possible_cpus() > 1) {
875 			lapic_clockevent.mult = 1;
876 			setup_APIC_timer();
877 		}
878 		return;
879 	}
880 
881 	if (calibrate_APIC_clock()) {
882 		/* No broadcast on UP ! */
883 		if (num_possible_cpus() > 1)
884 			setup_APIC_timer();
885 		return;
886 	}
887 
888 	/*
889 	 * If nmi_watchdog is set to IO_APIC, we need the
890 	 * PIT/HPET going.  Otherwise register lapic as a dummy
891 	 * device.
892 	 */
893 	lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
894 
895 	/* Setup the lapic or request the broadcast */
896 	setup_APIC_timer();
897 }
898 
899 void setup_secondary_APIC_clock(void)
900 {
901 	setup_APIC_timer();
902 }
903 
904 /*
905  * The guts of the apic timer interrupt
906  */
907 static void local_apic_timer_interrupt(void)
908 {
909 	int cpu = smp_processor_id();
910 	struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
911 
912 	/*
913 	 * Normally we should not be here till LAPIC has been initialized but
914 	 * in some cases like kdump, its possible that there is a pending LAPIC
915 	 * timer interrupt from previous kernel's context and is delivered in
916 	 * new kernel the moment interrupts are enabled.
917 	 *
918 	 * Interrupts are enabled early and LAPIC is setup much later, hence
919 	 * its possible that when we get here evt->event_handler is NULL.
920 	 * Check for event_handler being NULL and discard the interrupt as
921 	 * spurious.
922 	 */
923 	if (!evt->event_handler) {
924 		pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu);
925 		/* Switch it off */
926 		lapic_timer_shutdown(evt);
927 		return;
928 	}
929 
930 	/*
931 	 * the NMI deadlock-detector uses this.
932 	 */
933 	inc_irq_stat(apic_timer_irqs);
934 
935 	evt->event_handler(evt);
936 }
937 
938 /*
939  * Local APIC timer interrupt. This is the most natural way for doing
940  * local interrupts, but local timer interrupts can be emulated by
941  * broadcast interrupts too. [in case the hw doesn't support APIC timers]
942  *
943  * [ if a single-CPU system runs an SMP kernel then we call the local
944  *   interrupt as well. Thus we cannot inline the local irq ... ]
945  */
946 __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs)
947 {
948 	struct pt_regs *old_regs = set_irq_regs(regs);
949 
950 	/*
951 	 * NOTE! We'd better ACK the irq immediately,
952 	 * because timer handling can be slow.
953 	 *
954 	 * update_process_times() expects us to have done irq_enter().
955 	 * Besides, if we don't timer interrupts ignore the global
956 	 * interrupt lock, which is the WrongThing (tm) to do.
957 	 */
958 	entering_ack_irq();
959 	local_apic_timer_interrupt();
960 	exiting_irq();
961 
962 	set_irq_regs(old_regs);
963 }
964 
965 __visible void __irq_entry smp_trace_apic_timer_interrupt(struct pt_regs *regs)
966 {
967 	struct pt_regs *old_regs = set_irq_regs(regs);
968 
969 	/*
970 	 * NOTE! We'd better ACK the irq immediately,
971 	 * because timer handling can be slow.
972 	 *
973 	 * update_process_times() expects us to have done irq_enter().
974 	 * Besides, if we don't timer interrupts ignore the global
975 	 * interrupt lock, which is the WrongThing (tm) to do.
976 	 */
977 	entering_ack_irq();
978 	trace_local_timer_entry(LOCAL_TIMER_VECTOR);
979 	local_apic_timer_interrupt();
980 	trace_local_timer_exit(LOCAL_TIMER_VECTOR);
981 	exiting_irq();
982 
983 	set_irq_regs(old_regs);
984 }
985 
986 int setup_profiling_timer(unsigned int multiplier)
987 {
988 	return -EINVAL;
989 }
990 
991 /*
992  * Local APIC start and shutdown
993  */
994 
995 /**
996  * clear_local_APIC - shutdown the local APIC
997  *
998  * This is called, when a CPU is disabled and before rebooting, so the state of
999  * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
1000  * leftovers during boot.
1001  */
1002 void clear_local_APIC(void)
1003 {
1004 	int maxlvt;
1005 	u32 v;
1006 
1007 	/* APIC hasn't been mapped yet */
1008 	if (!x2apic_mode && !apic_phys)
1009 		return;
1010 
1011 	maxlvt = lapic_get_maxlvt();
1012 	/*
1013 	 * Masking an LVT entry can trigger a local APIC error
1014 	 * if the vector is zero. Mask LVTERR first to prevent this.
1015 	 */
1016 	if (maxlvt >= 3) {
1017 		v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
1018 		apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
1019 	}
1020 	/*
1021 	 * Careful: we have to set masks only first to deassert
1022 	 * any level-triggered sources.
1023 	 */
1024 	v = apic_read(APIC_LVTT);
1025 	apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
1026 	v = apic_read(APIC_LVT0);
1027 	apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1028 	v = apic_read(APIC_LVT1);
1029 	apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
1030 	if (maxlvt >= 4) {
1031 		v = apic_read(APIC_LVTPC);
1032 		apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
1033 	}
1034 
1035 	/* lets not touch this if we didn't frob it */
1036 #ifdef CONFIG_X86_THERMAL_VECTOR
1037 	if (maxlvt >= 5) {
1038 		v = apic_read(APIC_LVTTHMR);
1039 		apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
1040 	}
1041 #endif
1042 #ifdef CONFIG_X86_MCE_INTEL
1043 	if (maxlvt >= 6) {
1044 		v = apic_read(APIC_LVTCMCI);
1045 		if (!(v & APIC_LVT_MASKED))
1046 			apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED);
1047 	}
1048 #endif
1049 
1050 	/*
1051 	 * Clean APIC state for other OSs:
1052 	 */
1053 	apic_write(APIC_LVTT, APIC_LVT_MASKED);
1054 	apic_write(APIC_LVT0, APIC_LVT_MASKED);
1055 	apic_write(APIC_LVT1, APIC_LVT_MASKED);
1056 	if (maxlvt >= 3)
1057 		apic_write(APIC_LVTERR, APIC_LVT_MASKED);
1058 	if (maxlvt >= 4)
1059 		apic_write(APIC_LVTPC, APIC_LVT_MASKED);
1060 
1061 	/* Integrated APIC (!82489DX) ? */
1062 	if (lapic_is_integrated()) {
1063 		if (maxlvt > 3)
1064 			/* Clear ESR due to Pentium errata 3AP and 11AP */
1065 			apic_write(APIC_ESR, 0);
1066 		apic_read(APIC_ESR);
1067 	}
1068 }
1069 
1070 /**
1071  * disable_local_APIC - clear and disable the local APIC
1072  */
1073 void disable_local_APIC(void)
1074 {
1075 	unsigned int value;
1076 
1077 	/* APIC hasn't been mapped yet */
1078 	if (!x2apic_mode && !apic_phys)
1079 		return;
1080 
1081 	clear_local_APIC();
1082 
1083 	/*
1084 	 * Disable APIC (implies clearing of registers
1085 	 * for 82489DX!).
1086 	 */
1087 	value = apic_read(APIC_SPIV);
1088 	value &= ~APIC_SPIV_APIC_ENABLED;
1089 	apic_write(APIC_SPIV, value);
1090 
1091 #ifdef CONFIG_X86_32
1092 	/*
1093 	 * When LAPIC was disabled by the BIOS and enabled by the kernel,
1094 	 * restore the disabled state.
1095 	 */
1096 	if (enabled_via_apicbase) {
1097 		unsigned int l, h;
1098 
1099 		rdmsr(MSR_IA32_APICBASE, l, h);
1100 		l &= ~MSR_IA32_APICBASE_ENABLE;
1101 		wrmsr(MSR_IA32_APICBASE, l, h);
1102 	}
1103 #endif
1104 }
1105 
1106 /*
1107  * If Linux enabled the LAPIC against the BIOS default disable it down before
1108  * re-entering the BIOS on shutdown.  Otherwise the BIOS may get confused and
1109  * not power-off.  Additionally clear all LVT entries before disable_local_APIC
1110  * for the case where Linux didn't enable the LAPIC.
1111  */
1112 void lapic_shutdown(void)
1113 {
1114 	unsigned long flags;
1115 
1116 	if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config())
1117 		return;
1118 
1119 	local_irq_save(flags);
1120 
1121 #ifdef CONFIG_X86_32
1122 	if (!enabled_via_apicbase)
1123 		clear_local_APIC();
1124 	else
1125 #endif
1126 		disable_local_APIC();
1127 
1128 
1129 	local_irq_restore(flags);
1130 }
1131 
1132 /**
1133  * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1134  */
1135 void __init sync_Arb_IDs(void)
1136 {
1137 	/*
1138 	 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1139 	 * needed on AMD.
1140 	 */
1141 	if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1142 		return;
1143 
1144 	/*
1145 	 * Wait for idle.
1146 	 */
1147 	apic_wait_icr_idle();
1148 
1149 	apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1150 	apic_write(APIC_ICR, APIC_DEST_ALLINC |
1151 			APIC_INT_LEVELTRIG | APIC_DM_INIT);
1152 }
1153 
1154 /*
1155  * An initial setup of the virtual wire mode.
1156  */
1157 void __init init_bsp_APIC(void)
1158 {
1159 	unsigned int value;
1160 
1161 	/*
1162 	 * Don't do the setup now if we have a SMP BIOS as the
1163 	 * through-I/O-APIC virtual wire mode might be active.
1164 	 */
1165 	if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC))
1166 		return;
1167 
1168 	/*
1169 	 * Do not trust the local APIC being empty at bootup.
1170 	 */
1171 	clear_local_APIC();
1172 
1173 	/*
1174 	 * Enable APIC.
1175 	 */
1176 	value = apic_read(APIC_SPIV);
1177 	value &= ~APIC_VECTOR_MASK;
1178 	value |= APIC_SPIV_APIC_ENABLED;
1179 
1180 #ifdef CONFIG_X86_32
1181 	/* This bit is reserved on P4/Xeon and should be cleared */
1182 	if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1183 	    (boot_cpu_data.x86 == 15))
1184 		value &= ~APIC_SPIV_FOCUS_DISABLED;
1185 	else
1186 #endif
1187 		value |= APIC_SPIV_FOCUS_DISABLED;
1188 	value |= SPURIOUS_APIC_VECTOR;
1189 	apic_write(APIC_SPIV, value);
1190 
1191 	/*
1192 	 * Set up the virtual wire mode.
1193 	 */
1194 	apic_write(APIC_LVT0, APIC_DM_EXTINT);
1195 	value = APIC_DM_NMI;
1196 	if (!lapic_is_integrated())		/* 82489DX */
1197 		value |= APIC_LVT_LEVEL_TRIGGER;
1198 	if (apic_extnmi == APIC_EXTNMI_NONE)
1199 		value |= APIC_LVT_MASKED;
1200 	apic_write(APIC_LVT1, value);
1201 }
1202 
1203 static void lapic_setup_esr(void)
1204 {
1205 	unsigned int oldvalue, value, maxlvt;
1206 
1207 	if (!lapic_is_integrated()) {
1208 		pr_info("No ESR for 82489DX.\n");
1209 		return;
1210 	}
1211 
1212 	if (apic->disable_esr) {
1213 		/*
1214 		 * Something untraceable is creating bad interrupts on
1215 		 * secondary quads ... for the moment, just leave the
1216 		 * ESR disabled - we can't do anything useful with the
1217 		 * errors anyway - mbligh
1218 		 */
1219 		pr_info("Leaving ESR disabled.\n");
1220 		return;
1221 	}
1222 
1223 	maxlvt = lapic_get_maxlvt();
1224 	if (maxlvt > 3)		/* Due to the Pentium erratum 3AP. */
1225 		apic_write(APIC_ESR, 0);
1226 	oldvalue = apic_read(APIC_ESR);
1227 
1228 	/* enables sending errors */
1229 	value = ERROR_APIC_VECTOR;
1230 	apic_write(APIC_LVTERR, value);
1231 
1232 	/*
1233 	 * spec says clear errors after enabling vector.
1234 	 */
1235 	if (maxlvt > 3)
1236 		apic_write(APIC_ESR, 0);
1237 	value = apic_read(APIC_ESR);
1238 	if (value != oldvalue)
1239 		apic_printk(APIC_VERBOSE, "ESR value before enabling "
1240 			"vector: 0x%08x  after: 0x%08x\n",
1241 			oldvalue, value);
1242 }
1243 
1244 /**
1245  * setup_local_APIC - setup the local APIC
1246  *
1247  * Used to setup local APIC while initializing BSP or bringin up APs.
1248  * Always called with preemption disabled.
1249  */
1250 void setup_local_APIC(void)
1251 {
1252 	int cpu = smp_processor_id();
1253 	unsigned int value, queued;
1254 	int i, j, acked = 0;
1255 	unsigned long long tsc = 0, ntsc;
1256 	long long max_loops = cpu_khz ? cpu_khz : 1000000;
1257 
1258 	if (boot_cpu_has(X86_FEATURE_TSC))
1259 		tsc = rdtsc();
1260 
1261 	if (disable_apic) {
1262 		disable_ioapic_support();
1263 		return;
1264 	}
1265 
1266 #ifdef CONFIG_X86_32
1267 	/* Pound the ESR really hard over the head with a big hammer - mbligh */
1268 	if (lapic_is_integrated() && apic->disable_esr) {
1269 		apic_write(APIC_ESR, 0);
1270 		apic_write(APIC_ESR, 0);
1271 		apic_write(APIC_ESR, 0);
1272 		apic_write(APIC_ESR, 0);
1273 	}
1274 #endif
1275 	perf_events_lapic_init();
1276 
1277 	/*
1278 	 * Double-check whether this APIC is really registered.
1279 	 * This is meaningless in clustered apic mode, so we skip it.
1280 	 */
1281 	BUG_ON(!apic->apic_id_registered());
1282 
1283 	/*
1284 	 * Intel recommends to set DFR, LDR and TPR before enabling
1285 	 * an APIC.  See e.g. "AP-388 82489DX User's Manual" (Intel
1286 	 * document number 292116).  So here it goes...
1287 	 */
1288 	apic->init_apic_ldr();
1289 
1290 #ifdef CONFIG_X86_32
1291 	/*
1292 	 * APIC LDR is initialized.  If logical_apicid mapping was
1293 	 * initialized during get_smp_config(), make sure it matches the
1294 	 * actual value.
1295 	 */
1296 	i = early_per_cpu(x86_cpu_to_logical_apicid, cpu);
1297 	WARN_ON(i != BAD_APICID && i != logical_smp_processor_id());
1298 	/* always use the value from LDR */
1299 	early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
1300 		logical_smp_processor_id();
1301 #endif
1302 
1303 	/*
1304 	 * Set Task Priority to 'accept all'. We never change this
1305 	 * later on.
1306 	 */
1307 	value = apic_read(APIC_TASKPRI);
1308 	value &= ~APIC_TPRI_MASK;
1309 	apic_write(APIC_TASKPRI, value);
1310 
1311 	/*
1312 	 * After a crash, we no longer service the interrupts and a pending
1313 	 * interrupt from previous kernel might still have ISR bit set.
1314 	 *
1315 	 * Most probably by now CPU has serviced that pending interrupt and
1316 	 * it might not have done the ack_APIC_irq() because it thought,
1317 	 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1318 	 * does not clear the ISR bit and cpu thinks it has already serivced
1319 	 * the interrupt. Hence a vector might get locked. It was noticed
1320 	 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1321 	 */
1322 	do {
1323 		queued = 0;
1324 		for (i = APIC_ISR_NR - 1; i >= 0; i--)
1325 			queued |= apic_read(APIC_IRR + i*0x10);
1326 
1327 		for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1328 			value = apic_read(APIC_ISR + i*0x10);
1329 			for (j = 31; j >= 0; j--) {
1330 				if (value & (1<<j)) {
1331 					ack_APIC_irq();
1332 					acked++;
1333 				}
1334 			}
1335 		}
1336 		if (acked > 256) {
1337 			printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n",
1338 			       acked);
1339 			break;
1340 		}
1341 		if (queued) {
1342 			if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) {
1343 				ntsc = rdtsc();
1344 				max_loops = (cpu_khz << 10) - (ntsc - tsc);
1345 			} else
1346 				max_loops--;
1347 		}
1348 	} while (queued && max_loops > 0);
1349 	WARN_ON(max_loops <= 0);
1350 
1351 	/*
1352 	 * Now that we are all set up, enable the APIC
1353 	 */
1354 	value = apic_read(APIC_SPIV);
1355 	value &= ~APIC_VECTOR_MASK;
1356 	/*
1357 	 * Enable APIC
1358 	 */
1359 	value |= APIC_SPIV_APIC_ENABLED;
1360 
1361 #ifdef CONFIG_X86_32
1362 	/*
1363 	 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1364 	 * certain networking cards. If high frequency interrupts are
1365 	 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1366 	 * entry is masked/unmasked at a high rate as well then sooner or
1367 	 * later IOAPIC line gets 'stuck', no more interrupts are received
1368 	 * from the device. If focus CPU is disabled then the hang goes
1369 	 * away, oh well :-(
1370 	 *
1371 	 * [ This bug can be reproduced easily with a level-triggered
1372 	 *   PCI Ne2000 networking cards and PII/PIII processors, dual
1373 	 *   BX chipset. ]
1374 	 */
1375 	/*
1376 	 * Actually disabling the focus CPU check just makes the hang less
1377 	 * frequent as it makes the interrupt distributon model be more
1378 	 * like LRU than MRU (the short-term load is more even across CPUs).
1379 	 */
1380 
1381 	/*
1382 	 * - enable focus processor (bit==0)
1383 	 * - 64bit mode always use processor focus
1384 	 *   so no need to set it
1385 	 */
1386 	value &= ~APIC_SPIV_FOCUS_DISABLED;
1387 #endif
1388 
1389 	/*
1390 	 * Set spurious IRQ vector
1391 	 */
1392 	value |= SPURIOUS_APIC_VECTOR;
1393 	apic_write(APIC_SPIV, value);
1394 
1395 	/*
1396 	 * Set up LVT0, LVT1:
1397 	 *
1398 	 * set up through-local-APIC on the BP's LINT0. This is not
1399 	 * strictly necessary in pure symmetric-IO mode, but sometimes
1400 	 * we delegate interrupts to the 8259A.
1401 	 */
1402 	/*
1403 	 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1404 	 */
1405 	value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1406 	if (!cpu && (pic_mode || !value)) {
1407 		value = APIC_DM_EXTINT;
1408 		apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu);
1409 	} else {
1410 		value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1411 		apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu);
1412 	}
1413 	apic_write(APIC_LVT0, value);
1414 
1415 	/*
1416 	 * Only the BSP sees the LINT1 NMI signal by default. This can be
1417 	 * modified by apic_extnmi= boot option.
1418 	 */
1419 	if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) ||
1420 	    apic_extnmi == APIC_EXTNMI_ALL)
1421 		value = APIC_DM_NMI;
1422 	else
1423 		value = APIC_DM_NMI | APIC_LVT_MASKED;
1424 	if (!lapic_is_integrated())		/* 82489DX */
1425 		value |= APIC_LVT_LEVEL_TRIGGER;
1426 	apic_write(APIC_LVT1, value);
1427 
1428 #ifdef CONFIG_X86_MCE_INTEL
1429 	/* Recheck CMCI information after local APIC is up on CPU #0 */
1430 	if (!cpu)
1431 		cmci_recheck();
1432 #endif
1433 }
1434 
1435 static void end_local_APIC_setup(void)
1436 {
1437 	lapic_setup_esr();
1438 
1439 #ifdef CONFIG_X86_32
1440 	{
1441 		unsigned int value;
1442 		/* Disable the local apic timer */
1443 		value = apic_read(APIC_LVTT);
1444 		value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1445 		apic_write(APIC_LVTT, value);
1446 	}
1447 #endif
1448 
1449 	apic_pm_activate();
1450 }
1451 
1452 /*
1453  * APIC setup function for application processors. Called from smpboot.c
1454  */
1455 void apic_ap_setup(void)
1456 {
1457 	setup_local_APIC();
1458 	end_local_APIC_setup();
1459 }
1460 
1461 #ifdef CONFIG_X86_X2APIC
1462 int x2apic_mode;
1463 
1464 enum {
1465 	X2APIC_OFF,
1466 	X2APIC_ON,
1467 	X2APIC_DISABLED,
1468 };
1469 static int x2apic_state;
1470 
1471 static void __x2apic_disable(void)
1472 {
1473 	u64 msr;
1474 
1475 	if (!boot_cpu_has(X86_FEATURE_APIC))
1476 		return;
1477 
1478 	rdmsrl(MSR_IA32_APICBASE, msr);
1479 	if (!(msr & X2APIC_ENABLE))
1480 		return;
1481 	/* Disable xapic and x2apic first and then reenable xapic mode */
1482 	wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE));
1483 	wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE);
1484 	printk_once(KERN_INFO "x2apic disabled\n");
1485 }
1486 
1487 static void __x2apic_enable(void)
1488 {
1489 	u64 msr;
1490 
1491 	rdmsrl(MSR_IA32_APICBASE, msr);
1492 	if (msr & X2APIC_ENABLE)
1493 		return;
1494 	wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE);
1495 	printk_once(KERN_INFO "x2apic enabled\n");
1496 }
1497 
1498 static int __init setup_nox2apic(char *str)
1499 {
1500 	if (x2apic_enabled()) {
1501 		int apicid = native_apic_msr_read(APIC_ID);
1502 
1503 		if (apicid >= 255) {
1504 			pr_warning("Apicid: %08x, cannot enforce nox2apic\n",
1505 				   apicid);
1506 			return 0;
1507 		}
1508 		pr_warning("x2apic already enabled.\n");
1509 		__x2apic_disable();
1510 	}
1511 	setup_clear_cpu_cap(X86_FEATURE_X2APIC);
1512 	x2apic_state = X2APIC_DISABLED;
1513 	x2apic_mode = 0;
1514 	return 0;
1515 }
1516 early_param("nox2apic", setup_nox2apic);
1517 
1518 /* Called from cpu_init() to enable x2apic on (secondary) cpus */
1519 void x2apic_setup(void)
1520 {
1521 	/*
1522 	 * If x2apic is not in ON state, disable it if already enabled
1523 	 * from BIOS.
1524 	 */
1525 	if (x2apic_state != X2APIC_ON) {
1526 		__x2apic_disable();
1527 		return;
1528 	}
1529 	__x2apic_enable();
1530 }
1531 
1532 static __init void x2apic_disable(void)
1533 {
1534 	u32 x2apic_id, state = x2apic_state;
1535 
1536 	x2apic_mode = 0;
1537 	x2apic_state = X2APIC_DISABLED;
1538 
1539 	if (state != X2APIC_ON)
1540 		return;
1541 
1542 	x2apic_id = read_apic_id();
1543 	if (x2apic_id >= 255)
1544 		panic("Cannot disable x2apic, id: %08x\n", x2apic_id);
1545 
1546 	__x2apic_disable();
1547 	register_lapic_address(mp_lapic_addr);
1548 }
1549 
1550 static __init void x2apic_enable(void)
1551 {
1552 	if (x2apic_state != X2APIC_OFF)
1553 		return;
1554 
1555 	x2apic_mode = 1;
1556 	x2apic_state = X2APIC_ON;
1557 	__x2apic_enable();
1558 }
1559 
1560 static __init void try_to_enable_x2apic(int remap_mode)
1561 {
1562 	if (x2apic_state == X2APIC_DISABLED)
1563 		return;
1564 
1565 	if (remap_mode != IRQ_REMAP_X2APIC_MODE) {
1566 		/* IR is required if there is APIC ID > 255 even when running
1567 		 * under KVM
1568 		 */
1569 		if (max_physical_apicid > 255 ||
1570 		    !hypervisor_x2apic_available()) {
1571 			pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n");
1572 			x2apic_disable();
1573 			return;
1574 		}
1575 
1576 		/*
1577 		 * without IR all CPUs can be addressed by IOAPIC/MSI
1578 		 * only in physical mode
1579 		 */
1580 		x2apic_phys = 1;
1581 	}
1582 	x2apic_enable();
1583 }
1584 
1585 void __init check_x2apic(void)
1586 {
1587 	if (x2apic_enabled()) {
1588 		pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n");
1589 		x2apic_mode = 1;
1590 		x2apic_state = X2APIC_ON;
1591 	} else if (!boot_cpu_has(X86_FEATURE_X2APIC)) {
1592 		x2apic_state = X2APIC_DISABLED;
1593 	}
1594 }
1595 #else /* CONFIG_X86_X2APIC */
1596 static int __init validate_x2apic(void)
1597 {
1598 	if (!apic_is_x2apic_enabled())
1599 		return 0;
1600 	/*
1601 	 * Checkme: Can we simply turn off x2apic here instead of panic?
1602 	 */
1603 	panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n");
1604 }
1605 early_initcall(validate_x2apic);
1606 
1607 static inline void try_to_enable_x2apic(int remap_mode) { }
1608 static inline void __x2apic_enable(void) { }
1609 #endif /* !CONFIG_X86_X2APIC */
1610 
1611 static int __init try_to_enable_IR(void)
1612 {
1613 #ifdef CONFIG_X86_IO_APIC
1614 	if (!x2apic_enabled() && skip_ioapic_setup) {
1615 		pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n");
1616 		return -1;
1617 	}
1618 #endif
1619 	return irq_remapping_enable();
1620 }
1621 
1622 void __init enable_IR_x2apic(void)
1623 {
1624 	unsigned long flags;
1625 	int ret, ir_stat;
1626 
1627 	if (skip_ioapic_setup)
1628 		return;
1629 
1630 	ir_stat = irq_remapping_prepare();
1631 	if (ir_stat < 0 && !x2apic_supported())
1632 		return;
1633 
1634 	ret = save_ioapic_entries();
1635 	if (ret) {
1636 		pr_info("Saving IO-APIC state failed: %d\n", ret);
1637 		return;
1638 	}
1639 
1640 	local_irq_save(flags);
1641 	legacy_pic->mask_all();
1642 	mask_ioapic_entries();
1643 
1644 	/* If irq_remapping_prepare() succeeded, try to enable it */
1645 	if (ir_stat >= 0)
1646 		ir_stat = try_to_enable_IR();
1647 	/* ir_stat contains the remap mode or an error code */
1648 	try_to_enable_x2apic(ir_stat);
1649 
1650 	if (ir_stat < 0)
1651 		restore_ioapic_entries();
1652 	legacy_pic->restore_mask();
1653 	local_irq_restore(flags);
1654 }
1655 
1656 #ifdef CONFIG_X86_64
1657 /*
1658  * Detect and enable local APICs on non-SMP boards.
1659  * Original code written by Keir Fraser.
1660  * On AMD64 we trust the BIOS - if it says no APIC it is likely
1661  * not correctly set up (usually the APIC timer won't work etc.)
1662  */
1663 static int __init detect_init_APIC(void)
1664 {
1665 	if (!boot_cpu_has(X86_FEATURE_APIC)) {
1666 		pr_info("No local APIC present\n");
1667 		return -1;
1668 	}
1669 
1670 	mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1671 	return 0;
1672 }
1673 #else
1674 
1675 static int __init apic_verify(void)
1676 {
1677 	u32 features, h, l;
1678 
1679 	/*
1680 	 * The APIC feature bit should now be enabled
1681 	 * in `cpuid'
1682 	 */
1683 	features = cpuid_edx(1);
1684 	if (!(features & (1 << X86_FEATURE_APIC))) {
1685 		pr_warning("Could not enable APIC!\n");
1686 		return -1;
1687 	}
1688 	set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1689 	mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1690 
1691 	/* The BIOS may have set up the APIC at some other address */
1692 	if (boot_cpu_data.x86 >= 6) {
1693 		rdmsr(MSR_IA32_APICBASE, l, h);
1694 		if (l & MSR_IA32_APICBASE_ENABLE)
1695 			mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1696 	}
1697 
1698 	pr_info("Found and enabled local APIC!\n");
1699 	return 0;
1700 }
1701 
1702 int __init apic_force_enable(unsigned long addr)
1703 {
1704 	u32 h, l;
1705 
1706 	if (disable_apic)
1707 		return -1;
1708 
1709 	/*
1710 	 * Some BIOSes disable the local APIC in the APIC_BASE
1711 	 * MSR. This can only be done in software for Intel P6 or later
1712 	 * and AMD K7 (Model > 1) or later.
1713 	 */
1714 	if (boot_cpu_data.x86 >= 6) {
1715 		rdmsr(MSR_IA32_APICBASE, l, h);
1716 		if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1717 			pr_info("Local APIC disabled by BIOS -- reenabling.\n");
1718 			l &= ~MSR_IA32_APICBASE_BASE;
1719 			l |= MSR_IA32_APICBASE_ENABLE | addr;
1720 			wrmsr(MSR_IA32_APICBASE, l, h);
1721 			enabled_via_apicbase = 1;
1722 		}
1723 	}
1724 	return apic_verify();
1725 }
1726 
1727 /*
1728  * Detect and initialize APIC
1729  */
1730 static int __init detect_init_APIC(void)
1731 {
1732 	/* Disabled by kernel option? */
1733 	if (disable_apic)
1734 		return -1;
1735 
1736 	switch (boot_cpu_data.x86_vendor) {
1737 	case X86_VENDOR_AMD:
1738 		if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1739 		    (boot_cpu_data.x86 >= 15))
1740 			break;
1741 		goto no_apic;
1742 	case X86_VENDOR_INTEL:
1743 		if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1744 		    (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC)))
1745 			break;
1746 		goto no_apic;
1747 	default:
1748 		goto no_apic;
1749 	}
1750 
1751 	if (!boot_cpu_has(X86_FEATURE_APIC)) {
1752 		/*
1753 		 * Over-ride BIOS and try to enable the local APIC only if
1754 		 * "lapic" specified.
1755 		 */
1756 		if (!force_enable_local_apic) {
1757 			pr_info("Local APIC disabled by BIOS -- "
1758 				"you can enable it with \"lapic\"\n");
1759 			return -1;
1760 		}
1761 		if (apic_force_enable(APIC_DEFAULT_PHYS_BASE))
1762 			return -1;
1763 	} else {
1764 		if (apic_verify())
1765 			return -1;
1766 	}
1767 
1768 	apic_pm_activate();
1769 
1770 	return 0;
1771 
1772 no_apic:
1773 	pr_info("No local APIC present or hardware disabled\n");
1774 	return -1;
1775 }
1776 #endif
1777 
1778 /**
1779  * init_apic_mappings - initialize APIC mappings
1780  */
1781 void __init init_apic_mappings(void)
1782 {
1783 	unsigned int new_apicid;
1784 
1785 	if (x2apic_mode) {
1786 		boot_cpu_physical_apicid = read_apic_id();
1787 		return;
1788 	}
1789 
1790 	/* If no local APIC can be found return early */
1791 	if (!smp_found_config && detect_init_APIC()) {
1792 		/* lets NOP'ify apic operations */
1793 		pr_info("APIC: disable apic facility\n");
1794 		apic_disable();
1795 	} else {
1796 		apic_phys = mp_lapic_addr;
1797 
1798 		/*
1799 		 * acpi lapic path already maps that address in
1800 		 * acpi_register_lapic_address()
1801 		 */
1802 		if (!acpi_lapic && !smp_found_config)
1803 			register_lapic_address(apic_phys);
1804 	}
1805 
1806 	/*
1807 	 * Fetch the APIC ID of the BSP in case we have a
1808 	 * default configuration (or the MP table is broken).
1809 	 */
1810 	new_apicid = read_apic_id();
1811 	if (boot_cpu_physical_apicid != new_apicid) {
1812 		boot_cpu_physical_apicid = new_apicid;
1813 		/*
1814 		 * yeah -- we lie about apic_version
1815 		 * in case if apic was disabled via boot option
1816 		 * but it's not a problem for SMP compiled kernel
1817 		 * since smp_sanity_check is prepared for such a case
1818 		 * and disable smp mode
1819 		 */
1820 		boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
1821 	}
1822 }
1823 
1824 void __init register_lapic_address(unsigned long address)
1825 {
1826 	mp_lapic_addr = address;
1827 
1828 	if (!x2apic_mode) {
1829 		set_fixmap_nocache(FIX_APIC_BASE, address);
1830 		apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1831 			    APIC_BASE, address);
1832 	}
1833 	if (boot_cpu_physical_apicid == -1U) {
1834 		boot_cpu_physical_apicid  = read_apic_id();
1835 		boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
1836 	}
1837 }
1838 
1839 /*
1840  * Local APIC interrupts
1841  */
1842 
1843 /*
1844  * This interrupt should _never_ happen with our APIC/SMP architecture
1845  */
1846 static void __smp_spurious_interrupt(u8 vector)
1847 {
1848 	u32 v;
1849 
1850 	/*
1851 	 * Check if this really is a spurious interrupt and ACK it
1852 	 * if it is a vectored one.  Just in case...
1853 	 * Spurious interrupts should not be ACKed.
1854 	 */
1855 	v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1));
1856 	if (v & (1 << (vector & 0x1f)))
1857 		ack_APIC_irq();
1858 
1859 	inc_irq_stat(irq_spurious_count);
1860 
1861 	/* see sw-dev-man vol 3, chapter 7.4.13.5 */
1862 	pr_info("spurious APIC interrupt through vector %02x on CPU#%d, "
1863 		"should never happen.\n", vector, smp_processor_id());
1864 }
1865 
1866 __visible void smp_spurious_interrupt(struct pt_regs *regs)
1867 {
1868 	entering_irq();
1869 	__smp_spurious_interrupt(~regs->orig_ax);
1870 	exiting_irq();
1871 }
1872 
1873 __visible void smp_trace_spurious_interrupt(struct pt_regs *regs)
1874 {
1875 	u8 vector = ~regs->orig_ax;
1876 
1877 	entering_irq();
1878 	trace_spurious_apic_entry(vector);
1879 	__smp_spurious_interrupt(vector);
1880 	trace_spurious_apic_exit(vector);
1881 	exiting_irq();
1882 }
1883 
1884 /*
1885  * This interrupt should never happen with our APIC/SMP architecture
1886  */
1887 static void __smp_error_interrupt(struct pt_regs *regs)
1888 {
1889 	u32 v;
1890 	u32 i = 0;
1891 	static const char * const error_interrupt_reason[] = {
1892 		"Send CS error",		/* APIC Error Bit 0 */
1893 		"Receive CS error",		/* APIC Error Bit 1 */
1894 		"Send accept error",		/* APIC Error Bit 2 */
1895 		"Receive accept error",		/* APIC Error Bit 3 */
1896 		"Redirectable IPI",		/* APIC Error Bit 4 */
1897 		"Send illegal vector",		/* APIC Error Bit 5 */
1898 		"Received illegal vector",	/* APIC Error Bit 6 */
1899 		"Illegal register address",	/* APIC Error Bit 7 */
1900 	};
1901 
1902 	/* First tickle the hardware, only then report what went on. -- REW */
1903 	if (lapic_get_maxlvt() > 3)	/* Due to the Pentium erratum 3AP. */
1904 		apic_write(APIC_ESR, 0);
1905 	v = apic_read(APIC_ESR);
1906 	ack_APIC_irq();
1907 	atomic_inc(&irq_err_count);
1908 
1909 	apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x",
1910 		    smp_processor_id(), v);
1911 
1912 	v &= 0xff;
1913 	while (v) {
1914 		if (v & 0x1)
1915 			apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]);
1916 		i++;
1917 		v >>= 1;
1918 	}
1919 
1920 	apic_printk(APIC_DEBUG, KERN_CONT "\n");
1921 
1922 }
1923 
1924 __visible void smp_error_interrupt(struct pt_regs *regs)
1925 {
1926 	entering_irq();
1927 	__smp_error_interrupt(regs);
1928 	exiting_irq();
1929 }
1930 
1931 __visible void smp_trace_error_interrupt(struct pt_regs *regs)
1932 {
1933 	entering_irq();
1934 	trace_error_apic_entry(ERROR_APIC_VECTOR);
1935 	__smp_error_interrupt(regs);
1936 	trace_error_apic_exit(ERROR_APIC_VECTOR);
1937 	exiting_irq();
1938 }
1939 
1940 /**
1941  * connect_bsp_APIC - attach the APIC to the interrupt system
1942  */
1943 static void __init connect_bsp_APIC(void)
1944 {
1945 #ifdef CONFIG_X86_32
1946 	if (pic_mode) {
1947 		/*
1948 		 * Do not trust the local APIC being empty at bootup.
1949 		 */
1950 		clear_local_APIC();
1951 		/*
1952 		 * PIC mode, enable APIC mode in the IMCR, i.e.  connect BSP's
1953 		 * local APIC to INT and NMI lines.
1954 		 */
1955 		apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1956 				"enabling APIC mode.\n");
1957 		imcr_pic_to_apic();
1958 	}
1959 #endif
1960 }
1961 
1962 /**
1963  * disconnect_bsp_APIC - detach the APIC from the interrupt system
1964  * @virt_wire_setup:	indicates, whether virtual wire mode is selected
1965  *
1966  * Virtual wire mode is necessary to deliver legacy interrupts even when the
1967  * APIC is disabled.
1968  */
1969 void disconnect_bsp_APIC(int virt_wire_setup)
1970 {
1971 	unsigned int value;
1972 
1973 #ifdef CONFIG_X86_32
1974 	if (pic_mode) {
1975 		/*
1976 		 * Put the board back into PIC mode (has an effect only on
1977 		 * certain older boards).  Note that APIC interrupts, including
1978 		 * IPIs, won't work beyond this point!  The only exception are
1979 		 * INIT IPIs.
1980 		 */
1981 		apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1982 				"entering PIC mode.\n");
1983 		imcr_apic_to_pic();
1984 		return;
1985 	}
1986 #endif
1987 
1988 	/* Go back to Virtual Wire compatibility mode */
1989 
1990 	/* For the spurious interrupt use vector F, and enable it */
1991 	value = apic_read(APIC_SPIV);
1992 	value &= ~APIC_VECTOR_MASK;
1993 	value |= APIC_SPIV_APIC_ENABLED;
1994 	value |= 0xf;
1995 	apic_write(APIC_SPIV, value);
1996 
1997 	if (!virt_wire_setup) {
1998 		/*
1999 		 * For LVT0 make it edge triggered, active high,
2000 		 * external and enabled
2001 		 */
2002 		value = apic_read(APIC_LVT0);
2003 		value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2004 			APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2005 			APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2006 		value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2007 		value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
2008 		apic_write(APIC_LVT0, value);
2009 	} else {
2010 		/* Disable LVT0 */
2011 		apic_write(APIC_LVT0, APIC_LVT_MASKED);
2012 	}
2013 
2014 	/*
2015 	 * For LVT1 make it edge triggered, active high,
2016 	 * nmi and enabled
2017 	 */
2018 	value = apic_read(APIC_LVT1);
2019 	value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
2020 			APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
2021 			APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
2022 	value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
2023 	value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
2024 	apic_write(APIC_LVT1, value);
2025 }
2026 
2027 /*
2028  * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated
2029  * contiguously, it equals to current allocated max logical CPU ID plus 1.
2030  * All allocated CPU ID should be in [0, nr_logical_cpuidi), so the maximum of
2031  * nr_logical_cpuids is nr_cpu_ids.
2032  *
2033  * NOTE: Reserve 0 for BSP.
2034  */
2035 static int nr_logical_cpuids = 1;
2036 
2037 /*
2038  * Used to store mapping between logical CPU IDs and APIC IDs.
2039  */
2040 static int cpuid_to_apicid[] = {
2041 	[0 ... NR_CPUS - 1] = -1,
2042 };
2043 
2044 /*
2045  * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids
2046  * and cpuid_to_apicid[] synchronized.
2047  */
2048 static int allocate_logical_cpuid(int apicid)
2049 {
2050 	int i;
2051 
2052 	/*
2053 	 * cpuid <-> apicid mapping is persistent, so when a cpu is up,
2054 	 * check if the kernel has allocated a cpuid for it.
2055 	 */
2056 	for (i = 0; i < nr_logical_cpuids; i++) {
2057 		if (cpuid_to_apicid[i] == apicid)
2058 			return i;
2059 	}
2060 
2061 	/* Allocate a new cpuid. */
2062 	if (nr_logical_cpuids >= nr_cpu_ids) {
2063 		WARN_ONCE(1, "Only %d processors supported."
2064 			     "Processor %d/0x%x and the rest are ignored.\n",
2065 			     nr_cpu_ids - 1, nr_logical_cpuids, apicid);
2066 		return -1;
2067 	}
2068 
2069 	cpuid_to_apicid[nr_logical_cpuids] = apicid;
2070 	return nr_logical_cpuids++;
2071 }
2072 
2073 int __generic_processor_info(int apicid, int version, bool enabled)
2074 {
2075 	int cpu, max = nr_cpu_ids;
2076 	bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid,
2077 				phys_cpu_present_map);
2078 
2079 	/*
2080 	 * boot_cpu_physical_apicid is designed to have the apicid
2081 	 * returned by read_apic_id(), i.e, the apicid of the
2082 	 * currently booting-up processor. However, on some platforms,
2083 	 * it is temporarily modified by the apicid reported as BSP
2084 	 * through MP table. Concretely:
2085 	 *
2086 	 * - arch/x86/kernel/mpparse.c: MP_processor_info()
2087 	 * - arch/x86/mm/amdtopology.c: amd_numa_init()
2088 	 *
2089 	 * This function is executed with the modified
2090 	 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel
2091 	 * parameter doesn't work to disable APs on kdump 2nd kernel.
2092 	 *
2093 	 * Since fixing handling of boot_cpu_physical_apicid requires
2094 	 * another discussion and tests on each platform, we leave it
2095 	 * for now and here we use read_apic_id() directly in this
2096 	 * function, generic_processor_info().
2097 	 */
2098 	if (disabled_cpu_apicid != BAD_APICID &&
2099 	    disabled_cpu_apicid != read_apic_id() &&
2100 	    disabled_cpu_apicid == apicid) {
2101 		int thiscpu = num_processors + disabled_cpus;
2102 
2103 		pr_warning("APIC: Disabling requested cpu."
2104 			   " Processor %d/0x%x ignored.\n",
2105 			   thiscpu, apicid);
2106 
2107 		disabled_cpus++;
2108 		return -ENODEV;
2109 	}
2110 
2111 	/*
2112 	 * If boot cpu has not been detected yet, then only allow upto
2113 	 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu
2114 	 */
2115 	if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 &&
2116 	    apicid != boot_cpu_physical_apicid) {
2117 		int thiscpu = max + disabled_cpus - 1;
2118 
2119 		pr_warning(
2120 			"APIC: NR_CPUS/possible_cpus limit of %i almost"
2121 			" reached. Keeping one slot for boot cpu."
2122 			"  Processor %d/0x%x ignored.\n", max, thiscpu, apicid);
2123 
2124 		disabled_cpus++;
2125 		return -ENODEV;
2126 	}
2127 
2128 	if (num_processors >= nr_cpu_ids) {
2129 		int thiscpu = max + disabled_cpus;
2130 
2131 		if (enabled) {
2132 			pr_warning("APIC: NR_CPUS/possible_cpus limit of %i "
2133 				   "reached. Processor %d/0x%x ignored.\n",
2134 				   max, thiscpu, apicid);
2135 		}
2136 
2137 		disabled_cpus++;
2138 		return -EINVAL;
2139 	}
2140 
2141 	if (apicid == boot_cpu_physical_apicid) {
2142 		/*
2143 		 * x86_bios_cpu_apicid is required to have processors listed
2144 		 * in same order as logical cpu numbers. Hence the first
2145 		 * entry is BSP, and so on.
2146 		 * boot_cpu_init() already hold bit 0 in cpu_present_mask
2147 		 * for BSP.
2148 		 */
2149 		cpu = 0;
2150 
2151 		/* Logical cpuid 0 is reserved for BSP. */
2152 		cpuid_to_apicid[0] = apicid;
2153 	} else {
2154 		cpu = allocate_logical_cpuid(apicid);
2155 		if (cpu < 0) {
2156 			disabled_cpus++;
2157 			return -EINVAL;
2158 		}
2159 	}
2160 
2161 	/*
2162 	 * This can happen on physical hotplug. The sanity check at boot time
2163 	 * is done from native_smp_prepare_cpus() after num_possible_cpus() is
2164 	 * established.
2165 	 */
2166 	if (topology_update_package_map(apicid, cpu) < 0) {
2167 		int thiscpu = max + disabled_cpus;
2168 
2169 		pr_warning("APIC: Package limit reached. Processor %d/0x%x ignored.\n",
2170 			   thiscpu, apicid);
2171 
2172 		disabled_cpus++;
2173 		return -ENOSPC;
2174 	}
2175 
2176 	/*
2177 	 * Validate version
2178 	 */
2179 	if (version == 0x0) {
2180 		pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n",
2181 			   cpu, apicid);
2182 		version = 0x10;
2183 	}
2184 
2185 	if (version != boot_cpu_apic_version) {
2186 		pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n",
2187 			boot_cpu_apic_version, cpu, version);
2188 	}
2189 
2190 	if (apicid > max_physical_apicid)
2191 		max_physical_apicid = apicid;
2192 
2193 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64)
2194 	early_per_cpu(x86_cpu_to_apicid, cpu) = apicid;
2195 	early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
2196 #endif
2197 #ifdef CONFIG_X86_32
2198 	early_per_cpu(x86_cpu_to_logical_apicid, cpu) =
2199 		apic->x86_32_early_logical_apicid(cpu);
2200 #endif
2201 	set_cpu_possible(cpu, true);
2202 
2203 	if (enabled) {
2204 		num_processors++;
2205 		physid_set(apicid, phys_cpu_present_map);
2206 		set_cpu_present(cpu, true);
2207 	} else {
2208 		disabled_cpus++;
2209 	}
2210 
2211 	return cpu;
2212 }
2213 
2214 int generic_processor_info(int apicid, int version)
2215 {
2216 	return __generic_processor_info(apicid, version, true);
2217 }
2218 
2219 int hard_smp_processor_id(void)
2220 {
2221 	return read_apic_id();
2222 }
2223 
2224 void default_init_apic_ldr(void)
2225 {
2226 	unsigned long val;
2227 
2228 	apic_write(APIC_DFR, APIC_DFR_VALUE);
2229 	val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
2230 	val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
2231 	apic_write(APIC_LDR, val);
2232 }
2233 
2234 int default_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
2235 				   const struct cpumask *andmask,
2236 				   unsigned int *apicid)
2237 {
2238 	unsigned int cpu;
2239 
2240 	for_each_cpu_and(cpu, cpumask, andmask) {
2241 		if (cpumask_test_cpu(cpu, cpu_online_mask))
2242 			break;
2243 	}
2244 
2245 	if (likely(cpu < nr_cpu_ids)) {
2246 		*apicid = per_cpu(x86_cpu_to_apicid, cpu);
2247 		return 0;
2248 	}
2249 
2250 	return -EINVAL;
2251 }
2252 
2253 /*
2254  * Override the generic EOI implementation with an optimized version.
2255  * Only called during early boot when only one CPU is active and with
2256  * interrupts disabled, so we know this does not race with actual APIC driver
2257  * use.
2258  */
2259 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v))
2260 {
2261 	struct apic **drv;
2262 
2263 	for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
2264 		/* Should happen once for each apic */
2265 		WARN_ON((*drv)->eoi_write == eoi_write);
2266 		(*drv)->eoi_write = eoi_write;
2267 	}
2268 }
2269 
2270 static void __init apic_bsp_up_setup(void)
2271 {
2272 #ifdef CONFIG_X86_64
2273 	apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
2274 #else
2275 	/*
2276 	 * Hack: In case of kdump, after a crash, kernel might be booting
2277 	 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
2278 	 * might be zero if read from MP tables. Get it from LAPIC.
2279 	 */
2280 # ifdef CONFIG_CRASH_DUMP
2281 	boot_cpu_physical_apicid = read_apic_id();
2282 # endif
2283 #endif
2284 	physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
2285 }
2286 
2287 /**
2288  * apic_bsp_setup - Setup function for local apic and io-apic
2289  * @upmode:		Force UP mode (for APIC_init_uniprocessor)
2290  *
2291  * Returns:
2292  * apic_id of BSP APIC
2293  */
2294 int __init apic_bsp_setup(bool upmode)
2295 {
2296 	int id;
2297 
2298 	connect_bsp_APIC();
2299 	if (upmode)
2300 		apic_bsp_up_setup();
2301 	setup_local_APIC();
2302 
2303 	if (x2apic_mode)
2304 		id = apic_read(APIC_LDR);
2305 	else
2306 		id = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
2307 
2308 	enable_IO_APIC();
2309 	end_local_APIC_setup();
2310 	irq_remap_enable_fault_handling();
2311 	setup_IO_APIC();
2312 	/* Setup local timer */
2313 	x86_init.timers.setup_percpu_clockev();
2314 	return id;
2315 }
2316 
2317 /*
2318  * This initializes the IO-APIC and APIC hardware if this is
2319  * a UP kernel.
2320  */
2321 int __init APIC_init_uniprocessor(void)
2322 {
2323 	if (disable_apic) {
2324 		pr_info("Apic disabled\n");
2325 		return -1;
2326 	}
2327 #ifdef CONFIG_X86_64
2328 	if (!boot_cpu_has(X86_FEATURE_APIC)) {
2329 		disable_apic = 1;
2330 		pr_info("Apic disabled by BIOS\n");
2331 		return -1;
2332 	}
2333 #else
2334 	if (!smp_found_config && !boot_cpu_has(X86_FEATURE_APIC))
2335 		return -1;
2336 
2337 	/*
2338 	 * Complain if the BIOS pretends there is one.
2339 	 */
2340 	if (!boot_cpu_has(X86_FEATURE_APIC) &&
2341 	    APIC_INTEGRATED(boot_cpu_apic_version)) {
2342 		pr_err("BIOS bug, local APIC 0x%x not detected!...\n",
2343 			boot_cpu_physical_apicid);
2344 		return -1;
2345 	}
2346 #endif
2347 
2348 	if (!smp_found_config)
2349 		disable_ioapic_support();
2350 
2351 	default_setup_apic_routing();
2352 	apic_bsp_setup(true);
2353 	return 0;
2354 }
2355 
2356 #ifdef CONFIG_UP_LATE_INIT
2357 void __init up_late_init(void)
2358 {
2359 	APIC_init_uniprocessor();
2360 }
2361 #endif
2362 
2363 /*
2364  * Power management
2365  */
2366 #ifdef CONFIG_PM
2367 
2368 static struct {
2369 	/*
2370 	 * 'active' is true if the local APIC was enabled by us and
2371 	 * not the BIOS; this signifies that we are also responsible
2372 	 * for disabling it before entering apm/acpi suspend
2373 	 */
2374 	int active;
2375 	/* r/w apic fields */
2376 	unsigned int apic_id;
2377 	unsigned int apic_taskpri;
2378 	unsigned int apic_ldr;
2379 	unsigned int apic_dfr;
2380 	unsigned int apic_spiv;
2381 	unsigned int apic_lvtt;
2382 	unsigned int apic_lvtpc;
2383 	unsigned int apic_lvt0;
2384 	unsigned int apic_lvt1;
2385 	unsigned int apic_lvterr;
2386 	unsigned int apic_tmict;
2387 	unsigned int apic_tdcr;
2388 	unsigned int apic_thmr;
2389 	unsigned int apic_cmci;
2390 } apic_pm_state;
2391 
2392 static int lapic_suspend(void)
2393 {
2394 	unsigned long flags;
2395 	int maxlvt;
2396 
2397 	if (!apic_pm_state.active)
2398 		return 0;
2399 
2400 	maxlvt = lapic_get_maxlvt();
2401 
2402 	apic_pm_state.apic_id = apic_read(APIC_ID);
2403 	apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2404 	apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2405 	apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2406 	apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2407 	apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2408 	if (maxlvt >= 4)
2409 		apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2410 	apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2411 	apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2412 	apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2413 	apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2414 	apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2415 #ifdef CONFIG_X86_THERMAL_VECTOR
2416 	if (maxlvt >= 5)
2417 		apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2418 #endif
2419 #ifdef CONFIG_X86_MCE_INTEL
2420 	if (maxlvt >= 6)
2421 		apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI);
2422 #endif
2423 
2424 	local_irq_save(flags);
2425 	disable_local_APIC();
2426 
2427 	irq_remapping_disable();
2428 
2429 	local_irq_restore(flags);
2430 	return 0;
2431 }
2432 
2433 static void lapic_resume(void)
2434 {
2435 	unsigned int l, h;
2436 	unsigned long flags;
2437 	int maxlvt;
2438 
2439 	if (!apic_pm_state.active)
2440 		return;
2441 
2442 	local_irq_save(flags);
2443 
2444 	/*
2445 	 * IO-APIC and PIC have their own resume routines.
2446 	 * We just mask them here to make sure the interrupt
2447 	 * subsystem is completely quiet while we enable x2apic
2448 	 * and interrupt-remapping.
2449 	 */
2450 	mask_ioapic_entries();
2451 	legacy_pic->mask_all();
2452 
2453 	if (x2apic_mode) {
2454 		__x2apic_enable();
2455 	} else {
2456 		/*
2457 		 * Make sure the APICBASE points to the right address
2458 		 *
2459 		 * FIXME! This will be wrong if we ever support suspend on
2460 		 * SMP! We'll need to do this as part of the CPU restore!
2461 		 */
2462 		if (boot_cpu_data.x86 >= 6) {
2463 			rdmsr(MSR_IA32_APICBASE, l, h);
2464 			l &= ~MSR_IA32_APICBASE_BASE;
2465 			l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2466 			wrmsr(MSR_IA32_APICBASE, l, h);
2467 		}
2468 	}
2469 
2470 	maxlvt = lapic_get_maxlvt();
2471 	apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2472 	apic_write(APIC_ID, apic_pm_state.apic_id);
2473 	apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2474 	apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2475 	apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2476 	apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2477 	apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2478 	apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2479 #ifdef CONFIG_X86_THERMAL_VECTOR
2480 	if (maxlvt >= 5)
2481 		apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2482 #endif
2483 #ifdef CONFIG_X86_MCE_INTEL
2484 	if (maxlvt >= 6)
2485 		apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci);
2486 #endif
2487 	if (maxlvt >= 4)
2488 		apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2489 	apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2490 	apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2491 	apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2492 	apic_write(APIC_ESR, 0);
2493 	apic_read(APIC_ESR);
2494 	apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2495 	apic_write(APIC_ESR, 0);
2496 	apic_read(APIC_ESR);
2497 
2498 	irq_remapping_reenable(x2apic_mode);
2499 
2500 	local_irq_restore(flags);
2501 }
2502 
2503 /*
2504  * This device has no shutdown method - fully functioning local APICs
2505  * are needed on every CPU up until machine_halt/restart/poweroff.
2506  */
2507 
2508 static struct syscore_ops lapic_syscore_ops = {
2509 	.resume		= lapic_resume,
2510 	.suspend	= lapic_suspend,
2511 };
2512 
2513 static void apic_pm_activate(void)
2514 {
2515 	apic_pm_state.active = 1;
2516 }
2517 
2518 static int __init init_lapic_sysfs(void)
2519 {
2520 	/* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2521 	if (boot_cpu_has(X86_FEATURE_APIC))
2522 		register_syscore_ops(&lapic_syscore_ops);
2523 
2524 	return 0;
2525 }
2526 
2527 /* local apic needs to resume before other devices access its registers. */
2528 core_initcall(init_lapic_sysfs);
2529 
2530 #else	/* CONFIG_PM */
2531 
2532 static void apic_pm_activate(void) { }
2533 
2534 #endif	/* CONFIG_PM */
2535 
2536 #ifdef CONFIG_X86_64
2537 
2538 static int multi_checked;
2539 static int multi;
2540 
2541 static int set_multi(const struct dmi_system_id *d)
2542 {
2543 	if (multi)
2544 		return 0;
2545 	pr_info("APIC: %s detected, Multi Chassis\n", d->ident);
2546 	multi = 1;
2547 	return 0;
2548 }
2549 
2550 static const struct dmi_system_id multi_dmi_table[] = {
2551 	{
2552 		.callback = set_multi,
2553 		.ident = "IBM System Summit2",
2554 		.matches = {
2555 			DMI_MATCH(DMI_SYS_VENDOR, "IBM"),
2556 			DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"),
2557 		},
2558 	},
2559 	{}
2560 };
2561 
2562 static void dmi_check_multi(void)
2563 {
2564 	if (multi_checked)
2565 		return;
2566 
2567 	dmi_check_system(multi_dmi_table);
2568 	multi_checked = 1;
2569 }
2570 
2571 /*
2572  * apic_is_clustered_box() -- Check if we can expect good TSC
2573  *
2574  * Thus far, the major user of this is IBM's Summit2 series:
2575  * Clustered boxes may have unsynced TSC problems if they are
2576  * multi-chassis.
2577  * Use DMI to check them
2578  */
2579 int apic_is_clustered_box(void)
2580 {
2581 	dmi_check_multi();
2582 	return multi;
2583 }
2584 #endif
2585 
2586 /*
2587  * APIC command line parameters
2588  */
2589 static int __init setup_disableapic(char *arg)
2590 {
2591 	disable_apic = 1;
2592 	setup_clear_cpu_cap(X86_FEATURE_APIC);
2593 	return 0;
2594 }
2595 early_param("disableapic", setup_disableapic);
2596 
2597 /* same as disableapic, for compatibility */
2598 static int __init setup_nolapic(char *arg)
2599 {
2600 	return setup_disableapic(arg);
2601 }
2602 early_param("nolapic", setup_nolapic);
2603 
2604 static int __init parse_lapic_timer_c2_ok(char *arg)
2605 {
2606 	local_apic_timer_c2_ok = 1;
2607 	return 0;
2608 }
2609 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2610 
2611 static int __init parse_disable_apic_timer(char *arg)
2612 {
2613 	disable_apic_timer = 1;
2614 	return 0;
2615 }
2616 early_param("noapictimer", parse_disable_apic_timer);
2617 
2618 static int __init parse_nolapic_timer(char *arg)
2619 {
2620 	disable_apic_timer = 1;
2621 	return 0;
2622 }
2623 early_param("nolapic_timer", parse_nolapic_timer);
2624 
2625 static int __init apic_set_verbosity(char *arg)
2626 {
2627 	if (!arg)  {
2628 #ifdef CONFIG_X86_64
2629 		skip_ioapic_setup = 0;
2630 		return 0;
2631 #endif
2632 		return -EINVAL;
2633 	}
2634 
2635 	if (strcmp("debug", arg) == 0)
2636 		apic_verbosity = APIC_DEBUG;
2637 	else if (strcmp("verbose", arg) == 0)
2638 		apic_verbosity = APIC_VERBOSE;
2639 	else {
2640 		pr_warning("APIC Verbosity level %s not recognised"
2641 			" use apic=verbose or apic=debug\n", arg);
2642 		return -EINVAL;
2643 	}
2644 
2645 	return 0;
2646 }
2647 early_param("apic", apic_set_verbosity);
2648 
2649 static int __init lapic_insert_resource(void)
2650 {
2651 	if (!apic_phys)
2652 		return -1;
2653 
2654 	/* Put local APIC into the resource map. */
2655 	lapic_resource.start = apic_phys;
2656 	lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2657 	insert_resource(&iomem_resource, &lapic_resource);
2658 
2659 	return 0;
2660 }
2661 
2662 /*
2663  * need call insert after e820_reserve_resources()
2664  * that is using request_resource
2665  */
2666 late_initcall(lapic_insert_resource);
2667 
2668 static int __init apic_set_disabled_cpu_apicid(char *arg)
2669 {
2670 	if (!arg || !get_option(&arg, &disabled_cpu_apicid))
2671 		return -EINVAL;
2672 
2673 	return 0;
2674 }
2675 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid);
2676 
2677 static int __init apic_set_extnmi(char *arg)
2678 {
2679 	if (!arg)
2680 		return -EINVAL;
2681 
2682 	if (!strncmp("all", arg, 3))
2683 		apic_extnmi = APIC_EXTNMI_ALL;
2684 	else if (!strncmp("none", arg, 4))
2685 		apic_extnmi = APIC_EXTNMI_NONE;
2686 	else if (!strncmp("bsp", arg, 3))
2687 		apic_extnmi = APIC_EXTNMI_BSP;
2688 	else {
2689 		pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg);
2690 		return -EINVAL;
2691 	}
2692 
2693 	return 0;
2694 }
2695 early_param("apic_extnmi", apic_set_extnmi);
2696