1 /* 2 * Local APIC handling, local APIC timers 3 * 4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 5 * 6 * Fixes 7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 8 * thanks to Eric Gilmore 9 * and Rolf G. Tews 10 * for testing these extensively. 11 * Maciej W. Rozycki : Various updates and fixes. 12 * Mikael Pettersson : Power Management for UP-APIC. 13 * Pavel Machek and 14 * Mikael Pettersson : PM converted to driver model. 15 */ 16 17 #include <linux/perf_counter.h> 18 #include <linux/kernel_stat.h> 19 #include <linux/mc146818rtc.h> 20 #include <linux/acpi_pmtmr.h> 21 #include <linux/clockchips.h> 22 #include <linux/interrupt.h> 23 #include <linux/bootmem.h> 24 #include <linux/ftrace.h> 25 #include <linux/ioport.h> 26 #include <linux/module.h> 27 #include <linux/sysdev.h> 28 #include <linux/delay.h> 29 #include <linux/timex.h> 30 #include <linux/dmar.h> 31 #include <linux/init.h> 32 #include <linux/cpu.h> 33 #include <linux/dmi.h> 34 #include <linux/nmi.h> 35 #include <linux/smp.h> 36 #include <linux/mm.h> 37 38 #include <asm/perf_counter.h> 39 #include <asm/pgalloc.h> 40 #include <asm/atomic.h> 41 #include <asm/mpspec.h> 42 #include <asm/i8253.h> 43 #include <asm/i8259.h> 44 #include <asm/proto.h> 45 #include <asm/apic.h> 46 #include <asm/desc.h> 47 #include <asm/hpet.h> 48 #include <asm/idle.h> 49 #include <asm/mtrr.h> 50 #include <asm/smp.h> 51 #include <asm/mce.h> 52 53 unsigned int num_processors; 54 55 unsigned disabled_cpus __cpuinitdata; 56 57 /* Processor that is doing the boot up */ 58 unsigned int boot_cpu_physical_apicid = -1U; 59 60 /* 61 * The highest APIC ID seen during enumeration. 62 * 63 * This determines the messaging protocol we can use: if all APIC IDs 64 * are in the 0 ... 7 range, then we can use logical addressing which 65 * has some performance advantages (better broadcasting). 66 * 67 * If there's an APIC ID above 8, we use physical addressing. 68 */ 69 unsigned int max_physical_apicid; 70 71 /* 72 * Bitmask of physically existing CPUs: 73 */ 74 physid_mask_t phys_cpu_present_map; 75 76 /* 77 * Map cpu index to physical APIC ID 78 */ 79 DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID); 80 DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID); 81 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 82 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 83 84 #ifdef CONFIG_X86_32 85 /* 86 * Knob to control our willingness to enable the local APIC. 87 * 88 * +1=force-enable 89 */ 90 static int force_enable_local_apic; 91 /* 92 * APIC command line parameters 93 */ 94 static int __init parse_lapic(char *arg) 95 { 96 force_enable_local_apic = 1; 97 return 0; 98 } 99 early_param("lapic", parse_lapic); 100 /* Local APIC was disabled by the BIOS and enabled by the kernel */ 101 static int enabled_via_apicbase; 102 103 /* 104 * Handle interrupt mode configuration register (IMCR). 105 * This register controls whether the interrupt signals 106 * that reach the BSP come from the master PIC or from the 107 * local APIC. Before entering Symmetric I/O Mode, either 108 * the BIOS or the operating system must switch out of 109 * PIC Mode by changing the IMCR. 110 */ 111 static inline void imcr_pic_to_apic(void) 112 { 113 /* select IMCR register */ 114 outb(0x70, 0x22); 115 /* NMI and 8259 INTR go through APIC */ 116 outb(0x01, 0x23); 117 } 118 119 static inline void imcr_apic_to_pic(void) 120 { 121 /* select IMCR register */ 122 outb(0x70, 0x22); 123 /* NMI and 8259 INTR go directly to BSP */ 124 outb(0x00, 0x23); 125 } 126 #endif 127 128 #ifdef CONFIG_X86_64 129 static int apic_calibrate_pmtmr __initdata; 130 static __init int setup_apicpmtimer(char *s) 131 { 132 apic_calibrate_pmtmr = 1; 133 notsc_setup(NULL); 134 return 0; 135 } 136 __setup("apicpmtimer", setup_apicpmtimer); 137 #endif 138 139 int x2apic_mode; 140 #ifdef CONFIG_X86_X2APIC 141 /* x2apic enabled before OS handover */ 142 static int x2apic_preenabled; 143 static int disable_x2apic; 144 static __init int setup_nox2apic(char *str) 145 { 146 if (x2apic_enabled()) { 147 pr_warning("Bios already enabled x2apic, " 148 "can't enforce nox2apic"); 149 return 0; 150 } 151 152 disable_x2apic = 1; 153 setup_clear_cpu_cap(X86_FEATURE_X2APIC); 154 return 0; 155 } 156 early_param("nox2apic", setup_nox2apic); 157 #endif 158 159 unsigned long mp_lapic_addr; 160 int disable_apic; 161 /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 162 static int disable_apic_timer __cpuinitdata; 163 /* Local APIC timer works in C2 */ 164 int local_apic_timer_c2_ok; 165 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 166 167 int first_system_vector = 0xfe; 168 169 /* 170 * Debug level, exported for io_apic.c 171 */ 172 unsigned int apic_verbosity; 173 174 int pic_mode; 175 176 /* Have we found an MP table */ 177 int smp_found_config; 178 179 static struct resource lapic_resource = { 180 .name = "Local APIC", 181 .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 182 }; 183 184 static unsigned int calibration_result; 185 186 static int lapic_next_event(unsigned long delta, 187 struct clock_event_device *evt); 188 static void lapic_timer_setup(enum clock_event_mode mode, 189 struct clock_event_device *evt); 190 static void lapic_timer_broadcast(const struct cpumask *mask); 191 static void apic_pm_activate(void); 192 193 /* 194 * The local apic timer can be used for any function which is CPU local. 195 */ 196 static struct clock_event_device lapic_clockevent = { 197 .name = "lapic", 198 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT 199 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, 200 .shift = 32, 201 .set_mode = lapic_timer_setup, 202 .set_next_event = lapic_next_event, 203 .broadcast = lapic_timer_broadcast, 204 .rating = 100, 205 .irq = -1, 206 }; 207 static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 208 209 static unsigned long apic_phys; 210 211 /* 212 * Get the LAPIC version 213 */ 214 static inline int lapic_get_version(void) 215 { 216 return GET_APIC_VERSION(apic_read(APIC_LVR)); 217 } 218 219 /* 220 * Check, if the APIC is integrated or a separate chip 221 */ 222 static inline int lapic_is_integrated(void) 223 { 224 #ifdef CONFIG_X86_64 225 return 1; 226 #else 227 return APIC_INTEGRATED(lapic_get_version()); 228 #endif 229 } 230 231 /* 232 * Check, whether this is a modern or a first generation APIC 233 */ 234 static int modern_apic(void) 235 { 236 /* AMD systems use old APIC versions, so check the CPU */ 237 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 238 boot_cpu_data.x86 >= 0xf) 239 return 1; 240 return lapic_get_version() >= 0x14; 241 } 242 243 /* 244 * bare function to substitute write operation 245 * and it's _that_ fast :) 246 */ 247 static void native_apic_write_dummy(u32 reg, u32 v) 248 { 249 WARN_ON_ONCE((cpu_has_apic || !disable_apic)); 250 } 251 252 static u32 native_apic_read_dummy(u32 reg) 253 { 254 WARN_ON_ONCE((cpu_has_apic && !disable_apic)); 255 return 0; 256 } 257 258 /* 259 * right after this call apic->write/read doesn't do anything 260 * note that there is no restore operation it works one way 261 */ 262 void apic_disable(void) 263 { 264 apic->read = native_apic_read_dummy; 265 apic->write = native_apic_write_dummy; 266 } 267 268 void native_apic_wait_icr_idle(void) 269 { 270 while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 271 cpu_relax(); 272 } 273 274 u32 native_safe_apic_wait_icr_idle(void) 275 { 276 u32 send_status; 277 int timeout; 278 279 timeout = 0; 280 do { 281 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 282 if (!send_status) 283 break; 284 udelay(100); 285 } while (timeout++ < 1000); 286 287 return send_status; 288 } 289 290 void native_apic_icr_write(u32 low, u32 id) 291 { 292 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 293 apic_write(APIC_ICR, low); 294 } 295 296 u64 native_apic_icr_read(void) 297 { 298 u32 icr1, icr2; 299 300 icr2 = apic_read(APIC_ICR2); 301 icr1 = apic_read(APIC_ICR); 302 303 return icr1 | ((u64)icr2 << 32); 304 } 305 306 /** 307 * enable_NMI_through_LVT0 - enable NMI through local vector table 0 308 */ 309 void __cpuinit enable_NMI_through_LVT0(void) 310 { 311 unsigned int v; 312 313 /* unmask and set to NMI */ 314 v = APIC_DM_NMI; 315 316 /* Level triggered for 82489DX (32bit mode) */ 317 if (!lapic_is_integrated()) 318 v |= APIC_LVT_LEVEL_TRIGGER; 319 320 apic_write(APIC_LVT0, v); 321 } 322 323 #ifdef CONFIG_X86_32 324 /** 325 * get_physical_broadcast - Get number of physical broadcast IDs 326 */ 327 int get_physical_broadcast(void) 328 { 329 return modern_apic() ? 0xff : 0xf; 330 } 331 #endif 332 333 /** 334 * lapic_get_maxlvt - get the maximum number of local vector table entries 335 */ 336 int lapic_get_maxlvt(void) 337 { 338 unsigned int v; 339 340 v = apic_read(APIC_LVR); 341 /* 342 * - we always have APIC integrated on 64bit mode 343 * - 82489DXs do not report # of LVT entries 344 */ 345 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; 346 } 347 348 /* 349 * Local APIC timer 350 */ 351 352 /* Clock divisor */ 353 #define APIC_DIVISOR 16 354 355 /* 356 * This function sets up the local APIC timer, with a timeout of 357 * 'clocks' APIC bus clock. During calibration we actually call 358 * this function twice on the boot CPU, once with a bogus timeout 359 * value, second time for real. The other (noncalibrating) CPUs 360 * call this function only once, with the real, calibrated value. 361 * 362 * We do reads before writes even if unnecessary, to get around the 363 * P5 APIC double write bug. 364 */ 365 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 366 { 367 unsigned int lvtt_value, tmp_value; 368 369 lvtt_value = LOCAL_TIMER_VECTOR; 370 if (!oneshot) 371 lvtt_value |= APIC_LVT_TIMER_PERIODIC; 372 if (!lapic_is_integrated()) 373 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 374 375 if (!irqen) 376 lvtt_value |= APIC_LVT_MASKED; 377 378 apic_write(APIC_LVTT, lvtt_value); 379 380 /* 381 * Divide PICLK by 16 382 */ 383 tmp_value = apic_read(APIC_TDCR); 384 apic_write(APIC_TDCR, 385 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 386 APIC_TDR_DIV_16); 387 388 if (!oneshot) 389 apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 390 } 391 392 /* 393 * Setup extended LVT, AMD specific (K8, family 10h) 394 * 395 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and 396 * MCE interrupts are supported. Thus MCE offset must be set to 0. 397 * 398 * If mask=1, the LVT entry does not generate interrupts while mask=0 399 * enables the vector. See also the BKDGs. 400 */ 401 402 #define APIC_EILVT_LVTOFF_MCE 0 403 #define APIC_EILVT_LVTOFF_IBS 1 404 405 static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask) 406 { 407 unsigned long reg = (lvt_off << 4) + APIC_EILVTn(0); 408 unsigned int v = (mask << 16) | (msg_type << 8) | vector; 409 410 apic_write(reg, v); 411 } 412 413 u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask) 414 { 415 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask); 416 return APIC_EILVT_LVTOFF_MCE; 417 } 418 419 u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask) 420 { 421 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask); 422 return APIC_EILVT_LVTOFF_IBS; 423 } 424 EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs); 425 426 /* 427 * Program the next event, relative to now 428 */ 429 static int lapic_next_event(unsigned long delta, 430 struct clock_event_device *evt) 431 { 432 apic_write(APIC_TMICT, delta); 433 return 0; 434 } 435 436 /* 437 * Setup the lapic timer in periodic or oneshot mode 438 */ 439 static void lapic_timer_setup(enum clock_event_mode mode, 440 struct clock_event_device *evt) 441 { 442 unsigned long flags; 443 unsigned int v; 444 445 /* Lapic used as dummy for broadcast ? */ 446 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 447 return; 448 449 local_irq_save(flags); 450 451 switch (mode) { 452 case CLOCK_EVT_MODE_PERIODIC: 453 case CLOCK_EVT_MODE_ONESHOT: 454 __setup_APIC_LVTT(calibration_result, 455 mode != CLOCK_EVT_MODE_PERIODIC, 1); 456 break; 457 case CLOCK_EVT_MODE_UNUSED: 458 case CLOCK_EVT_MODE_SHUTDOWN: 459 v = apic_read(APIC_LVTT); 460 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 461 apic_write(APIC_LVTT, v); 462 apic_write(APIC_TMICT, 0xffffffff); 463 break; 464 case CLOCK_EVT_MODE_RESUME: 465 /* Nothing to do here */ 466 break; 467 } 468 469 local_irq_restore(flags); 470 } 471 472 /* 473 * Local APIC timer broadcast function 474 */ 475 static void lapic_timer_broadcast(const struct cpumask *mask) 476 { 477 #ifdef CONFIG_SMP 478 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 479 #endif 480 } 481 482 /* 483 * Setup the local APIC timer for this CPU. Copy the initilized values 484 * of the boot CPU and register the clock event in the framework. 485 */ 486 static void __cpuinit setup_APIC_timer(void) 487 { 488 struct clock_event_device *levt = &__get_cpu_var(lapic_events); 489 490 if (cpu_has(¤t_cpu_data, X86_FEATURE_ARAT)) { 491 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 492 /* Make LAPIC timer preferrable over percpu HPET */ 493 lapic_clockevent.rating = 150; 494 } 495 496 memcpy(levt, &lapic_clockevent, sizeof(*levt)); 497 levt->cpumask = cpumask_of(smp_processor_id()); 498 499 clockevents_register_device(levt); 500 } 501 502 /* 503 * In this functions we calibrate APIC bus clocks to the external timer. 504 * 505 * We want to do the calibration only once since we want to have local timer 506 * irqs syncron. CPUs connected by the same APIC bus have the very same bus 507 * frequency. 508 * 509 * This was previously done by reading the PIT/HPET and waiting for a wrap 510 * around to find out, that a tick has elapsed. I have a box, where the PIT 511 * readout is broken, so it never gets out of the wait loop again. This was 512 * also reported by others. 513 * 514 * Monitoring the jiffies value is inaccurate and the clockevents 515 * infrastructure allows us to do a simple substitution of the interrupt 516 * handler. 517 * 518 * The calibration routine also uses the pm_timer when possible, as the PIT 519 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 520 * back to normal later in the boot process). 521 */ 522 523 #define LAPIC_CAL_LOOPS (HZ/10) 524 525 static __initdata int lapic_cal_loops = -1; 526 static __initdata long lapic_cal_t1, lapic_cal_t2; 527 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 528 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 529 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 530 531 /* 532 * Temporary interrupt handler. 533 */ 534 static void __init lapic_cal_handler(struct clock_event_device *dev) 535 { 536 unsigned long long tsc = 0; 537 long tapic = apic_read(APIC_TMCCT); 538 unsigned long pm = acpi_pm_read_early(); 539 540 if (cpu_has_tsc) 541 rdtscll(tsc); 542 543 switch (lapic_cal_loops++) { 544 case 0: 545 lapic_cal_t1 = tapic; 546 lapic_cal_tsc1 = tsc; 547 lapic_cal_pm1 = pm; 548 lapic_cal_j1 = jiffies; 549 break; 550 551 case LAPIC_CAL_LOOPS: 552 lapic_cal_t2 = tapic; 553 lapic_cal_tsc2 = tsc; 554 if (pm < lapic_cal_pm1) 555 pm += ACPI_PM_OVRRUN; 556 lapic_cal_pm2 = pm; 557 lapic_cal_j2 = jiffies; 558 break; 559 } 560 } 561 562 static int __init 563 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 564 { 565 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 566 const long pm_thresh = pm_100ms / 100; 567 unsigned long mult; 568 u64 res; 569 570 #ifndef CONFIG_X86_PM_TIMER 571 return -1; 572 #endif 573 574 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 575 576 /* Check, if the PM timer is available */ 577 if (!deltapm) 578 return -1; 579 580 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 581 582 if (deltapm > (pm_100ms - pm_thresh) && 583 deltapm < (pm_100ms + pm_thresh)) { 584 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 585 return 0; 586 } 587 588 res = (((u64)deltapm) * mult) >> 22; 589 do_div(res, 1000000); 590 pr_warning("APIC calibration not consistent " 591 "with PM-Timer: %ldms instead of 100ms\n",(long)res); 592 593 /* Correct the lapic counter value */ 594 res = (((u64)(*delta)) * pm_100ms); 595 do_div(res, deltapm); 596 pr_info("APIC delta adjusted to PM-Timer: " 597 "%lu (%ld)\n", (unsigned long)res, *delta); 598 *delta = (long)res; 599 600 /* Correct the tsc counter value */ 601 if (cpu_has_tsc) { 602 res = (((u64)(*deltatsc)) * pm_100ms); 603 do_div(res, deltapm); 604 apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 605 "PM-Timer: %lu (%ld) \n", 606 (unsigned long)res, *deltatsc); 607 *deltatsc = (long)res; 608 } 609 610 return 0; 611 } 612 613 static int __init calibrate_APIC_clock(void) 614 { 615 struct clock_event_device *levt = &__get_cpu_var(lapic_events); 616 void (*real_handler)(struct clock_event_device *dev); 617 unsigned long deltaj; 618 long delta, deltatsc; 619 int pm_referenced = 0; 620 621 local_irq_disable(); 622 623 /* Replace the global interrupt handler */ 624 real_handler = global_clock_event->event_handler; 625 global_clock_event->event_handler = lapic_cal_handler; 626 627 /* 628 * Setup the APIC counter to maximum. There is no way the lapic 629 * can underflow in the 100ms detection time frame 630 */ 631 __setup_APIC_LVTT(0xffffffff, 0, 0); 632 633 /* Let the interrupts run */ 634 local_irq_enable(); 635 636 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 637 cpu_relax(); 638 639 local_irq_disable(); 640 641 /* Restore the real event handler */ 642 global_clock_event->event_handler = real_handler; 643 644 /* Build delta t1-t2 as apic timer counts down */ 645 delta = lapic_cal_t1 - lapic_cal_t2; 646 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 647 648 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 649 650 /* we trust the PM based calibration if possible */ 651 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 652 &delta, &deltatsc); 653 654 /* Calculate the scaled math multiplication factor */ 655 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 656 lapic_clockevent.shift); 657 lapic_clockevent.max_delta_ns = 658 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); 659 lapic_clockevent.min_delta_ns = 660 clockevent_delta2ns(0xF, &lapic_clockevent); 661 662 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 663 664 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 665 apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult); 666 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 667 calibration_result); 668 669 if (cpu_has_tsc) { 670 apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 671 "%ld.%04ld MHz.\n", 672 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 673 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 674 } 675 676 apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 677 "%u.%04u MHz.\n", 678 calibration_result / (1000000 / HZ), 679 calibration_result % (1000000 / HZ)); 680 681 /* 682 * Do a sanity check on the APIC calibration result 683 */ 684 if (calibration_result < (1000000 / HZ)) { 685 local_irq_enable(); 686 pr_warning("APIC frequency too slow, disabling apic timer\n"); 687 return -1; 688 } 689 690 levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 691 692 /* 693 * PM timer calibration failed or not turned on 694 * so lets try APIC timer based calibration 695 */ 696 if (!pm_referenced) { 697 apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 698 699 /* 700 * Setup the apic timer manually 701 */ 702 levt->event_handler = lapic_cal_handler; 703 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); 704 lapic_cal_loops = -1; 705 706 /* Let the interrupts run */ 707 local_irq_enable(); 708 709 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 710 cpu_relax(); 711 712 /* Stop the lapic timer */ 713 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); 714 715 /* Jiffies delta */ 716 deltaj = lapic_cal_j2 - lapic_cal_j1; 717 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 718 719 /* Check, if the jiffies result is consistent */ 720 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 721 apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 722 else 723 levt->features |= CLOCK_EVT_FEAT_DUMMY; 724 } else 725 local_irq_enable(); 726 727 if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 728 pr_warning("APIC timer disabled due to verification failure\n"); 729 return -1; 730 } 731 732 return 0; 733 } 734 735 /* 736 * Setup the boot APIC 737 * 738 * Calibrate and verify the result. 739 */ 740 void __init setup_boot_APIC_clock(void) 741 { 742 /* 743 * The local apic timer can be disabled via the kernel 744 * commandline or from the CPU detection code. Register the lapic 745 * timer as a dummy clock event source on SMP systems, so the 746 * broadcast mechanism is used. On UP systems simply ignore it. 747 */ 748 if (disable_apic_timer) { 749 pr_info("Disabling APIC timer\n"); 750 /* No broadcast on UP ! */ 751 if (num_possible_cpus() > 1) { 752 lapic_clockevent.mult = 1; 753 setup_APIC_timer(); 754 } 755 return; 756 } 757 758 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 759 "calibrating APIC timer ...\n"); 760 761 if (calibrate_APIC_clock()) { 762 /* No broadcast on UP ! */ 763 if (num_possible_cpus() > 1) 764 setup_APIC_timer(); 765 return; 766 } 767 768 /* 769 * If nmi_watchdog is set to IO_APIC, we need the 770 * PIT/HPET going. Otherwise register lapic as a dummy 771 * device. 772 */ 773 if (nmi_watchdog != NMI_IO_APIC) 774 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 775 else 776 pr_warning("APIC timer registered as dummy," 777 " due to nmi_watchdog=%d!\n", nmi_watchdog); 778 779 /* Setup the lapic or request the broadcast */ 780 setup_APIC_timer(); 781 } 782 783 void __cpuinit setup_secondary_APIC_clock(void) 784 { 785 setup_APIC_timer(); 786 } 787 788 /* 789 * The guts of the apic timer interrupt 790 */ 791 static void local_apic_timer_interrupt(void) 792 { 793 int cpu = smp_processor_id(); 794 struct clock_event_device *evt = &per_cpu(lapic_events, cpu); 795 796 /* 797 * Normally we should not be here till LAPIC has been initialized but 798 * in some cases like kdump, its possible that there is a pending LAPIC 799 * timer interrupt from previous kernel's context and is delivered in 800 * new kernel the moment interrupts are enabled. 801 * 802 * Interrupts are enabled early and LAPIC is setup much later, hence 803 * its possible that when we get here evt->event_handler is NULL. 804 * Check for event_handler being NULL and discard the interrupt as 805 * spurious. 806 */ 807 if (!evt->event_handler) { 808 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); 809 /* Switch it off */ 810 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); 811 return; 812 } 813 814 /* 815 * the NMI deadlock-detector uses this. 816 */ 817 inc_irq_stat(apic_timer_irqs); 818 819 evt->event_handler(evt); 820 } 821 822 /* 823 * Local APIC timer interrupt. This is the most natural way for doing 824 * local interrupts, but local timer interrupts can be emulated by 825 * broadcast interrupts too. [in case the hw doesn't support APIC timers] 826 * 827 * [ if a single-CPU system runs an SMP kernel then we call the local 828 * interrupt as well. Thus we cannot inline the local irq ... ] 829 */ 830 void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) 831 { 832 struct pt_regs *old_regs = set_irq_regs(regs); 833 834 /* 835 * NOTE! We'd better ACK the irq immediately, 836 * because timer handling can be slow. 837 */ 838 ack_APIC_irq(); 839 /* 840 * update_process_times() expects us to have done irq_enter(). 841 * Besides, if we don't timer interrupts ignore the global 842 * interrupt lock, which is the WrongThing (tm) to do. 843 */ 844 exit_idle(); 845 irq_enter(); 846 local_apic_timer_interrupt(); 847 irq_exit(); 848 849 set_irq_regs(old_regs); 850 } 851 852 int setup_profiling_timer(unsigned int multiplier) 853 { 854 return -EINVAL; 855 } 856 857 /* 858 * Local APIC start and shutdown 859 */ 860 861 /** 862 * clear_local_APIC - shutdown the local APIC 863 * 864 * This is called, when a CPU is disabled and before rebooting, so the state of 865 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 866 * leftovers during boot. 867 */ 868 void clear_local_APIC(void) 869 { 870 int maxlvt; 871 u32 v; 872 873 /* APIC hasn't been mapped yet */ 874 if (!x2apic_mode && !apic_phys) 875 return; 876 877 maxlvt = lapic_get_maxlvt(); 878 /* 879 * Masking an LVT entry can trigger a local APIC error 880 * if the vector is zero. Mask LVTERR first to prevent this. 881 */ 882 if (maxlvt >= 3) { 883 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 884 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 885 } 886 /* 887 * Careful: we have to set masks only first to deassert 888 * any level-triggered sources. 889 */ 890 v = apic_read(APIC_LVTT); 891 apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 892 v = apic_read(APIC_LVT0); 893 apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 894 v = apic_read(APIC_LVT1); 895 apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 896 if (maxlvt >= 4) { 897 v = apic_read(APIC_LVTPC); 898 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 899 } 900 901 /* lets not touch this if we didn't frob it */ 902 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) 903 if (maxlvt >= 5) { 904 v = apic_read(APIC_LVTTHMR); 905 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 906 } 907 #endif 908 #ifdef CONFIG_X86_MCE_INTEL 909 if (maxlvt >= 6) { 910 v = apic_read(APIC_LVTCMCI); 911 if (!(v & APIC_LVT_MASKED)) 912 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 913 } 914 #endif 915 916 /* 917 * Clean APIC state for other OSs: 918 */ 919 apic_write(APIC_LVTT, APIC_LVT_MASKED); 920 apic_write(APIC_LVT0, APIC_LVT_MASKED); 921 apic_write(APIC_LVT1, APIC_LVT_MASKED); 922 if (maxlvt >= 3) 923 apic_write(APIC_LVTERR, APIC_LVT_MASKED); 924 if (maxlvt >= 4) 925 apic_write(APIC_LVTPC, APIC_LVT_MASKED); 926 927 /* Integrated APIC (!82489DX) ? */ 928 if (lapic_is_integrated()) { 929 if (maxlvt > 3) 930 /* Clear ESR due to Pentium errata 3AP and 11AP */ 931 apic_write(APIC_ESR, 0); 932 apic_read(APIC_ESR); 933 } 934 } 935 936 /** 937 * disable_local_APIC - clear and disable the local APIC 938 */ 939 void disable_local_APIC(void) 940 { 941 unsigned int value; 942 943 /* APIC hasn't been mapped yet */ 944 if (!apic_phys) 945 return; 946 947 clear_local_APIC(); 948 949 /* 950 * Disable APIC (implies clearing of registers 951 * for 82489DX!). 952 */ 953 value = apic_read(APIC_SPIV); 954 value &= ~APIC_SPIV_APIC_ENABLED; 955 apic_write(APIC_SPIV, value); 956 957 #ifdef CONFIG_X86_32 958 /* 959 * When LAPIC was disabled by the BIOS and enabled by the kernel, 960 * restore the disabled state. 961 */ 962 if (enabled_via_apicbase) { 963 unsigned int l, h; 964 965 rdmsr(MSR_IA32_APICBASE, l, h); 966 l &= ~MSR_IA32_APICBASE_ENABLE; 967 wrmsr(MSR_IA32_APICBASE, l, h); 968 } 969 #endif 970 } 971 972 /* 973 * If Linux enabled the LAPIC against the BIOS default disable it down before 974 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 975 * not power-off. Additionally clear all LVT entries before disable_local_APIC 976 * for the case where Linux didn't enable the LAPIC. 977 */ 978 void lapic_shutdown(void) 979 { 980 unsigned long flags; 981 982 if (!cpu_has_apic) 983 return; 984 985 local_irq_save(flags); 986 987 #ifdef CONFIG_X86_32 988 if (!enabled_via_apicbase) 989 clear_local_APIC(); 990 else 991 #endif 992 disable_local_APIC(); 993 994 995 local_irq_restore(flags); 996 } 997 998 /* 999 * This is to verify that we're looking at a real local APIC. 1000 * Check these against your board if the CPUs aren't getting 1001 * started for no apparent reason. 1002 */ 1003 int __init verify_local_APIC(void) 1004 { 1005 unsigned int reg0, reg1; 1006 1007 /* 1008 * The version register is read-only in a real APIC. 1009 */ 1010 reg0 = apic_read(APIC_LVR); 1011 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); 1012 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); 1013 reg1 = apic_read(APIC_LVR); 1014 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); 1015 1016 /* 1017 * The two version reads above should print the same 1018 * numbers. If the second one is different, then we 1019 * poke at a non-APIC. 1020 */ 1021 if (reg1 != reg0) 1022 return 0; 1023 1024 /* 1025 * Check if the version looks reasonably. 1026 */ 1027 reg1 = GET_APIC_VERSION(reg0); 1028 if (reg1 == 0x00 || reg1 == 0xff) 1029 return 0; 1030 reg1 = lapic_get_maxlvt(); 1031 if (reg1 < 0x02 || reg1 == 0xff) 1032 return 0; 1033 1034 /* 1035 * The ID register is read/write in a real APIC. 1036 */ 1037 reg0 = apic_read(APIC_ID); 1038 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); 1039 apic_write(APIC_ID, reg0 ^ apic->apic_id_mask); 1040 reg1 = apic_read(APIC_ID); 1041 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); 1042 apic_write(APIC_ID, reg0); 1043 if (reg1 != (reg0 ^ apic->apic_id_mask)) 1044 return 0; 1045 1046 /* 1047 * The next two are just to see if we have sane values. 1048 * They're only really relevant if we're in Virtual Wire 1049 * compatibility mode, but most boxes are anymore. 1050 */ 1051 reg0 = apic_read(APIC_LVT0); 1052 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); 1053 reg1 = apic_read(APIC_LVT1); 1054 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); 1055 1056 return 1; 1057 } 1058 1059 /** 1060 * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1061 */ 1062 void __init sync_Arb_IDs(void) 1063 { 1064 /* 1065 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1066 * needed on AMD. 1067 */ 1068 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1069 return; 1070 1071 /* 1072 * Wait for idle. 1073 */ 1074 apic_wait_icr_idle(); 1075 1076 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1077 apic_write(APIC_ICR, APIC_DEST_ALLINC | 1078 APIC_INT_LEVELTRIG | APIC_DM_INIT); 1079 } 1080 1081 /* 1082 * An initial setup of the virtual wire mode. 1083 */ 1084 void __init init_bsp_APIC(void) 1085 { 1086 unsigned int value; 1087 1088 /* 1089 * Don't do the setup now if we have a SMP BIOS as the 1090 * through-I/O-APIC virtual wire mode might be active. 1091 */ 1092 if (smp_found_config || !cpu_has_apic) 1093 return; 1094 1095 /* 1096 * Do not trust the local APIC being empty at bootup. 1097 */ 1098 clear_local_APIC(); 1099 1100 /* 1101 * Enable APIC. 1102 */ 1103 value = apic_read(APIC_SPIV); 1104 value &= ~APIC_VECTOR_MASK; 1105 value |= APIC_SPIV_APIC_ENABLED; 1106 1107 #ifdef CONFIG_X86_32 1108 /* This bit is reserved on P4/Xeon and should be cleared */ 1109 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1110 (boot_cpu_data.x86 == 15)) 1111 value &= ~APIC_SPIV_FOCUS_DISABLED; 1112 else 1113 #endif 1114 value |= APIC_SPIV_FOCUS_DISABLED; 1115 value |= SPURIOUS_APIC_VECTOR; 1116 apic_write(APIC_SPIV, value); 1117 1118 /* 1119 * Set up the virtual wire mode. 1120 */ 1121 apic_write(APIC_LVT0, APIC_DM_EXTINT); 1122 value = APIC_DM_NMI; 1123 if (!lapic_is_integrated()) /* 82489DX */ 1124 value |= APIC_LVT_LEVEL_TRIGGER; 1125 apic_write(APIC_LVT1, value); 1126 } 1127 1128 static void __cpuinit lapic_setup_esr(void) 1129 { 1130 unsigned int oldvalue, value, maxlvt; 1131 1132 if (!lapic_is_integrated()) { 1133 pr_info("No ESR for 82489DX.\n"); 1134 return; 1135 } 1136 1137 if (apic->disable_esr) { 1138 /* 1139 * Something untraceable is creating bad interrupts on 1140 * secondary quads ... for the moment, just leave the 1141 * ESR disabled - we can't do anything useful with the 1142 * errors anyway - mbligh 1143 */ 1144 pr_info("Leaving ESR disabled.\n"); 1145 return; 1146 } 1147 1148 maxlvt = lapic_get_maxlvt(); 1149 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1150 apic_write(APIC_ESR, 0); 1151 oldvalue = apic_read(APIC_ESR); 1152 1153 /* enables sending errors */ 1154 value = ERROR_APIC_VECTOR; 1155 apic_write(APIC_LVTERR, value); 1156 1157 /* 1158 * spec says clear errors after enabling vector. 1159 */ 1160 if (maxlvt > 3) 1161 apic_write(APIC_ESR, 0); 1162 value = apic_read(APIC_ESR); 1163 if (value != oldvalue) 1164 apic_printk(APIC_VERBOSE, "ESR value before enabling " 1165 "vector: 0x%08x after: 0x%08x\n", 1166 oldvalue, value); 1167 } 1168 1169 1170 /** 1171 * setup_local_APIC - setup the local APIC 1172 */ 1173 void __cpuinit setup_local_APIC(void) 1174 { 1175 unsigned int value; 1176 int i, j; 1177 1178 if (disable_apic) { 1179 arch_disable_smp_support(); 1180 return; 1181 } 1182 1183 #ifdef CONFIG_X86_32 1184 /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1185 if (lapic_is_integrated() && apic->disable_esr) { 1186 apic_write(APIC_ESR, 0); 1187 apic_write(APIC_ESR, 0); 1188 apic_write(APIC_ESR, 0); 1189 apic_write(APIC_ESR, 0); 1190 } 1191 #endif 1192 perf_counters_lapic_init(); 1193 1194 preempt_disable(); 1195 1196 /* 1197 * Double-check whether this APIC is really registered. 1198 * This is meaningless in clustered apic mode, so we skip it. 1199 */ 1200 if (!apic->apic_id_registered()) 1201 BUG(); 1202 1203 /* 1204 * Intel recommends to set DFR, LDR and TPR before enabling 1205 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1206 * document number 292116). So here it goes... 1207 */ 1208 apic->init_apic_ldr(); 1209 1210 /* 1211 * Set Task Priority to 'accept all'. We never change this 1212 * later on. 1213 */ 1214 value = apic_read(APIC_TASKPRI); 1215 value &= ~APIC_TPRI_MASK; 1216 apic_write(APIC_TASKPRI, value); 1217 1218 /* 1219 * After a crash, we no longer service the interrupts and a pending 1220 * interrupt from previous kernel might still have ISR bit set. 1221 * 1222 * Most probably by now CPU has serviced that pending interrupt and 1223 * it might not have done the ack_APIC_irq() because it thought, 1224 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it 1225 * does not clear the ISR bit and cpu thinks it has already serivced 1226 * the interrupt. Hence a vector might get locked. It was noticed 1227 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. 1228 */ 1229 for (i = APIC_ISR_NR - 1; i >= 0; i--) { 1230 value = apic_read(APIC_ISR + i*0x10); 1231 for (j = 31; j >= 0; j--) { 1232 if (value & (1<<j)) 1233 ack_APIC_irq(); 1234 } 1235 } 1236 1237 /* 1238 * Now that we are all set up, enable the APIC 1239 */ 1240 value = apic_read(APIC_SPIV); 1241 value &= ~APIC_VECTOR_MASK; 1242 /* 1243 * Enable APIC 1244 */ 1245 value |= APIC_SPIV_APIC_ENABLED; 1246 1247 #ifdef CONFIG_X86_32 1248 /* 1249 * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1250 * certain networking cards. If high frequency interrupts are 1251 * happening on a particular IOAPIC pin, plus the IOAPIC routing 1252 * entry is masked/unmasked at a high rate as well then sooner or 1253 * later IOAPIC line gets 'stuck', no more interrupts are received 1254 * from the device. If focus CPU is disabled then the hang goes 1255 * away, oh well :-( 1256 * 1257 * [ This bug can be reproduced easily with a level-triggered 1258 * PCI Ne2000 networking cards and PII/PIII processors, dual 1259 * BX chipset. ] 1260 */ 1261 /* 1262 * Actually disabling the focus CPU check just makes the hang less 1263 * frequent as it makes the interrupt distributon model be more 1264 * like LRU than MRU (the short-term load is more even across CPUs). 1265 * See also the comment in end_level_ioapic_irq(). --macro 1266 */ 1267 1268 /* 1269 * - enable focus processor (bit==0) 1270 * - 64bit mode always use processor focus 1271 * so no need to set it 1272 */ 1273 value &= ~APIC_SPIV_FOCUS_DISABLED; 1274 #endif 1275 1276 /* 1277 * Set spurious IRQ vector 1278 */ 1279 value |= SPURIOUS_APIC_VECTOR; 1280 apic_write(APIC_SPIV, value); 1281 1282 /* 1283 * Set up LVT0, LVT1: 1284 * 1285 * set up through-local-APIC on the BP's LINT0. This is not 1286 * strictly necessary in pure symmetric-IO mode, but sometimes 1287 * we delegate interrupts to the 8259A. 1288 */ 1289 /* 1290 * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1291 */ 1292 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 1293 if (!smp_processor_id() && (pic_mode || !value)) { 1294 value = APIC_DM_EXTINT; 1295 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", 1296 smp_processor_id()); 1297 } else { 1298 value = APIC_DM_EXTINT | APIC_LVT_MASKED; 1299 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", 1300 smp_processor_id()); 1301 } 1302 apic_write(APIC_LVT0, value); 1303 1304 /* 1305 * only the BP should see the LINT1 NMI signal, obviously. 1306 */ 1307 if (!smp_processor_id()) 1308 value = APIC_DM_NMI; 1309 else 1310 value = APIC_DM_NMI | APIC_LVT_MASKED; 1311 if (!lapic_is_integrated()) /* 82489DX */ 1312 value |= APIC_LVT_LEVEL_TRIGGER; 1313 apic_write(APIC_LVT1, value); 1314 1315 preempt_enable(); 1316 1317 #ifdef CONFIG_X86_MCE_INTEL 1318 /* Recheck CMCI information after local APIC is up on CPU #0 */ 1319 if (smp_processor_id() == 0) 1320 cmci_recheck(); 1321 #endif 1322 } 1323 1324 void __cpuinit end_local_APIC_setup(void) 1325 { 1326 lapic_setup_esr(); 1327 1328 #ifdef CONFIG_X86_32 1329 { 1330 unsigned int value; 1331 /* Disable the local apic timer */ 1332 value = apic_read(APIC_LVTT); 1333 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1334 apic_write(APIC_LVTT, value); 1335 } 1336 #endif 1337 1338 setup_apic_nmi_watchdog(NULL); 1339 apic_pm_activate(); 1340 } 1341 1342 #ifdef CONFIG_X86_X2APIC 1343 void check_x2apic(void) 1344 { 1345 if (x2apic_enabled()) { 1346 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n"); 1347 x2apic_preenabled = x2apic_mode = 1; 1348 } 1349 } 1350 1351 void enable_x2apic(void) 1352 { 1353 int msr, msr2; 1354 1355 if (!x2apic_mode) 1356 return; 1357 1358 rdmsr(MSR_IA32_APICBASE, msr, msr2); 1359 if (!(msr & X2APIC_ENABLE)) { 1360 pr_info("Enabling x2apic\n"); 1361 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0); 1362 } 1363 } 1364 #endif /* CONFIG_X86_X2APIC */ 1365 1366 void __init enable_IR_x2apic(void) 1367 { 1368 #ifdef CONFIG_INTR_REMAP 1369 int ret; 1370 unsigned long flags; 1371 struct IO_APIC_route_entry **ioapic_entries = NULL; 1372 1373 ret = dmar_table_init(); 1374 if (ret) { 1375 pr_debug("dmar_table_init() failed with %d:\n", ret); 1376 goto ir_failed; 1377 } 1378 1379 if (!intr_remapping_supported()) { 1380 pr_debug("intr-remapping not supported\n"); 1381 goto ir_failed; 1382 } 1383 1384 1385 if (!x2apic_preenabled && skip_ioapic_setup) { 1386 pr_info("Skipped enabling intr-remap because of skipping " 1387 "io-apic setup\n"); 1388 return; 1389 } 1390 1391 ioapic_entries = alloc_ioapic_entries(); 1392 if (!ioapic_entries) { 1393 pr_info("Allocate ioapic_entries failed: %d\n", ret); 1394 goto end; 1395 } 1396 1397 ret = save_IO_APIC_setup(ioapic_entries); 1398 if (ret) { 1399 pr_info("Saving IO-APIC state failed: %d\n", ret); 1400 goto end; 1401 } 1402 1403 local_irq_save(flags); 1404 mask_IO_APIC_setup(ioapic_entries); 1405 mask_8259A(); 1406 1407 ret = enable_intr_remapping(x2apic_supported()); 1408 if (ret) 1409 goto end_restore; 1410 1411 pr_info("Enabled Interrupt-remapping\n"); 1412 1413 if (x2apic_supported() && !x2apic_mode) { 1414 x2apic_mode = 1; 1415 enable_x2apic(); 1416 pr_info("Enabled x2apic\n"); 1417 } 1418 1419 end_restore: 1420 if (ret) 1421 /* 1422 * IR enabling failed 1423 */ 1424 restore_IO_APIC_setup(ioapic_entries); 1425 1426 unmask_8259A(); 1427 local_irq_restore(flags); 1428 1429 end: 1430 if (ioapic_entries) 1431 free_ioapic_entries(ioapic_entries); 1432 1433 if (!ret) 1434 return; 1435 1436 ir_failed: 1437 if (x2apic_preenabled) 1438 panic("x2apic enabled by bios. But IR enabling failed"); 1439 else if (cpu_has_x2apic) 1440 pr_info("Not enabling x2apic,Intr-remapping\n"); 1441 #else 1442 if (!cpu_has_x2apic) 1443 return; 1444 1445 if (x2apic_preenabled) 1446 panic("x2apic enabled prior OS handover," 1447 " enable CONFIG_X86_X2APIC, CONFIG_INTR_REMAP"); 1448 #endif 1449 1450 return; 1451 } 1452 1453 1454 #ifdef CONFIG_X86_64 1455 /* 1456 * Detect and enable local APICs on non-SMP boards. 1457 * Original code written by Keir Fraser. 1458 * On AMD64 we trust the BIOS - if it says no APIC it is likely 1459 * not correctly set up (usually the APIC timer won't work etc.) 1460 */ 1461 static int __init detect_init_APIC(void) 1462 { 1463 if (!cpu_has_apic) { 1464 pr_info("No local APIC present\n"); 1465 return -1; 1466 } 1467 1468 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1469 return 0; 1470 } 1471 #else 1472 /* 1473 * Detect and initialize APIC 1474 */ 1475 static int __init detect_init_APIC(void) 1476 { 1477 u32 h, l, features; 1478 1479 /* Disabled by kernel option? */ 1480 if (disable_apic) 1481 return -1; 1482 1483 switch (boot_cpu_data.x86_vendor) { 1484 case X86_VENDOR_AMD: 1485 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 1486 (boot_cpu_data.x86 >= 15)) 1487 break; 1488 goto no_apic; 1489 case X86_VENDOR_INTEL: 1490 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 1491 (boot_cpu_data.x86 == 5 && cpu_has_apic)) 1492 break; 1493 goto no_apic; 1494 default: 1495 goto no_apic; 1496 } 1497 1498 if (!cpu_has_apic) { 1499 /* 1500 * Over-ride BIOS and try to enable the local APIC only if 1501 * "lapic" specified. 1502 */ 1503 if (!force_enable_local_apic) { 1504 pr_info("Local APIC disabled by BIOS -- " 1505 "you can enable it with \"lapic\"\n"); 1506 return -1; 1507 } 1508 /* 1509 * Some BIOSes disable the local APIC in the APIC_BASE 1510 * MSR. This can only be done in software for Intel P6 or later 1511 * and AMD K7 (Model > 1) or later. 1512 */ 1513 rdmsr(MSR_IA32_APICBASE, l, h); 1514 if (!(l & MSR_IA32_APICBASE_ENABLE)) { 1515 pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 1516 l &= ~MSR_IA32_APICBASE_BASE; 1517 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; 1518 wrmsr(MSR_IA32_APICBASE, l, h); 1519 enabled_via_apicbase = 1; 1520 } 1521 } 1522 /* 1523 * The APIC feature bit should now be enabled 1524 * in `cpuid' 1525 */ 1526 features = cpuid_edx(1); 1527 if (!(features & (1 << X86_FEATURE_APIC))) { 1528 pr_warning("Could not enable APIC!\n"); 1529 return -1; 1530 } 1531 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 1532 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1533 1534 /* The BIOS may have set up the APIC at some other address */ 1535 rdmsr(MSR_IA32_APICBASE, l, h); 1536 if (l & MSR_IA32_APICBASE_ENABLE) 1537 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 1538 1539 pr_info("Found and enabled local APIC!\n"); 1540 1541 apic_pm_activate(); 1542 1543 return 0; 1544 1545 no_apic: 1546 pr_info("No local APIC present or hardware disabled\n"); 1547 return -1; 1548 } 1549 #endif 1550 1551 #ifdef CONFIG_X86_64 1552 void __init early_init_lapic_mapping(void) 1553 { 1554 unsigned long phys_addr; 1555 1556 /* 1557 * If no local APIC can be found then go out 1558 * : it means there is no mpatable and MADT 1559 */ 1560 if (!smp_found_config) 1561 return; 1562 1563 phys_addr = mp_lapic_addr; 1564 1565 set_fixmap_nocache(FIX_APIC_BASE, phys_addr); 1566 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 1567 APIC_BASE, phys_addr); 1568 1569 /* 1570 * Fetch the APIC ID of the BSP in case we have a 1571 * default configuration (or the MP table is broken). 1572 */ 1573 boot_cpu_physical_apicid = read_apic_id(); 1574 } 1575 #endif 1576 1577 /** 1578 * init_apic_mappings - initialize APIC mappings 1579 */ 1580 void __init init_apic_mappings(void) 1581 { 1582 unsigned int new_apicid; 1583 1584 if (x2apic_mode) { 1585 boot_cpu_physical_apicid = read_apic_id(); 1586 return; 1587 } 1588 1589 /* If no local APIC can be found return early */ 1590 if (!smp_found_config && detect_init_APIC()) { 1591 /* lets NOP'ify apic operations */ 1592 pr_info("APIC: disable apic facility\n"); 1593 apic_disable(); 1594 } else { 1595 apic_phys = mp_lapic_addr; 1596 1597 /* 1598 * acpi lapic path already maps that address in 1599 * acpi_register_lapic_address() 1600 */ 1601 if (!acpi_lapic) 1602 set_fixmap_nocache(FIX_APIC_BASE, apic_phys); 1603 1604 apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n", 1605 APIC_BASE, apic_phys); 1606 } 1607 1608 /* 1609 * Fetch the APIC ID of the BSP in case we have a 1610 * default configuration (or the MP table is broken). 1611 */ 1612 new_apicid = read_apic_id(); 1613 if (boot_cpu_physical_apicid != new_apicid) { 1614 boot_cpu_physical_apicid = new_apicid; 1615 /* 1616 * yeah -- we lie about apic_version 1617 * in case if apic was disabled via boot option 1618 * but it's not a problem for SMP compiled kernel 1619 * since smp_sanity_check is prepared for such a case 1620 * and disable smp mode 1621 */ 1622 apic_version[new_apicid] = 1623 GET_APIC_VERSION(apic_read(APIC_LVR)); 1624 } 1625 } 1626 1627 /* 1628 * This initializes the IO-APIC and APIC hardware if this is 1629 * a UP kernel. 1630 */ 1631 int apic_version[MAX_APICS]; 1632 1633 int __init APIC_init_uniprocessor(void) 1634 { 1635 if (disable_apic) { 1636 pr_info("Apic disabled\n"); 1637 return -1; 1638 } 1639 #ifdef CONFIG_X86_64 1640 if (!cpu_has_apic) { 1641 disable_apic = 1; 1642 pr_info("Apic disabled by BIOS\n"); 1643 return -1; 1644 } 1645 #else 1646 if (!smp_found_config && !cpu_has_apic) 1647 return -1; 1648 1649 /* 1650 * Complain if the BIOS pretends there is one. 1651 */ 1652 if (!cpu_has_apic && 1653 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 1654 pr_err("BIOS bug, local APIC 0x%x not detected!...\n", 1655 boot_cpu_physical_apicid); 1656 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 1657 return -1; 1658 } 1659 #endif 1660 1661 enable_IR_x2apic(); 1662 #ifdef CONFIG_X86_64 1663 default_setup_apic_routing(); 1664 #endif 1665 1666 verify_local_APIC(); 1667 connect_bsp_APIC(); 1668 1669 #ifdef CONFIG_X86_64 1670 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); 1671 #else 1672 /* 1673 * Hack: In case of kdump, after a crash, kernel might be booting 1674 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 1675 * might be zero if read from MP tables. Get it from LAPIC. 1676 */ 1677 # ifdef CONFIG_CRASH_DUMP 1678 boot_cpu_physical_apicid = read_apic_id(); 1679 # endif 1680 #endif 1681 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1682 setup_local_APIC(); 1683 1684 #ifdef CONFIG_X86_IO_APIC 1685 /* 1686 * Now enable IO-APICs, actually call clear_IO_APIC 1687 * We need clear_IO_APIC before enabling error vector 1688 */ 1689 if (!skip_ioapic_setup && nr_ioapics) 1690 enable_IO_APIC(); 1691 #endif 1692 1693 end_local_APIC_setup(); 1694 1695 #ifdef CONFIG_X86_IO_APIC 1696 if (smp_found_config && !skip_ioapic_setup && nr_ioapics) 1697 setup_IO_APIC(); 1698 else { 1699 nr_ioapics = 0; 1700 localise_nmi_watchdog(); 1701 } 1702 #else 1703 localise_nmi_watchdog(); 1704 #endif 1705 1706 setup_boot_clock(); 1707 #ifdef CONFIG_X86_64 1708 check_nmi_watchdog(); 1709 #endif 1710 1711 return 0; 1712 } 1713 1714 /* 1715 * Local APIC interrupts 1716 */ 1717 1718 /* 1719 * This interrupt should _never_ happen with our APIC/SMP architecture 1720 */ 1721 void smp_spurious_interrupt(struct pt_regs *regs) 1722 { 1723 u32 v; 1724 1725 exit_idle(); 1726 irq_enter(); 1727 /* 1728 * Check if this really is a spurious interrupt and ACK it 1729 * if it is a vectored one. Just in case... 1730 * Spurious interrupts should not be ACKed. 1731 */ 1732 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); 1733 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) 1734 ack_APIC_irq(); 1735 1736 inc_irq_stat(irq_spurious_count); 1737 1738 /* see sw-dev-man vol 3, chapter 7.4.13.5 */ 1739 pr_info("spurious APIC interrupt on CPU#%d, " 1740 "should never happen.\n", smp_processor_id()); 1741 irq_exit(); 1742 } 1743 1744 /* 1745 * This interrupt should never happen with our APIC/SMP architecture 1746 */ 1747 void smp_error_interrupt(struct pt_regs *regs) 1748 { 1749 u32 v, v1; 1750 1751 exit_idle(); 1752 irq_enter(); 1753 /* First tickle the hardware, only then report what went on. -- REW */ 1754 v = apic_read(APIC_ESR); 1755 apic_write(APIC_ESR, 0); 1756 v1 = apic_read(APIC_ESR); 1757 ack_APIC_irq(); 1758 atomic_inc(&irq_err_count); 1759 1760 /* 1761 * Here is what the APIC error bits mean: 1762 * 0: Send CS error 1763 * 1: Receive CS error 1764 * 2: Send accept error 1765 * 3: Receive accept error 1766 * 4: Reserved 1767 * 5: Send illegal vector 1768 * 6: Received illegal vector 1769 * 7: Illegal register address 1770 */ 1771 pr_debug("APIC error on CPU%d: %02x(%02x)\n", 1772 smp_processor_id(), v , v1); 1773 irq_exit(); 1774 } 1775 1776 /** 1777 * connect_bsp_APIC - attach the APIC to the interrupt system 1778 */ 1779 void __init connect_bsp_APIC(void) 1780 { 1781 #ifdef CONFIG_X86_32 1782 if (pic_mode) { 1783 /* 1784 * Do not trust the local APIC being empty at bootup. 1785 */ 1786 clear_local_APIC(); 1787 /* 1788 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 1789 * local APIC to INT and NMI lines. 1790 */ 1791 apic_printk(APIC_VERBOSE, "leaving PIC mode, " 1792 "enabling APIC mode.\n"); 1793 imcr_pic_to_apic(); 1794 } 1795 #endif 1796 if (apic->enable_apic_mode) 1797 apic->enable_apic_mode(); 1798 } 1799 1800 /** 1801 * disconnect_bsp_APIC - detach the APIC from the interrupt system 1802 * @virt_wire_setup: indicates, whether virtual wire mode is selected 1803 * 1804 * Virtual wire mode is necessary to deliver legacy interrupts even when the 1805 * APIC is disabled. 1806 */ 1807 void disconnect_bsp_APIC(int virt_wire_setup) 1808 { 1809 unsigned int value; 1810 1811 #ifdef CONFIG_X86_32 1812 if (pic_mode) { 1813 /* 1814 * Put the board back into PIC mode (has an effect only on 1815 * certain older boards). Note that APIC interrupts, including 1816 * IPIs, won't work beyond this point! The only exception are 1817 * INIT IPIs. 1818 */ 1819 apic_printk(APIC_VERBOSE, "disabling APIC mode, " 1820 "entering PIC mode.\n"); 1821 imcr_apic_to_pic(); 1822 return; 1823 } 1824 #endif 1825 1826 /* Go back to Virtual Wire compatibility mode */ 1827 1828 /* For the spurious interrupt use vector F, and enable it */ 1829 value = apic_read(APIC_SPIV); 1830 value &= ~APIC_VECTOR_MASK; 1831 value |= APIC_SPIV_APIC_ENABLED; 1832 value |= 0xf; 1833 apic_write(APIC_SPIV, value); 1834 1835 if (!virt_wire_setup) { 1836 /* 1837 * For LVT0 make it edge triggered, active high, 1838 * external and enabled 1839 */ 1840 value = apic_read(APIC_LVT0); 1841 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 1842 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 1843 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 1844 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 1845 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 1846 apic_write(APIC_LVT0, value); 1847 } else { 1848 /* Disable LVT0 */ 1849 apic_write(APIC_LVT0, APIC_LVT_MASKED); 1850 } 1851 1852 /* 1853 * For LVT1 make it edge triggered, active high, 1854 * nmi and enabled 1855 */ 1856 value = apic_read(APIC_LVT1); 1857 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 1858 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 1859 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 1860 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 1861 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 1862 apic_write(APIC_LVT1, value); 1863 } 1864 1865 void __cpuinit generic_processor_info(int apicid, int version) 1866 { 1867 int cpu; 1868 1869 /* 1870 * Validate version 1871 */ 1872 if (version == 0x0) { 1873 pr_warning("BIOS bug, APIC version is 0 for CPU#%d! " 1874 "fixing up to 0x10. (tell your hw vendor)\n", 1875 version); 1876 version = 0x10; 1877 } 1878 apic_version[apicid] = version; 1879 1880 if (num_processors >= nr_cpu_ids) { 1881 int max = nr_cpu_ids; 1882 int thiscpu = max + disabled_cpus; 1883 1884 pr_warning( 1885 "ACPI: NR_CPUS/possible_cpus limit of %i reached." 1886 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 1887 1888 disabled_cpus++; 1889 return; 1890 } 1891 1892 num_processors++; 1893 cpu = cpumask_next_zero(-1, cpu_present_mask); 1894 1895 if (version != apic_version[boot_cpu_physical_apicid]) 1896 WARN_ONCE(1, 1897 "ACPI: apic version mismatch, bootcpu: %x cpu %d: %x\n", 1898 apic_version[boot_cpu_physical_apicid], cpu, version); 1899 1900 physid_set(apicid, phys_cpu_present_map); 1901 if (apicid == boot_cpu_physical_apicid) { 1902 /* 1903 * x86_bios_cpu_apicid is required to have processors listed 1904 * in same order as logical cpu numbers. Hence the first 1905 * entry is BSP, and so on. 1906 */ 1907 cpu = 0; 1908 } 1909 if (apicid > max_physical_apicid) 1910 max_physical_apicid = apicid; 1911 1912 #ifdef CONFIG_X86_32 1913 /* 1914 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y 1915 * but we need to work other dependencies like SMP_SUSPEND etc 1916 * before this can be done without some confusion. 1917 * if (CPU_HOTPLUG_ENABLED || num_processors > 8) 1918 * - Ashok Raj <ashok.raj@intel.com> 1919 */ 1920 if (max_physical_apicid >= 8) { 1921 switch (boot_cpu_data.x86_vendor) { 1922 case X86_VENDOR_INTEL: 1923 if (!APIC_XAPIC(version)) { 1924 def_to_bigsmp = 0; 1925 break; 1926 } 1927 /* If P4 and above fall through */ 1928 case X86_VENDOR_AMD: 1929 def_to_bigsmp = 1; 1930 } 1931 } 1932 #endif 1933 1934 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 1935 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 1936 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 1937 #endif 1938 1939 set_cpu_possible(cpu, true); 1940 set_cpu_present(cpu, true); 1941 } 1942 1943 int hard_smp_processor_id(void) 1944 { 1945 return read_apic_id(); 1946 } 1947 1948 void default_init_apic_ldr(void) 1949 { 1950 unsigned long val; 1951 1952 apic_write(APIC_DFR, APIC_DFR_VALUE); 1953 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; 1954 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); 1955 apic_write(APIC_LDR, val); 1956 } 1957 1958 #ifdef CONFIG_X86_32 1959 int default_apicid_to_node(int logical_apicid) 1960 { 1961 #ifdef CONFIG_SMP 1962 return apicid_2_node[hard_smp_processor_id()]; 1963 #else 1964 return 0; 1965 #endif 1966 } 1967 #endif 1968 1969 /* 1970 * Power management 1971 */ 1972 #ifdef CONFIG_PM 1973 1974 static struct { 1975 /* 1976 * 'active' is true if the local APIC was enabled by us and 1977 * not the BIOS; this signifies that we are also responsible 1978 * for disabling it before entering apm/acpi suspend 1979 */ 1980 int active; 1981 /* r/w apic fields */ 1982 unsigned int apic_id; 1983 unsigned int apic_taskpri; 1984 unsigned int apic_ldr; 1985 unsigned int apic_dfr; 1986 unsigned int apic_spiv; 1987 unsigned int apic_lvtt; 1988 unsigned int apic_lvtpc; 1989 unsigned int apic_lvt0; 1990 unsigned int apic_lvt1; 1991 unsigned int apic_lvterr; 1992 unsigned int apic_tmict; 1993 unsigned int apic_tdcr; 1994 unsigned int apic_thmr; 1995 } apic_pm_state; 1996 1997 static int lapic_suspend(struct sys_device *dev, pm_message_t state) 1998 { 1999 unsigned long flags; 2000 int maxlvt; 2001 2002 if (!apic_pm_state.active) 2003 return 0; 2004 2005 maxlvt = lapic_get_maxlvt(); 2006 2007 apic_pm_state.apic_id = apic_read(APIC_ID); 2008 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 2009 apic_pm_state.apic_ldr = apic_read(APIC_LDR); 2010 apic_pm_state.apic_dfr = apic_read(APIC_DFR); 2011 apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2012 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2013 if (maxlvt >= 4) 2014 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2015 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2016 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2017 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2018 apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2019 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 2020 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) 2021 if (maxlvt >= 5) 2022 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2023 #endif 2024 2025 local_irq_save(flags); 2026 disable_local_APIC(); 2027 2028 if (intr_remapping_enabled) 2029 disable_intr_remapping(); 2030 2031 local_irq_restore(flags); 2032 return 0; 2033 } 2034 2035 static int lapic_resume(struct sys_device *dev) 2036 { 2037 unsigned int l, h; 2038 unsigned long flags; 2039 int maxlvt; 2040 int ret = 0; 2041 struct IO_APIC_route_entry **ioapic_entries = NULL; 2042 2043 if (!apic_pm_state.active) 2044 return 0; 2045 2046 local_irq_save(flags); 2047 if (intr_remapping_enabled) { 2048 ioapic_entries = alloc_ioapic_entries(); 2049 if (!ioapic_entries) { 2050 WARN(1, "Alloc ioapic_entries in lapic resume failed."); 2051 ret = -ENOMEM; 2052 goto restore; 2053 } 2054 2055 ret = save_IO_APIC_setup(ioapic_entries); 2056 if (ret) { 2057 WARN(1, "Saving IO-APIC state failed: %d\n", ret); 2058 free_ioapic_entries(ioapic_entries); 2059 goto restore; 2060 } 2061 2062 mask_IO_APIC_setup(ioapic_entries); 2063 mask_8259A(); 2064 } 2065 2066 if (x2apic_mode) 2067 enable_x2apic(); 2068 else { 2069 /* 2070 * Make sure the APICBASE points to the right address 2071 * 2072 * FIXME! This will be wrong if we ever support suspend on 2073 * SMP! We'll need to do this as part of the CPU restore! 2074 */ 2075 rdmsr(MSR_IA32_APICBASE, l, h); 2076 l &= ~MSR_IA32_APICBASE_BASE; 2077 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2078 wrmsr(MSR_IA32_APICBASE, l, h); 2079 } 2080 2081 maxlvt = lapic_get_maxlvt(); 2082 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2083 apic_write(APIC_ID, apic_pm_state.apic_id); 2084 apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2085 apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2086 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2087 apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2088 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2089 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 2090 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) 2091 if (maxlvt >= 5) 2092 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2093 #endif 2094 if (maxlvt >= 4) 2095 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2096 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2097 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2098 apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2099 apic_write(APIC_ESR, 0); 2100 apic_read(APIC_ESR); 2101 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2102 apic_write(APIC_ESR, 0); 2103 apic_read(APIC_ESR); 2104 2105 if (intr_remapping_enabled) { 2106 reenable_intr_remapping(x2apic_mode); 2107 unmask_8259A(); 2108 restore_IO_APIC_setup(ioapic_entries); 2109 free_ioapic_entries(ioapic_entries); 2110 } 2111 restore: 2112 local_irq_restore(flags); 2113 2114 return ret; 2115 } 2116 2117 /* 2118 * This device has no shutdown method - fully functioning local APICs 2119 * are needed on every CPU up until machine_halt/restart/poweroff. 2120 */ 2121 2122 static struct sysdev_class lapic_sysclass = { 2123 .name = "lapic", 2124 .resume = lapic_resume, 2125 .suspend = lapic_suspend, 2126 }; 2127 2128 static struct sys_device device_lapic = { 2129 .id = 0, 2130 .cls = &lapic_sysclass, 2131 }; 2132 2133 static void __cpuinit apic_pm_activate(void) 2134 { 2135 apic_pm_state.active = 1; 2136 } 2137 2138 static int __init init_lapic_sysfs(void) 2139 { 2140 int error; 2141 2142 if (!cpu_has_apic) 2143 return 0; 2144 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 2145 2146 error = sysdev_class_register(&lapic_sysclass); 2147 if (!error) 2148 error = sysdev_register(&device_lapic); 2149 return error; 2150 } 2151 2152 /* local apic needs to resume before other devices access its registers. */ 2153 core_initcall(init_lapic_sysfs); 2154 2155 #else /* CONFIG_PM */ 2156 2157 static void apic_pm_activate(void) { } 2158 2159 #endif /* CONFIG_PM */ 2160 2161 #ifdef CONFIG_X86_64 2162 2163 static int __cpuinit apic_cluster_num(void) 2164 { 2165 int i, clusters, zeros; 2166 unsigned id; 2167 u16 *bios_cpu_apicid; 2168 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); 2169 2170 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); 2171 bitmap_zero(clustermap, NUM_APIC_CLUSTERS); 2172 2173 for (i = 0; i < nr_cpu_ids; i++) { 2174 /* are we being called early in kernel startup? */ 2175 if (bios_cpu_apicid) { 2176 id = bios_cpu_apicid[i]; 2177 } else if (i < nr_cpu_ids) { 2178 if (cpu_present(i)) 2179 id = per_cpu(x86_bios_cpu_apicid, i); 2180 else 2181 continue; 2182 } else 2183 break; 2184 2185 if (id != BAD_APICID) 2186 __set_bit(APIC_CLUSTERID(id), clustermap); 2187 } 2188 2189 /* Problem: Partially populated chassis may not have CPUs in some of 2190 * the APIC clusters they have been allocated. Only present CPUs have 2191 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. 2192 * Since clusters are allocated sequentially, count zeros only if 2193 * they are bounded by ones. 2194 */ 2195 clusters = 0; 2196 zeros = 0; 2197 for (i = 0; i < NUM_APIC_CLUSTERS; i++) { 2198 if (test_bit(i, clustermap)) { 2199 clusters += 1 + zeros; 2200 zeros = 0; 2201 } else 2202 ++zeros; 2203 } 2204 2205 return clusters; 2206 } 2207 2208 static int __cpuinitdata multi_checked; 2209 static int __cpuinitdata multi; 2210 2211 static int __cpuinit set_multi(const struct dmi_system_id *d) 2212 { 2213 if (multi) 2214 return 0; 2215 pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2216 multi = 1; 2217 return 0; 2218 } 2219 2220 static const __cpuinitconst struct dmi_system_id multi_dmi_table[] = { 2221 { 2222 .callback = set_multi, 2223 .ident = "IBM System Summit2", 2224 .matches = { 2225 DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2226 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2227 }, 2228 }, 2229 {} 2230 }; 2231 2232 static void __cpuinit dmi_check_multi(void) 2233 { 2234 if (multi_checked) 2235 return; 2236 2237 dmi_check_system(multi_dmi_table); 2238 multi_checked = 1; 2239 } 2240 2241 /* 2242 * apic_is_clustered_box() -- Check if we can expect good TSC 2243 * 2244 * Thus far, the major user of this is IBM's Summit2 series: 2245 * Clustered boxes may have unsynced TSC problems if they are 2246 * multi-chassis. 2247 * Use DMI to check them 2248 */ 2249 __cpuinit int apic_is_clustered_box(void) 2250 { 2251 dmi_check_multi(); 2252 if (multi) 2253 return 1; 2254 2255 if (!is_vsmp_box()) 2256 return 0; 2257 2258 /* 2259 * ScaleMP vSMPowered boxes have one cluster per board and TSCs are 2260 * not guaranteed to be synced between boards 2261 */ 2262 if (apic_cluster_num() > 1) 2263 return 1; 2264 2265 return 0; 2266 } 2267 #endif 2268 2269 /* 2270 * APIC command line parameters 2271 */ 2272 static int __init setup_disableapic(char *arg) 2273 { 2274 disable_apic = 1; 2275 setup_clear_cpu_cap(X86_FEATURE_APIC); 2276 return 0; 2277 } 2278 early_param("disableapic", setup_disableapic); 2279 2280 /* same as disableapic, for compatibility */ 2281 static int __init setup_nolapic(char *arg) 2282 { 2283 return setup_disableapic(arg); 2284 } 2285 early_param("nolapic", setup_nolapic); 2286 2287 static int __init parse_lapic_timer_c2_ok(char *arg) 2288 { 2289 local_apic_timer_c2_ok = 1; 2290 return 0; 2291 } 2292 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2293 2294 static int __init parse_disable_apic_timer(char *arg) 2295 { 2296 disable_apic_timer = 1; 2297 return 0; 2298 } 2299 early_param("noapictimer", parse_disable_apic_timer); 2300 2301 static int __init parse_nolapic_timer(char *arg) 2302 { 2303 disable_apic_timer = 1; 2304 return 0; 2305 } 2306 early_param("nolapic_timer", parse_nolapic_timer); 2307 2308 static int __init apic_set_verbosity(char *arg) 2309 { 2310 if (!arg) { 2311 #ifdef CONFIG_X86_64 2312 skip_ioapic_setup = 0; 2313 return 0; 2314 #endif 2315 return -EINVAL; 2316 } 2317 2318 if (strcmp("debug", arg) == 0) 2319 apic_verbosity = APIC_DEBUG; 2320 else if (strcmp("verbose", arg) == 0) 2321 apic_verbosity = APIC_VERBOSE; 2322 else { 2323 pr_warning("APIC Verbosity level %s not recognised" 2324 " use apic=verbose or apic=debug\n", arg); 2325 return -EINVAL; 2326 } 2327 2328 return 0; 2329 } 2330 early_param("apic", apic_set_verbosity); 2331 2332 static int __init lapic_insert_resource(void) 2333 { 2334 if (!apic_phys) 2335 return -1; 2336 2337 /* Put local APIC into the resource map. */ 2338 lapic_resource.start = apic_phys; 2339 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2340 insert_resource(&iomem_resource, &lapic_resource); 2341 2342 return 0; 2343 } 2344 2345 /* 2346 * need call insert after e820_reserve_resources() 2347 * that is using request_resource 2348 */ 2349 late_initcall(lapic_insert_resource); 2350