1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Local APIC handling, local APIC timers 4 * 5 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * 7 * Fixes 8 * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 9 * thanks to Eric Gilmore 10 * and Rolf G. Tews 11 * for testing these extensively. 12 * Maciej W. Rozycki : Various updates and fixes. 13 * Mikael Pettersson : Power Management for UP-APIC. 14 * Pavel Machek and 15 * Mikael Pettersson : PM converted to driver model. 16 */ 17 18 #include <linux/perf_event.h> 19 #include <linux/kernel_stat.h> 20 #include <linux/mc146818rtc.h> 21 #include <linux/acpi_pmtmr.h> 22 #include <linux/clockchips.h> 23 #include <linux/interrupt.h> 24 #include <linux/memblock.h> 25 #include <linux/ftrace.h> 26 #include <linux/ioport.h> 27 #include <linux/export.h> 28 #include <linux/syscore_ops.h> 29 #include <linux/delay.h> 30 #include <linux/timex.h> 31 #include <linux/i8253.h> 32 #include <linux/dmar.h> 33 #include <linux/init.h> 34 #include <linux/cpu.h> 35 #include <linux/dmi.h> 36 #include <linux/smp.h> 37 #include <linux/mm.h> 38 39 #include <asm/trace/irq_vectors.h> 40 #include <asm/irq_remapping.h> 41 #include <asm/perf_event.h> 42 #include <asm/x86_init.h> 43 #include <asm/pgalloc.h> 44 #include <linux/atomic.h> 45 #include <asm/mpspec.h> 46 #include <asm/i8259.h> 47 #include <asm/proto.h> 48 #include <asm/traps.h> 49 #include <asm/apic.h> 50 #include <asm/io_apic.h> 51 #include <asm/desc.h> 52 #include <asm/hpet.h> 53 #include <asm/mtrr.h> 54 #include <asm/time.h> 55 #include <asm/smp.h> 56 #include <asm/mce.h> 57 #include <asm/tsc.h> 58 #include <asm/hypervisor.h> 59 #include <asm/cpu_device_id.h> 60 #include <asm/intel-family.h> 61 #include <asm/irq_regs.h> 62 63 unsigned int num_processors; 64 65 unsigned disabled_cpus; 66 67 /* Processor that is doing the boot up */ 68 unsigned int boot_cpu_physical_apicid __ro_after_init = -1U; 69 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); 70 71 u8 boot_cpu_apic_version __ro_after_init; 72 73 /* 74 * The highest APIC ID seen during enumeration. 75 */ 76 static unsigned int max_physical_apicid; 77 78 /* 79 * Bitmask of physically existing CPUs: 80 */ 81 physid_mask_t phys_cpu_present_map; 82 83 /* 84 * Processor to be disabled specified by kernel parameter 85 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to 86 * avoid undefined behaviour caused by sending INIT from AP to BSP. 87 */ 88 static unsigned int disabled_cpu_apicid __ro_after_init = BAD_APICID; 89 90 /* 91 * This variable controls which CPUs receive external NMIs. By default, 92 * external NMIs are delivered only to the BSP. 93 */ 94 static int apic_extnmi __ro_after_init = APIC_EXTNMI_BSP; 95 96 /* 97 * Map cpu index to physical APIC ID 98 */ 99 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); 100 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID); 101 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX); 102 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 103 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 104 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid); 105 106 #ifdef CONFIG_X86_32 107 108 /* 109 * On x86_32, the mapping between cpu and logical apicid may vary 110 * depending on apic in use. The following early percpu variable is 111 * used for the mapping. This is where the behaviors of x86_64 and 32 112 * actually diverge. Let's keep it ugly for now. 113 */ 114 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID); 115 116 /* Local APIC was disabled by the BIOS and enabled by the kernel */ 117 static int enabled_via_apicbase __ro_after_init; 118 119 /* 120 * Handle interrupt mode configuration register (IMCR). 121 * This register controls whether the interrupt signals 122 * that reach the BSP come from the master PIC or from the 123 * local APIC. Before entering Symmetric I/O Mode, either 124 * the BIOS or the operating system must switch out of 125 * PIC Mode by changing the IMCR. 126 */ 127 static inline void imcr_pic_to_apic(void) 128 { 129 /* select IMCR register */ 130 outb(0x70, 0x22); 131 /* NMI and 8259 INTR go through APIC */ 132 outb(0x01, 0x23); 133 } 134 135 static inline void imcr_apic_to_pic(void) 136 { 137 /* select IMCR register */ 138 outb(0x70, 0x22); 139 /* NMI and 8259 INTR go directly to BSP */ 140 outb(0x00, 0x23); 141 } 142 #endif 143 144 /* 145 * Knob to control our willingness to enable the local APIC. 146 * 147 * +1=force-enable 148 */ 149 static int force_enable_local_apic __initdata; 150 151 /* 152 * APIC command line parameters 153 */ 154 static int __init parse_lapic(char *arg) 155 { 156 if (IS_ENABLED(CONFIG_X86_32) && !arg) 157 force_enable_local_apic = 1; 158 else if (arg && !strncmp(arg, "notscdeadline", 13)) 159 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 160 return 0; 161 } 162 early_param("lapic", parse_lapic); 163 164 #ifdef CONFIG_X86_64 165 static int apic_calibrate_pmtmr __initdata; 166 static __init int setup_apicpmtimer(char *s) 167 { 168 apic_calibrate_pmtmr = 1; 169 notsc_setup(NULL); 170 return 0; 171 } 172 __setup("apicpmtimer", setup_apicpmtimer); 173 #endif 174 175 unsigned long mp_lapic_addr __ro_after_init; 176 int disable_apic __ro_after_init; 177 /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 178 static int disable_apic_timer __initdata; 179 /* Local APIC timer works in C2 */ 180 int local_apic_timer_c2_ok __ro_after_init; 181 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 182 183 /* 184 * Debug level, exported for io_apic.c 185 */ 186 int apic_verbosity __ro_after_init; 187 188 int pic_mode __ro_after_init; 189 190 /* Have we found an MP table */ 191 int smp_found_config __ro_after_init; 192 193 static struct resource lapic_resource = { 194 .name = "Local APIC", 195 .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 196 }; 197 198 unsigned int lapic_timer_period = 0; 199 200 static void apic_pm_activate(void); 201 202 static unsigned long apic_phys __ro_after_init; 203 204 /* 205 * Get the LAPIC version 206 */ 207 static inline int lapic_get_version(void) 208 { 209 return GET_APIC_VERSION(apic_read(APIC_LVR)); 210 } 211 212 /* 213 * Check, if the APIC is integrated or a separate chip 214 */ 215 static inline int lapic_is_integrated(void) 216 { 217 return APIC_INTEGRATED(lapic_get_version()); 218 } 219 220 /* 221 * Check, whether this is a modern or a first generation APIC 222 */ 223 static int modern_apic(void) 224 { 225 /* AMD systems use old APIC versions, so check the CPU */ 226 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 227 boot_cpu_data.x86 >= 0xf) 228 return 1; 229 230 /* Hygon systems use modern APIC */ 231 if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 232 return 1; 233 234 return lapic_get_version() >= 0x14; 235 } 236 237 /* 238 * right after this call apic become NOOP driven 239 * so apic->write/read doesn't do anything 240 */ 241 static void __init apic_disable(void) 242 { 243 pr_info("APIC: switched to apic NOOP\n"); 244 apic = &apic_noop; 245 } 246 247 void native_apic_wait_icr_idle(void) 248 { 249 while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 250 cpu_relax(); 251 } 252 253 u32 native_safe_apic_wait_icr_idle(void) 254 { 255 u32 send_status; 256 int timeout; 257 258 timeout = 0; 259 do { 260 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 261 if (!send_status) 262 break; 263 inc_irq_stat(icr_read_retry_count); 264 udelay(100); 265 } while (timeout++ < 1000); 266 267 return send_status; 268 } 269 270 void native_apic_icr_write(u32 low, u32 id) 271 { 272 unsigned long flags; 273 274 local_irq_save(flags); 275 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 276 apic_write(APIC_ICR, low); 277 local_irq_restore(flags); 278 } 279 280 u64 native_apic_icr_read(void) 281 { 282 u32 icr1, icr2; 283 284 icr2 = apic_read(APIC_ICR2); 285 icr1 = apic_read(APIC_ICR); 286 287 return icr1 | ((u64)icr2 << 32); 288 } 289 290 #ifdef CONFIG_X86_32 291 /** 292 * get_physical_broadcast - Get number of physical broadcast IDs 293 */ 294 int get_physical_broadcast(void) 295 { 296 return modern_apic() ? 0xff : 0xf; 297 } 298 #endif 299 300 /** 301 * lapic_get_maxlvt - get the maximum number of local vector table entries 302 */ 303 int lapic_get_maxlvt(void) 304 { 305 /* 306 * - we always have APIC integrated on 64bit mode 307 * - 82489DXs do not report # of LVT entries 308 */ 309 return lapic_is_integrated() ? GET_APIC_MAXLVT(apic_read(APIC_LVR)) : 2; 310 } 311 312 /* 313 * Local APIC timer 314 */ 315 316 /* Clock divisor */ 317 #define APIC_DIVISOR 16 318 #define TSC_DIVISOR 8 319 320 /* 321 * This function sets up the local APIC timer, with a timeout of 322 * 'clocks' APIC bus clock. During calibration we actually call 323 * this function twice on the boot CPU, once with a bogus timeout 324 * value, second time for real. The other (noncalibrating) CPUs 325 * call this function only once, with the real, calibrated value. 326 * 327 * We do reads before writes even if unnecessary, to get around the 328 * P5 APIC double write bug. 329 */ 330 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 331 { 332 unsigned int lvtt_value, tmp_value; 333 334 lvtt_value = LOCAL_TIMER_VECTOR; 335 if (!oneshot) 336 lvtt_value |= APIC_LVT_TIMER_PERIODIC; 337 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 338 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE; 339 340 if (!lapic_is_integrated()) 341 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 342 343 if (!irqen) 344 lvtt_value |= APIC_LVT_MASKED; 345 346 apic_write(APIC_LVTT, lvtt_value); 347 348 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { 349 /* 350 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, 351 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized. 352 * According to Intel, MFENCE can do the serialization here. 353 */ 354 asm volatile("mfence" : : : "memory"); 355 356 printk_once(KERN_DEBUG "TSC deadline timer enabled\n"); 357 return; 358 } 359 360 /* 361 * Divide PICLK by 16 362 */ 363 tmp_value = apic_read(APIC_TDCR); 364 apic_write(APIC_TDCR, 365 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 366 APIC_TDR_DIV_16); 367 368 if (!oneshot) 369 apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 370 } 371 372 /* 373 * Setup extended LVT, AMD specific 374 * 375 * Software should use the LVT offsets the BIOS provides. The offsets 376 * are determined by the subsystems using it like those for MCE 377 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts 378 * are supported. Beginning with family 10h at least 4 offsets are 379 * available. 380 * 381 * Since the offsets must be consistent for all cores, we keep track 382 * of the LVT offsets in software and reserve the offset for the same 383 * vector also to be used on other cores. An offset is freed by 384 * setting the entry to APIC_EILVT_MASKED. 385 * 386 * If the BIOS is right, there should be no conflicts. Otherwise a 387 * "[Firmware Bug]: ..." error message is generated. However, if 388 * software does not properly determines the offsets, it is not 389 * necessarily a BIOS bug. 390 */ 391 392 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; 393 394 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) 395 { 396 return (old & APIC_EILVT_MASKED) 397 || (new == APIC_EILVT_MASKED) 398 || ((new & ~APIC_EILVT_MASKED) == old); 399 } 400 401 static unsigned int reserve_eilvt_offset(int offset, unsigned int new) 402 { 403 unsigned int rsvd, vector; 404 405 if (offset >= APIC_EILVT_NR_MAX) 406 return ~0; 407 408 rsvd = atomic_read(&eilvt_offsets[offset]); 409 do { 410 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ 411 if (vector && !eilvt_entry_is_changeable(vector, new)) 412 /* may not change if vectors are different */ 413 return rsvd; 414 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); 415 } while (rsvd != new); 416 417 rsvd &= ~APIC_EILVT_MASKED; 418 if (rsvd && rsvd != vector) 419 pr_info("LVT offset %d assigned for vector 0x%02x\n", 420 offset, rsvd); 421 422 return new; 423 } 424 425 /* 426 * If mask=1, the LVT entry does not generate interrupts while mask=0 427 * enables the vector. See also the BKDGs. Must be called with 428 * preemption disabled. 429 */ 430 431 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) 432 { 433 unsigned long reg = APIC_EILVTn(offset); 434 unsigned int new, old, reserved; 435 436 new = (mask << 16) | (msg_type << 8) | vector; 437 old = apic_read(reg); 438 reserved = reserve_eilvt_offset(offset, new); 439 440 if (reserved != new) { 441 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 442 "vector 0x%x, but the register is already in use for " 443 "vector 0x%x on another cpu\n", 444 smp_processor_id(), reg, offset, new, reserved); 445 return -EINVAL; 446 } 447 448 if (!eilvt_entry_is_changeable(old, new)) { 449 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 450 "vector 0x%x, but the register is already in use for " 451 "vector 0x%x on this cpu\n", 452 smp_processor_id(), reg, offset, new, old); 453 return -EBUSY; 454 } 455 456 apic_write(reg, new); 457 458 return 0; 459 } 460 EXPORT_SYMBOL_GPL(setup_APIC_eilvt); 461 462 /* 463 * Program the next event, relative to now 464 */ 465 static int lapic_next_event(unsigned long delta, 466 struct clock_event_device *evt) 467 { 468 apic_write(APIC_TMICT, delta); 469 return 0; 470 } 471 472 static int lapic_next_deadline(unsigned long delta, 473 struct clock_event_device *evt) 474 { 475 u64 tsc; 476 477 tsc = rdtsc(); 478 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); 479 return 0; 480 } 481 482 static int lapic_timer_shutdown(struct clock_event_device *evt) 483 { 484 unsigned int v; 485 486 /* Lapic used as dummy for broadcast ? */ 487 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 488 return 0; 489 490 v = apic_read(APIC_LVTT); 491 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 492 apic_write(APIC_LVTT, v); 493 apic_write(APIC_TMICT, 0); 494 return 0; 495 } 496 497 static inline int 498 lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot) 499 { 500 /* Lapic used as dummy for broadcast ? */ 501 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 502 return 0; 503 504 __setup_APIC_LVTT(lapic_timer_period, oneshot, 1); 505 return 0; 506 } 507 508 static int lapic_timer_set_periodic(struct clock_event_device *evt) 509 { 510 return lapic_timer_set_periodic_oneshot(evt, false); 511 } 512 513 static int lapic_timer_set_oneshot(struct clock_event_device *evt) 514 { 515 return lapic_timer_set_periodic_oneshot(evt, true); 516 } 517 518 /* 519 * Local APIC timer broadcast function 520 */ 521 static void lapic_timer_broadcast(const struct cpumask *mask) 522 { 523 #ifdef CONFIG_SMP 524 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 525 #endif 526 } 527 528 529 /* 530 * The local apic timer can be used for any function which is CPU local. 531 */ 532 static struct clock_event_device lapic_clockevent = { 533 .name = "lapic", 534 .features = CLOCK_EVT_FEAT_PERIODIC | 535 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP 536 | CLOCK_EVT_FEAT_DUMMY, 537 .shift = 32, 538 .set_state_shutdown = lapic_timer_shutdown, 539 .set_state_periodic = lapic_timer_set_periodic, 540 .set_state_oneshot = lapic_timer_set_oneshot, 541 .set_state_oneshot_stopped = lapic_timer_shutdown, 542 .set_next_event = lapic_next_event, 543 .broadcast = lapic_timer_broadcast, 544 .rating = 100, 545 .irq = -1, 546 }; 547 static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 548 549 #define DEADLINE_MODEL_MATCH_FUNC(model, func) \ 550 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&func } 551 552 #define DEADLINE_MODEL_MATCH_REV(model, rev) \ 553 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)rev } 554 555 static u32 hsx_deadline_rev(void) 556 { 557 switch (boot_cpu_data.x86_stepping) { 558 case 0x02: return 0x3a; /* EP */ 559 case 0x04: return 0x0f; /* EX */ 560 } 561 562 return ~0U; 563 } 564 565 static u32 bdx_deadline_rev(void) 566 { 567 switch (boot_cpu_data.x86_stepping) { 568 case 0x02: return 0x00000011; 569 case 0x03: return 0x0700000e; 570 case 0x04: return 0x0f00000c; 571 case 0x05: return 0x0e000003; 572 } 573 574 return ~0U; 575 } 576 577 static u32 skx_deadline_rev(void) 578 { 579 switch (boot_cpu_data.x86_stepping) { 580 case 0x03: return 0x01000136; 581 case 0x04: return 0x02000014; 582 } 583 584 if (boot_cpu_data.x86_stepping > 4) 585 return 0; 586 587 return ~0U; 588 } 589 590 static const struct x86_cpu_id deadline_match[] = { 591 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_HASWELL_X, hsx_deadline_rev), 592 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_X, 0x0b000020), 593 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_BROADWELL_D, bdx_deadline_rev), 594 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_SKYLAKE_X, skx_deadline_rev), 595 596 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL, 0x22), 597 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_L, 0x20), 598 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_G, 0x17), 599 600 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL, 0x25), 601 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_G, 0x17), 602 603 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_L, 0xb2), 604 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE, 0xb2), 605 606 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_L, 0x52), 607 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE, 0x52), 608 609 {}, 610 }; 611 612 static void apic_check_deadline_errata(void) 613 { 614 const struct x86_cpu_id *m; 615 u32 rev; 616 617 if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER) || 618 boot_cpu_has(X86_FEATURE_HYPERVISOR)) 619 return; 620 621 m = x86_match_cpu(deadline_match); 622 if (!m) 623 return; 624 625 /* 626 * Function pointers will have the MSB set due to address layout, 627 * immediate revisions will not. 628 */ 629 if ((long)m->driver_data < 0) 630 rev = ((u32 (*)(void))(m->driver_data))(); 631 else 632 rev = (u32)m->driver_data; 633 634 if (boot_cpu_data.microcode >= rev) 635 return; 636 637 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 638 pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; " 639 "please update microcode to version: 0x%x (or later)\n", rev); 640 } 641 642 /* 643 * Setup the local APIC timer for this CPU. Copy the initialized values 644 * of the boot CPU and register the clock event in the framework. 645 */ 646 static void setup_APIC_timer(void) 647 { 648 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 649 650 if (this_cpu_has(X86_FEATURE_ARAT)) { 651 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 652 /* Make LAPIC timer preferrable over percpu HPET */ 653 lapic_clockevent.rating = 150; 654 } 655 656 memcpy(levt, &lapic_clockevent, sizeof(*levt)); 657 levt->cpumask = cpumask_of(smp_processor_id()); 658 659 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 660 levt->name = "lapic-deadline"; 661 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | 662 CLOCK_EVT_FEAT_DUMMY); 663 levt->set_next_event = lapic_next_deadline; 664 clockevents_config_and_register(levt, 665 tsc_khz * (1000 / TSC_DIVISOR), 666 0xF, ~0UL); 667 } else 668 clockevents_register_device(levt); 669 } 670 671 /* 672 * Install the updated TSC frequency from recalibration at the TSC 673 * deadline clockevent devices. 674 */ 675 static void __lapic_update_tsc_freq(void *info) 676 { 677 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 678 679 if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 680 return; 681 682 clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR)); 683 } 684 685 void lapic_update_tsc_freq(void) 686 { 687 /* 688 * The clockevent device's ->mult and ->shift can both be 689 * changed. In order to avoid races, schedule the frequency 690 * update code on each CPU. 691 */ 692 on_each_cpu(__lapic_update_tsc_freq, NULL, 0); 693 } 694 695 /* 696 * In this functions we calibrate APIC bus clocks to the external timer. 697 * 698 * We want to do the calibration only once since we want to have local timer 699 * irqs syncron. CPUs connected by the same APIC bus have the very same bus 700 * frequency. 701 * 702 * This was previously done by reading the PIT/HPET and waiting for a wrap 703 * around to find out, that a tick has elapsed. I have a box, where the PIT 704 * readout is broken, so it never gets out of the wait loop again. This was 705 * also reported by others. 706 * 707 * Monitoring the jiffies value is inaccurate and the clockevents 708 * infrastructure allows us to do a simple substitution of the interrupt 709 * handler. 710 * 711 * The calibration routine also uses the pm_timer when possible, as the PIT 712 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 713 * back to normal later in the boot process). 714 */ 715 716 #define LAPIC_CAL_LOOPS (HZ/10) 717 718 static __initdata int lapic_cal_loops = -1; 719 static __initdata long lapic_cal_t1, lapic_cal_t2; 720 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 721 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 722 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 723 724 /* 725 * Temporary interrupt handler and polled calibration function. 726 */ 727 static void __init lapic_cal_handler(struct clock_event_device *dev) 728 { 729 unsigned long long tsc = 0; 730 long tapic = apic_read(APIC_TMCCT); 731 unsigned long pm = acpi_pm_read_early(); 732 733 if (boot_cpu_has(X86_FEATURE_TSC)) 734 tsc = rdtsc(); 735 736 switch (lapic_cal_loops++) { 737 case 0: 738 lapic_cal_t1 = tapic; 739 lapic_cal_tsc1 = tsc; 740 lapic_cal_pm1 = pm; 741 lapic_cal_j1 = jiffies; 742 break; 743 744 case LAPIC_CAL_LOOPS: 745 lapic_cal_t2 = tapic; 746 lapic_cal_tsc2 = tsc; 747 if (pm < lapic_cal_pm1) 748 pm += ACPI_PM_OVRRUN; 749 lapic_cal_pm2 = pm; 750 lapic_cal_j2 = jiffies; 751 break; 752 } 753 } 754 755 static int __init 756 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 757 { 758 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 759 const long pm_thresh = pm_100ms / 100; 760 unsigned long mult; 761 u64 res; 762 763 #ifndef CONFIG_X86_PM_TIMER 764 return -1; 765 #endif 766 767 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 768 769 /* Check, if the PM timer is available */ 770 if (!deltapm) 771 return -1; 772 773 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 774 775 if (deltapm > (pm_100ms - pm_thresh) && 776 deltapm < (pm_100ms + pm_thresh)) { 777 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 778 return 0; 779 } 780 781 res = (((u64)deltapm) * mult) >> 22; 782 do_div(res, 1000000); 783 pr_warn("APIC calibration not consistent " 784 "with PM-Timer: %ldms instead of 100ms\n", (long)res); 785 786 /* Correct the lapic counter value */ 787 res = (((u64)(*delta)) * pm_100ms); 788 do_div(res, deltapm); 789 pr_info("APIC delta adjusted to PM-Timer: " 790 "%lu (%ld)\n", (unsigned long)res, *delta); 791 *delta = (long)res; 792 793 /* Correct the tsc counter value */ 794 if (boot_cpu_has(X86_FEATURE_TSC)) { 795 res = (((u64)(*deltatsc)) * pm_100ms); 796 do_div(res, deltapm); 797 apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 798 "PM-Timer: %lu (%ld)\n", 799 (unsigned long)res, *deltatsc); 800 *deltatsc = (long)res; 801 } 802 803 return 0; 804 } 805 806 static int __init lapic_init_clockevent(void) 807 { 808 if (!lapic_timer_period) 809 return -1; 810 811 /* Calculate the scaled math multiplication factor */ 812 lapic_clockevent.mult = div_sc(lapic_timer_period/APIC_DIVISOR, 813 TICK_NSEC, lapic_clockevent.shift); 814 lapic_clockevent.max_delta_ns = 815 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); 816 lapic_clockevent.max_delta_ticks = 0x7FFFFFFF; 817 lapic_clockevent.min_delta_ns = 818 clockevent_delta2ns(0xF, &lapic_clockevent); 819 lapic_clockevent.min_delta_ticks = 0xF; 820 821 return 0; 822 } 823 824 bool __init apic_needs_pit(void) 825 { 826 /* 827 * If the frequencies are not known, PIT is required for both TSC 828 * and apic timer calibration. 829 */ 830 if (!tsc_khz || !cpu_khz) 831 return true; 832 833 /* Is there an APIC at all or is it disabled? */ 834 if (!boot_cpu_has(X86_FEATURE_APIC) || disable_apic) 835 return true; 836 837 /* 838 * If interrupt delivery mode is legacy PIC or virtual wire without 839 * configuration, the local APIC timer wont be set up. Make sure 840 * that the PIT is initialized. 841 */ 842 if (apic_intr_mode == APIC_PIC || 843 apic_intr_mode == APIC_VIRTUAL_WIRE_NO_CONFIG) 844 return true; 845 846 /* Virt guests may lack ARAT, but still have DEADLINE */ 847 if (!boot_cpu_has(X86_FEATURE_ARAT)) 848 return true; 849 850 /* Deadline timer is based on TSC so no further PIT action required */ 851 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 852 return false; 853 854 /* APIC timer disabled? */ 855 if (disable_apic_timer) 856 return true; 857 /* 858 * The APIC timer frequency is known already, no PIT calibration 859 * required. If unknown, let the PIT be initialized. 860 */ 861 return lapic_timer_period == 0; 862 } 863 864 static int __init calibrate_APIC_clock(void) 865 { 866 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 867 u64 tsc_perj = 0, tsc_start = 0; 868 unsigned long jif_start; 869 unsigned long deltaj; 870 long delta, deltatsc; 871 int pm_referenced = 0; 872 873 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 874 return 0; 875 876 /* 877 * Check if lapic timer has already been calibrated by platform 878 * specific routine, such as tsc calibration code. If so just fill 879 * in the clockevent structure and return. 880 */ 881 if (!lapic_init_clockevent()) { 882 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", 883 lapic_timer_period); 884 /* 885 * Direct calibration methods must have an always running 886 * local APIC timer, no need for broadcast timer. 887 */ 888 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 889 return 0; 890 } 891 892 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 893 "calibrating APIC timer ...\n"); 894 895 /* 896 * There are platforms w/o global clockevent devices. Instead of 897 * making the calibration conditional on that, use a polling based 898 * approach everywhere. 899 */ 900 local_irq_disable(); 901 902 /* 903 * Setup the APIC counter to maximum. There is no way the lapic 904 * can underflow in the 100ms detection time frame 905 */ 906 __setup_APIC_LVTT(0xffffffff, 0, 0); 907 908 /* 909 * Methods to terminate the calibration loop: 910 * 1) Global clockevent if available (jiffies) 911 * 2) TSC if available and frequency is known 912 */ 913 jif_start = READ_ONCE(jiffies); 914 915 if (tsc_khz) { 916 tsc_start = rdtsc(); 917 tsc_perj = div_u64((u64)tsc_khz * 1000, HZ); 918 } 919 920 /* 921 * Enable interrupts so the tick can fire, if a global 922 * clockevent device is available 923 */ 924 local_irq_enable(); 925 926 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) { 927 /* Wait for a tick to elapse */ 928 while (1) { 929 if (tsc_khz) { 930 u64 tsc_now = rdtsc(); 931 if ((tsc_now - tsc_start) >= tsc_perj) { 932 tsc_start += tsc_perj; 933 break; 934 } 935 } else { 936 unsigned long jif_now = READ_ONCE(jiffies); 937 938 if (time_after(jif_now, jif_start)) { 939 jif_start = jif_now; 940 break; 941 } 942 } 943 cpu_relax(); 944 } 945 946 /* Invoke the calibration routine */ 947 local_irq_disable(); 948 lapic_cal_handler(NULL); 949 local_irq_enable(); 950 } 951 952 local_irq_disable(); 953 954 /* Build delta t1-t2 as apic timer counts down */ 955 delta = lapic_cal_t1 - lapic_cal_t2; 956 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 957 958 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 959 960 /* we trust the PM based calibration if possible */ 961 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 962 &delta, &deltatsc); 963 964 lapic_timer_period = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 965 lapic_init_clockevent(); 966 967 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 968 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); 969 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 970 lapic_timer_period); 971 972 if (boot_cpu_has(X86_FEATURE_TSC)) { 973 apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 974 "%ld.%04ld MHz.\n", 975 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 976 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 977 } 978 979 apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 980 "%u.%04u MHz.\n", 981 lapic_timer_period / (1000000 / HZ), 982 lapic_timer_period % (1000000 / HZ)); 983 984 /* 985 * Do a sanity check on the APIC calibration result 986 */ 987 if (lapic_timer_period < (1000000 / HZ)) { 988 local_irq_enable(); 989 pr_warn("APIC frequency too slow, disabling apic timer\n"); 990 return -1; 991 } 992 993 levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 994 995 /* 996 * PM timer calibration failed or not turned on so lets try APIC 997 * timer based calibration, if a global clockevent device is 998 * available. 999 */ 1000 if (!pm_referenced && global_clock_event) { 1001 apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 1002 1003 /* 1004 * Setup the apic timer manually 1005 */ 1006 levt->event_handler = lapic_cal_handler; 1007 lapic_timer_set_periodic(levt); 1008 lapic_cal_loops = -1; 1009 1010 /* Let the interrupts run */ 1011 local_irq_enable(); 1012 1013 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 1014 cpu_relax(); 1015 1016 /* Stop the lapic timer */ 1017 local_irq_disable(); 1018 lapic_timer_shutdown(levt); 1019 1020 /* Jiffies delta */ 1021 deltaj = lapic_cal_j2 - lapic_cal_j1; 1022 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 1023 1024 /* Check, if the jiffies result is consistent */ 1025 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 1026 apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 1027 else 1028 levt->features |= CLOCK_EVT_FEAT_DUMMY; 1029 } 1030 local_irq_enable(); 1031 1032 if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 1033 pr_warn("APIC timer disabled due to verification failure\n"); 1034 return -1; 1035 } 1036 1037 return 0; 1038 } 1039 1040 /* 1041 * Setup the boot APIC 1042 * 1043 * Calibrate and verify the result. 1044 */ 1045 void __init setup_boot_APIC_clock(void) 1046 { 1047 /* 1048 * The local apic timer can be disabled via the kernel 1049 * commandline or from the CPU detection code. Register the lapic 1050 * timer as a dummy clock event source on SMP systems, so the 1051 * broadcast mechanism is used. On UP systems simply ignore it. 1052 */ 1053 if (disable_apic_timer) { 1054 pr_info("Disabling APIC timer\n"); 1055 /* No broadcast on UP ! */ 1056 if (num_possible_cpus() > 1) { 1057 lapic_clockevent.mult = 1; 1058 setup_APIC_timer(); 1059 } 1060 return; 1061 } 1062 1063 if (calibrate_APIC_clock()) { 1064 /* No broadcast on UP ! */ 1065 if (num_possible_cpus() > 1) 1066 setup_APIC_timer(); 1067 return; 1068 } 1069 1070 /* 1071 * If nmi_watchdog is set to IO_APIC, we need the 1072 * PIT/HPET going. Otherwise register lapic as a dummy 1073 * device. 1074 */ 1075 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 1076 1077 /* Setup the lapic or request the broadcast */ 1078 setup_APIC_timer(); 1079 amd_e400_c1e_apic_setup(); 1080 } 1081 1082 void setup_secondary_APIC_clock(void) 1083 { 1084 setup_APIC_timer(); 1085 amd_e400_c1e_apic_setup(); 1086 } 1087 1088 /* 1089 * The guts of the apic timer interrupt 1090 */ 1091 static void local_apic_timer_interrupt(void) 1092 { 1093 struct clock_event_device *evt = this_cpu_ptr(&lapic_events); 1094 1095 /* 1096 * Normally we should not be here till LAPIC has been initialized but 1097 * in some cases like kdump, its possible that there is a pending LAPIC 1098 * timer interrupt from previous kernel's context and is delivered in 1099 * new kernel the moment interrupts are enabled. 1100 * 1101 * Interrupts are enabled early and LAPIC is setup much later, hence 1102 * its possible that when we get here evt->event_handler is NULL. 1103 * Check for event_handler being NULL and discard the interrupt as 1104 * spurious. 1105 */ 1106 if (!evt->event_handler) { 1107 pr_warn("Spurious LAPIC timer interrupt on cpu %d\n", 1108 smp_processor_id()); 1109 /* Switch it off */ 1110 lapic_timer_shutdown(evt); 1111 return; 1112 } 1113 1114 /* 1115 * the NMI deadlock-detector uses this. 1116 */ 1117 inc_irq_stat(apic_timer_irqs); 1118 1119 evt->event_handler(evt); 1120 } 1121 1122 /* 1123 * Local APIC timer interrupt. This is the most natural way for doing 1124 * local interrupts, but local timer interrupts can be emulated by 1125 * broadcast interrupts too. [in case the hw doesn't support APIC timers] 1126 * 1127 * [ if a single-CPU system runs an SMP kernel then we call the local 1128 * interrupt as well. Thus we cannot inline the local irq ... ] 1129 */ 1130 __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) 1131 { 1132 struct pt_regs *old_regs = set_irq_regs(regs); 1133 1134 /* 1135 * NOTE! We'd better ACK the irq immediately, 1136 * because timer handling can be slow. 1137 * 1138 * update_process_times() expects us to have done irq_enter(). 1139 * Besides, if we don't timer interrupts ignore the global 1140 * interrupt lock, which is the WrongThing (tm) to do. 1141 */ 1142 entering_ack_irq(); 1143 trace_local_timer_entry(LOCAL_TIMER_VECTOR); 1144 local_apic_timer_interrupt(); 1145 trace_local_timer_exit(LOCAL_TIMER_VECTOR); 1146 exiting_irq(); 1147 1148 set_irq_regs(old_regs); 1149 } 1150 1151 int setup_profiling_timer(unsigned int multiplier) 1152 { 1153 return -EINVAL; 1154 } 1155 1156 /* 1157 * Local APIC start and shutdown 1158 */ 1159 1160 /** 1161 * clear_local_APIC - shutdown the local APIC 1162 * 1163 * This is called, when a CPU is disabled and before rebooting, so the state of 1164 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 1165 * leftovers during boot. 1166 */ 1167 void clear_local_APIC(void) 1168 { 1169 int maxlvt; 1170 u32 v; 1171 1172 /* APIC hasn't been mapped yet */ 1173 if (!x2apic_mode && !apic_phys) 1174 return; 1175 1176 maxlvt = lapic_get_maxlvt(); 1177 /* 1178 * Masking an LVT entry can trigger a local APIC error 1179 * if the vector is zero. Mask LVTERR first to prevent this. 1180 */ 1181 if (maxlvt >= 3) { 1182 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 1183 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 1184 } 1185 /* 1186 * Careful: we have to set masks only first to deassert 1187 * any level-triggered sources. 1188 */ 1189 v = apic_read(APIC_LVTT); 1190 apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 1191 v = apic_read(APIC_LVT0); 1192 apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 1193 v = apic_read(APIC_LVT1); 1194 apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 1195 if (maxlvt >= 4) { 1196 v = apic_read(APIC_LVTPC); 1197 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 1198 } 1199 1200 /* lets not touch this if we didn't frob it */ 1201 #ifdef CONFIG_X86_THERMAL_VECTOR 1202 if (maxlvt >= 5) { 1203 v = apic_read(APIC_LVTTHMR); 1204 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 1205 } 1206 #endif 1207 #ifdef CONFIG_X86_MCE_INTEL 1208 if (maxlvt >= 6) { 1209 v = apic_read(APIC_LVTCMCI); 1210 if (!(v & APIC_LVT_MASKED)) 1211 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 1212 } 1213 #endif 1214 1215 /* 1216 * Clean APIC state for other OSs: 1217 */ 1218 apic_write(APIC_LVTT, APIC_LVT_MASKED); 1219 apic_write(APIC_LVT0, APIC_LVT_MASKED); 1220 apic_write(APIC_LVT1, APIC_LVT_MASKED); 1221 if (maxlvt >= 3) 1222 apic_write(APIC_LVTERR, APIC_LVT_MASKED); 1223 if (maxlvt >= 4) 1224 apic_write(APIC_LVTPC, APIC_LVT_MASKED); 1225 1226 /* Integrated APIC (!82489DX) ? */ 1227 if (lapic_is_integrated()) { 1228 if (maxlvt > 3) 1229 /* Clear ESR due to Pentium errata 3AP and 11AP */ 1230 apic_write(APIC_ESR, 0); 1231 apic_read(APIC_ESR); 1232 } 1233 } 1234 1235 /** 1236 * apic_soft_disable - Clears and software disables the local APIC on hotplug 1237 * 1238 * Contrary to disable_local_APIC() this does not touch the enable bit in 1239 * MSR_IA32_APICBASE. Clearing that bit on systems based on the 3 wire APIC 1240 * bus would require a hardware reset as the APIC would lose track of bus 1241 * arbitration. On systems with FSB delivery APICBASE could be disabled, 1242 * but it has to be guaranteed that no interrupt is sent to the APIC while 1243 * in that state and it's not clear from the SDM whether it still responds 1244 * to INIT/SIPI messages. Stay on the safe side and use software disable. 1245 */ 1246 void apic_soft_disable(void) 1247 { 1248 u32 value; 1249 1250 clear_local_APIC(); 1251 1252 /* Soft disable APIC (implies clearing of registers for 82489DX!). */ 1253 value = apic_read(APIC_SPIV); 1254 value &= ~APIC_SPIV_APIC_ENABLED; 1255 apic_write(APIC_SPIV, value); 1256 } 1257 1258 /** 1259 * disable_local_APIC - clear and disable the local APIC 1260 */ 1261 void disable_local_APIC(void) 1262 { 1263 /* APIC hasn't been mapped yet */ 1264 if (!x2apic_mode && !apic_phys) 1265 return; 1266 1267 apic_soft_disable(); 1268 1269 #ifdef CONFIG_X86_32 1270 /* 1271 * When LAPIC was disabled by the BIOS and enabled by the kernel, 1272 * restore the disabled state. 1273 */ 1274 if (enabled_via_apicbase) { 1275 unsigned int l, h; 1276 1277 rdmsr(MSR_IA32_APICBASE, l, h); 1278 l &= ~MSR_IA32_APICBASE_ENABLE; 1279 wrmsr(MSR_IA32_APICBASE, l, h); 1280 } 1281 #endif 1282 } 1283 1284 /* 1285 * If Linux enabled the LAPIC against the BIOS default disable it down before 1286 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 1287 * not power-off. Additionally clear all LVT entries before disable_local_APIC 1288 * for the case where Linux didn't enable the LAPIC. 1289 */ 1290 void lapic_shutdown(void) 1291 { 1292 unsigned long flags; 1293 1294 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) 1295 return; 1296 1297 local_irq_save(flags); 1298 1299 #ifdef CONFIG_X86_32 1300 if (!enabled_via_apicbase) 1301 clear_local_APIC(); 1302 else 1303 #endif 1304 disable_local_APIC(); 1305 1306 1307 local_irq_restore(flags); 1308 } 1309 1310 /** 1311 * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1312 */ 1313 void __init sync_Arb_IDs(void) 1314 { 1315 /* 1316 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1317 * needed on AMD. 1318 */ 1319 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1320 return; 1321 1322 /* 1323 * Wait for idle. 1324 */ 1325 apic_wait_icr_idle(); 1326 1327 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1328 apic_write(APIC_ICR, APIC_DEST_ALLINC | 1329 APIC_INT_LEVELTRIG | APIC_DM_INIT); 1330 } 1331 1332 enum apic_intr_mode_id apic_intr_mode __ro_after_init; 1333 1334 static int __init __apic_intr_mode_select(void) 1335 { 1336 /* Check kernel option */ 1337 if (disable_apic) { 1338 pr_info("APIC disabled via kernel command line\n"); 1339 return APIC_PIC; 1340 } 1341 1342 /* Check BIOS */ 1343 #ifdef CONFIG_X86_64 1344 /* On 64-bit, the APIC must be integrated, Check local APIC only */ 1345 if (!boot_cpu_has(X86_FEATURE_APIC)) { 1346 disable_apic = 1; 1347 pr_info("APIC disabled by BIOS\n"); 1348 return APIC_PIC; 1349 } 1350 #else 1351 /* On 32-bit, the APIC may be integrated APIC or 82489DX */ 1352 1353 /* Neither 82489DX nor integrated APIC ? */ 1354 if (!boot_cpu_has(X86_FEATURE_APIC) && !smp_found_config) { 1355 disable_apic = 1; 1356 return APIC_PIC; 1357 } 1358 1359 /* If the BIOS pretends there is an integrated APIC ? */ 1360 if (!boot_cpu_has(X86_FEATURE_APIC) && 1361 APIC_INTEGRATED(boot_cpu_apic_version)) { 1362 disable_apic = 1; 1363 pr_err(FW_BUG "Local APIC %d not detected, force emulation\n", 1364 boot_cpu_physical_apicid); 1365 return APIC_PIC; 1366 } 1367 #endif 1368 1369 /* Check MP table or ACPI MADT configuration */ 1370 if (!smp_found_config) { 1371 disable_ioapic_support(); 1372 if (!acpi_lapic) { 1373 pr_info("APIC: ACPI MADT or MP tables are not detected\n"); 1374 return APIC_VIRTUAL_WIRE_NO_CONFIG; 1375 } 1376 return APIC_VIRTUAL_WIRE; 1377 } 1378 1379 #ifdef CONFIG_SMP 1380 /* If SMP should be disabled, then really disable it! */ 1381 if (!setup_max_cpus) { 1382 pr_info("APIC: SMP mode deactivated\n"); 1383 return APIC_SYMMETRIC_IO_NO_ROUTING; 1384 } 1385 1386 if (read_apic_id() != boot_cpu_physical_apicid) { 1387 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1388 read_apic_id(), boot_cpu_physical_apicid); 1389 /* Or can we switch back to PIC here? */ 1390 } 1391 #endif 1392 1393 return APIC_SYMMETRIC_IO; 1394 } 1395 1396 /* Select the interrupt delivery mode for the BSP */ 1397 void __init apic_intr_mode_select(void) 1398 { 1399 apic_intr_mode = __apic_intr_mode_select(); 1400 } 1401 1402 /* 1403 * An initial setup of the virtual wire mode. 1404 */ 1405 void __init init_bsp_APIC(void) 1406 { 1407 unsigned int value; 1408 1409 /* 1410 * Don't do the setup now if we have a SMP BIOS as the 1411 * through-I/O-APIC virtual wire mode might be active. 1412 */ 1413 if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC)) 1414 return; 1415 1416 /* 1417 * Do not trust the local APIC being empty at bootup. 1418 */ 1419 clear_local_APIC(); 1420 1421 /* 1422 * Enable APIC. 1423 */ 1424 value = apic_read(APIC_SPIV); 1425 value &= ~APIC_VECTOR_MASK; 1426 value |= APIC_SPIV_APIC_ENABLED; 1427 1428 #ifdef CONFIG_X86_32 1429 /* This bit is reserved on P4/Xeon and should be cleared */ 1430 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1431 (boot_cpu_data.x86 == 15)) 1432 value &= ~APIC_SPIV_FOCUS_DISABLED; 1433 else 1434 #endif 1435 value |= APIC_SPIV_FOCUS_DISABLED; 1436 value |= SPURIOUS_APIC_VECTOR; 1437 apic_write(APIC_SPIV, value); 1438 1439 /* 1440 * Set up the virtual wire mode. 1441 */ 1442 apic_write(APIC_LVT0, APIC_DM_EXTINT); 1443 value = APIC_DM_NMI; 1444 if (!lapic_is_integrated()) /* 82489DX */ 1445 value |= APIC_LVT_LEVEL_TRIGGER; 1446 if (apic_extnmi == APIC_EXTNMI_NONE) 1447 value |= APIC_LVT_MASKED; 1448 apic_write(APIC_LVT1, value); 1449 } 1450 1451 static void __init apic_bsp_setup(bool upmode); 1452 1453 /* Init the interrupt delivery mode for the BSP */ 1454 void __init apic_intr_mode_init(void) 1455 { 1456 bool upmode = IS_ENABLED(CONFIG_UP_LATE_INIT); 1457 1458 switch (apic_intr_mode) { 1459 case APIC_PIC: 1460 pr_info("APIC: Keep in PIC mode(8259)\n"); 1461 return; 1462 case APIC_VIRTUAL_WIRE: 1463 pr_info("APIC: Switch to virtual wire mode setup\n"); 1464 default_setup_apic_routing(); 1465 break; 1466 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1467 pr_info("APIC: Switch to virtual wire mode setup with no configuration\n"); 1468 upmode = true; 1469 default_setup_apic_routing(); 1470 break; 1471 case APIC_SYMMETRIC_IO: 1472 pr_info("APIC: Switch to symmetric I/O mode setup\n"); 1473 default_setup_apic_routing(); 1474 break; 1475 case APIC_SYMMETRIC_IO_NO_ROUTING: 1476 pr_info("APIC: Switch to symmetric I/O mode setup in no SMP routine\n"); 1477 break; 1478 } 1479 1480 apic_bsp_setup(upmode); 1481 } 1482 1483 static void lapic_setup_esr(void) 1484 { 1485 unsigned int oldvalue, value, maxlvt; 1486 1487 if (!lapic_is_integrated()) { 1488 pr_info("No ESR for 82489DX.\n"); 1489 return; 1490 } 1491 1492 if (apic->disable_esr) { 1493 /* 1494 * Something untraceable is creating bad interrupts on 1495 * secondary quads ... for the moment, just leave the 1496 * ESR disabled - we can't do anything useful with the 1497 * errors anyway - mbligh 1498 */ 1499 pr_info("Leaving ESR disabled.\n"); 1500 return; 1501 } 1502 1503 maxlvt = lapic_get_maxlvt(); 1504 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1505 apic_write(APIC_ESR, 0); 1506 oldvalue = apic_read(APIC_ESR); 1507 1508 /* enables sending errors */ 1509 value = ERROR_APIC_VECTOR; 1510 apic_write(APIC_LVTERR, value); 1511 1512 /* 1513 * spec says clear errors after enabling vector. 1514 */ 1515 if (maxlvt > 3) 1516 apic_write(APIC_ESR, 0); 1517 value = apic_read(APIC_ESR); 1518 if (value != oldvalue) 1519 apic_printk(APIC_VERBOSE, "ESR value before enabling " 1520 "vector: 0x%08x after: 0x%08x\n", 1521 oldvalue, value); 1522 } 1523 1524 #define APIC_IR_REGS APIC_ISR_NR 1525 #define APIC_IR_BITS (APIC_IR_REGS * 32) 1526 #define APIC_IR_MAPSIZE (APIC_IR_BITS / BITS_PER_LONG) 1527 1528 union apic_ir { 1529 unsigned long map[APIC_IR_MAPSIZE]; 1530 u32 regs[APIC_IR_REGS]; 1531 }; 1532 1533 static bool apic_check_and_ack(union apic_ir *irr, union apic_ir *isr) 1534 { 1535 int i, bit; 1536 1537 /* Read the IRRs */ 1538 for (i = 0; i < APIC_IR_REGS; i++) 1539 irr->regs[i] = apic_read(APIC_IRR + i * 0x10); 1540 1541 /* Read the ISRs */ 1542 for (i = 0; i < APIC_IR_REGS; i++) 1543 isr->regs[i] = apic_read(APIC_ISR + i * 0x10); 1544 1545 /* 1546 * If the ISR map is not empty. ACK the APIC and run another round 1547 * to verify whether a pending IRR has been unblocked and turned 1548 * into a ISR. 1549 */ 1550 if (!bitmap_empty(isr->map, APIC_IR_BITS)) { 1551 /* 1552 * There can be multiple ISR bits set when a high priority 1553 * interrupt preempted a lower priority one. Issue an ACK 1554 * per set bit. 1555 */ 1556 for_each_set_bit(bit, isr->map, APIC_IR_BITS) 1557 ack_APIC_irq(); 1558 return true; 1559 } 1560 1561 return !bitmap_empty(irr->map, APIC_IR_BITS); 1562 } 1563 1564 /* 1565 * After a crash, we no longer service the interrupts and a pending 1566 * interrupt from previous kernel might still have ISR bit set. 1567 * 1568 * Most probably by now the CPU has serviced that pending interrupt and it 1569 * might not have done the ack_APIC_irq() because it thought, interrupt 1570 * came from i8259 as ExtInt. LAPIC did not get EOI so it does not clear 1571 * the ISR bit and cpu thinks it has already serivced the interrupt. Hence 1572 * a vector might get locked. It was noticed for timer irq (vector 1573 * 0x31). Issue an extra EOI to clear ISR. 1574 * 1575 * If there are pending IRR bits they turn into ISR bits after a higher 1576 * priority ISR bit has been acked. 1577 */ 1578 static void apic_pending_intr_clear(void) 1579 { 1580 union apic_ir irr, isr; 1581 unsigned int i; 1582 1583 /* 512 loops are way oversized and give the APIC a chance to obey. */ 1584 for (i = 0; i < 512; i++) { 1585 if (!apic_check_and_ack(&irr, &isr)) 1586 return; 1587 } 1588 /* Dump the IRR/ISR content if that failed */ 1589 pr_warn("APIC: Stale IRR: %256pb ISR: %256pb\n", irr.map, isr.map); 1590 } 1591 1592 /** 1593 * setup_local_APIC - setup the local APIC 1594 * 1595 * Used to setup local APIC while initializing BSP or bringing up APs. 1596 * Always called with preemption disabled. 1597 */ 1598 static void setup_local_APIC(void) 1599 { 1600 int cpu = smp_processor_id(); 1601 unsigned int value; 1602 1603 if (disable_apic) { 1604 disable_ioapic_support(); 1605 return; 1606 } 1607 1608 /* 1609 * If this comes from kexec/kcrash the APIC might be enabled in 1610 * SPIV. Soft disable it before doing further initialization. 1611 */ 1612 value = apic_read(APIC_SPIV); 1613 value &= ~APIC_SPIV_APIC_ENABLED; 1614 apic_write(APIC_SPIV, value); 1615 1616 #ifdef CONFIG_X86_32 1617 /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1618 if (lapic_is_integrated() && apic->disable_esr) { 1619 apic_write(APIC_ESR, 0); 1620 apic_write(APIC_ESR, 0); 1621 apic_write(APIC_ESR, 0); 1622 apic_write(APIC_ESR, 0); 1623 } 1624 #endif 1625 /* 1626 * Double-check whether this APIC is really registered. 1627 * This is meaningless in clustered apic mode, so we skip it. 1628 */ 1629 BUG_ON(!apic->apic_id_registered()); 1630 1631 /* 1632 * Intel recommends to set DFR, LDR and TPR before enabling 1633 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1634 * document number 292116). So here it goes... 1635 */ 1636 apic->init_apic_ldr(); 1637 1638 #ifdef CONFIG_X86_32 1639 if (apic->dest_logical) { 1640 int logical_apicid, ldr_apicid; 1641 1642 /* 1643 * APIC LDR is initialized. If logical_apicid mapping was 1644 * initialized during get_smp_config(), make sure it matches 1645 * the actual value. 1646 */ 1647 logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu); 1648 ldr_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 1649 if (logical_apicid != BAD_APICID) 1650 WARN_ON(logical_apicid != ldr_apicid); 1651 /* Always use the value from LDR. */ 1652 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = ldr_apicid; 1653 } 1654 #endif 1655 1656 /* 1657 * Set Task Priority to 'accept all except vectors 0-31'. An APIC 1658 * vector in the 16-31 range could be delivered if TPR == 0, but we 1659 * would think it's an exception and terrible things will happen. We 1660 * never change this later on. 1661 */ 1662 value = apic_read(APIC_TASKPRI); 1663 value &= ~APIC_TPRI_MASK; 1664 value |= 0x10; 1665 apic_write(APIC_TASKPRI, value); 1666 1667 /* Clear eventually stale ISR/IRR bits */ 1668 apic_pending_intr_clear(); 1669 1670 /* 1671 * Now that we are all set up, enable the APIC 1672 */ 1673 value = apic_read(APIC_SPIV); 1674 value &= ~APIC_VECTOR_MASK; 1675 /* 1676 * Enable APIC 1677 */ 1678 value |= APIC_SPIV_APIC_ENABLED; 1679 1680 #ifdef CONFIG_X86_32 1681 /* 1682 * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1683 * certain networking cards. If high frequency interrupts are 1684 * happening on a particular IOAPIC pin, plus the IOAPIC routing 1685 * entry is masked/unmasked at a high rate as well then sooner or 1686 * later IOAPIC line gets 'stuck', no more interrupts are received 1687 * from the device. If focus CPU is disabled then the hang goes 1688 * away, oh well :-( 1689 * 1690 * [ This bug can be reproduced easily with a level-triggered 1691 * PCI Ne2000 networking cards and PII/PIII processors, dual 1692 * BX chipset. ] 1693 */ 1694 /* 1695 * Actually disabling the focus CPU check just makes the hang less 1696 * frequent as it makes the interrupt distributon model be more 1697 * like LRU than MRU (the short-term load is more even across CPUs). 1698 */ 1699 1700 /* 1701 * - enable focus processor (bit==0) 1702 * - 64bit mode always use processor focus 1703 * so no need to set it 1704 */ 1705 value &= ~APIC_SPIV_FOCUS_DISABLED; 1706 #endif 1707 1708 /* 1709 * Set spurious IRQ vector 1710 */ 1711 value |= SPURIOUS_APIC_VECTOR; 1712 apic_write(APIC_SPIV, value); 1713 1714 perf_events_lapic_init(); 1715 1716 /* 1717 * Set up LVT0, LVT1: 1718 * 1719 * set up through-local-APIC on the boot CPU's LINT0. This is not 1720 * strictly necessary in pure symmetric-IO mode, but sometimes 1721 * we delegate interrupts to the 8259A. 1722 */ 1723 /* 1724 * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1725 */ 1726 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 1727 if (!cpu && (pic_mode || !value || skip_ioapic_setup)) { 1728 value = APIC_DM_EXTINT; 1729 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); 1730 } else { 1731 value = APIC_DM_EXTINT | APIC_LVT_MASKED; 1732 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); 1733 } 1734 apic_write(APIC_LVT0, value); 1735 1736 /* 1737 * Only the BSP sees the LINT1 NMI signal by default. This can be 1738 * modified by apic_extnmi= boot option. 1739 */ 1740 if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) || 1741 apic_extnmi == APIC_EXTNMI_ALL) 1742 value = APIC_DM_NMI; 1743 else 1744 value = APIC_DM_NMI | APIC_LVT_MASKED; 1745 1746 /* Is 82489DX ? */ 1747 if (!lapic_is_integrated()) 1748 value |= APIC_LVT_LEVEL_TRIGGER; 1749 apic_write(APIC_LVT1, value); 1750 1751 #ifdef CONFIG_X86_MCE_INTEL 1752 /* Recheck CMCI information after local APIC is up on CPU #0 */ 1753 if (!cpu) 1754 cmci_recheck(); 1755 #endif 1756 } 1757 1758 static void end_local_APIC_setup(void) 1759 { 1760 lapic_setup_esr(); 1761 1762 #ifdef CONFIG_X86_32 1763 { 1764 unsigned int value; 1765 /* Disable the local apic timer */ 1766 value = apic_read(APIC_LVTT); 1767 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1768 apic_write(APIC_LVTT, value); 1769 } 1770 #endif 1771 1772 apic_pm_activate(); 1773 } 1774 1775 /* 1776 * APIC setup function for application processors. Called from smpboot.c 1777 */ 1778 void apic_ap_setup(void) 1779 { 1780 setup_local_APIC(); 1781 end_local_APIC_setup(); 1782 } 1783 1784 #ifdef CONFIG_X86_X2APIC 1785 int x2apic_mode; 1786 1787 enum { 1788 X2APIC_OFF, 1789 X2APIC_ON, 1790 X2APIC_DISABLED, 1791 }; 1792 static int x2apic_state; 1793 1794 static void __x2apic_disable(void) 1795 { 1796 u64 msr; 1797 1798 if (!boot_cpu_has(X86_FEATURE_APIC)) 1799 return; 1800 1801 rdmsrl(MSR_IA32_APICBASE, msr); 1802 if (!(msr & X2APIC_ENABLE)) 1803 return; 1804 /* Disable xapic and x2apic first and then reenable xapic mode */ 1805 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); 1806 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); 1807 printk_once(KERN_INFO "x2apic disabled\n"); 1808 } 1809 1810 static void __x2apic_enable(void) 1811 { 1812 u64 msr; 1813 1814 rdmsrl(MSR_IA32_APICBASE, msr); 1815 if (msr & X2APIC_ENABLE) 1816 return; 1817 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); 1818 printk_once(KERN_INFO "x2apic enabled\n"); 1819 } 1820 1821 static int __init setup_nox2apic(char *str) 1822 { 1823 if (x2apic_enabled()) { 1824 int apicid = native_apic_msr_read(APIC_ID); 1825 1826 if (apicid >= 255) { 1827 pr_warn("Apicid: %08x, cannot enforce nox2apic\n", 1828 apicid); 1829 return 0; 1830 } 1831 pr_warn("x2apic already enabled.\n"); 1832 __x2apic_disable(); 1833 } 1834 setup_clear_cpu_cap(X86_FEATURE_X2APIC); 1835 x2apic_state = X2APIC_DISABLED; 1836 x2apic_mode = 0; 1837 return 0; 1838 } 1839 early_param("nox2apic", setup_nox2apic); 1840 1841 /* Called from cpu_init() to enable x2apic on (secondary) cpus */ 1842 void x2apic_setup(void) 1843 { 1844 /* 1845 * If x2apic is not in ON state, disable it if already enabled 1846 * from BIOS. 1847 */ 1848 if (x2apic_state != X2APIC_ON) { 1849 __x2apic_disable(); 1850 return; 1851 } 1852 __x2apic_enable(); 1853 } 1854 1855 static __init void x2apic_disable(void) 1856 { 1857 u32 x2apic_id, state = x2apic_state; 1858 1859 x2apic_mode = 0; 1860 x2apic_state = X2APIC_DISABLED; 1861 1862 if (state != X2APIC_ON) 1863 return; 1864 1865 x2apic_id = read_apic_id(); 1866 if (x2apic_id >= 255) 1867 panic("Cannot disable x2apic, id: %08x\n", x2apic_id); 1868 1869 __x2apic_disable(); 1870 register_lapic_address(mp_lapic_addr); 1871 } 1872 1873 static __init void x2apic_enable(void) 1874 { 1875 if (x2apic_state != X2APIC_OFF) 1876 return; 1877 1878 x2apic_mode = 1; 1879 x2apic_state = X2APIC_ON; 1880 __x2apic_enable(); 1881 } 1882 1883 static __init void try_to_enable_x2apic(int remap_mode) 1884 { 1885 if (x2apic_state == X2APIC_DISABLED) 1886 return; 1887 1888 if (remap_mode != IRQ_REMAP_X2APIC_MODE) { 1889 /* IR is required if there is APIC ID > 255 even when running 1890 * under KVM 1891 */ 1892 if (max_physical_apicid > 255 || 1893 !x86_init.hyper.x2apic_available()) { 1894 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n"); 1895 x2apic_disable(); 1896 return; 1897 } 1898 1899 /* 1900 * without IR all CPUs can be addressed by IOAPIC/MSI 1901 * only in physical mode 1902 */ 1903 x2apic_phys = 1; 1904 } 1905 x2apic_enable(); 1906 } 1907 1908 void __init check_x2apic(void) 1909 { 1910 if (x2apic_enabled()) { 1911 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n"); 1912 x2apic_mode = 1; 1913 x2apic_state = X2APIC_ON; 1914 } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) { 1915 x2apic_state = X2APIC_DISABLED; 1916 } 1917 } 1918 #else /* CONFIG_X86_X2APIC */ 1919 static int __init validate_x2apic(void) 1920 { 1921 if (!apic_is_x2apic_enabled()) 1922 return 0; 1923 /* 1924 * Checkme: Can we simply turn off x2apic here instead of panic? 1925 */ 1926 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n"); 1927 } 1928 early_initcall(validate_x2apic); 1929 1930 static inline void try_to_enable_x2apic(int remap_mode) { } 1931 static inline void __x2apic_enable(void) { } 1932 #endif /* !CONFIG_X86_X2APIC */ 1933 1934 void __init enable_IR_x2apic(void) 1935 { 1936 unsigned long flags; 1937 int ret, ir_stat; 1938 1939 if (skip_ioapic_setup) { 1940 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n"); 1941 return; 1942 } 1943 1944 ir_stat = irq_remapping_prepare(); 1945 if (ir_stat < 0 && !x2apic_supported()) 1946 return; 1947 1948 ret = save_ioapic_entries(); 1949 if (ret) { 1950 pr_info("Saving IO-APIC state failed: %d\n", ret); 1951 return; 1952 } 1953 1954 local_irq_save(flags); 1955 legacy_pic->mask_all(); 1956 mask_ioapic_entries(); 1957 1958 /* If irq_remapping_prepare() succeeded, try to enable it */ 1959 if (ir_stat >= 0) 1960 ir_stat = irq_remapping_enable(); 1961 /* ir_stat contains the remap mode or an error code */ 1962 try_to_enable_x2apic(ir_stat); 1963 1964 if (ir_stat < 0) 1965 restore_ioapic_entries(); 1966 legacy_pic->restore_mask(); 1967 local_irq_restore(flags); 1968 } 1969 1970 #ifdef CONFIG_X86_64 1971 /* 1972 * Detect and enable local APICs on non-SMP boards. 1973 * Original code written by Keir Fraser. 1974 * On AMD64 we trust the BIOS - if it says no APIC it is likely 1975 * not correctly set up (usually the APIC timer won't work etc.) 1976 */ 1977 static int __init detect_init_APIC(void) 1978 { 1979 if (!boot_cpu_has(X86_FEATURE_APIC)) { 1980 pr_info("No local APIC present\n"); 1981 return -1; 1982 } 1983 1984 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1985 return 0; 1986 } 1987 #else 1988 1989 static int __init apic_verify(void) 1990 { 1991 u32 features, h, l; 1992 1993 /* 1994 * The APIC feature bit should now be enabled 1995 * in `cpuid' 1996 */ 1997 features = cpuid_edx(1); 1998 if (!(features & (1 << X86_FEATURE_APIC))) { 1999 pr_warn("Could not enable APIC!\n"); 2000 return -1; 2001 } 2002 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 2003 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 2004 2005 /* The BIOS may have set up the APIC at some other address */ 2006 if (boot_cpu_data.x86 >= 6) { 2007 rdmsr(MSR_IA32_APICBASE, l, h); 2008 if (l & MSR_IA32_APICBASE_ENABLE) 2009 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 2010 } 2011 2012 pr_info("Found and enabled local APIC!\n"); 2013 return 0; 2014 } 2015 2016 int __init apic_force_enable(unsigned long addr) 2017 { 2018 u32 h, l; 2019 2020 if (disable_apic) 2021 return -1; 2022 2023 /* 2024 * Some BIOSes disable the local APIC in the APIC_BASE 2025 * MSR. This can only be done in software for Intel P6 or later 2026 * and AMD K7 (Model > 1) or later. 2027 */ 2028 if (boot_cpu_data.x86 >= 6) { 2029 rdmsr(MSR_IA32_APICBASE, l, h); 2030 if (!(l & MSR_IA32_APICBASE_ENABLE)) { 2031 pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 2032 l &= ~MSR_IA32_APICBASE_BASE; 2033 l |= MSR_IA32_APICBASE_ENABLE | addr; 2034 wrmsr(MSR_IA32_APICBASE, l, h); 2035 enabled_via_apicbase = 1; 2036 } 2037 } 2038 return apic_verify(); 2039 } 2040 2041 /* 2042 * Detect and initialize APIC 2043 */ 2044 static int __init detect_init_APIC(void) 2045 { 2046 /* Disabled by kernel option? */ 2047 if (disable_apic) 2048 return -1; 2049 2050 switch (boot_cpu_data.x86_vendor) { 2051 case X86_VENDOR_AMD: 2052 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 2053 (boot_cpu_data.x86 >= 15)) 2054 break; 2055 goto no_apic; 2056 case X86_VENDOR_HYGON: 2057 break; 2058 case X86_VENDOR_INTEL: 2059 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 2060 (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC))) 2061 break; 2062 goto no_apic; 2063 default: 2064 goto no_apic; 2065 } 2066 2067 if (!boot_cpu_has(X86_FEATURE_APIC)) { 2068 /* 2069 * Over-ride BIOS and try to enable the local APIC only if 2070 * "lapic" specified. 2071 */ 2072 if (!force_enable_local_apic) { 2073 pr_info("Local APIC disabled by BIOS -- " 2074 "you can enable it with \"lapic\"\n"); 2075 return -1; 2076 } 2077 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) 2078 return -1; 2079 } else { 2080 if (apic_verify()) 2081 return -1; 2082 } 2083 2084 apic_pm_activate(); 2085 2086 return 0; 2087 2088 no_apic: 2089 pr_info("No local APIC present or hardware disabled\n"); 2090 return -1; 2091 } 2092 #endif 2093 2094 /** 2095 * init_apic_mappings - initialize APIC mappings 2096 */ 2097 void __init init_apic_mappings(void) 2098 { 2099 unsigned int new_apicid; 2100 2101 apic_check_deadline_errata(); 2102 2103 if (x2apic_mode) { 2104 boot_cpu_physical_apicid = read_apic_id(); 2105 return; 2106 } 2107 2108 /* If no local APIC can be found return early */ 2109 if (!smp_found_config && detect_init_APIC()) { 2110 /* lets NOP'ify apic operations */ 2111 pr_info("APIC: disable apic facility\n"); 2112 apic_disable(); 2113 } else { 2114 apic_phys = mp_lapic_addr; 2115 2116 /* 2117 * If the system has ACPI MADT tables or MP info, the LAPIC 2118 * address is already registered. 2119 */ 2120 if (!acpi_lapic && !smp_found_config) 2121 register_lapic_address(apic_phys); 2122 } 2123 2124 /* 2125 * Fetch the APIC ID of the BSP in case we have a 2126 * default configuration (or the MP table is broken). 2127 */ 2128 new_apicid = read_apic_id(); 2129 if (boot_cpu_physical_apicid != new_apicid) { 2130 boot_cpu_physical_apicid = new_apicid; 2131 /* 2132 * yeah -- we lie about apic_version 2133 * in case if apic was disabled via boot option 2134 * but it's not a problem for SMP compiled kernel 2135 * since apic_intr_mode_select is prepared for such 2136 * a case and disable smp mode 2137 */ 2138 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 2139 } 2140 } 2141 2142 void __init register_lapic_address(unsigned long address) 2143 { 2144 mp_lapic_addr = address; 2145 2146 if (!x2apic_mode) { 2147 set_fixmap_nocache(FIX_APIC_BASE, address); 2148 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 2149 APIC_BASE, address); 2150 } 2151 if (boot_cpu_physical_apicid == -1U) { 2152 boot_cpu_physical_apicid = read_apic_id(); 2153 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 2154 } 2155 } 2156 2157 /* 2158 * Local APIC interrupts 2159 */ 2160 2161 /* 2162 * This interrupt should _never_ happen with our APIC/SMP architecture 2163 */ 2164 __visible void __irq_entry smp_spurious_interrupt(struct pt_regs *regs) 2165 { 2166 u8 vector = ~regs->orig_ax; 2167 u32 v; 2168 2169 entering_irq(); 2170 trace_spurious_apic_entry(vector); 2171 2172 inc_irq_stat(irq_spurious_count); 2173 2174 /* 2175 * If this is a spurious interrupt then do not acknowledge 2176 */ 2177 if (vector == SPURIOUS_APIC_VECTOR) { 2178 /* See SDM vol 3 */ 2179 pr_info("Spurious APIC interrupt (vector 0xFF) on CPU#%d, should never happen.\n", 2180 smp_processor_id()); 2181 goto out; 2182 } 2183 2184 /* 2185 * If it is a vectored one, verify it's set in the ISR. If set, 2186 * acknowledge it. 2187 */ 2188 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1)); 2189 if (v & (1 << (vector & 0x1f))) { 2190 pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Acked\n", 2191 vector, smp_processor_id()); 2192 ack_APIC_irq(); 2193 } else { 2194 pr_info("Spurious interrupt (vector 0x%02x) on CPU#%d. Not pending!\n", 2195 vector, smp_processor_id()); 2196 } 2197 out: 2198 trace_spurious_apic_exit(vector); 2199 exiting_irq(); 2200 } 2201 2202 /* 2203 * This interrupt should never happen with our APIC/SMP architecture 2204 */ 2205 __visible void __irq_entry smp_error_interrupt(struct pt_regs *regs) 2206 { 2207 static const char * const error_interrupt_reason[] = { 2208 "Send CS error", /* APIC Error Bit 0 */ 2209 "Receive CS error", /* APIC Error Bit 1 */ 2210 "Send accept error", /* APIC Error Bit 2 */ 2211 "Receive accept error", /* APIC Error Bit 3 */ 2212 "Redirectable IPI", /* APIC Error Bit 4 */ 2213 "Send illegal vector", /* APIC Error Bit 5 */ 2214 "Received illegal vector", /* APIC Error Bit 6 */ 2215 "Illegal register address", /* APIC Error Bit 7 */ 2216 }; 2217 u32 v, i = 0; 2218 2219 entering_irq(); 2220 trace_error_apic_entry(ERROR_APIC_VECTOR); 2221 2222 /* First tickle the hardware, only then report what went on. -- REW */ 2223 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */ 2224 apic_write(APIC_ESR, 0); 2225 v = apic_read(APIC_ESR); 2226 ack_APIC_irq(); 2227 atomic_inc(&irq_err_count); 2228 2229 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x", 2230 smp_processor_id(), v); 2231 2232 v &= 0xff; 2233 while (v) { 2234 if (v & 0x1) 2235 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); 2236 i++; 2237 v >>= 1; 2238 } 2239 2240 apic_printk(APIC_DEBUG, KERN_CONT "\n"); 2241 2242 trace_error_apic_exit(ERROR_APIC_VECTOR); 2243 exiting_irq(); 2244 } 2245 2246 /** 2247 * connect_bsp_APIC - attach the APIC to the interrupt system 2248 */ 2249 static void __init connect_bsp_APIC(void) 2250 { 2251 #ifdef CONFIG_X86_32 2252 if (pic_mode) { 2253 /* 2254 * Do not trust the local APIC being empty at bootup. 2255 */ 2256 clear_local_APIC(); 2257 /* 2258 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 2259 * local APIC to INT and NMI lines. 2260 */ 2261 apic_printk(APIC_VERBOSE, "leaving PIC mode, " 2262 "enabling APIC mode.\n"); 2263 imcr_pic_to_apic(); 2264 } 2265 #endif 2266 } 2267 2268 /** 2269 * disconnect_bsp_APIC - detach the APIC from the interrupt system 2270 * @virt_wire_setup: indicates, whether virtual wire mode is selected 2271 * 2272 * Virtual wire mode is necessary to deliver legacy interrupts even when the 2273 * APIC is disabled. 2274 */ 2275 void disconnect_bsp_APIC(int virt_wire_setup) 2276 { 2277 unsigned int value; 2278 2279 #ifdef CONFIG_X86_32 2280 if (pic_mode) { 2281 /* 2282 * Put the board back into PIC mode (has an effect only on 2283 * certain older boards). Note that APIC interrupts, including 2284 * IPIs, won't work beyond this point! The only exception are 2285 * INIT IPIs. 2286 */ 2287 apic_printk(APIC_VERBOSE, "disabling APIC mode, " 2288 "entering PIC mode.\n"); 2289 imcr_apic_to_pic(); 2290 return; 2291 } 2292 #endif 2293 2294 /* Go back to Virtual Wire compatibility mode */ 2295 2296 /* For the spurious interrupt use vector F, and enable it */ 2297 value = apic_read(APIC_SPIV); 2298 value &= ~APIC_VECTOR_MASK; 2299 value |= APIC_SPIV_APIC_ENABLED; 2300 value |= 0xf; 2301 apic_write(APIC_SPIV, value); 2302 2303 if (!virt_wire_setup) { 2304 /* 2305 * For LVT0 make it edge triggered, active high, 2306 * external and enabled 2307 */ 2308 value = apic_read(APIC_LVT0); 2309 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2310 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2311 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2312 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2313 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 2314 apic_write(APIC_LVT0, value); 2315 } else { 2316 /* Disable LVT0 */ 2317 apic_write(APIC_LVT0, APIC_LVT_MASKED); 2318 } 2319 2320 /* 2321 * For LVT1 make it edge triggered, active high, 2322 * nmi and enabled 2323 */ 2324 value = apic_read(APIC_LVT1); 2325 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2326 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2327 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2328 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2329 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 2330 apic_write(APIC_LVT1, value); 2331 } 2332 2333 /* 2334 * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated 2335 * contiguously, it equals to current allocated max logical CPU ID plus 1. 2336 * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range, 2337 * so the maximum of nr_logical_cpuids is nr_cpu_ids. 2338 * 2339 * NOTE: Reserve 0 for BSP. 2340 */ 2341 static int nr_logical_cpuids = 1; 2342 2343 /* 2344 * Used to store mapping between logical CPU IDs and APIC IDs. 2345 */ 2346 static int cpuid_to_apicid[] = { 2347 [0 ... NR_CPUS - 1] = -1, 2348 }; 2349 2350 #ifdef CONFIG_SMP 2351 /** 2352 * apic_id_is_primary_thread - Check whether APIC ID belongs to a primary thread 2353 * @apicid: APIC ID to check 2354 */ 2355 bool apic_id_is_primary_thread(unsigned int apicid) 2356 { 2357 u32 mask; 2358 2359 if (smp_num_siblings == 1) 2360 return true; 2361 /* Isolate the SMT bit(s) in the APICID and check for 0 */ 2362 mask = (1U << (fls(smp_num_siblings) - 1)) - 1; 2363 return !(apicid & mask); 2364 } 2365 #endif 2366 2367 /* 2368 * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids 2369 * and cpuid_to_apicid[] synchronized. 2370 */ 2371 static int allocate_logical_cpuid(int apicid) 2372 { 2373 int i; 2374 2375 /* 2376 * cpuid <-> apicid mapping is persistent, so when a cpu is up, 2377 * check if the kernel has allocated a cpuid for it. 2378 */ 2379 for (i = 0; i < nr_logical_cpuids; i++) { 2380 if (cpuid_to_apicid[i] == apicid) 2381 return i; 2382 } 2383 2384 /* Allocate a new cpuid. */ 2385 if (nr_logical_cpuids >= nr_cpu_ids) { 2386 WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. " 2387 "Processor %d/0x%x and the rest are ignored.\n", 2388 nr_cpu_ids, nr_logical_cpuids, apicid); 2389 return -EINVAL; 2390 } 2391 2392 cpuid_to_apicid[nr_logical_cpuids] = apicid; 2393 return nr_logical_cpuids++; 2394 } 2395 2396 int generic_processor_info(int apicid, int version) 2397 { 2398 int cpu, max = nr_cpu_ids; 2399 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, 2400 phys_cpu_present_map); 2401 2402 /* 2403 * boot_cpu_physical_apicid is designed to have the apicid 2404 * returned by read_apic_id(), i.e, the apicid of the 2405 * currently booting-up processor. However, on some platforms, 2406 * it is temporarily modified by the apicid reported as BSP 2407 * through MP table. Concretely: 2408 * 2409 * - arch/x86/kernel/mpparse.c: MP_processor_info() 2410 * - arch/x86/mm/amdtopology.c: amd_numa_init() 2411 * 2412 * This function is executed with the modified 2413 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel 2414 * parameter doesn't work to disable APs on kdump 2nd kernel. 2415 * 2416 * Since fixing handling of boot_cpu_physical_apicid requires 2417 * another discussion and tests on each platform, we leave it 2418 * for now and here we use read_apic_id() directly in this 2419 * function, generic_processor_info(). 2420 */ 2421 if (disabled_cpu_apicid != BAD_APICID && 2422 disabled_cpu_apicid != read_apic_id() && 2423 disabled_cpu_apicid == apicid) { 2424 int thiscpu = num_processors + disabled_cpus; 2425 2426 pr_warn("APIC: Disabling requested cpu." 2427 " Processor %d/0x%x ignored.\n", thiscpu, apicid); 2428 2429 disabled_cpus++; 2430 return -ENODEV; 2431 } 2432 2433 /* 2434 * If boot cpu has not been detected yet, then only allow upto 2435 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu 2436 */ 2437 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && 2438 apicid != boot_cpu_physical_apicid) { 2439 int thiscpu = max + disabled_cpus - 1; 2440 2441 pr_warn("APIC: NR_CPUS/possible_cpus limit of %i almost" 2442 " reached. Keeping one slot for boot cpu." 2443 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 2444 2445 disabled_cpus++; 2446 return -ENODEV; 2447 } 2448 2449 if (num_processors >= nr_cpu_ids) { 2450 int thiscpu = max + disabled_cpus; 2451 2452 pr_warn("APIC: NR_CPUS/possible_cpus limit of %i reached. " 2453 "Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 2454 2455 disabled_cpus++; 2456 return -EINVAL; 2457 } 2458 2459 if (apicid == boot_cpu_physical_apicid) { 2460 /* 2461 * x86_bios_cpu_apicid is required to have processors listed 2462 * in same order as logical cpu numbers. Hence the first 2463 * entry is BSP, and so on. 2464 * boot_cpu_init() already hold bit 0 in cpu_present_mask 2465 * for BSP. 2466 */ 2467 cpu = 0; 2468 2469 /* Logical cpuid 0 is reserved for BSP. */ 2470 cpuid_to_apicid[0] = apicid; 2471 } else { 2472 cpu = allocate_logical_cpuid(apicid); 2473 if (cpu < 0) { 2474 disabled_cpus++; 2475 return -EINVAL; 2476 } 2477 } 2478 2479 /* 2480 * Validate version 2481 */ 2482 if (version == 0x0) { 2483 pr_warn("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", 2484 cpu, apicid); 2485 version = 0x10; 2486 } 2487 2488 if (version != boot_cpu_apic_version) { 2489 pr_warn("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", 2490 boot_cpu_apic_version, cpu, version); 2491 } 2492 2493 if (apicid > max_physical_apicid) 2494 max_physical_apicid = apicid; 2495 2496 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 2497 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 2498 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 2499 #endif 2500 #ifdef CONFIG_X86_32 2501 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 2502 apic->x86_32_early_logical_apicid(cpu); 2503 #endif 2504 set_cpu_possible(cpu, true); 2505 physid_set(apicid, phys_cpu_present_map); 2506 set_cpu_present(cpu, true); 2507 num_processors++; 2508 2509 return cpu; 2510 } 2511 2512 int hard_smp_processor_id(void) 2513 { 2514 return read_apic_id(); 2515 } 2516 2517 /* 2518 * Override the generic EOI implementation with an optimized version. 2519 * Only called during early boot when only one CPU is active and with 2520 * interrupts disabled, so we know this does not race with actual APIC driver 2521 * use. 2522 */ 2523 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) 2524 { 2525 struct apic **drv; 2526 2527 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { 2528 /* Should happen once for each apic */ 2529 WARN_ON((*drv)->eoi_write == eoi_write); 2530 (*drv)->native_eoi_write = (*drv)->eoi_write; 2531 (*drv)->eoi_write = eoi_write; 2532 } 2533 } 2534 2535 static void __init apic_bsp_up_setup(void) 2536 { 2537 #ifdef CONFIG_X86_64 2538 apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid)); 2539 #else 2540 /* 2541 * Hack: In case of kdump, after a crash, kernel might be booting 2542 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 2543 * might be zero if read from MP tables. Get it from LAPIC. 2544 */ 2545 # ifdef CONFIG_CRASH_DUMP 2546 boot_cpu_physical_apicid = read_apic_id(); 2547 # endif 2548 #endif 2549 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 2550 } 2551 2552 /** 2553 * apic_bsp_setup - Setup function for local apic and io-apic 2554 * @upmode: Force UP mode (for APIC_init_uniprocessor) 2555 */ 2556 static void __init apic_bsp_setup(bool upmode) 2557 { 2558 connect_bsp_APIC(); 2559 if (upmode) 2560 apic_bsp_up_setup(); 2561 setup_local_APIC(); 2562 2563 enable_IO_APIC(); 2564 end_local_APIC_setup(); 2565 irq_remap_enable_fault_handling(); 2566 setup_IO_APIC(); 2567 } 2568 2569 #ifdef CONFIG_UP_LATE_INIT 2570 void __init up_late_init(void) 2571 { 2572 if (apic_intr_mode == APIC_PIC) 2573 return; 2574 2575 /* Setup local timer */ 2576 x86_init.timers.setup_percpu_clockev(); 2577 } 2578 #endif 2579 2580 /* 2581 * Power management 2582 */ 2583 #ifdef CONFIG_PM 2584 2585 static struct { 2586 /* 2587 * 'active' is true if the local APIC was enabled by us and 2588 * not the BIOS; this signifies that we are also responsible 2589 * for disabling it before entering apm/acpi suspend 2590 */ 2591 int active; 2592 /* r/w apic fields */ 2593 unsigned int apic_id; 2594 unsigned int apic_taskpri; 2595 unsigned int apic_ldr; 2596 unsigned int apic_dfr; 2597 unsigned int apic_spiv; 2598 unsigned int apic_lvtt; 2599 unsigned int apic_lvtpc; 2600 unsigned int apic_lvt0; 2601 unsigned int apic_lvt1; 2602 unsigned int apic_lvterr; 2603 unsigned int apic_tmict; 2604 unsigned int apic_tdcr; 2605 unsigned int apic_thmr; 2606 unsigned int apic_cmci; 2607 } apic_pm_state; 2608 2609 static int lapic_suspend(void) 2610 { 2611 unsigned long flags; 2612 int maxlvt; 2613 2614 if (!apic_pm_state.active) 2615 return 0; 2616 2617 maxlvt = lapic_get_maxlvt(); 2618 2619 apic_pm_state.apic_id = apic_read(APIC_ID); 2620 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 2621 apic_pm_state.apic_ldr = apic_read(APIC_LDR); 2622 apic_pm_state.apic_dfr = apic_read(APIC_DFR); 2623 apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2624 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2625 if (maxlvt >= 4) 2626 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2627 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2628 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2629 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2630 apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2631 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 2632 #ifdef CONFIG_X86_THERMAL_VECTOR 2633 if (maxlvt >= 5) 2634 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2635 #endif 2636 #ifdef CONFIG_X86_MCE_INTEL 2637 if (maxlvt >= 6) 2638 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI); 2639 #endif 2640 2641 local_irq_save(flags); 2642 2643 /* 2644 * Mask IOAPIC before disabling the local APIC to prevent stale IRR 2645 * entries on some implementations. 2646 */ 2647 mask_ioapic_entries(); 2648 2649 disable_local_APIC(); 2650 2651 irq_remapping_disable(); 2652 2653 local_irq_restore(flags); 2654 return 0; 2655 } 2656 2657 static void lapic_resume(void) 2658 { 2659 unsigned int l, h; 2660 unsigned long flags; 2661 int maxlvt; 2662 2663 if (!apic_pm_state.active) 2664 return; 2665 2666 local_irq_save(flags); 2667 2668 /* 2669 * IO-APIC and PIC have their own resume routines. 2670 * We just mask them here to make sure the interrupt 2671 * subsystem is completely quiet while we enable x2apic 2672 * and interrupt-remapping. 2673 */ 2674 mask_ioapic_entries(); 2675 legacy_pic->mask_all(); 2676 2677 if (x2apic_mode) { 2678 __x2apic_enable(); 2679 } else { 2680 /* 2681 * Make sure the APICBASE points to the right address 2682 * 2683 * FIXME! This will be wrong if we ever support suspend on 2684 * SMP! We'll need to do this as part of the CPU restore! 2685 */ 2686 if (boot_cpu_data.x86 >= 6) { 2687 rdmsr(MSR_IA32_APICBASE, l, h); 2688 l &= ~MSR_IA32_APICBASE_BASE; 2689 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2690 wrmsr(MSR_IA32_APICBASE, l, h); 2691 } 2692 } 2693 2694 maxlvt = lapic_get_maxlvt(); 2695 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2696 apic_write(APIC_ID, apic_pm_state.apic_id); 2697 apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2698 apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2699 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2700 apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2701 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2702 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 2703 #ifdef CONFIG_X86_THERMAL_VECTOR 2704 if (maxlvt >= 5) 2705 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2706 #endif 2707 #ifdef CONFIG_X86_MCE_INTEL 2708 if (maxlvt >= 6) 2709 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci); 2710 #endif 2711 if (maxlvt >= 4) 2712 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2713 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2714 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2715 apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2716 apic_write(APIC_ESR, 0); 2717 apic_read(APIC_ESR); 2718 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2719 apic_write(APIC_ESR, 0); 2720 apic_read(APIC_ESR); 2721 2722 irq_remapping_reenable(x2apic_mode); 2723 2724 local_irq_restore(flags); 2725 } 2726 2727 /* 2728 * This device has no shutdown method - fully functioning local APICs 2729 * are needed on every CPU up until machine_halt/restart/poweroff. 2730 */ 2731 2732 static struct syscore_ops lapic_syscore_ops = { 2733 .resume = lapic_resume, 2734 .suspend = lapic_suspend, 2735 }; 2736 2737 static void apic_pm_activate(void) 2738 { 2739 apic_pm_state.active = 1; 2740 } 2741 2742 static int __init init_lapic_sysfs(void) 2743 { 2744 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 2745 if (boot_cpu_has(X86_FEATURE_APIC)) 2746 register_syscore_ops(&lapic_syscore_ops); 2747 2748 return 0; 2749 } 2750 2751 /* local apic needs to resume before other devices access its registers. */ 2752 core_initcall(init_lapic_sysfs); 2753 2754 #else /* CONFIG_PM */ 2755 2756 static void apic_pm_activate(void) { } 2757 2758 #endif /* CONFIG_PM */ 2759 2760 #ifdef CONFIG_X86_64 2761 2762 static int multi_checked; 2763 static int multi; 2764 2765 static int set_multi(const struct dmi_system_id *d) 2766 { 2767 if (multi) 2768 return 0; 2769 pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2770 multi = 1; 2771 return 0; 2772 } 2773 2774 static const struct dmi_system_id multi_dmi_table[] = { 2775 { 2776 .callback = set_multi, 2777 .ident = "IBM System Summit2", 2778 .matches = { 2779 DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2780 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2781 }, 2782 }, 2783 {} 2784 }; 2785 2786 static void dmi_check_multi(void) 2787 { 2788 if (multi_checked) 2789 return; 2790 2791 dmi_check_system(multi_dmi_table); 2792 multi_checked = 1; 2793 } 2794 2795 /* 2796 * apic_is_clustered_box() -- Check if we can expect good TSC 2797 * 2798 * Thus far, the major user of this is IBM's Summit2 series: 2799 * Clustered boxes may have unsynced TSC problems if they are 2800 * multi-chassis. 2801 * Use DMI to check them 2802 */ 2803 int apic_is_clustered_box(void) 2804 { 2805 dmi_check_multi(); 2806 return multi; 2807 } 2808 #endif 2809 2810 /* 2811 * APIC command line parameters 2812 */ 2813 static int __init setup_disableapic(char *arg) 2814 { 2815 disable_apic = 1; 2816 setup_clear_cpu_cap(X86_FEATURE_APIC); 2817 return 0; 2818 } 2819 early_param("disableapic", setup_disableapic); 2820 2821 /* same as disableapic, for compatibility */ 2822 static int __init setup_nolapic(char *arg) 2823 { 2824 return setup_disableapic(arg); 2825 } 2826 early_param("nolapic", setup_nolapic); 2827 2828 static int __init parse_lapic_timer_c2_ok(char *arg) 2829 { 2830 local_apic_timer_c2_ok = 1; 2831 return 0; 2832 } 2833 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2834 2835 static int __init parse_disable_apic_timer(char *arg) 2836 { 2837 disable_apic_timer = 1; 2838 return 0; 2839 } 2840 early_param("noapictimer", parse_disable_apic_timer); 2841 2842 static int __init parse_nolapic_timer(char *arg) 2843 { 2844 disable_apic_timer = 1; 2845 return 0; 2846 } 2847 early_param("nolapic_timer", parse_nolapic_timer); 2848 2849 static int __init apic_set_verbosity(char *arg) 2850 { 2851 if (!arg) { 2852 #ifdef CONFIG_X86_64 2853 skip_ioapic_setup = 0; 2854 return 0; 2855 #endif 2856 return -EINVAL; 2857 } 2858 2859 if (strcmp("debug", arg) == 0) 2860 apic_verbosity = APIC_DEBUG; 2861 else if (strcmp("verbose", arg) == 0) 2862 apic_verbosity = APIC_VERBOSE; 2863 #ifdef CONFIG_X86_64 2864 else { 2865 pr_warn("APIC Verbosity level %s not recognised" 2866 " use apic=verbose or apic=debug\n", arg); 2867 return -EINVAL; 2868 } 2869 #endif 2870 2871 return 0; 2872 } 2873 early_param("apic", apic_set_verbosity); 2874 2875 static int __init lapic_insert_resource(void) 2876 { 2877 if (!apic_phys) 2878 return -1; 2879 2880 /* Put local APIC into the resource map. */ 2881 lapic_resource.start = apic_phys; 2882 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2883 insert_resource(&iomem_resource, &lapic_resource); 2884 2885 return 0; 2886 } 2887 2888 /* 2889 * need call insert after e820__reserve_resources() 2890 * that is using request_resource 2891 */ 2892 late_initcall(lapic_insert_resource); 2893 2894 static int __init apic_set_disabled_cpu_apicid(char *arg) 2895 { 2896 if (!arg || !get_option(&arg, &disabled_cpu_apicid)) 2897 return -EINVAL; 2898 2899 return 0; 2900 } 2901 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); 2902 2903 static int __init apic_set_extnmi(char *arg) 2904 { 2905 if (!arg) 2906 return -EINVAL; 2907 2908 if (!strncmp("all", arg, 3)) 2909 apic_extnmi = APIC_EXTNMI_ALL; 2910 else if (!strncmp("none", arg, 4)) 2911 apic_extnmi = APIC_EXTNMI_NONE; 2912 else if (!strncmp("bsp", arg, 3)) 2913 apic_extnmi = APIC_EXTNMI_BSP; 2914 else { 2915 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg); 2916 return -EINVAL; 2917 } 2918 2919 return 0; 2920 } 2921 early_param("apic_extnmi", apic_set_extnmi); 2922