1 /* 2 * Local APIC handling, local APIC timers 3 * 4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 5 * 6 * Fixes 7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 8 * thanks to Eric Gilmore 9 * and Rolf G. Tews 10 * for testing these extensively. 11 * Maciej W. Rozycki : Various updates and fixes. 12 * Mikael Pettersson : Power Management for UP-APIC. 13 * Pavel Machek and 14 * Mikael Pettersson : PM converted to driver model. 15 */ 16 17 #include <linux/perf_event.h> 18 #include <linux/kernel_stat.h> 19 #include <linux/mc146818rtc.h> 20 #include <linux/acpi_pmtmr.h> 21 #include <linux/clockchips.h> 22 #include <linux/interrupt.h> 23 #include <linux/bootmem.h> 24 #include <linux/ftrace.h> 25 #include <linux/ioport.h> 26 #include <linux/export.h> 27 #include <linux/syscore_ops.h> 28 #include <linux/delay.h> 29 #include <linux/timex.h> 30 #include <linux/i8253.h> 31 #include <linux/dmar.h> 32 #include <linux/init.h> 33 #include <linux/cpu.h> 34 #include <linux/dmi.h> 35 #include <linux/smp.h> 36 #include <linux/mm.h> 37 38 #include <asm/trace/irq_vectors.h> 39 #include <asm/irq_remapping.h> 40 #include <asm/perf_event.h> 41 #include <asm/x86_init.h> 42 #include <asm/pgalloc.h> 43 #include <linux/atomic.h> 44 #include <asm/mpspec.h> 45 #include <asm/i8259.h> 46 #include <asm/proto.h> 47 #include <asm/apic.h> 48 #include <asm/io_apic.h> 49 #include <asm/desc.h> 50 #include <asm/hpet.h> 51 #include <asm/mtrr.h> 52 #include <asm/time.h> 53 #include <asm/smp.h> 54 #include <asm/mce.h> 55 #include <asm/tsc.h> 56 #include <asm/hypervisor.h> 57 #include <asm/cpu_device_id.h> 58 #include <asm/intel-family.h> 59 60 unsigned int num_processors; 61 62 unsigned disabled_cpus; 63 64 /* Processor that is doing the boot up */ 65 unsigned int boot_cpu_physical_apicid = -1U; 66 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); 67 68 u8 boot_cpu_apic_version; 69 70 /* 71 * The highest APIC ID seen during enumeration. 72 */ 73 static unsigned int max_physical_apicid; 74 75 /* 76 * Bitmask of physically existing CPUs: 77 */ 78 physid_mask_t phys_cpu_present_map; 79 80 /* 81 * Processor to be disabled specified by kernel parameter 82 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to 83 * avoid undefined behaviour caused by sending INIT from AP to BSP. 84 */ 85 static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID; 86 87 /* 88 * This variable controls which CPUs receive external NMIs. By default, 89 * external NMIs are delivered only to the BSP. 90 */ 91 static int apic_extnmi = APIC_EXTNMI_BSP; 92 93 /* 94 * Map cpu index to physical APIC ID 95 */ 96 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); 97 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID); 98 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX); 99 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 100 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 101 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid); 102 103 #ifdef CONFIG_X86_32 104 105 /* 106 * On x86_32, the mapping between cpu and logical apicid may vary 107 * depending on apic in use. The following early percpu variable is 108 * used for the mapping. This is where the behaviors of x86_64 and 32 109 * actually diverge. Let's keep it ugly for now. 110 */ 111 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID); 112 113 /* Local APIC was disabled by the BIOS and enabled by the kernel */ 114 static int enabled_via_apicbase; 115 116 /* 117 * Handle interrupt mode configuration register (IMCR). 118 * This register controls whether the interrupt signals 119 * that reach the BSP come from the master PIC or from the 120 * local APIC. Before entering Symmetric I/O Mode, either 121 * the BIOS or the operating system must switch out of 122 * PIC Mode by changing the IMCR. 123 */ 124 static inline void imcr_pic_to_apic(void) 125 { 126 /* select IMCR register */ 127 outb(0x70, 0x22); 128 /* NMI and 8259 INTR go through APIC */ 129 outb(0x01, 0x23); 130 } 131 132 static inline void imcr_apic_to_pic(void) 133 { 134 /* select IMCR register */ 135 outb(0x70, 0x22); 136 /* NMI and 8259 INTR go directly to BSP */ 137 outb(0x00, 0x23); 138 } 139 #endif 140 141 /* 142 * Knob to control our willingness to enable the local APIC. 143 * 144 * +1=force-enable 145 */ 146 static int force_enable_local_apic __initdata; 147 148 /* 149 * APIC command line parameters 150 */ 151 static int __init parse_lapic(char *arg) 152 { 153 if (IS_ENABLED(CONFIG_X86_32) && !arg) 154 force_enable_local_apic = 1; 155 else if (arg && !strncmp(arg, "notscdeadline", 13)) 156 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 157 return 0; 158 } 159 early_param("lapic", parse_lapic); 160 161 #ifdef CONFIG_X86_64 162 static int apic_calibrate_pmtmr __initdata; 163 static __init int setup_apicpmtimer(char *s) 164 { 165 apic_calibrate_pmtmr = 1; 166 notsc_setup(NULL); 167 return 0; 168 } 169 __setup("apicpmtimer", setup_apicpmtimer); 170 #endif 171 172 unsigned long mp_lapic_addr; 173 int disable_apic; 174 /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 175 static int disable_apic_timer __initdata; 176 /* Local APIC timer works in C2 */ 177 int local_apic_timer_c2_ok; 178 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 179 180 /* 181 * Debug level, exported for io_apic.c 182 */ 183 unsigned int apic_verbosity; 184 185 int pic_mode; 186 187 /* Have we found an MP table */ 188 int smp_found_config; 189 190 static struct resource lapic_resource = { 191 .name = "Local APIC", 192 .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 193 }; 194 195 unsigned int lapic_timer_frequency = 0; 196 197 static void apic_pm_activate(void); 198 199 static unsigned long apic_phys; 200 201 /* 202 * Get the LAPIC version 203 */ 204 static inline int lapic_get_version(void) 205 { 206 return GET_APIC_VERSION(apic_read(APIC_LVR)); 207 } 208 209 /* 210 * Check, if the APIC is integrated or a separate chip 211 */ 212 static inline int lapic_is_integrated(void) 213 { 214 #ifdef CONFIG_X86_64 215 return 1; 216 #else 217 return APIC_INTEGRATED(lapic_get_version()); 218 #endif 219 } 220 221 /* 222 * Check, whether this is a modern or a first generation APIC 223 */ 224 static int modern_apic(void) 225 { 226 /* AMD systems use old APIC versions, so check the CPU */ 227 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 228 boot_cpu_data.x86 >= 0xf) 229 return 1; 230 return lapic_get_version() >= 0x14; 231 } 232 233 /* 234 * right after this call apic become NOOP driven 235 * so apic->write/read doesn't do anything 236 */ 237 static void __init apic_disable(void) 238 { 239 pr_info("APIC: switched to apic NOOP\n"); 240 apic = &apic_noop; 241 } 242 243 void native_apic_wait_icr_idle(void) 244 { 245 while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 246 cpu_relax(); 247 } 248 249 u32 native_safe_apic_wait_icr_idle(void) 250 { 251 u32 send_status; 252 int timeout; 253 254 timeout = 0; 255 do { 256 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 257 if (!send_status) 258 break; 259 inc_irq_stat(icr_read_retry_count); 260 udelay(100); 261 } while (timeout++ < 1000); 262 263 return send_status; 264 } 265 266 void native_apic_icr_write(u32 low, u32 id) 267 { 268 unsigned long flags; 269 270 local_irq_save(flags); 271 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 272 apic_write(APIC_ICR, low); 273 local_irq_restore(flags); 274 } 275 276 u64 native_apic_icr_read(void) 277 { 278 u32 icr1, icr2; 279 280 icr2 = apic_read(APIC_ICR2); 281 icr1 = apic_read(APIC_ICR); 282 283 return icr1 | ((u64)icr2 << 32); 284 } 285 286 #ifdef CONFIG_X86_32 287 /** 288 * get_physical_broadcast - Get number of physical broadcast IDs 289 */ 290 int get_physical_broadcast(void) 291 { 292 return modern_apic() ? 0xff : 0xf; 293 } 294 #endif 295 296 /** 297 * lapic_get_maxlvt - get the maximum number of local vector table entries 298 */ 299 int lapic_get_maxlvt(void) 300 { 301 unsigned int v; 302 303 v = apic_read(APIC_LVR); 304 /* 305 * - we always have APIC integrated on 64bit mode 306 * - 82489DXs do not report # of LVT entries 307 */ 308 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; 309 } 310 311 /* 312 * Local APIC timer 313 */ 314 315 /* Clock divisor */ 316 #define APIC_DIVISOR 16 317 #define TSC_DIVISOR 8 318 319 /* 320 * This function sets up the local APIC timer, with a timeout of 321 * 'clocks' APIC bus clock. During calibration we actually call 322 * this function twice on the boot CPU, once with a bogus timeout 323 * value, second time for real. The other (noncalibrating) CPUs 324 * call this function only once, with the real, calibrated value. 325 * 326 * We do reads before writes even if unnecessary, to get around the 327 * P5 APIC double write bug. 328 */ 329 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 330 { 331 unsigned int lvtt_value, tmp_value; 332 333 lvtt_value = LOCAL_TIMER_VECTOR; 334 if (!oneshot) 335 lvtt_value |= APIC_LVT_TIMER_PERIODIC; 336 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 337 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE; 338 339 if (!lapic_is_integrated()) 340 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 341 342 if (!irqen) 343 lvtt_value |= APIC_LVT_MASKED; 344 345 apic_write(APIC_LVTT, lvtt_value); 346 347 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { 348 /* 349 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, 350 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized. 351 * According to Intel, MFENCE can do the serialization here. 352 */ 353 asm volatile("mfence" : : : "memory"); 354 355 printk_once(KERN_DEBUG "TSC deadline timer enabled\n"); 356 return; 357 } 358 359 /* 360 * Divide PICLK by 16 361 */ 362 tmp_value = apic_read(APIC_TDCR); 363 apic_write(APIC_TDCR, 364 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 365 APIC_TDR_DIV_16); 366 367 if (!oneshot) 368 apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 369 } 370 371 /* 372 * Setup extended LVT, AMD specific 373 * 374 * Software should use the LVT offsets the BIOS provides. The offsets 375 * are determined by the subsystems using it like those for MCE 376 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts 377 * are supported. Beginning with family 10h at least 4 offsets are 378 * available. 379 * 380 * Since the offsets must be consistent for all cores, we keep track 381 * of the LVT offsets in software and reserve the offset for the same 382 * vector also to be used on other cores. An offset is freed by 383 * setting the entry to APIC_EILVT_MASKED. 384 * 385 * If the BIOS is right, there should be no conflicts. Otherwise a 386 * "[Firmware Bug]: ..." error message is generated. However, if 387 * software does not properly determines the offsets, it is not 388 * necessarily a BIOS bug. 389 */ 390 391 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; 392 393 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) 394 { 395 return (old & APIC_EILVT_MASKED) 396 || (new == APIC_EILVT_MASKED) 397 || ((new & ~APIC_EILVT_MASKED) == old); 398 } 399 400 static unsigned int reserve_eilvt_offset(int offset, unsigned int new) 401 { 402 unsigned int rsvd, vector; 403 404 if (offset >= APIC_EILVT_NR_MAX) 405 return ~0; 406 407 rsvd = atomic_read(&eilvt_offsets[offset]); 408 do { 409 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ 410 if (vector && !eilvt_entry_is_changeable(vector, new)) 411 /* may not change if vectors are different */ 412 return rsvd; 413 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); 414 } while (rsvd != new); 415 416 rsvd &= ~APIC_EILVT_MASKED; 417 if (rsvd && rsvd != vector) 418 pr_info("LVT offset %d assigned for vector 0x%02x\n", 419 offset, rsvd); 420 421 return new; 422 } 423 424 /* 425 * If mask=1, the LVT entry does not generate interrupts while mask=0 426 * enables the vector. See also the BKDGs. Must be called with 427 * preemption disabled. 428 */ 429 430 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) 431 { 432 unsigned long reg = APIC_EILVTn(offset); 433 unsigned int new, old, reserved; 434 435 new = (mask << 16) | (msg_type << 8) | vector; 436 old = apic_read(reg); 437 reserved = reserve_eilvt_offset(offset, new); 438 439 if (reserved != new) { 440 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 441 "vector 0x%x, but the register is already in use for " 442 "vector 0x%x on another cpu\n", 443 smp_processor_id(), reg, offset, new, reserved); 444 return -EINVAL; 445 } 446 447 if (!eilvt_entry_is_changeable(old, new)) { 448 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 449 "vector 0x%x, but the register is already in use for " 450 "vector 0x%x on this cpu\n", 451 smp_processor_id(), reg, offset, new, old); 452 return -EBUSY; 453 } 454 455 apic_write(reg, new); 456 457 return 0; 458 } 459 EXPORT_SYMBOL_GPL(setup_APIC_eilvt); 460 461 /* 462 * Program the next event, relative to now 463 */ 464 static int lapic_next_event(unsigned long delta, 465 struct clock_event_device *evt) 466 { 467 apic_write(APIC_TMICT, delta); 468 return 0; 469 } 470 471 static int lapic_next_deadline(unsigned long delta, 472 struct clock_event_device *evt) 473 { 474 u64 tsc; 475 476 tsc = rdtsc(); 477 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); 478 return 0; 479 } 480 481 static int lapic_timer_shutdown(struct clock_event_device *evt) 482 { 483 unsigned int v; 484 485 /* Lapic used as dummy for broadcast ? */ 486 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 487 return 0; 488 489 v = apic_read(APIC_LVTT); 490 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 491 apic_write(APIC_LVTT, v); 492 apic_write(APIC_TMICT, 0); 493 return 0; 494 } 495 496 static inline int 497 lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot) 498 { 499 /* Lapic used as dummy for broadcast ? */ 500 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 501 return 0; 502 503 __setup_APIC_LVTT(lapic_timer_frequency, oneshot, 1); 504 return 0; 505 } 506 507 static int lapic_timer_set_periodic(struct clock_event_device *evt) 508 { 509 return lapic_timer_set_periodic_oneshot(evt, false); 510 } 511 512 static int lapic_timer_set_oneshot(struct clock_event_device *evt) 513 { 514 return lapic_timer_set_periodic_oneshot(evt, true); 515 } 516 517 /* 518 * Local APIC timer broadcast function 519 */ 520 static void lapic_timer_broadcast(const struct cpumask *mask) 521 { 522 #ifdef CONFIG_SMP 523 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 524 #endif 525 } 526 527 528 /* 529 * The local apic timer can be used for any function which is CPU local. 530 */ 531 static struct clock_event_device lapic_clockevent = { 532 .name = "lapic", 533 .features = CLOCK_EVT_FEAT_PERIODIC | 534 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP 535 | CLOCK_EVT_FEAT_DUMMY, 536 .shift = 32, 537 .set_state_shutdown = lapic_timer_shutdown, 538 .set_state_periodic = lapic_timer_set_periodic, 539 .set_state_oneshot = lapic_timer_set_oneshot, 540 .set_state_oneshot_stopped = lapic_timer_shutdown, 541 .set_next_event = lapic_next_event, 542 .broadcast = lapic_timer_broadcast, 543 .rating = 100, 544 .irq = -1, 545 }; 546 static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 547 548 #define DEADLINE_MODEL_MATCH_FUNC(model, func) \ 549 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&func } 550 551 #define DEADLINE_MODEL_MATCH_REV(model, rev) \ 552 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)rev } 553 554 static u32 hsx_deadline_rev(void) 555 { 556 switch (boot_cpu_data.x86_mask) { 557 case 0x02: return 0x3a; /* EP */ 558 case 0x04: return 0x0f; /* EX */ 559 } 560 561 return ~0U; 562 } 563 564 static u32 bdx_deadline_rev(void) 565 { 566 switch (boot_cpu_data.x86_mask) { 567 case 0x02: return 0x00000011; 568 case 0x03: return 0x0700000e; 569 case 0x04: return 0x0f00000c; 570 case 0x05: return 0x0e000003; 571 } 572 573 return ~0U; 574 } 575 576 static const struct x86_cpu_id deadline_match[] = { 577 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_HASWELL_X, hsx_deadline_rev), 578 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_X, 0x0b000020), 579 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_BROADWELL_XEON_D, bdx_deadline_rev), 580 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_X, 0x02000014), 581 582 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_CORE, 0x22), 583 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_ULT, 0x20), 584 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_GT3E, 0x17), 585 586 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_CORE, 0x25), 587 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_GT3E, 0x17), 588 589 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_MOBILE, 0xb2), 590 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_DESKTOP, 0xb2), 591 592 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_MOBILE, 0x52), 593 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_DESKTOP, 0x52), 594 595 {}, 596 }; 597 598 static void apic_check_deadline_errata(void) 599 { 600 const struct x86_cpu_id *m; 601 u32 rev; 602 603 if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 604 return; 605 606 m = x86_match_cpu(deadline_match); 607 if (!m) 608 return; 609 610 /* 611 * Function pointers will have the MSB set due to address layout, 612 * immediate revisions will not. 613 */ 614 if ((long)m->driver_data < 0) 615 rev = ((u32 (*)(void))(m->driver_data))(); 616 else 617 rev = (u32)m->driver_data; 618 619 if (boot_cpu_data.microcode >= rev) 620 return; 621 622 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 623 pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; " 624 "please update microcode to version: 0x%x (or later)\n", rev); 625 } 626 627 /* 628 * Setup the local APIC timer for this CPU. Copy the initialized values 629 * of the boot CPU and register the clock event in the framework. 630 */ 631 static void setup_APIC_timer(void) 632 { 633 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 634 635 if (this_cpu_has(X86_FEATURE_ARAT)) { 636 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 637 /* Make LAPIC timer preferrable over percpu HPET */ 638 lapic_clockevent.rating = 150; 639 } 640 641 memcpy(levt, &lapic_clockevent, sizeof(*levt)); 642 levt->cpumask = cpumask_of(smp_processor_id()); 643 644 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 645 levt->name = "lapic-deadline"; 646 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | 647 CLOCK_EVT_FEAT_DUMMY); 648 levt->set_next_event = lapic_next_deadline; 649 clockevents_config_and_register(levt, 650 tsc_khz * (1000 / TSC_DIVISOR), 651 0xF, ~0UL); 652 } else 653 clockevents_register_device(levt); 654 } 655 656 /* 657 * Install the updated TSC frequency from recalibration at the TSC 658 * deadline clockevent devices. 659 */ 660 static void __lapic_update_tsc_freq(void *info) 661 { 662 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 663 664 if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 665 return; 666 667 clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR)); 668 } 669 670 void lapic_update_tsc_freq(void) 671 { 672 /* 673 * The clockevent device's ->mult and ->shift can both be 674 * changed. In order to avoid races, schedule the frequency 675 * update code on each CPU. 676 */ 677 on_each_cpu(__lapic_update_tsc_freq, NULL, 0); 678 } 679 680 /* 681 * In this functions we calibrate APIC bus clocks to the external timer. 682 * 683 * We want to do the calibration only once since we want to have local timer 684 * irqs syncron. CPUs connected by the same APIC bus have the very same bus 685 * frequency. 686 * 687 * This was previously done by reading the PIT/HPET and waiting for a wrap 688 * around to find out, that a tick has elapsed. I have a box, where the PIT 689 * readout is broken, so it never gets out of the wait loop again. This was 690 * also reported by others. 691 * 692 * Monitoring the jiffies value is inaccurate and the clockevents 693 * infrastructure allows us to do a simple substitution of the interrupt 694 * handler. 695 * 696 * The calibration routine also uses the pm_timer when possible, as the PIT 697 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 698 * back to normal later in the boot process). 699 */ 700 701 #define LAPIC_CAL_LOOPS (HZ/10) 702 703 static __initdata int lapic_cal_loops = -1; 704 static __initdata long lapic_cal_t1, lapic_cal_t2; 705 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 706 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 707 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 708 709 /* 710 * Temporary interrupt handler. 711 */ 712 static void __init lapic_cal_handler(struct clock_event_device *dev) 713 { 714 unsigned long long tsc = 0; 715 long tapic = apic_read(APIC_TMCCT); 716 unsigned long pm = acpi_pm_read_early(); 717 718 if (boot_cpu_has(X86_FEATURE_TSC)) 719 tsc = rdtsc(); 720 721 switch (lapic_cal_loops++) { 722 case 0: 723 lapic_cal_t1 = tapic; 724 lapic_cal_tsc1 = tsc; 725 lapic_cal_pm1 = pm; 726 lapic_cal_j1 = jiffies; 727 break; 728 729 case LAPIC_CAL_LOOPS: 730 lapic_cal_t2 = tapic; 731 lapic_cal_tsc2 = tsc; 732 if (pm < lapic_cal_pm1) 733 pm += ACPI_PM_OVRRUN; 734 lapic_cal_pm2 = pm; 735 lapic_cal_j2 = jiffies; 736 break; 737 } 738 } 739 740 static int __init 741 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 742 { 743 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 744 const long pm_thresh = pm_100ms / 100; 745 unsigned long mult; 746 u64 res; 747 748 #ifndef CONFIG_X86_PM_TIMER 749 return -1; 750 #endif 751 752 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 753 754 /* Check, if the PM timer is available */ 755 if (!deltapm) 756 return -1; 757 758 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 759 760 if (deltapm > (pm_100ms - pm_thresh) && 761 deltapm < (pm_100ms + pm_thresh)) { 762 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 763 return 0; 764 } 765 766 res = (((u64)deltapm) * mult) >> 22; 767 do_div(res, 1000000); 768 pr_warning("APIC calibration not consistent " 769 "with PM-Timer: %ldms instead of 100ms\n",(long)res); 770 771 /* Correct the lapic counter value */ 772 res = (((u64)(*delta)) * pm_100ms); 773 do_div(res, deltapm); 774 pr_info("APIC delta adjusted to PM-Timer: " 775 "%lu (%ld)\n", (unsigned long)res, *delta); 776 *delta = (long)res; 777 778 /* Correct the tsc counter value */ 779 if (boot_cpu_has(X86_FEATURE_TSC)) { 780 res = (((u64)(*deltatsc)) * pm_100ms); 781 do_div(res, deltapm); 782 apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 783 "PM-Timer: %lu (%ld)\n", 784 (unsigned long)res, *deltatsc); 785 *deltatsc = (long)res; 786 } 787 788 return 0; 789 } 790 791 static int __init calibrate_APIC_clock(void) 792 { 793 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 794 void (*real_handler)(struct clock_event_device *dev); 795 unsigned long deltaj; 796 long delta, deltatsc; 797 int pm_referenced = 0; 798 799 /** 800 * check if lapic timer has already been calibrated by platform 801 * specific routine, such as tsc calibration code. if so, we just fill 802 * in the clockevent structure and return. 803 */ 804 805 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 806 return 0; 807 } else if (lapic_timer_frequency) { 808 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", 809 lapic_timer_frequency); 810 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR, 811 TICK_NSEC, lapic_clockevent.shift); 812 lapic_clockevent.max_delta_ns = 813 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); 814 lapic_clockevent.max_delta_ticks = 0x7FFFFF; 815 lapic_clockevent.min_delta_ns = 816 clockevent_delta2ns(0xF, &lapic_clockevent); 817 lapic_clockevent.min_delta_ticks = 0xF; 818 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 819 return 0; 820 } 821 822 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 823 "calibrating APIC timer ...\n"); 824 825 local_irq_disable(); 826 827 /* Replace the global interrupt handler */ 828 real_handler = global_clock_event->event_handler; 829 global_clock_event->event_handler = lapic_cal_handler; 830 831 /* 832 * Setup the APIC counter to maximum. There is no way the lapic 833 * can underflow in the 100ms detection time frame 834 */ 835 __setup_APIC_LVTT(0xffffffff, 0, 0); 836 837 /* Let the interrupts run */ 838 local_irq_enable(); 839 840 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 841 cpu_relax(); 842 843 local_irq_disable(); 844 845 /* Restore the real event handler */ 846 global_clock_event->event_handler = real_handler; 847 848 /* Build delta t1-t2 as apic timer counts down */ 849 delta = lapic_cal_t1 - lapic_cal_t2; 850 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 851 852 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 853 854 /* we trust the PM based calibration if possible */ 855 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 856 &delta, &deltatsc); 857 858 /* Calculate the scaled math multiplication factor */ 859 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 860 lapic_clockevent.shift); 861 lapic_clockevent.max_delta_ns = 862 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); 863 lapic_clockevent.max_delta_ticks = 0x7FFFFFFF; 864 lapic_clockevent.min_delta_ns = 865 clockevent_delta2ns(0xF, &lapic_clockevent); 866 lapic_clockevent.min_delta_ticks = 0xF; 867 868 lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 869 870 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 871 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); 872 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 873 lapic_timer_frequency); 874 875 if (boot_cpu_has(X86_FEATURE_TSC)) { 876 apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 877 "%ld.%04ld MHz.\n", 878 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 879 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 880 } 881 882 apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 883 "%u.%04u MHz.\n", 884 lapic_timer_frequency / (1000000 / HZ), 885 lapic_timer_frequency % (1000000 / HZ)); 886 887 /* 888 * Do a sanity check on the APIC calibration result 889 */ 890 if (lapic_timer_frequency < (1000000 / HZ)) { 891 local_irq_enable(); 892 pr_warning("APIC frequency too slow, disabling apic timer\n"); 893 return -1; 894 } 895 896 levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 897 898 /* 899 * PM timer calibration failed or not turned on 900 * so lets try APIC timer based calibration 901 */ 902 if (!pm_referenced) { 903 apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 904 905 /* 906 * Setup the apic timer manually 907 */ 908 levt->event_handler = lapic_cal_handler; 909 lapic_timer_set_periodic(levt); 910 lapic_cal_loops = -1; 911 912 /* Let the interrupts run */ 913 local_irq_enable(); 914 915 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 916 cpu_relax(); 917 918 /* Stop the lapic timer */ 919 local_irq_disable(); 920 lapic_timer_shutdown(levt); 921 922 /* Jiffies delta */ 923 deltaj = lapic_cal_j2 - lapic_cal_j1; 924 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 925 926 /* Check, if the jiffies result is consistent */ 927 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 928 apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 929 else 930 levt->features |= CLOCK_EVT_FEAT_DUMMY; 931 } 932 local_irq_enable(); 933 934 if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 935 pr_warning("APIC timer disabled due to verification failure\n"); 936 return -1; 937 } 938 939 return 0; 940 } 941 942 /* 943 * Setup the boot APIC 944 * 945 * Calibrate and verify the result. 946 */ 947 void __init setup_boot_APIC_clock(void) 948 { 949 /* 950 * The local apic timer can be disabled via the kernel 951 * commandline or from the CPU detection code. Register the lapic 952 * timer as a dummy clock event source on SMP systems, so the 953 * broadcast mechanism is used. On UP systems simply ignore it. 954 */ 955 if (disable_apic_timer) { 956 pr_info("Disabling APIC timer\n"); 957 /* No broadcast on UP ! */ 958 if (num_possible_cpus() > 1) { 959 lapic_clockevent.mult = 1; 960 setup_APIC_timer(); 961 } 962 return; 963 } 964 965 if (calibrate_APIC_clock()) { 966 /* No broadcast on UP ! */ 967 if (num_possible_cpus() > 1) 968 setup_APIC_timer(); 969 return; 970 } 971 972 /* 973 * If nmi_watchdog is set to IO_APIC, we need the 974 * PIT/HPET going. Otherwise register lapic as a dummy 975 * device. 976 */ 977 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 978 979 /* Setup the lapic or request the broadcast */ 980 setup_APIC_timer(); 981 amd_e400_c1e_apic_setup(); 982 } 983 984 void setup_secondary_APIC_clock(void) 985 { 986 setup_APIC_timer(); 987 amd_e400_c1e_apic_setup(); 988 } 989 990 /* 991 * The guts of the apic timer interrupt 992 */ 993 static void local_apic_timer_interrupt(void) 994 { 995 struct clock_event_device *evt = this_cpu_ptr(&lapic_events); 996 997 /* 998 * Normally we should not be here till LAPIC has been initialized but 999 * in some cases like kdump, its possible that there is a pending LAPIC 1000 * timer interrupt from previous kernel's context and is delivered in 1001 * new kernel the moment interrupts are enabled. 1002 * 1003 * Interrupts are enabled early and LAPIC is setup much later, hence 1004 * its possible that when we get here evt->event_handler is NULL. 1005 * Check for event_handler being NULL and discard the interrupt as 1006 * spurious. 1007 */ 1008 if (!evt->event_handler) { 1009 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", 1010 smp_processor_id()); 1011 /* Switch it off */ 1012 lapic_timer_shutdown(evt); 1013 return; 1014 } 1015 1016 /* 1017 * the NMI deadlock-detector uses this. 1018 */ 1019 inc_irq_stat(apic_timer_irqs); 1020 1021 evt->event_handler(evt); 1022 } 1023 1024 /* 1025 * Local APIC timer interrupt. This is the most natural way for doing 1026 * local interrupts, but local timer interrupts can be emulated by 1027 * broadcast interrupts too. [in case the hw doesn't support APIC timers] 1028 * 1029 * [ if a single-CPU system runs an SMP kernel then we call the local 1030 * interrupt as well. Thus we cannot inline the local irq ... ] 1031 */ 1032 __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) 1033 { 1034 struct pt_regs *old_regs = set_irq_regs(regs); 1035 1036 /* 1037 * NOTE! We'd better ACK the irq immediately, 1038 * because timer handling can be slow. 1039 * 1040 * update_process_times() expects us to have done irq_enter(). 1041 * Besides, if we don't timer interrupts ignore the global 1042 * interrupt lock, which is the WrongThing (tm) to do. 1043 */ 1044 entering_ack_irq(); 1045 trace_local_timer_entry(LOCAL_TIMER_VECTOR); 1046 local_apic_timer_interrupt(); 1047 trace_local_timer_exit(LOCAL_TIMER_VECTOR); 1048 exiting_irq(); 1049 1050 set_irq_regs(old_regs); 1051 } 1052 1053 int setup_profiling_timer(unsigned int multiplier) 1054 { 1055 return -EINVAL; 1056 } 1057 1058 /* 1059 * Local APIC start and shutdown 1060 */ 1061 1062 /** 1063 * clear_local_APIC - shutdown the local APIC 1064 * 1065 * This is called, when a CPU is disabled and before rebooting, so the state of 1066 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 1067 * leftovers during boot. 1068 */ 1069 void clear_local_APIC(void) 1070 { 1071 int maxlvt; 1072 u32 v; 1073 1074 /* APIC hasn't been mapped yet */ 1075 if (!x2apic_mode && !apic_phys) 1076 return; 1077 1078 maxlvt = lapic_get_maxlvt(); 1079 /* 1080 * Masking an LVT entry can trigger a local APIC error 1081 * if the vector is zero. Mask LVTERR first to prevent this. 1082 */ 1083 if (maxlvt >= 3) { 1084 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 1085 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 1086 } 1087 /* 1088 * Careful: we have to set masks only first to deassert 1089 * any level-triggered sources. 1090 */ 1091 v = apic_read(APIC_LVTT); 1092 apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 1093 v = apic_read(APIC_LVT0); 1094 apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 1095 v = apic_read(APIC_LVT1); 1096 apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 1097 if (maxlvt >= 4) { 1098 v = apic_read(APIC_LVTPC); 1099 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 1100 } 1101 1102 /* lets not touch this if we didn't frob it */ 1103 #ifdef CONFIG_X86_THERMAL_VECTOR 1104 if (maxlvt >= 5) { 1105 v = apic_read(APIC_LVTTHMR); 1106 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 1107 } 1108 #endif 1109 #ifdef CONFIG_X86_MCE_INTEL 1110 if (maxlvt >= 6) { 1111 v = apic_read(APIC_LVTCMCI); 1112 if (!(v & APIC_LVT_MASKED)) 1113 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 1114 } 1115 #endif 1116 1117 /* 1118 * Clean APIC state for other OSs: 1119 */ 1120 apic_write(APIC_LVTT, APIC_LVT_MASKED); 1121 apic_write(APIC_LVT0, APIC_LVT_MASKED); 1122 apic_write(APIC_LVT1, APIC_LVT_MASKED); 1123 if (maxlvt >= 3) 1124 apic_write(APIC_LVTERR, APIC_LVT_MASKED); 1125 if (maxlvt >= 4) 1126 apic_write(APIC_LVTPC, APIC_LVT_MASKED); 1127 1128 /* Integrated APIC (!82489DX) ? */ 1129 if (lapic_is_integrated()) { 1130 if (maxlvt > 3) 1131 /* Clear ESR due to Pentium errata 3AP and 11AP */ 1132 apic_write(APIC_ESR, 0); 1133 apic_read(APIC_ESR); 1134 } 1135 } 1136 1137 /** 1138 * disable_local_APIC - clear and disable the local APIC 1139 */ 1140 void disable_local_APIC(void) 1141 { 1142 unsigned int value; 1143 1144 /* APIC hasn't been mapped yet */ 1145 if (!x2apic_mode && !apic_phys) 1146 return; 1147 1148 clear_local_APIC(); 1149 1150 /* 1151 * Disable APIC (implies clearing of registers 1152 * for 82489DX!). 1153 */ 1154 value = apic_read(APIC_SPIV); 1155 value &= ~APIC_SPIV_APIC_ENABLED; 1156 apic_write(APIC_SPIV, value); 1157 1158 #ifdef CONFIG_X86_32 1159 /* 1160 * When LAPIC was disabled by the BIOS and enabled by the kernel, 1161 * restore the disabled state. 1162 */ 1163 if (enabled_via_apicbase) { 1164 unsigned int l, h; 1165 1166 rdmsr(MSR_IA32_APICBASE, l, h); 1167 l &= ~MSR_IA32_APICBASE_ENABLE; 1168 wrmsr(MSR_IA32_APICBASE, l, h); 1169 } 1170 #endif 1171 } 1172 1173 /* 1174 * If Linux enabled the LAPIC against the BIOS default disable it down before 1175 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 1176 * not power-off. Additionally clear all LVT entries before disable_local_APIC 1177 * for the case where Linux didn't enable the LAPIC. 1178 */ 1179 void lapic_shutdown(void) 1180 { 1181 unsigned long flags; 1182 1183 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) 1184 return; 1185 1186 local_irq_save(flags); 1187 1188 #ifdef CONFIG_X86_32 1189 if (!enabled_via_apicbase) 1190 clear_local_APIC(); 1191 else 1192 #endif 1193 disable_local_APIC(); 1194 1195 1196 local_irq_restore(flags); 1197 } 1198 1199 /** 1200 * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1201 */ 1202 void __init sync_Arb_IDs(void) 1203 { 1204 /* 1205 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1206 * needed on AMD. 1207 */ 1208 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1209 return; 1210 1211 /* 1212 * Wait for idle. 1213 */ 1214 apic_wait_icr_idle(); 1215 1216 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1217 apic_write(APIC_ICR, APIC_DEST_ALLINC | 1218 APIC_INT_LEVELTRIG | APIC_DM_INIT); 1219 } 1220 1221 /* 1222 * An initial setup of the virtual wire mode. 1223 */ 1224 void __init init_bsp_APIC(void) 1225 { 1226 unsigned int value; 1227 1228 /* 1229 * Don't do the setup now if we have a SMP BIOS as the 1230 * through-I/O-APIC virtual wire mode might be active. 1231 */ 1232 if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC)) 1233 return; 1234 1235 /* 1236 * Do not trust the local APIC being empty at bootup. 1237 */ 1238 clear_local_APIC(); 1239 1240 /* 1241 * Enable APIC. 1242 */ 1243 value = apic_read(APIC_SPIV); 1244 value &= ~APIC_VECTOR_MASK; 1245 value |= APIC_SPIV_APIC_ENABLED; 1246 1247 #ifdef CONFIG_X86_32 1248 /* This bit is reserved on P4/Xeon and should be cleared */ 1249 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1250 (boot_cpu_data.x86 == 15)) 1251 value &= ~APIC_SPIV_FOCUS_DISABLED; 1252 else 1253 #endif 1254 value |= APIC_SPIV_FOCUS_DISABLED; 1255 value |= SPURIOUS_APIC_VECTOR; 1256 apic_write(APIC_SPIV, value); 1257 1258 /* 1259 * Set up the virtual wire mode. 1260 */ 1261 apic_write(APIC_LVT0, APIC_DM_EXTINT); 1262 value = APIC_DM_NMI; 1263 if (!lapic_is_integrated()) /* 82489DX */ 1264 value |= APIC_LVT_LEVEL_TRIGGER; 1265 if (apic_extnmi == APIC_EXTNMI_NONE) 1266 value |= APIC_LVT_MASKED; 1267 apic_write(APIC_LVT1, value); 1268 } 1269 1270 static void lapic_setup_esr(void) 1271 { 1272 unsigned int oldvalue, value, maxlvt; 1273 1274 if (!lapic_is_integrated()) { 1275 pr_info("No ESR for 82489DX.\n"); 1276 return; 1277 } 1278 1279 if (apic->disable_esr) { 1280 /* 1281 * Something untraceable is creating bad interrupts on 1282 * secondary quads ... for the moment, just leave the 1283 * ESR disabled - we can't do anything useful with the 1284 * errors anyway - mbligh 1285 */ 1286 pr_info("Leaving ESR disabled.\n"); 1287 return; 1288 } 1289 1290 maxlvt = lapic_get_maxlvt(); 1291 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1292 apic_write(APIC_ESR, 0); 1293 oldvalue = apic_read(APIC_ESR); 1294 1295 /* enables sending errors */ 1296 value = ERROR_APIC_VECTOR; 1297 apic_write(APIC_LVTERR, value); 1298 1299 /* 1300 * spec says clear errors after enabling vector. 1301 */ 1302 if (maxlvt > 3) 1303 apic_write(APIC_ESR, 0); 1304 value = apic_read(APIC_ESR); 1305 if (value != oldvalue) 1306 apic_printk(APIC_VERBOSE, "ESR value before enabling " 1307 "vector: 0x%08x after: 0x%08x\n", 1308 oldvalue, value); 1309 } 1310 1311 /** 1312 * setup_local_APIC - setup the local APIC 1313 * 1314 * Used to setup local APIC while initializing BSP or bringing up APs. 1315 * Always called with preemption disabled. 1316 */ 1317 void setup_local_APIC(void) 1318 { 1319 int cpu = smp_processor_id(); 1320 unsigned int value, queued; 1321 int i, j, acked = 0; 1322 unsigned long long tsc = 0, ntsc; 1323 long long max_loops = cpu_khz ? cpu_khz : 1000000; 1324 1325 if (boot_cpu_has(X86_FEATURE_TSC)) 1326 tsc = rdtsc(); 1327 1328 if (disable_apic) { 1329 disable_ioapic_support(); 1330 return; 1331 } 1332 1333 #ifdef CONFIG_X86_32 1334 /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1335 if (lapic_is_integrated() && apic->disable_esr) { 1336 apic_write(APIC_ESR, 0); 1337 apic_write(APIC_ESR, 0); 1338 apic_write(APIC_ESR, 0); 1339 apic_write(APIC_ESR, 0); 1340 } 1341 #endif 1342 perf_events_lapic_init(); 1343 1344 /* 1345 * Double-check whether this APIC is really registered. 1346 * This is meaningless in clustered apic mode, so we skip it. 1347 */ 1348 BUG_ON(!apic->apic_id_registered()); 1349 1350 /* 1351 * Intel recommends to set DFR, LDR and TPR before enabling 1352 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1353 * document number 292116). So here it goes... 1354 */ 1355 apic->init_apic_ldr(); 1356 1357 #ifdef CONFIG_X86_32 1358 /* 1359 * APIC LDR is initialized. If logical_apicid mapping was 1360 * initialized during get_smp_config(), make sure it matches the 1361 * actual value. 1362 */ 1363 i = early_per_cpu(x86_cpu_to_logical_apicid, cpu); 1364 WARN_ON(i != BAD_APICID && i != logical_smp_processor_id()); 1365 /* always use the value from LDR */ 1366 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 1367 logical_smp_processor_id(); 1368 #endif 1369 1370 /* 1371 * Set Task Priority to 'accept all'. We never change this 1372 * later on. 1373 */ 1374 value = apic_read(APIC_TASKPRI); 1375 value &= ~APIC_TPRI_MASK; 1376 apic_write(APIC_TASKPRI, value); 1377 1378 /* 1379 * After a crash, we no longer service the interrupts and a pending 1380 * interrupt from previous kernel might still have ISR bit set. 1381 * 1382 * Most probably by now CPU has serviced that pending interrupt and 1383 * it might not have done the ack_APIC_irq() because it thought, 1384 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it 1385 * does not clear the ISR bit and cpu thinks it has already serivced 1386 * the interrupt. Hence a vector might get locked. It was noticed 1387 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. 1388 */ 1389 do { 1390 queued = 0; 1391 for (i = APIC_ISR_NR - 1; i >= 0; i--) 1392 queued |= apic_read(APIC_IRR + i*0x10); 1393 1394 for (i = APIC_ISR_NR - 1; i >= 0; i--) { 1395 value = apic_read(APIC_ISR + i*0x10); 1396 for (j = 31; j >= 0; j--) { 1397 if (value & (1<<j)) { 1398 ack_APIC_irq(); 1399 acked++; 1400 } 1401 } 1402 } 1403 if (acked > 256) { 1404 printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n", 1405 acked); 1406 break; 1407 } 1408 if (queued) { 1409 if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) { 1410 ntsc = rdtsc(); 1411 max_loops = (cpu_khz << 10) - (ntsc - tsc); 1412 } else 1413 max_loops--; 1414 } 1415 } while (queued && max_loops > 0); 1416 WARN_ON(max_loops <= 0); 1417 1418 /* 1419 * Now that we are all set up, enable the APIC 1420 */ 1421 value = apic_read(APIC_SPIV); 1422 value &= ~APIC_VECTOR_MASK; 1423 /* 1424 * Enable APIC 1425 */ 1426 value |= APIC_SPIV_APIC_ENABLED; 1427 1428 #ifdef CONFIG_X86_32 1429 /* 1430 * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1431 * certain networking cards. If high frequency interrupts are 1432 * happening on a particular IOAPIC pin, plus the IOAPIC routing 1433 * entry is masked/unmasked at a high rate as well then sooner or 1434 * later IOAPIC line gets 'stuck', no more interrupts are received 1435 * from the device. If focus CPU is disabled then the hang goes 1436 * away, oh well :-( 1437 * 1438 * [ This bug can be reproduced easily with a level-triggered 1439 * PCI Ne2000 networking cards and PII/PIII processors, dual 1440 * BX chipset. ] 1441 */ 1442 /* 1443 * Actually disabling the focus CPU check just makes the hang less 1444 * frequent as it makes the interrupt distributon model be more 1445 * like LRU than MRU (the short-term load is more even across CPUs). 1446 */ 1447 1448 /* 1449 * - enable focus processor (bit==0) 1450 * - 64bit mode always use processor focus 1451 * so no need to set it 1452 */ 1453 value &= ~APIC_SPIV_FOCUS_DISABLED; 1454 #endif 1455 1456 /* 1457 * Set spurious IRQ vector 1458 */ 1459 value |= SPURIOUS_APIC_VECTOR; 1460 apic_write(APIC_SPIV, value); 1461 1462 /* 1463 * Set up LVT0, LVT1: 1464 * 1465 * set up through-local-APIC on the BP's LINT0. This is not 1466 * strictly necessary in pure symmetric-IO mode, but sometimes 1467 * we delegate interrupts to the 8259A. 1468 */ 1469 /* 1470 * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1471 */ 1472 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 1473 if (!cpu && (pic_mode || !value)) { 1474 value = APIC_DM_EXTINT; 1475 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); 1476 } else { 1477 value = APIC_DM_EXTINT | APIC_LVT_MASKED; 1478 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); 1479 } 1480 apic_write(APIC_LVT0, value); 1481 1482 /* 1483 * Only the BSP sees the LINT1 NMI signal by default. This can be 1484 * modified by apic_extnmi= boot option. 1485 */ 1486 if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) || 1487 apic_extnmi == APIC_EXTNMI_ALL) 1488 value = APIC_DM_NMI; 1489 else 1490 value = APIC_DM_NMI | APIC_LVT_MASKED; 1491 if (!lapic_is_integrated()) /* 82489DX */ 1492 value |= APIC_LVT_LEVEL_TRIGGER; 1493 apic_write(APIC_LVT1, value); 1494 1495 #ifdef CONFIG_X86_MCE_INTEL 1496 /* Recheck CMCI information after local APIC is up on CPU #0 */ 1497 if (!cpu) 1498 cmci_recheck(); 1499 #endif 1500 } 1501 1502 static void end_local_APIC_setup(void) 1503 { 1504 lapic_setup_esr(); 1505 1506 #ifdef CONFIG_X86_32 1507 { 1508 unsigned int value; 1509 /* Disable the local apic timer */ 1510 value = apic_read(APIC_LVTT); 1511 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1512 apic_write(APIC_LVTT, value); 1513 } 1514 #endif 1515 1516 apic_pm_activate(); 1517 } 1518 1519 /* 1520 * APIC setup function for application processors. Called from smpboot.c 1521 */ 1522 void apic_ap_setup(void) 1523 { 1524 setup_local_APIC(); 1525 end_local_APIC_setup(); 1526 } 1527 1528 #ifdef CONFIG_X86_X2APIC 1529 int x2apic_mode; 1530 1531 enum { 1532 X2APIC_OFF, 1533 X2APIC_ON, 1534 X2APIC_DISABLED, 1535 }; 1536 static int x2apic_state; 1537 1538 static void __x2apic_disable(void) 1539 { 1540 u64 msr; 1541 1542 if (!boot_cpu_has(X86_FEATURE_APIC)) 1543 return; 1544 1545 rdmsrl(MSR_IA32_APICBASE, msr); 1546 if (!(msr & X2APIC_ENABLE)) 1547 return; 1548 /* Disable xapic and x2apic first and then reenable xapic mode */ 1549 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); 1550 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); 1551 printk_once(KERN_INFO "x2apic disabled\n"); 1552 } 1553 1554 static void __x2apic_enable(void) 1555 { 1556 u64 msr; 1557 1558 rdmsrl(MSR_IA32_APICBASE, msr); 1559 if (msr & X2APIC_ENABLE) 1560 return; 1561 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); 1562 printk_once(KERN_INFO "x2apic enabled\n"); 1563 } 1564 1565 static int __init setup_nox2apic(char *str) 1566 { 1567 if (x2apic_enabled()) { 1568 int apicid = native_apic_msr_read(APIC_ID); 1569 1570 if (apicid >= 255) { 1571 pr_warning("Apicid: %08x, cannot enforce nox2apic\n", 1572 apicid); 1573 return 0; 1574 } 1575 pr_warning("x2apic already enabled.\n"); 1576 __x2apic_disable(); 1577 } 1578 setup_clear_cpu_cap(X86_FEATURE_X2APIC); 1579 x2apic_state = X2APIC_DISABLED; 1580 x2apic_mode = 0; 1581 return 0; 1582 } 1583 early_param("nox2apic", setup_nox2apic); 1584 1585 /* Called from cpu_init() to enable x2apic on (secondary) cpus */ 1586 void x2apic_setup(void) 1587 { 1588 /* 1589 * If x2apic is not in ON state, disable it if already enabled 1590 * from BIOS. 1591 */ 1592 if (x2apic_state != X2APIC_ON) { 1593 __x2apic_disable(); 1594 return; 1595 } 1596 __x2apic_enable(); 1597 } 1598 1599 static __init void x2apic_disable(void) 1600 { 1601 u32 x2apic_id, state = x2apic_state; 1602 1603 x2apic_mode = 0; 1604 x2apic_state = X2APIC_DISABLED; 1605 1606 if (state != X2APIC_ON) 1607 return; 1608 1609 x2apic_id = read_apic_id(); 1610 if (x2apic_id >= 255) 1611 panic("Cannot disable x2apic, id: %08x\n", x2apic_id); 1612 1613 __x2apic_disable(); 1614 register_lapic_address(mp_lapic_addr); 1615 } 1616 1617 static __init void x2apic_enable(void) 1618 { 1619 if (x2apic_state != X2APIC_OFF) 1620 return; 1621 1622 x2apic_mode = 1; 1623 x2apic_state = X2APIC_ON; 1624 __x2apic_enable(); 1625 } 1626 1627 static __init void try_to_enable_x2apic(int remap_mode) 1628 { 1629 if (x2apic_state == X2APIC_DISABLED) 1630 return; 1631 1632 if (remap_mode != IRQ_REMAP_X2APIC_MODE) { 1633 /* IR is required if there is APIC ID > 255 even when running 1634 * under KVM 1635 */ 1636 if (max_physical_apicid > 255 || 1637 !hypervisor_x2apic_available()) { 1638 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n"); 1639 x2apic_disable(); 1640 return; 1641 } 1642 1643 /* 1644 * without IR all CPUs can be addressed by IOAPIC/MSI 1645 * only in physical mode 1646 */ 1647 x2apic_phys = 1; 1648 } 1649 x2apic_enable(); 1650 } 1651 1652 void __init check_x2apic(void) 1653 { 1654 if (x2apic_enabled()) { 1655 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n"); 1656 x2apic_mode = 1; 1657 x2apic_state = X2APIC_ON; 1658 } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) { 1659 x2apic_state = X2APIC_DISABLED; 1660 } 1661 } 1662 #else /* CONFIG_X86_X2APIC */ 1663 static int __init validate_x2apic(void) 1664 { 1665 if (!apic_is_x2apic_enabled()) 1666 return 0; 1667 /* 1668 * Checkme: Can we simply turn off x2apic here instead of panic? 1669 */ 1670 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n"); 1671 } 1672 early_initcall(validate_x2apic); 1673 1674 static inline void try_to_enable_x2apic(int remap_mode) { } 1675 static inline void __x2apic_enable(void) { } 1676 #endif /* !CONFIG_X86_X2APIC */ 1677 1678 void __init enable_IR_x2apic(void) 1679 { 1680 unsigned long flags; 1681 int ret, ir_stat; 1682 1683 if (skip_ioapic_setup) { 1684 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n"); 1685 return; 1686 } 1687 1688 ir_stat = irq_remapping_prepare(); 1689 if (ir_stat < 0 && !x2apic_supported()) 1690 return; 1691 1692 ret = save_ioapic_entries(); 1693 if (ret) { 1694 pr_info("Saving IO-APIC state failed: %d\n", ret); 1695 return; 1696 } 1697 1698 local_irq_save(flags); 1699 legacy_pic->mask_all(); 1700 mask_ioapic_entries(); 1701 1702 /* If irq_remapping_prepare() succeeded, try to enable it */ 1703 if (ir_stat >= 0) 1704 ir_stat = irq_remapping_enable(); 1705 /* ir_stat contains the remap mode or an error code */ 1706 try_to_enable_x2apic(ir_stat); 1707 1708 if (ir_stat < 0) 1709 restore_ioapic_entries(); 1710 legacy_pic->restore_mask(); 1711 local_irq_restore(flags); 1712 } 1713 1714 #ifdef CONFIG_X86_64 1715 /* 1716 * Detect and enable local APICs on non-SMP boards. 1717 * Original code written by Keir Fraser. 1718 * On AMD64 we trust the BIOS - if it says no APIC it is likely 1719 * not correctly set up (usually the APIC timer won't work etc.) 1720 */ 1721 static int __init detect_init_APIC(void) 1722 { 1723 if (!boot_cpu_has(X86_FEATURE_APIC)) { 1724 pr_info("No local APIC present\n"); 1725 return -1; 1726 } 1727 1728 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1729 return 0; 1730 } 1731 #else 1732 1733 static int __init apic_verify(void) 1734 { 1735 u32 features, h, l; 1736 1737 /* 1738 * The APIC feature bit should now be enabled 1739 * in `cpuid' 1740 */ 1741 features = cpuid_edx(1); 1742 if (!(features & (1 << X86_FEATURE_APIC))) { 1743 pr_warning("Could not enable APIC!\n"); 1744 return -1; 1745 } 1746 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 1747 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1748 1749 /* The BIOS may have set up the APIC at some other address */ 1750 if (boot_cpu_data.x86 >= 6) { 1751 rdmsr(MSR_IA32_APICBASE, l, h); 1752 if (l & MSR_IA32_APICBASE_ENABLE) 1753 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 1754 } 1755 1756 pr_info("Found and enabled local APIC!\n"); 1757 return 0; 1758 } 1759 1760 int __init apic_force_enable(unsigned long addr) 1761 { 1762 u32 h, l; 1763 1764 if (disable_apic) 1765 return -1; 1766 1767 /* 1768 * Some BIOSes disable the local APIC in the APIC_BASE 1769 * MSR. This can only be done in software for Intel P6 or later 1770 * and AMD K7 (Model > 1) or later. 1771 */ 1772 if (boot_cpu_data.x86 >= 6) { 1773 rdmsr(MSR_IA32_APICBASE, l, h); 1774 if (!(l & MSR_IA32_APICBASE_ENABLE)) { 1775 pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 1776 l &= ~MSR_IA32_APICBASE_BASE; 1777 l |= MSR_IA32_APICBASE_ENABLE | addr; 1778 wrmsr(MSR_IA32_APICBASE, l, h); 1779 enabled_via_apicbase = 1; 1780 } 1781 } 1782 return apic_verify(); 1783 } 1784 1785 /* 1786 * Detect and initialize APIC 1787 */ 1788 static int __init detect_init_APIC(void) 1789 { 1790 /* Disabled by kernel option? */ 1791 if (disable_apic) 1792 return -1; 1793 1794 switch (boot_cpu_data.x86_vendor) { 1795 case X86_VENDOR_AMD: 1796 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 1797 (boot_cpu_data.x86 >= 15)) 1798 break; 1799 goto no_apic; 1800 case X86_VENDOR_INTEL: 1801 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 1802 (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC))) 1803 break; 1804 goto no_apic; 1805 default: 1806 goto no_apic; 1807 } 1808 1809 if (!boot_cpu_has(X86_FEATURE_APIC)) { 1810 /* 1811 * Over-ride BIOS and try to enable the local APIC only if 1812 * "lapic" specified. 1813 */ 1814 if (!force_enable_local_apic) { 1815 pr_info("Local APIC disabled by BIOS -- " 1816 "you can enable it with \"lapic\"\n"); 1817 return -1; 1818 } 1819 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) 1820 return -1; 1821 } else { 1822 if (apic_verify()) 1823 return -1; 1824 } 1825 1826 apic_pm_activate(); 1827 1828 return 0; 1829 1830 no_apic: 1831 pr_info("No local APIC present or hardware disabled\n"); 1832 return -1; 1833 } 1834 #endif 1835 1836 /** 1837 * init_apic_mappings - initialize APIC mappings 1838 */ 1839 void __init init_apic_mappings(void) 1840 { 1841 unsigned int new_apicid; 1842 1843 apic_check_deadline_errata(); 1844 1845 if (x2apic_mode) { 1846 boot_cpu_physical_apicid = read_apic_id(); 1847 return; 1848 } 1849 1850 /* If no local APIC can be found return early */ 1851 if (!smp_found_config && detect_init_APIC()) { 1852 /* lets NOP'ify apic operations */ 1853 pr_info("APIC: disable apic facility\n"); 1854 apic_disable(); 1855 } else { 1856 apic_phys = mp_lapic_addr; 1857 1858 /* 1859 * If the system has ACPI MADT tables or MP info, the LAPIC 1860 * address is already registered. 1861 */ 1862 if (!acpi_lapic && !smp_found_config) 1863 register_lapic_address(apic_phys); 1864 } 1865 1866 /* 1867 * Fetch the APIC ID of the BSP in case we have a 1868 * default configuration (or the MP table is broken). 1869 */ 1870 new_apicid = read_apic_id(); 1871 if (boot_cpu_physical_apicid != new_apicid) { 1872 boot_cpu_physical_apicid = new_apicid; 1873 /* 1874 * yeah -- we lie about apic_version 1875 * in case if apic was disabled via boot option 1876 * but it's not a problem for SMP compiled kernel 1877 * since smp_sanity_check is prepared for such a case 1878 * and disable smp mode 1879 */ 1880 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 1881 } 1882 } 1883 1884 void __init register_lapic_address(unsigned long address) 1885 { 1886 mp_lapic_addr = address; 1887 1888 if (!x2apic_mode) { 1889 set_fixmap_nocache(FIX_APIC_BASE, address); 1890 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 1891 APIC_BASE, address); 1892 } 1893 if (boot_cpu_physical_apicid == -1U) { 1894 boot_cpu_physical_apicid = read_apic_id(); 1895 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 1896 } 1897 } 1898 1899 /* 1900 * Local APIC interrupts 1901 */ 1902 1903 /* 1904 * This interrupt should _never_ happen with our APIC/SMP architecture 1905 */ 1906 __visible void __irq_entry smp_spurious_interrupt(struct pt_regs *regs) 1907 { 1908 u8 vector = ~regs->orig_ax; 1909 u32 v; 1910 1911 entering_irq(); 1912 trace_spurious_apic_entry(vector); 1913 1914 /* 1915 * Check if this really is a spurious interrupt and ACK it 1916 * if it is a vectored one. Just in case... 1917 * Spurious interrupts should not be ACKed. 1918 */ 1919 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1)); 1920 if (v & (1 << (vector & 0x1f))) 1921 ack_APIC_irq(); 1922 1923 inc_irq_stat(irq_spurious_count); 1924 1925 /* see sw-dev-man vol 3, chapter 7.4.13.5 */ 1926 pr_info("spurious APIC interrupt through vector %02x on CPU#%d, " 1927 "should never happen.\n", vector, smp_processor_id()); 1928 1929 trace_spurious_apic_exit(vector); 1930 exiting_irq(); 1931 } 1932 1933 /* 1934 * This interrupt should never happen with our APIC/SMP architecture 1935 */ 1936 __visible void __irq_entry smp_error_interrupt(struct pt_regs *regs) 1937 { 1938 static const char * const error_interrupt_reason[] = { 1939 "Send CS error", /* APIC Error Bit 0 */ 1940 "Receive CS error", /* APIC Error Bit 1 */ 1941 "Send accept error", /* APIC Error Bit 2 */ 1942 "Receive accept error", /* APIC Error Bit 3 */ 1943 "Redirectable IPI", /* APIC Error Bit 4 */ 1944 "Send illegal vector", /* APIC Error Bit 5 */ 1945 "Received illegal vector", /* APIC Error Bit 6 */ 1946 "Illegal register address", /* APIC Error Bit 7 */ 1947 }; 1948 u32 v, i = 0; 1949 1950 entering_irq(); 1951 trace_error_apic_entry(ERROR_APIC_VECTOR); 1952 1953 /* First tickle the hardware, only then report what went on. -- REW */ 1954 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */ 1955 apic_write(APIC_ESR, 0); 1956 v = apic_read(APIC_ESR); 1957 ack_APIC_irq(); 1958 atomic_inc(&irq_err_count); 1959 1960 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x", 1961 smp_processor_id(), v); 1962 1963 v &= 0xff; 1964 while (v) { 1965 if (v & 0x1) 1966 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); 1967 i++; 1968 v >>= 1; 1969 } 1970 1971 apic_printk(APIC_DEBUG, KERN_CONT "\n"); 1972 1973 trace_error_apic_exit(ERROR_APIC_VECTOR); 1974 exiting_irq(); 1975 } 1976 1977 /** 1978 * connect_bsp_APIC - attach the APIC to the interrupt system 1979 */ 1980 static void __init connect_bsp_APIC(void) 1981 { 1982 #ifdef CONFIG_X86_32 1983 if (pic_mode) { 1984 /* 1985 * Do not trust the local APIC being empty at bootup. 1986 */ 1987 clear_local_APIC(); 1988 /* 1989 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 1990 * local APIC to INT and NMI lines. 1991 */ 1992 apic_printk(APIC_VERBOSE, "leaving PIC mode, " 1993 "enabling APIC mode.\n"); 1994 imcr_pic_to_apic(); 1995 } 1996 #endif 1997 } 1998 1999 /** 2000 * disconnect_bsp_APIC - detach the APIC from the interrupt system 2001 * @virt_wire_setup: indicates, whether virtual wire mode is selected 2002 * 2003 * Virtual wire mode is necessary to deliver legacy interrupts even when the 2004 * APIC is disabled. 2005 */ 2006 void disconnect_bsp_APIC(int virt_wire_setup) 2007 { 2008 unsigned int value; 2009 2010 #ifdef CONFIG_X86_32 2011 if (pic_mode) { 2012 /* 2013 * Put the board back into PIC mode (has an effect only on 2014 * certain older boards). Note that APIC interrupts, including 2015 * IPIs, won't work beyond this point! The only exception are 2016 * INIT IPIs. 2017 */ 2018 apic_printk(APIC_VERBOSE, "disabling APIC mode, " 2019 "entering PIC mode.\n"); 2020 imcr_apic_to_pic(); 2021 return; 2022 } 2023 #endif 2024 2025 /* Go back to Virtual Wire compatibility mode */ 2026 2027 /* For the spurious interrupt use vector F, and enable it */ 2028 value = apic_read(APIC_SPIV); 2029 value &= ~APIC_VECTOR_MASK; 2030 value |= APIC_SPIV_APIC_ENABLED; 2031 value |= 0xf; 2032 apic_write(APIC_SPIV, value); 2033 2034 if (!virt_wire_setup) { 2035 /* 2036 * For LVT0 make it edge triggered, active high, 2037 * external and enabled 2038 */ 2039 value = apic_read(APIC_LVT0); 2040 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2041 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2042 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2043 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2044 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 2045 apic_write(APIC_LVT0, value); 2046 } else { 2047 /* Disable LVT0 */ 2048 apic_write(APIC_LVT0, APIC_LVT_MASKED); 2049 } 2050 2051 /* 2052 * For LVT1 make it edge triggered, active high, 2053 * nmi and enabled 2054 */ 2055 value = apic_read(APIC_LVT1); 2056 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2057 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2058 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2059 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2060 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 2061 apic_write(APIC_LVT1, value); 2062 } 2063 2064 /* 2065 * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated 2066 * contiguously, it equals to current allocated max logical CPU ID plus 1. 2067 * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range, 2068 * so the maximum of nr_logical_cpuids is nr_cpu_ids. 2069 * 2070 * NOTE: Reserve 0 for BSP. 2071 */ 2072 static int nr_logical_cpuids = 1; 2073 2074 /* 2075 * Used to store mapping between logical CPU IDs and APIC IDs. 2076 */ 2077 static int cpuid_to_apicid[] = { 2078 [0 ... NR_CPUS - 1] = -1, 2079 }; 2080 2081 /* 2082 * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids 2083 * and cpuid_to_apicid[] synchronized. 2084 */ 2085 static int allocate_logical_cpuid(int apicid) 2086 { 2087 int i; 2088 2089 /* 2090 * cpuid <-> apicid mapping is persistent, so when a cpu is up, 2091 * check if the kernel has allocated a cpuid for it. 2092 */ 2093 for (i = 0; i < nr_logical_cpuids; i++) { 2094 if (cpuid_to_apicid[i] == apicid) 2095 return i; 2096 } 2097 2098 /* Allocate a new cpuid. */ 2099 if (nr_logical_cpuids >= nr_cpu_ids) { 2100 WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. " 2101 "Processor %d/0x%x and the rest are ignored.\n", 2102 nr_cpu_ids, nr_logical_cpuids, apicid); 2103 return -EINVAL; 2104 } 2105 2106 cpuid_to_apicid[nr_logical_cpuids] = apicid; 2107 return nr_logical_cpuids++; 2108 } 2109 2110 int generic_processor_info(int apicid, int version) 2111 { 2112 int cpu, max = nr_cpu_ids; 2113 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, 2114 phys_cpu_present_map); 2115 2116 /* 2117 * boot_cpu_physical_apicid is designed to have the apicid 2118 * returned by read_apic_id(), i.e, the apicid of the 2119 * currently booting-up processor. However, on some platforms, 2120 * it is temporarily modified by the apicid reported as BSP 2121 * through MP table. Concretely: 2122 * 2123 * - arch/x86/kernel/mpparse.c: MP_processor_info() 2124 * - arch/x86/mm/amdtopology.c: amd_numa_init() 2125 * 2126 * This function is executed with the modified 2127 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel 2128 * parameter doesn't work to disable APs on kdump 2nd kernel. 2129 * 2130 * Since fixing handling of boot_cpu_physical_apicid requires 2131 * another discussion and tests on each platform, we leave it 2132 * for now and here we use read_apic_id() directly in this 2133 * function, generic_processor_info(). 2134 */ 2135 if (disabled_cpu_apicid != BAD_APICID && 2136 disabled_cpu_apicid != read_apic_id() && 2137 disabled_cpu_apicid == apicid) { 2138 int thiscpu = num_processors + disabled_cpus; 2139 2140 pr_warning("APIC: Disabling requested cpu." 2141 " Processor %d/0x%x ignored.\n", 2142 thiscpu, apicid); 2143 2144 disabled_cpus++; 2145 return -ENODEV; 2146 } 2147 2148 /* 2149 * If boot cpu has not been detected yet, then only allow upto 2150 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu 2151 */ 2152 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && 2153 apicid != boot_cpu_physical_apicid) { 2154 int thiscpu = max + disabled_cpus - 1; 2155 2156 pr_warning( 2157 "APIC: NR_CPUS/possible_cpus limit of %i almost" 2158 " reached. Keeping one slot for boot cpu." 2159 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 2160 2161 disabled_cpus++; 2162 return -ENODEV; 2163 } 2164 2165 if (num_processors >= nr_cpu_ids) { 2166 int thiscpu = max + disabled_cpus; 2167 2168 pr_warning("APIC: NR_CPUS/possible_cpus limit of %i " 2169 "reached. Processor %d/0x%x ignored.\n", 2170 max, thiscpu, apicid); 2171 2172 disabled_cpus++; 2173 return -EINVAL; 2174 } 2175 2176 if (apicid == boot_cpu_physical_apicid) { 2177 /* 2178 * x86_bios_cpu_apicid is required to have processors listed 2179 * in same order as logical cpu numbers. Hence the first 2180 * entry is BSP, and so on. 2181 * boot_cpu_init() already hold bit 0 in cpu_present_mask 2182 * for BSP. 2183 */ 2184 cpu = 0; 2185 2186 /* Logical cpuid 0 is reserved for BSP. */ 2187 cpuid_to_apicid[0] = apicid; 2188 } else { 2189 cpu = allocate_logical_cpuid(apicid); 2190 if (cpu < 0) { 2191 disabled_cpus++; 2192 return -EINVAL; 2193 } 2194 } 2195 2196 /* 2197 * Validate version 2198 */ 2199 if (version == 0x0) { 2200 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", 2201 cpu, apicid); 2202 version = 0x10; 2203 } 2204 2205 if (version != boot_cpu_apic_version) { 2206 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", 2207 boot_cpu_apic_version, cpu, version); 2208 } 2209 2210 if (apicid > max_physical_apicid) 2211 max_physical_apicid = apicid; 2212 2213 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 2214 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 2215 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 2216 #endif 2217 #ifdef CONFIG_X86_32 2218 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 2219 apic->x86_32_early_logical_apicid(cpu); 2220 #endif 2221 set_cpu_possible(cpu, true); 2222 physid_set(apicid, phys_cpu_present_map); 2223 set_cpu_present(cpu, true); 2224 num_processors++; 2225 2226 return cpu; 2227 } 2228 2229 int hard_smp_processor_id(void) 2230 { 2231 return read_apic_id(); 2232 } 2233 2234 void default_init_apic_ldr(void) 2235 { 2236 unsigned long val; 2237 2238 apic_write(APIC_DFR, APIC_DFR_VALUE); 2239 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; 2240 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); 2241 apic_write(APIC_LDR, val); 2242 } 2243 2244 int default_cpu_mask_to_apicid(const struct cpumask *mask, 2245 struct irq_data *irqdata, 2246 unsigned int *apicid) 2247 { 2248 unsigned int cpu = cpumask_first(mask); 2249 2250 if (cpu >= nr_cpu_ids) 2251 return -EINVAL; 2252 *apicid = per_cpu(x86_cpu_to_apicid, cpu); 2253 irq_data_update_effective_affinity(irqdata, cpumask_of(cpu)); 2254 return 0; 2255 } 2256 2257 int flat_cpu_mask_to_apicid(const struct cpumask *mask, 2258 struct irq_data *irqdata, 2259 unsigned int *apicid) 2260 2261 { 2262 struct cpumask *effmsk = irq_data_get_effective_affinity_mask(irqdata); 2263 unsigned long cpu_mask = cpumask_bits(mask)[0] & APIC_ALL_CPUS; 2264 2265 if (!cpu_mask) 2266 return -EINVAL; 2267 *apicid = (unsigned int)cpu_mask; 2268 cpumask_bits(effmsk)[0] = cpu_mask; 2269 return 0; 2270 } 2271 2272 /* 2273 * Override the generic EOI implementation with an optimized version. 2274 * Only called during early boot when only one CPU is active and with 2275 * interrupts disabled, so we know this does not race with actual APIC driver 2276 * use. 2277 */ 2278 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) 2279 { 2280 struct apic **drv; 2281 2282 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { 2283 /* Should happen once for each apic */ 2284 WARN_ON((*drv)->eoi_write == eoi_write); 2285 (*drv)->native_eoi_write = (*drv)->eoi_write; 2286 (*drv)->eoi_write = eoi_write; 2287 } 2288 } 2289 2290 static void __init apic_bsp_up_setup(void) 2291 { 2292 #ifdef CONFIG_X86_64 2293 apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid)); 2294 #else 2295 /* 2296 * Hack: In case of kdump, after a crash, kernel might be booting 2297 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 2298 * might be zero if read from MP tables. Get it from LAPIC. 2299 */ 2300 # ifdef CONFIG_CRASH_DUMP 2301 boot_cpu_physical_apicid = read_apic_id(); 2302 # endif 2303 #endif 2304 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 2305 } 2306 2307 /** 2308 * apic_bsp_setup - Setup function for local apic and io-apic 2309 * @upmode: Force UP mode (for APIC_init_uniprocessor) 2310 * 2311 * Returns: 2312 * apic_id of BSP APIC 2313 */ 2314 int __init apic_bsp_setup(bool upmode) 2315 { 2316 int id; 2317 2318 connect_bsp_APIC(); 2319 if (upmode) 2320 apic_bsp_up_setup(); 2321 setup_local_APIC(); 2322 2323 if (x2apic_mode) 2324 id = apic_read(APIC_LDR); 2325 else 2326 id = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 2327 2328 enable_IO_APIC(); 2329 end_local_APIC_setup(); 2330 irq_remap_enable_fault_handling(); 2331 setup_IO_APIC(); 2332 /* Setup local timer */ 2333 x86_init.timers.setup_percpu_clockev(); 2334 return id; 2335 } 2336 2337 /* 2338 * This initializes the IO-APIC and APIC hardware if this is 2339 * a UP kernel. 2340 */ 2341 int __init APIC_init_uniprocessor(void) 2342 { 2343 if (disable_apic) { 2344 pr_info("Apic disabled\n"); 2345 return -1; 2346 } 2347 #ifdef CONFIG_X86_64 2348 if (!boot_cpu_has(X86_FEATURE_APIC)) { 2349 disable_apic = 1; 2350 pr_info("Apic disabled by BIOS\n"); 2351 return -1; 2352 } 2353 #else 2354 if (!smp_found_config && !boot_cpu_has(X86_FEATURE_APIC)) 2355 return -1; 2356 2357 /* 2358 * Complain if the BIOS pretends there is one. 2359 */ 2360 if (!boot_cpu_has(X86_FEATURE_APIC) && 2361 APIC_INTEGRATED(boot_cpu_apic_version)) { 2362 pr_err("BIOS bug, local APIC 0x%x not detected!...\n", 2363 boot_cpu_physical_apicid); 2364 return -1; 2365 } 2366 #endif 2367 2368 if (!smp_found_config) 2369 disable_ioapic_support(); 2370 2371 default_setup_apic_routing(); 2372 apic_bsp_setup(true); 2373 return 0; 2374 } 2375 2376 #ifdef CONFIG_UP_LATE_INIT 2377 void __init up_late_init(void) 2378 { 2379 APIC_init_uniprocessor(); 2380 } 2381 #endif 2382 2383 /* 2384 * Power management 2385 */ 2386 #ifdef CONFIG_PM 2387 2388 static struct { 2389 /* 2390 * 'active' is true if the local APIC was enabled by us and 2391 * not the BIOS; this signifies that we are also responsible 2392 * for disabling it before entering apm/acpi suspend 2393 */ 2394 int active; 2395 /* r/w apic fields */ 2396 unsigned int apic_id; 2397 unsigned int apic_taskpri; 2398 unsigned int apic_ldr; 2399 unsigned int apic_dfr; 2400 unsigned int apic_spiv; 2401 unsigned int apic_lvtt; 2402 unsigned int apic_lvtpc; 2403 unsigned int apic_lvt0; 2404 unsigned int apic_lvt1; 2405 unsigned int apic_lvterr; 2406 unsigned int apic_tmict; 2407 unsigned int apic_tdcr; 2408 unsigned int apic_thmr; 2409 unsigned int apic_cmci; 2410 } apic_pm_state; 2411 2412 static int lapic_suspend(void) 2413 { 2414 unsigned long flags; 2415 int maxlvt; 2416 2417 if (!apic_pm_state.active) 2418 return 0; 2419 2420 maxlvt = lapic_get_maxlvt(); 2421 2422 apic_pm_state.apic_id = apic_read(APIC_ID); 2423 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 2424 apic_pm_state.apic_ldr = apic_read(APIC_LDR); 2425 apic_pm_state.apic_dfr = apic_read(APIC_DFR); 2426 apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2427 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2428 if (maxlvt >= 4) 2429 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2430 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2431 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2432 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2433 apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2434 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 2435 #ifdef CONFIG_X86_THERMAL_VECTOR 2436 if (maxlvt >= 5) 2437 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2438 #endif 2439 #ifdef CONFIG_X86_MCE_INTEL 2440 if (maxlvt >= 6) 2441 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI); 2442 #endif 2443 2444 local_irq_save(flags); 2445 disable_local_APIC(); 2446 2447 irq_remapping_disable(); 2448 2449 local_irq_restore(flags); 2450 return 0; 2451 } 2452 2453 static void lapic_resume(void) 2454 { 2455 unsigned int l, h; 2456 unsigned long flags; 2457 int maxlvt; 2458 2459 if (!apic_pm_state.active) 2460 return; 2461 2462 local_irq_save(flags); 2463 2464 /* 2465 * IO-APIC and PIC have their own resume routines. 2466 * We just mask them here to make sure the interrupt 2467 * subsystem is completely quiet while we enable x2apic 2468 * and interrupt-remapping. 2469 */ 2470 mask_ioapic_entries(); 2471 legacy_pic->mask_all(); 2472 2473 if (x2apic_mode) { 2474 __x2apic_enable(); 2475 } else { 2476 /* 2477 * Make sure the APICBASE points to the right address 2478 * 2479 * FIXME! This will be wrong if we ever support suspend on 2480 * SMP! We'll need to do this as part of the CPU restore! 2481 */ 2482 if (boot_cpu_data.x86 >= 6) { 2483 rdmsr(MSR_IA32_APICBASE, l, h); 2484 l &= ~MSR_IA32_APICBASE_BASE; 2485 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2486 wrmsr(MSR_IA32_APICBASE, l, h); 2487 } 2488 } 2489 2490 maxlvt = lapic_get_maxlvt(); 2491 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2492 apic_write(APIC_ID, apic_pm_state.apic_id); 2493 apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2494 apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2495 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2496 apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2497 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2498 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 2499 #ifdef CONFIG_X86_THERMAL_VECTOR 2500 if (maxlvt >= 5) 2501 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2502 #endif 2503 #ifdef CONFIG_X86_MCE_INTEL 2504 if (maxlvt >= 6) 2505 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci); 2506 #endif 2507 if (maxlvt >= 4) 2508 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2509 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2510 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2511 apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2512 apic_write(APIC_ESR, 0); 2513 apic_read(APIC_ESR); 2514 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2515 apic_write(APIC_ESR, 0); 2516 apic_read(APIC_ESR); 2517 2518 irq_remapping_reenable(x2apic_mode); 2519 2520 local_irq_restore(flags); 2521 } 2522 2523 /* 2524 * This device has no shutdown method - fully functioning local APICs 2525 * are needed on every CPU up until machine_halt/restart/poweroff. 2526 */ 2527 2528 static struct syscore_ops lapic_syscore_ops = { 2529 .resume = lapic_resume, 2530 .suspend = lapic_suspend, 2531 }; 2532 2533 static void apic_pm_activate(void) 2534 { 2535 apic_pm_state.active = 1; 2536 } 2537 2538 static int __init init_lapic_sysfs(void) 2539 { 2540 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 2541 if (boot_cpu_has(X86_FEATURE_APIC)) 2542 register_syscore_ops(&lapic_syscore_ops); 2543 2544 return 0; 2545 } 2546 2547 /* local apic needs to resume before other devices access its registers. */ 2548 core_initcall(init_lapic_sysfs); 2549 2550 #else /* CONFIG_PM */ 2551 2552 static void apic_pm_activate(void) { } 2553 2554 #endif /* CONFIG_PM */ 2555 2556 #ifdef CONFIG_X86_64 2557 2558 static int multi_checked; 2559 static int multi; 2560 2561 static int set_multi(const struct dmi_system_id *d) 2562 { 2563 if (multi) 2564 return 0; 2565 pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2566 multi = 1; 2567 return 0; 2568 } 2569 2570 static const struct dmi_system_id multi_dmi_table[] = { 2571 { 2572 .callback = set_multi, 2573 .ident = "IBM System Summit2", 2574 .matches = { 2575 DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2576 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2577 }, 2578 }, 2579 {} 2580 }; 2581 2582 static void dmi_check_multi(void) 2583 { 2584 if (multi_checked) 2585 return; 2586 2587 dmi_check_system(multi_dmi_table); 2588 multi_checked = 1; 2589 } 2590 2591 /* 2592 * apic_is_clustered_box() -- Check if we can expect good TSC 2593 * 2594 * Thus far, the major user of this is IBM's Summit2 series: 2595 * Clustered boxes may have unsynced TSC problems if they are 2596 * multi-chassis. 2597 * Use DMI to check them 2598 */ 2599 int apic_is_clustered_box(void) 2600 { 2601 dmi_check_multi(); 2602 return multi; 2603 } 2604 #endif 2605 2606 /* 2607 * APIC command line parameters 2608 */ 2609 static int __init setup_disableapic(char *arg) 2610 { 2611 disable_apic = 1; 2612 setup_clear_cpu_cap(X86_FEATURE_APIC); 2613 return 0; 2614 } 2615 early_param("disableapic", setup_disableapic); 2616 2617 /* same as disableapic, for compatibility */ 2618 static int __init setup_nolapic(char *arg) 2619 { 2620 return setup_disableapic(arg); 2621 } 2622 early_param("nolapic", setup_nolapic); 2623 2624 static int __init parse_lapic_timer_c2_ok(char *arg) 2625 { 2626 local_apic_timer_c2_ok = 1; 2627 return 0; 2628 } 2629 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2630 2631 static int __init parse_disable_apic_timer(char *arg) 2632 { 2633 disable_apic_timer = 1; 2634 return 0; 2635 } 2636 early_param("noapictimer", parse_disable_apic_timer); 2637 2638 static int __init parse_nolapic_timer(char *arg) 2639 { 2640 disable_apic_timer = 1; 2641 return 0; 2642 } 2643 early_param("nolapic_timer", parse_nolapic_timer); 2644 2645 static int __init apic_set_verbosity(char *arg) 2646 { 2647 if (!arg) { 2648 #ifdef CONFIG_X86_64 2649 skip_ioapic_setup = 0; 2650 return 0; 2651 #endif 2652 return -EINVAL; 2653 } 2654 2655 if (strcmp("debug", arg) == 0) 2656 apic_verbosity = APIC_DEBUG; 2657 else if (strcmp("verbose", arg) == 0) 2658 apic_verbosity = APIC_VERBOSE; 2659 else { 2660 pr_warning("APIC Verbosity level %s not recognised" 2661 " use apic=verbose or apic=debug\n", arg); 2662 return -EINVAL; 2663 } 2664 2665 return 0; 2666 } 2667 early_param("apic", apic_set_verbosity); 2668 2669 static int __init lapic_insert_resource(void) 2670 { 2671 if (!apic_phys) 2672 return -1; 2673 2674 /* Put local APIC into the resource map. */ 2675 lapic_resource.start = apic_phys; 2676 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2677 insert_resource(&iomem_resource, &lapic_resource); 2678 2679 return 0; 2680 } 2681 2682 /* 2683 * need call insert after e820__reserve_resources() 2684 * that is using request_resource 2685 */ 2686 late_initcall(lapic_insert_resource); 2687 2688 static int __init apic_set_disabled_cpu_apicid(char *arg) 2689 { 2690 if (!arg || !get_option(&arg, &disabled_cpu_apicid)) 2691 return -EINVAL; 2692 2693 return 0; 2694 } 2695 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); 2696 2697 static int __init apic_set_extnmi(char *arg) 2698 { 2699 if (!arg) 2700 return -EINVAL; 2701 2702 if (!strncmp("all", arg, 3)) 2703 apic_extnmi = APIC_EXTNMI_ALL; 2704 else if (!strncmp("none", arg, 4)) 2705 apic_extnmi = APIC_EXTNMI_NONE; 2706 else if (!strncmp("bsp", arg, 3)) 2707 apic_extnmi = APIC_EXTNMI_BSP; 2708 else { 2709 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg); 2710 return -EINVAL; 2711 } 2712 2713 return 0; 2714 } 2715 early_param("apic_extnmi", apic_set_extnmi); 2716