1 /* 2 * Local APIC handling, local APIC timers 3 * 4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 5 * 6 * Fixes 7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 8 * thanks to Eric Gilmore 9 * and Rolf G. Tews 10 * for testing these extensively. 11 * Maciej W. Rozycki : Various updates and fixes. 12 * Mikael Pettersson : Power Management for UP-APIC. 13 * Pavel Machek and 14 * Mikael Pettersson : PM converted to driver model. 15 */ 16 17 #include <linux/perf_event.h> 18 #include <linux/kernel_stat.h> 19 #include <linux/mc146818rtc.h> 20 #include <linux/acpi_pmtmr.h> 21 #include <linux/clockchips.h> 22 #include <linux/interrupt.h> 23 #include <linux/bootmem.h> 24 #include <linux/ftrace.h> 25 #include <linux/ioport.h> 26 #include <linux/module.h> 27 #include <linux/syscore_ops.h> 28 #include <linux/delay.h> 29 #include <linux/timex.h> 30 #include <linux/i8253.h> 31 #include <linux/dmar.h> 32 #include <linux/init.h> 33 #include <linux/cpu.h> 34 #include <linux/dmi.h> 35 #include <linux/smp.h> 36 #include <linux/mm.h> 37 38 #include <asm/perf_event.h> 39 #include <asm/x86_init.h> 40 #include <asm/pgalloc.h> 41 #include <linux/atomic.h> 42 #include <asm/mpspec.h> 43 #include <asm/i8259.h> 44 #include <asm/proto.h> 45 #include <asm/apic.h> 46 #include <asm/io_apic.h> 47 #include <asm/desc.h> 48 #include <asm/hpet.h> 49 #include <asm/idle.h> 50 #include <asm/mtrr.h> 51 #include <asm/time.h> 52 #include <asm/smp.h> 53 #include <asm/mce.h> 54 #include <asm/tsc.h> 55 #include <asm/hypervisor.h> 56 57 unsigned int num_processors; 58 59 unsigned disabled_cpus __cpuinitdata; 60 61 /* Processor that is doing the boot up */ 62 unsigned int boot_cpu_physical_apicid = -1U; 63 64 /* 65 * The highest APIC ID seen during enumeration. 66 */ 67 unsigned int max_physical_apicid; 68 69 /* 70 * Bitmask of physically existing CPUs: 71 */ 72 physid_mask_t phys_cpu_present_map; 73 74 /* 75 * Map cpu index to physical APIC ID 76 */ 77 DEFINE_EARLY_PER_CPU(u16, x86_cpu_to_apicid, BAD_APICID); 78 DEFINE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid, BAD_APICID); 79 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 80 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 81 82 #ifdef CONFIG_X86_32 83 84 /* 85 * On x86_32, the mapping between cpu and logical apicid may vary 86 * depending on apic in use. The following early percpu variable is 87 * used for the mapping. This is where the behaviors of x86_64 and 32 88 * actually diverge. Let's keep it ugly for now. 89 */ 90 DEFINE_EARLY_PER_CPU(int, x86_cpu_to_logical_apicid, BAD_APICID); 91 92 /* 93 * Knob to control our willingness to enable the local APIC. 94 * 95 * +1=force-enable 96 */ 97 static int force_enable_local_apic __initdata; 98 /* 99 * APIC command line parameters 100 */ 101 static int __init parse_lapic(char *arg) 102 { 103 force_enable_local_apic = 1; 104 return 0; 105 } 106 early_param("lapic", parse_lapic); 107 /* Local APIC was disabled by the BIOS and enabled by the kernel */ 108 static int enabled_via_apicbase; 109 110 /* 111 * Handle interrupt mode configuration register (IMCR). 112 * This register controls whether the interrupt signals 113 * that reach the BSP come from the master PIC or from the 114 * local APIC. Before entering Symmetric I/O Mode, either 115 * the BIOS or the operating system must switch out of 116 * PIC Mode by changing the IMCR. 117 */ 118 static inline void imcr_pic_to_apic(void) 119 { 120 /* select IMCR register */ 121 outb(0x70, 0x22); 122 /* NMI and 8259 INTR go through APIC */ 123 outb(0x01, 0x23); 124 } 125 126 static inline void imcr_apic_to_pic(void) 127 { 128 /* select IMCR register */ 129 outb(0x70, 0x22); 130 /* NMI and 8259 INTR go directly to BSP */ 131 outb(0x00, 0x23); 132 } 133 #endif 134 135 #ifdef CONFIG_X86_64 136 static int apic_calibrate_pmtmr __initdata; 137 static __init int setup_apicpmtimer(char *s) 138 { 139 apic_calibrate_pmtmr = 1; 140 notsc_setup(NULL); 141 return 0; 142 } 143 __setup("apicpmtimer", setup_apicpmtimer); 144 #endif 145 146 int x2apic_mode; 147 #ifdef CONFIG_X86_X2APIC 148 /* x2apic enabled before OS handover */ 149 int x2apic_preenabled; 150 static int x2apic_disabled; 151 static int nox2apic; 152 static __init int setup_nox2apic(char *str) 153 { 154 if (x2apic_enabled()) { 155 int apicid = native_apic_msr_read(APIC_ID); 156 157 if (apicid >= 255) { 158 pr_warning("Apicid: %08x, cannot enforce nox2apic\n", 159 apicid); 160 return 0; 161 } 162 163 pr_warning("x2apic already enabled. will disable it\n"); 164 } else 165 setup_clear_cpu_cap(X86_FEATURE_X2APIC); 166 167 nox2apic = 1; 168 169 return 0; 170 } 171 early_param("nox2apic", setup_nox2apic); 172 #endif 173 174 unsigned long mp_lapic_addr; 175 int disable_apic; 176 /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 177 static int disable_apic_timer __initdata; 178 /* Local APIC timer works in C2 */ 179 int local_apic_timer_c2_ok; 180 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 181 182 int first_system_vector = 0xfe; 183 184 /* 185 * Debug level, exported for io_apic.c 186 */ 187 unsigned int apic_verbosity; 188 189 int pic_mode; 190 191 /* Have we found an MP table */ 192 int smp_found_config; 193 194 static struct resource lapic_resource = { 195 .name = "Local APIC", 196 .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 197 }; 198 199 unsigned int lapic_timer_frequency = 0; 200 201 static void apic_pm_activate(void); 202 203 static unsigned long apic_phys; 204 205 /* 206 * Get the LAPIC version 207 */ 208 static inline int lapic_get_version(void) 209 { 210 return GET_APIC_VERSION(apic_read(APIC_LVR)); 211 } 212 213 /* 214 * Check, if the APIC is integrated or a separate chip 215 */ 216 static inline int lapic_is_integrated(void) 217 { 218 #ifdef CONFIG_X86_64 219 return 1; 220 #else 221 return APIC_INTEGRATED(lapic_get_version()); 222 #endif 223 } 224 225 /* 226 * Check, whether this is a modern or a first generation APIC 227 */ 228 static int modern_apic(void) 229 { 230 /* AMD systems use old APIC versions, so check the CPU */ 231 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 232 boot_cpu_data.x86 >= 0xf) 233 return 1; 234 return lapic_get_version() >= 0x14; 235 } 236 237 /* 238 * right after this call apic become NOOP driven 239 * so apic->write/read doesn't do anything 240 */ 241 static void __init apic_disable(void) 242 { 243 pr_info("APIC: switched to apic NOOP\n"); 244 apic = &apic_noop; 245 } 246 247 void native_apic_wait_icr_idle(void) 248 { 249 while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 250 cpu_relax(); 251 } 252 253 u32 native_safe_apic_wait_icr_idle(void) 254 { 255 u32 send_status; 256 int timeout; 257 258 timeout = 0; 259 do { 260 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 261 if (!send_status) 262 break; 263 inc_irq_stat(icr_read_retry_count); 264 udelay(100); 265 } while (timeout++ < 1000); 266 267 return send_status; 268 } 269 270 void native_apic_icr_write(u32 low, u32 id) 271 { 272 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 273 apic_write(APIC_ICR, low); 274 } 275 276 u64 native_apic_icr_read(void) 277 { 278 u32 icr1, icr2; 279 280 icr2 = apic_read(APIC_ICR2); 281 icr1 = apic_read(APIC_ICR); 282 283 return icr1 | ((u64)icr2 << 32); 284 } 285 286 #ifdef CONFIG_X86_32 287 /** 288 * get_physical_broadcast - Get number of physical broadcast IDs 289 */ 290 int get_physical_broadcast(void) 291 { 292 return modern_apic() ? 0xff : 0xf; 293 } 294 #endif 295 296 /** 297 * lapic_get_maxlvt - get the maximum number of local vector table entries 298 */ 299 int lapic_get_maxlvt(void) 300 { 301 unsigned int v; 302 303 v = apic_read(APIC_LVR); 304 /* 305 * - we always have APIC integrated on 64bit mode 306 * - 82489DXs do not report # of LVT entries 307 */ 308 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; 309 } 310 311 /* 312 * Local APIC timer 313 */ 314 315 /* Clock divisor */ 316 #define APIC_DIVISOR 16 317 318 /* 319 * This function sets up the local APIC timer, with a timeout of 320 * 'clocks' APIC bus clock. During calibration we actually call 321 * this function twice on the boot CPU, once with a bogus timeout 322 * value, second time for real. The other (noncalibrating) CPUs 323 * call this function only once, with the real, calibrated value. 324 * 325 * We do reads before writes even if unnecessary, to get around the 326 * P5 APIC double write bug. 327 */ 328 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 329 { 330 unsigned int lvtt_value, tmp_value; 331 332 lvtt_value = LOCAL_TIMER_VECTOR; 333 if (!oneshot) 334 lvtt_value |= APIC_LVT_TIMER_PERIODIC; 335 if (!lapic_is_integrated()) 336 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 337 338 if (!irqen) 339 lvtt_value |= APIC_LVT_MASKED; 340 341 apic_write(APIC_LVTT, lvtt_value); 342 343 /* 344 * Divide PICLK by 16 345 */ 346 tmp_value = apic_read(APIC_TDCR); 347 apic_write(APIC_TDCR, 348 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 349 APIC_TDR_DIV_16); 350 351 if (!oneshot) 352 apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 353 } 354 355 /* 356 * Setup extended LVT, AMD specific 357 * 358 * Software should use the LVT offsets the BIOS provides. The offsets 359 * are determined by the subsystems using it like those for MCE 360 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts 361 * are supported. Beginning with family 10h at least 4 offsets are 362 * available. 363 * 364 * Since the offsets must be consistent for all cores, we keep track 365 * of the LVT offsets in software and reserve the offset for the same 366 * vector also to be used on other cores. An offset is freed by 367 * setting the entry to APIC_EILVT_MASKED. 368 * 369 * If the BIOS is right, there should be no conflicts. Otherwise a 370 * "[Firmware Bug]: ..." error message is generated. However, if 371 * software does not properly determines the offsets, it is not 372 * necessarily a BIOS bug. 373 */ 374 375 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; 376 377 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) 378 { 379 return (old & APIC_EILVT_MASKED) 380 || (new == APIC_EILVT_MASKED) 381 || ((new & ~APIC_EILVT_MASKED) == old); 382 } 383 384 static unsigned int reserve_eilvt_offset(int offset, unsigned int new) 385 { 386 unsigned int rsvd, vector; 387 388 if (offset >= APIC_EILVT_NR_MAX) 389 return ~0; 390 391 rsvd = atomic_read(&eilvt_offsets[offset]); 392 do { 393 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ 394 if (vector && !eilvt_entry_is_changeable(vector, new)) 395 /* may not change if vectors are different */ 396 return rsvd; 397 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); 398 } while (rsvd != new); 399 400 rsvd &= ~APIC_EILVT_MASKED; 401 if (rsvd && rsvd != vector) 402 pr_info("LVT offset %d assigned for vector 0x%02x\n", 403 offset, rsvd); 404 405 return new; 406 } 407 408 /* 409 * If mask=1, the LVT entry does not generate interrupts while mask=0 410 * enables the vector. See also the BKDGs. Must be called with 411 * preemption disabled. 412 */ 413 414 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) 415 { 416 unsigned long reg = APIC_EILVTn(offset); 417 unsigned int new, old, reserved; 418 419 new = (mask << 16) | (msg_type << 8) | vector; 420 old = apic_read(reg); 421 reserved = reserve_eilvt_offset(offset, new); 422 423 if (reserved != new) { 424 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 425 "vector 0x%x, but the register is already in use for " 426 "vector 0x%x on another cpu\n", 427 smp_processor_id(), reg, offset, new, reserved); 428 return -EINVAL; 429 } 430 431 if (!eilvt_entry_is_changeable(old, new)) { 432 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 433 "vector 0x%x, but the register is already in use for " 434 "vector 0x%x on this cpu\n", 435 smp_processor_id(), reg, offset, new, old); 436 return -EBUSY; 437 } 438 439 apic_write(reg, new); 440 441 return 0; 442 } 443 EXPORT_SYMBOL_GPL(setup_APIC_eilvt); 444 445 /* 446 * Program the next event, relative to now 447 */ 448 static int lapic_next_event(unsigned long delta, 449 struct clock_event_device *evt) 450 { 451 apic_write(APIC_TMICT, delta); 452 return 0; 453 } 454 455 /* 456 * Setup the lapic timer in periodic or oneshot mode 457 */ 458 static void lapic_timer_setup(enum clock_event_mode mode, 459 struct clock_event_device *evt) 460 { 461 unsigned long flags; 462 unsigned int v; 463 464 /* Lapic used as dummy for broadcast ? */ 465 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 466 return; 467 468 local_irq_save(flags); 469 470 switch (mode) { 471 case CLOCK_EVT_MODE_PERIODIC: 472 case CLOCK_EVT_MODE_ONESHOT: 473 __setup_APIC_LVTT(lapic_timer_frequency, 474 mode != CLOCK_EVT_MODE_PERIODIC, 1); 475 break; 476 case CLOCK_EVT_MODE_UNUSED: 477 case CLOCK_EVT_MODE_SHUTDOWN: 478 v = apic_read(APIC_LVTT); 479 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 480 apic_write(APIC_LVTT, v); 481 apic_write(APIC_TMICT, 0); 482 break; 483 case CLOCK_EVT_MODE_RESUME: 484 /* Nothing to do here */ 485 break; 486 } 487 488 local_irq_restore(flags); 489 } 490 491 /* 492 * Local APIC timer broadcast function 493 */ 494 static void lapic_timer_broadcast(const struct cpumask *mask) 495 { 496 #ifdef CONFIG_SMP 497 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 498 #endif 499 } 500 501 502 /* 503 * The local apic timer can be used for any function which is CPU local. 504 */ 505 static struct clock_event_device lapic_clockevent = { 506 .name = "lapic", 507 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT 508 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY, 509 .shift = 32, 510 .set_mode = lapic_timer_setup, 511 .set_next_event = lapic_next_event, 512 .broadcast = lapic_timer_broadcast, 513 .rating = 100, 514 .irq = -1, 515 }; 516 static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 517 518 /* 519 * Setup the local APIC timer for this CPU. Copy the initialized values 520 * of the boot CPU and register the clock event in the framework. 521 */ 522 static void __cpuinit setup_APIC_timer(void) 523 { 524 struct clock_event_device *levt = &__get_cpu_var(lapic_events); 525 526 if (this_cpu_has(X86_FEATURE_ARAT)) { 527 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 528 /* Make LAPIC timer preferrable over percpu HPET */ 529 lapic_clockevent.rating = 150; 530 } 531 532 memcpy(levt, &lapic_clockevent, sizeof(*levt)); 533 levt->cpumask = cpumask_of(smp_processor_id()); 534 535 clockevents_register_device(levt); 536 } 537 538 /* 539 * In this functions we calibrate APIC bus clocks to the external timer. 540 * 541 * We want to do the calibration only once since we want to have local timer 542 * irqs syncron. CPUs connected by the same APIC bus have the very same bus 543 * frequency. 544 * 545 * This was previously done by reading the PIT/HPET and waiting for a wrap 546 * around to find out, that a tick has elapsed. I have a box, where the PIT 547 * readout is broken, so it never gets out of the wait loop again. This was 548 * also reported by others. 549 * 550 * Monitoring the jiffies value is inaccurate and the clockevents 551 * infrastructure allows us to do a simple substitution of the interrupt 552 * handler. 553 * 554 * The calibration routine also uses the pm_timer when possible, as the PIT 555 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 556 * back to normal later in the boot process). 557 */ 558 559 #define LAPIC_CAL_LOOPS (HZ/10) 560 561 static __initdata int lapic_cal_loops = -1; 562 static __initdata long lapic_cal_t1, lapic_cal_t2; 563 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 564 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 565 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 566 567 /* 568 * Temporary interrupt handler. 569 */ 570 static void __init lapic_cal_handler(struct clock_event_device *dev) 571 { 572 unsigned long long tsc = 0; 573 long tapic = apic_read(APIC_TMCCT); 574 unsigned long pm = acpi_pm_read_early(); 575 576 if (cpu_has_tsc) 577 rdtscll(tsc); 578 579 switch (lapic_cal_loops++) { 580 case 0: 581 lapic_cal_t1 = tapic; 582 lapic_cal_tsc1 = tsc; 583 lapic_cal_pm1 = pm; 584 lapic_cal_j1 = jiffies; 585 break; 586 587 case LAPIC_CAL_LOOPS: 588 lapic_cal_t2 = tapic; 589 lapic_cal_tsc2 = tsc; 590 if (pm < lapic_cal_pm1) 591 pm += ACPI_PM_OVRRUN; 592 lapic_cal_pm2 = pm; 593 lapic_cal_j2 = jiffies; 594 break; 595 } 596 } 597 598 static int __init 599 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 600 { 601 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 602 const long pm_thresh = pm_100ms / 100; 603 unsigned long mult; 604 u64 res; 605 606 #ifndef CONFIG_X86_PM_TIMER 607 return -1; 608 #endif 609 610 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 611 612 /* Check, if the PM timer is available */ 613 if (!deltapm) 614 return -1; 615 616 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 617 618 if (deltapm > (pm_100ms - pm_thresh) && 619 deltapm < (pm_100ms + pm_thresh)) { 620 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 621 return 0; 622 } 623 624 res = (((u64)deltapm) * mult) >> 22; 625 do_div(res, 1000000); 626 pr_warning("APIC calibration not consistent " 627 "with PM-Timer: %ldms instead of 100ms\n",(long)res); 628 629 /* Correct the lapic counter value */ 630 res = (((u64)(*delta)) * pm_100ms); 631 do_div(res, deltapm); 632 pr_info("APIC delta adjusted to PM-Timer: " 633 "%lu (%ld)\n", (unsigned long)res, *delta); 634 *delta = (long)res; 635 636 /* Correct the tsc counter value */ 637 if (cpu_has_tsc) { 638 res = (((u64)(*deltatsc)) * pm_100ms); 639 do_div(res, deltapm); 640 apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 641 "PM-Timer: %lu (%ld)\n", 642 (unsigned long)res, *deltatsc); 643 *deltatsc = (long)res; 644 } 645 646 return 0; 647 } 648 649 static int __init calibrate_APIC_clock(void) 650 { 651 struct clock_event_device *levt = &__get_cpu_var(lapic_events); 652 void (*real_handler)(struct clock_event_device *dev); 653 unsigned long deltaj; 654 long delta, deltatsc; 655 int pm_referenced = 0; 656 657 /** 658 * check if lapic timer has already been calibrated by platform 659 * specific routine, such as tsc calibration code. if so, we just fill 660 * in the clockevent structure and return. 661 */ 662 663 if (lapic_timer_frequency) { 664 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", 665 lapic_timer_frequency); 666 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR, 667 TICK_NSEC, lapic_clockevent.shift); 668 lapic_clockevent.max_delta_ns = 669 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); 670 lapic_clockevent.min_delta_ns = 671 clockevent_delta2ns(0xF, &lapic_clockevent); 672 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 673 return 0; 674 } 675 676 local_irq_disable(); 677 678 /* Replace the global interrupt handler */ 679 real_handler = global_clock_event->event_handler; 680 global_clock_event->event_handler = lapic_cal_handler; 681 682 /* 683 * Setup the APIC counter to maximum. There is no way the lapic 684 * can underflow in the 100ms detection time frame 685 */ 686 __setup_APIC_LVTT(0xffffffff, 0, 0); 687 688 /* Let the interrupts run */ 689 local_irq_enable(); 690 691 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 692 cpu_relax(); 693 694 local_irq_disable(); 695 696 /* Restore the real event handler */ 697 global_clock_event->event_handler = real_handler; 698 699 /* Build delta t1-t2 as apic timer counts down */ 700 delta = lapic_cal_t1 - lapic_cal_t2; 701 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 702 703 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 704 705 /* we trust the PM based calibration if possible */ 706 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 707 &delta, &deltatsc); 708 709 /* Calculate the scaled math multiplication factor */ 710 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 711 lapic_clockevent.shift); 712 lapic_clockevent.max_delta_ns = 713 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); 714 lapic_clockevent.min_delta_ns = 715 clockevent_delta2ns(0xF, &lapic_clockevent); 716 717 lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 718 719 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 720 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); 721 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 722 lapic_timer_frequency); 723 724 if (cpu_has_tsc) { 725 apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 726 "%ld.%04ld MHz.\n", 727 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 728 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 729 } 730 731 apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 732 "%u.%04u MHz.\n", 733 lapic_timer_frequency / (1000000 / HZ), 734 lapic_timer_frequency % (1000000 / HZ)); 735 736 /* 737 * Do a sanity check on the APIC calibration result 738 */ 739 if (lapic_timer_frequency < (1000000 / HZ)) { 740 local_irq_enable(); 741 pr_warning("APIC frequency too slow, disabling apic timer\n"); 742 return -1; 743 } 744 745 levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 746 747 /* 748 * PM timer calibration failed or not turned on 749 * so lets try APIC timer based calibration 750 */ 751 if (!pm_referenced) { 752 apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 753 754 /* 755 * Setup the apic timer manually 756 */ 757 levt->event_handler = lapic_cal_handler; 758 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt); 759 lapic_cal_loops = -1; 760 761 /* Let the interrupts run */ 762 local_irq_enable(); 763 764 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 765 cpu_relax(); 766 767 /* Stop the lapic timer */ 768 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt); 769 770 /* Jiffies delta */ 771 deltaj = lapic_cal_j2 - lapic_cal_j1; 772 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 773 774 /* Check, if the jiffies result is consistent */ 775 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 776 apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 777 else 778 levt->features |= CLOCK_EVT_FEAT_DUMMY; 779 } else 780 local_irq_enable(); 781 782 if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 783 pr_warning("APIC timer disabled due to verification failure\n"); 784 return -1; 785 } 786 787 return 0; 788 } 789 790 /* 791 * Setup the boot APIC 792 * 793 * Calibrate and verify the result. 794 */ 795 void __init setup_boot_APIC_clock(void) 796 { 797 /* 798 * The local apic timer can be disabled via the kernel 799 * commandline or from the CPU detection code. Register the lapic 800 * timer as a dummy clock event source on SMP systems, so the 801 * broadcast mechanism is used. On UP systems simply ignore it. 802 */ 803 if (disable_apic_timer) { 804 pr_info("Disabling APIC timer\n"); 805 /* No broadcast on UP ! */ 806 if (num_possible_cpus() > 1) { 807 lapic_clockevent.mult = 1; 808 setup_APIC_timer(); 809 } 810 return; 811 } 812 813 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 814 "calibrating APIC timer ...\n"); 815 816 if (calibrate_APIC_clock()) { 817 /* No broadcast on UP ! */ 818 if (num_possible_cpus() > 1) 819 setup_APIC_timer(); 820 return; 821 } 822 823 /* 824 * If nmi_watchdog is set to IO_APIC, we need the 825 * PIT/HPET going. Otherwise register lapic as a dummy 826 * device. 827 */ 828 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 829 830 /* Setup the lapic or request the broadcast */ 831 setup_APIC_timer(); 832 } 833 834 void __cpuinit setup_secondary_APIC_clock(void) 835 { 836 setup_APIC_timer(); 837 } 838 839 /* 840 * The guts of the apic timer interrupt 841 */ 842 static void local_apic_timer_interrupt(void) 843 { 844 int cpu = smp_processor_id(); 845 struct clock_event_device *evt = &per_cpu(lapic_events, cpu); 846 847 /* 848 * Normally we should not be here till LAPIC has been initialized but 849 * in some cases like kdump, its possible that there is a pending LAPIC 850 * timer interrupt from previous kernel's context and is delivered in 851 * new kernel the moment interrupts are enabled. 852 * 853 * Interrupts are enabled early and LAPIC is setup much later, hence 854 * its possible that when we get here evt->event_handler is NULL. 855 * Check for event_handler being NULL and discard the interrupt as 856 * spurious. 857 */ 858 if (!evt->event_handler) { 859 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); 860 /* Switch it off */ 861 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt); 862 return; 863 } 864 865 /* 866 * the NMI deadlock-detector uses this. 867 */ 868 inc_irq_stat(apic_timer_irqs); 869 870 evt->event_handler(evt); 871 } 872 873 /* 874 * Local APIC timer interrupt. This is the most natural way for doing 875 * local interrupts, but local timer interrupts can be emulated by 876 * broadcast interrupts too. [in case the hw doesn't support APIC timers] 877 * 878 * [ if a single-CPU system runs an SMP kernel then we call the local 879 * interrupt as well. Thus we cannot inline the local irq ... ] 880 */ 881 void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) 882 { 883 struct pt_regs *old_regs = set_irq_regs(regs); 884 885 /* 886 * NOTE! We'd better ACK the irq immediately, 887 * because timer handling can be slow. 888 */ 889 ack_APIC_irq(); 890 /* 891 * update_process_times() expects us to have done irq_enter(). 892 * Besides, if we don't timer interrupts ignore the global 893 * interrupt lock, which is the WrongThing (tm) to do. 894 */ 895 irq_enter(); 896 exit_idle(); 897 local_apic_timer_interrupt(); 898 irq_exit(); 899 900 set_irq_regs(old_regs); 901 } 902 903 int setup_profiling_timer(unsigned int multiplier) 904 { 905 return -EINVAL; 906 } 907 908 /* 909 * Local APIC start and shutdown 910 */ 911 912 /** 913 * clear_local_APIC - shutdown the local APIC 914 * 915 * This is called, when a CPU is disabled and before rebooting, so the state of 916 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 917 * leftovers during boot. 918 */ 919 void clear_local_APIC(void) 920 { 921 int maxlvt; 922 u32 v; 923 924 /* APIC hasn't been mapped yet */ 925 if (!x2apic_mode && !apic_phys) 926 return; 927 928 maxlvt = lapic_get_maxlvt(); 929 /* 930 * Masking an LVT entry can trigger a local APIC error 931 * if the vector is zero. Mask LVTERR first to prevent this. 932 */ 933 if (maxlvt >= 3) { 934 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 935 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 936 } 937 /* 938 * Careful: we have to set masks only first to deassert 939 * any level-triggered sources. 940 */ 941 v = apic_read(APIC_LVTT); 942 apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 943 v = apic_read(APIC_LVT0); 944 apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 945 v = apic_read(APIC_LVT1); 946 apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 947 if (maxlvt >= 4) { 948 v = apic_read(APIC_LVTPC); 949 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 950 } 951 952 /* lets not touch this if we didn't frob it */ 953 #ifdef CONFIG_X86_THERMAL_VECTOR 954 if (maxlvt >= 5) { 955 v = apic_read(APIC_LVTTHMR); 956 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 957 } 958 #endif 959 #ifdef CONFIG_X86_MCE_INTEL 960 if (maxlvt >= 6) { 961 v = apic_read(APIC_LVTCMCI); 962 if (!(v & APIC_LVT_MASKED)) 963 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 964 } 965 #endif 966 967 /* 968 * Clean APIC state for other OSs: 969 */ 970 apic_write(APIC_LVTT, APIC_LVT_MASKED); 971 apic_write(APIC_LVT0, APIC_LVT_MASKED); 972 apic_write(APIC_LVT1, APIC_LVT_MASKED); 973 if (maxlvt >= 3) 974 apic_write(APIC_LVTERR, APIC_LVT_MASKED); 975 if (maxlvt >= 4) 976 apic_write(APIC_LVTPC, APIC_LVT_MASKED); 977 978 /* Integrated APIC (!82489DX) ? */ 979 if (lapic_is_integrated()) { 980 if (maxlvt > 3) 981 /* Clear ESR due to Pentium errata 3AP and 11AP */ 982 apic_write(APIC_ESR, 0); 983 apic_read(APIC_ESR); 984 } 985 } 986 987 /** 988 * disable_local_APIC - clear and disable the local APIC 989 */ 990 void disable_local_APIC(void) 991 { 992 unsigned int value; 993 994 /* APIC hasn't been mapped yet */ 995 if (!x2apic_mode && !apic_phys) 996 return; 997 998 clear_local_APIC(); 999 1000 /* 1001 * Disable APIC (implies clearing of registers 1002 * for 82489DX!). 1003 */ 1004 value = apic_read(APIC_SPIV); 1005 value &= ~APIC_SPIV_APIC_ENABLED; 1006 apic_write(APIC_SPIV, value); 1007 1008 #ifdef CONFIG_X86_32 1009 /* 1010 * When LAPIC was disabled by the BIOS and enabled by the kernel, 1011 * restore the disabled state. 1012 */ 1013 if (enabled_via_apicbase) { 1014 unsigned int l, h; 1015 1016 rdmsr(MSR_IA32_APICBASE, l, h); 1017 l &= ~MSR_IA32_APICBASE_ENABLE; 1018 wrmsr(MSR_IA32_APICBASE, l, h); 1019 } 1020 #endif 1021 } 1022 1023 /* 1024 * If Linux enabled the LAPIC against the BIOS default disable it down before 1025 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 1026 * not power-off. Additionally clear all LVT entries before disable_local_APIC 1027 * for the case where Linux didn't enable the LAPIC. 1028 */ 1029 void lapic_shutdown(void) 1030 { 1031 unsigned long flags; 1032 1033 if (!cpu_has_apic && !apic_from_smp_config()) 1034 return; 1035 1036 local_irq_save(flags); 1037 1038 #ifdef CONFIG_X86_32 1039 if (!enabled_via_apicbase) 1040 clear_local_APIC(); 1041 else 1042 #endif 1043 disable_local_APIC(); 1044 1045 1046 local_irq_restore(flags); 1047 } 1048 1049 /* 1050 * This is to verify that we're looking at a real local APIC. 1051 * Check these against your board if the CPUs aren't getting 1052 * started for no apparent reason. 1053 */ 1054 int __init verify_local_APIC(void) 1055 { 1056 unsigned int reg0, reg1; 1057 1058 /* 1059 * The version register is read-only in a real APIC. 1060 */ 1061 reg0 = apic_read(APIC_LVR); 1062 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0); 1063 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); 1064 reg1 = apic_read(APIC_LVR); 1065 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1); 1066 1067 /* 1068 * The two version reads above should print the same 1069 * numbers. If the second one is different, then we 1070 * poke at a non-APIC. 1071 */ 1072 if (reg1 != reg0) 1073 return 0; 1074 1075 /* 1076 * Check if the version looks reasonably. 1077 */ 1078 reg1 = GET_APIC_VERSION(reg0); 1079 if (reg1 == 0x00 || reg1 == 0xff) 1080 return 0; 1081 reg1 = lapic_get_maxlvt(); 1082 if (reg1 < 0x02 || reg1 == 0xff) 1083 return 0; 1084 1085 /* 1086 * The ID register is read/write in a real APIC. 1087 */ 1088 reg0 = apic_read(APIC_ID); 1089 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0); 1090 apic_write(APIC_ID, reg0 ^ apic->apic_id_mask); 1091 reg1 = apic_read(APIC_ID); 1092 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1); 1093 apic_write(APIC_ID, reg0); 1094 if (reg1 != (reg0 ^ apic->apic_id_mask)) 1095 return 0; 1096 1097 /* 1098 * The next two are just to see if we have sane values. 1099 * They're only really relevant if we're in Virtual Wire 1100 * compatibility mode, but most boxes are anymore. 1101 */ 1102 reg0 = apic_read(APIC_LVT0); 1103 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0); 1104 reg1 = apic_read(APIC_LVT1); 1105 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1); 1106 1107 return 1; 1108 } 1109 1110 /** 1111 * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1112 */ 1113 void __init sync_Arb_IDs(void) 1114 { 1115 /* 1116 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1117 * needed on AMD. 1118 */ 1119 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1120 return; 1121 1122 /* 1123 * Wait for idle. 1124 */ 1125 apic_wait_icr_idle(); 1126 1127 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1128 apic_write(APIC_ICR, APIC_DEST_ALLINC | 1129 APIC_INT_LEVELTRIG | APIC_DM_INIT); 1130 } 1131 1132 /* 1133 * An initial setup of the virtual wire mode. 1134 */ 1135 void __init init_bsp_APIC(void) 1136 { 1137 unsigned int value; 1138 1139 /* 1140 * Don't do the setup now if we have a SMP BIOS as the 1141 * through-I/O-APIC virtual wire mode might be active. 1142 */ 1143 if (smp_found_config || !cpu_has_apic) 1144 return; 1145 1146 /* 1147 * Do not trust the local APIC being empty at bootup. 1148 */ 1149 clear_local_APIC(); 1150 1151 /* 1152 * Enable APIC. 1153 */ 1154 value = apic_read(APIC_SPIV); 1155 value &= ~APIC_VECTOR_MASK; 1156 value |= APIC_SPIV_APIC_ENABLED; 1157 1158 #ifdef CONFIG_X86_32 1159 /* This bit is reserved on P4/Xeon and should be cleared */ 1160 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1161 (boot_cpu_data.x86 == 15)) 1162 value &= ~APIC_SPIV_FOCUS_DISABLED; 1163 else 1164 #endif 1165 value |= APIC_SPIV_FOCUS_DISABLED; 1166 value |= SPURIOUS_APIC_VECTOR; 1167 apic_write(APIC_SPIV, value); 1168 1169 /* 1170 * Set up the virtual wire mode. 1171 */ 1172 apic_write(APIC_LVT0, APIC_DM_EXTINT); 1173 value = APIC_DM_NMI; 1174 if (!lapic_is_integrated()) /* 82489DX */ 1175 value |= APIC_LVT_LEVEL_TRIGGER; 1176 apic_write(APIC_LVT1, value); 1177 } 1178 1179 static void __cpuinit lapic_setup_esr(void) 1180 { 1181 unsigned int oldvalue, value, maxlvt; 1182 1183 if (!lapic_is_integrated()) { 1184 pr_info("No ESR for 82489DX.\n"); 1185 return; 1186 } 1187 1188 if (apic->disable_esr) { 1189 /* 1190 * Something untraceable is creating bad interrupts on 1191 * secondary quads ... for the moment, just leave the 1192 * ESR disabled - we can't do anything useful with the 1193 * errors anyway - mbligh 1194 */ 1195 pr_info("Leaving ESR disabled.\n"); 1196 return; 1197 } 1198 1199 maxlvt = lapic_get_maxlvt(); 1200 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1201 apic_write(APIC_ESR, 0); 1202 oldvalue = apic_read(APIC_ESR); 1203 1204 /* enables sending errors */ 1205 value = ERROR_APIC_VECTOR; 1206 apic_write(APIC_LVTERR, value); 1207 1208 /* 1209 * spec says clear errors after enabling vector. 1210 */ 1211 if (maxlvt > 3) 1212 apic_write(APIC_ESR, 0); 1213 value = apic_read(APIC_ESR); 1214 if (value != oldvalue) 1215 apic_printk(APIC_VERBOSE, "ESR value before enabling " 1216 "vector: 0x%08x after: 0x%08x\n", 1217 oldvalue, value); 1218 } 1219 1220 /** 1221 * setup_local_APIC - setup the local APIC 1222 * 1223 * Used to setup local APIC while initializing BSP or bringin up APs. 1224 * Always called with preemption disabled. 1225 */ 1226 void __cpuinit setup_local_APIC(void) 1227 { 1228 int cpu = smp_processor_id(); 1229 unsigned int value, queued; 1230 int i, j, acked = 0; 1231 unsigned long long tsc = 0, ntsc; 1232 long long max_loops = cpu_khz; 1233 1234 if (cpu_has_tsc) 1235 rdtscll(tsc); 1236 1237 if (disable_apic) { 1238 disable_ioapic_support(); 1239 return; 1240 } 1241 1242 #ifdef CONFIG_X86_32 1243 /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1244 if (lapic_is_integrated() && apic->disable_esr) { 1245 apic_write(APIC_ESR, 0); 1246 apic_write(APIC_ESR, 0); 1247 apic_write(APIC_ESR, 0); 1248 apic_write(APIC_ESR, 0); 1249 } 1250 #endif 1251 perf_events_lapic_init(); 1252 1253 /* 1254 * Double-check whether this APIC is really registered. 1255 * This is meaningless in clustered apic mode, so we skip it. 1256 */ 1257 BUG_ON(!apic->apic_id_registered()); 1258 1259 /* 1260 * Intel recommends to set DFR, LDR and TPR before enabling 1261 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1262 * document number 292116). So here it goes... 1263 */ 1264 apic->init_apic_ldr(); 1265 1266 #ifdef CONFIG_X86_32 1267 /* 1268 * APIC LDR is initialized. If logical_apicid mapping was 1269 * initialized during get_smp_config(), make sure it matches the 1270 * actual value. 1271 */ 1272 i = early_per_cpu(x86_cpu_to_logical_apicid, cpu); 1273 WARN_ON(i != BAD_APICID && i != logical_smp_processor_id()); 1274 /* always use the value from LDR */ 1275 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 1276 logical_smp_processor_id(); 1277 1278 /* 1279 * Some NUMA implementations (NUMAQ) don't initialize apicid to 1280 * node mapping during NUMA init. Now that logical apicid is 1281 * guaranteed to be known, give it another chance. This is already 1282 * a bit too late - percpu allocation has already happened without 1283 * proper NUMA affinity. 1284 */ 1285 if (apic->x86_32_numa_cpu_node) 1286 set_apicid_to_node(early_per_cpu(x86_cpu_to_apicid, cpu), 1287 apic->x86_32_numa_cpu_node(cpu)); 1288 #endif 1289 1290 /* 1291 * Set Task Priority to 'accept all'. We never change this 1292 * later on. 1293 */ 1294 value = apic_read(APIC_TASKPRI); 1295 value &= ~APIC_TPRI_MASK; 1296 apic_write(APIC_TASKPRI, value); 1297 1298 /* 1299 * After a crash, we no longer service the interrupts and a pending 1300 * interrupt from previous kernel might still have ISR bit set. 1301 * 1302 * Most probably by now CPU has serviced that pending interrupt and 1303 * it might not have done the ack_APIC_irq() because it thought, 1304 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it 1305 * does not clear the ISR bit and cpu thinks it has already serivced 1306 * the interrupt. Hence a vector might get locked. It was noticed 1307 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. 1308 */ 1309 do { 1310 queued = 0; 1311 for (i = APIC_ISR_NR - 1; i >= 0; i--) 1312 queued |= apic_read(APIC_IRR + i*0x10); 1313 1314 for (i = APIC_ISR_NR - 1; i >= 0; i--) { 1315 value = apic_read(APIC_ISR + i*0x10); 1316 for (j = 31; j >= 0; j--) { 1317 if (value & (1<<j)) { 1318 ack_APIC_irq(); 1319 acked++; 1320 } 1321 } 1322 } 1323 if (acked > 256) { 1324 printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n", 1325 acked); 1326 break; 1327 } 1328 if (cpu_has_tsc) { 1329 rdtscll(ntsc); 1330 max_loops = (cpu_khz << 10) - (ntsc - tsc); 1331 } else 1332 max_loops--; 1333 } while (queued && max_loops > 0); 1334 WARN_ON(max_loops <= 0); 1335 1336 /* 1337 * Now that we are all set up, enable the APIC 1338 */ 1339 value = apic_read(APIC_SPIV); 1340 value &= ~APIC_VECTOR_MASK; 1341 /* 1342 * Enable APIC 1343 */ 1344 value |= APIC_SPIV_APIC_ENABLED; 1345 1346 #ifdef CONFIG_X86_32 1347 /* 1348 * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1349 * certain networking cards. If high frequency interrupts are 1350 * happening on a particular IOAPIC pin, plus the IOAPIC routing 1351 * entry is masked/unmasked at a high rate as well then sooner or 1352 * later IOAPIC line gets 'stuck', no more interrupts are received 1353 * from the device. If focus CPU is disabled then the hang goes 1354 * away, oh well :-( 1355 * 1356 * [ This bug can be reproduced easily with a level-triggered 1357 * PCI Ne2000 networking cards and PII/PIII processors, dual 1358 * BX chipset. ] 1359 */ 1360 /* 1361 * Actually disabling the focus CPU check just makes the hang less 1362 * frequent as it makes the interrupt distributon model be more 1363 * like LRU than MRU (the short-term load is more even across CPUs). 1364 * See also the comment in end_level_ioapic_irq(). --macro 1365 */ 1366 1367 /* 1368 * - enable focus processor (bit==0) 1369 * - 64bit mode always use processor focus 1370 * so no need to set it 1371 */ 1372 value &= ~APIC_SPIV_FOCUS_DISABLED; 1373 #endif 1374 1375 /* 1376 * Set spurious IRQ vector 1377 */ 1378 value |= SPURIOUS_APIC_VECTOR; 1379 apic_write(APIC_SPIV, value); 1380 1381 /* 1382 * Set up LVT0, LVT1: 1383 * 1384 * set up through-local-APIC on the BP's LINT0. This is not 1385 * strictly necessary in pure symmetric-IO mode, but sometimes 1386 * we delegate interrupts to the 8259A. 1387 */ 1388 /* 1389 * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1390 */ 1391 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 1392 if (!cpu && (pic_mode || !value)) { 1393 value = APIC_DM_EXTINT; 1394 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); 1395 } else { 1396 value = APIC_DM_EXTINT | APIC_LVT_MASKED; 1397 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); 1398 } 1399 apic_write(APIC_LVT0, value); 1400 1401 /* 1402 * only the BP should see the LINT1 NMI signal, obviously. 1403 */ 1404 if (!cpu) 1405 value = APIC_DM_NMI; 1406 else 1407 value = APIC_DM_NMI | APIC_LVT_MASKED; 1408 if (!lapic_is_integrated()) /* 82489DX */ 1409 value |= APIC_LVT_LEVEL_TRIGGER; 1410 apic_write(APIC_LVT1, value); 1411 1412 #ifdef CONFIG_X86_MCE_INTEL 1413 /* Recheck CMCI information after local APIC is up on CPU #0 */ 1414 if (!cpu) 1415 cmci_recheck(); 1416 #endif 1417 } 1418 1419 void __cpuinit end_local_APIC_setup(void) 1420 { 1421 lapic_setup_esr(); 1422 1423 #ifdef CONFIG_X86_32 1424 { 1425 unsigned int value; 1426 /* Disable the local apic timer */ 1427 value = apic_read(APIC_LVTT); 1428 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1429 apic_write(APIC_LVTT, value); 1430 } 1431 #endif 1432 1433 apic_pm_activate(); 1434 } 1435 1436 void __init bsp_end_local_APIC_setup(void) 1437 { 1438 end_local_APIC_setup(); 1439 1440 /* 1441 * Now that local APIC setup is completed for BP, configure the fault 1442 * handling for interrupt remapping. 1443 */ 1444 if (intr_remapping_enabled) 1445 enable_drhd_fault_handling(); 1446 1447 } 1448 1449 #ifdef CONFIG_X86_X2APIC 1450 /* 1451 * Need to disable xapic and x2apic at the same time and then enable xapic mode 1452 */ 1453 static inline void __disable_x2apic(u64 msr) 1454 { 1455 wrmsrl(MSR_IA32_APICBASE, 1456 msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); 1457 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); 1458 } 1459 1460 static __init void disable_x2apic(void) 1461 { 1462 u64 msr; 1463 1464 if (!cpu_has_x2apic) 1465 return; 1466 1467 rdmsrl(MSR_IA32_APICBASE, msr); 1468 if (msr & X2APIC_ENABLE) { 1469 u32 x2apic_id = read_apic_id(); 1470 1471 if (x2apic_id >= 255) 1472 panic("Cannot disable x2apic, id: %08x\n", x2apic_id); 1473 1474 pr_info("Disabling x2apic\n"); 1475 __disable_x2apic(msr); 1476 1477 if (nox2apic) { 1478 clear_cpu_cap(&cpu_data(0), X86_FEATURE_X2APIC); 1479 setup_clear_cpu_cap(X86_FEATURE_X2APIC); 1480 } 1481 1482 x2apic_disabled = 1; 1483 x2apic_mode = 0; 1484 1485 register_lapic_address(mp_lapic_addr); 1486 } 1487 } 1488 1489 void check_x2apic(void) 1490 { 1491 if (x2apic_enabled()) { 1492 pr_info("x2apic enabled by BIOS, switching to x2apic ops\n"); 1493 x2apic_preenabled = x2apic_mode = 1; 1494 } 1495 } 1496 1497 void enable_x2apic(void) 1498 { 1499 u64 msr; 1500 1501 rdmsrl(MSR_IA32_APICBASE, msr); 1502 if (x2apic_disabled) { 1503 __disable_x2apic(msr); 1504 return; 1505 } 1506 1507 if (!x2apic_mode) 1508 return; 1509 1510 if (!(msr & X2APIC_ENABLE)) { 1511 printk_once(KERN_INFO "Enabling x2apic\n"); 1512 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); 1513 } 1514 } 1515 #endif /* CONFIG_X86_X2APIC */ 1516 1517 int __init enable_IR(void) 1518 { 1519 #ifdef CONFIG_IRQ_REMAP 1520 if (!intr_remapping_supported()) { 1521 pr_debug("intr-remapping not supported\n"); 1522 return -1; 1523 } 1524 1525 if (!x2apic_preenabled && skip_ioapic_setup) { 1526 pr_info("Skipped enabling intr-remap because of skipping " 1527 "io-apic setup\n"); 1528 return -1; 1529 } 1530 1531 return enable_intr_remapping(); 1532 #endif 1533 return -1; 1534 } 1535 1536 void __init enable_IR_x2apic(void) 1537 { 1538 unsigned long flags; 1539 int ret, x2apic_enabled = 0; 1540 int dmar_table_init_ret; 1541 1542 dmar_table_init_ret = dmar_table_init(); 1543 if (dmar_table_init_ret && !x2apic_supported()) 1544 return; 1545 1546 ret = save_ioapic_entries(); 1547 if (ret) { 1548 pr_info("Saving IO-APIC state failed: %d\n", ret); 1549 return; 1550 } 1551 1552 local_irq_save(flags); 1553 legacy_pic->mask_all(); 1554 mask_ioapic_entries(); 1555 1556 if (x2apic_preenabled && nox2apic) 1557 disable_x2apic(); 1558 1559 if (dmar_table_init_ret) 1560 ret = -1; 1561 else 1562 ret = enable_IR(); 1563 1564 if (!x2apic_supported()) 1565 goto skip_x2apic; 1566 1567 if (ret < 0) { 1568 /* IR is required if there is APIC ID > 255 even when running 1569 * under KVM 1570 */ 1571 if (max_physical_apicid > 255 || 1572 !hypervisor_x2apic_available()) { 1573 if (x2apic_preenabled) 1574 disable_x2apic(); 1575 goto skip_x2apic; 1576 } 1577 /* 1578 * without IR all CPUs can be addressed by IOAPIC/MSI 1579 * only in physical mode 1580 */ 1581 x2apic_force_phys(); 1582 } 1583 1584 if (ret == IRQ_REMAP_XAPIC_MODE) { 1585 pr_info("x2apic not enabled, IRQ remapping is in xapic mode\n"); 1586 goto skip_x2apic; 1587 } 1588 1589 x2apic_enabled = 1; 1590 1591 if (x2apic_supported() && !x2apic_mode) { 1592 x2apic_mode = 1; 1593 enable_x2apic(); 1594 pr_info("Enabled x2apic\n"); 1595 } 1596 1597 skip_x2apic: 1598 if (ret < 0) /* IR enabling failed */ 1599 restore_ioapic_entries(); 1600 legacy_pic->restore_mask(); 1601 local_irq_restore(flags); 1602 } 1603 1604 #ifdef CONFIG_X86_64 1605 /* 1606 * Detect and enable local APICs on non-SMP boards. 1607 * Original code written by Keir Fraser. 1608 * On AMD64 we trust the BIOS - if it says no APIC it is likely 1609 * not correctly set up (usually the APIC timer won't work etc.) 1610 */ 1611 static int __init detect_init_APIC(void) 1612 { 1613 if (!cpu_has_apic) { 1614 pr_info("No local APIC present\n"); 1615 return -1; 1616 } 1617 1618 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1619 return 0; 1620 } 1621 #else 1622 1623 static int __init apic_verify(void) 1624 { 1625 u32 features, h, l; 1626 1627 /* 1628 * The APIC feature bit should now be enabled 1629 * in `cpuid' 1630 */ 1631 features = cpuid_edx(1); 1632 if (!(features & (1 << X86_FEATURE_APIC))) { 1633 pr_warning("Could not enable APIC!\n"); 1634 return -1; 1635 } 1636 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 1637 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1638 1639 /* The BIOS may have set up the APIC at some other address */ 1640 if (boot_cpu_data.x86 >= 6) { 1641 rdmsr(MSR_IA32_APICBASE, l, h); 1642 if (l & MSR_IA32_APICBASE_ENABLE) 1643 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 1644 } 1645 1646 pr_info("Found and enabled local APIC!\n"); 1647 return 0; 1648 } 1649 1650 int __init apic_force_enable(unsigned long addr) 1651 { 1652 u32 h, l; 1653 1654 if (disable_apic) 1655 return -1; 1656 1657 /* 1658 * Some BIOSes disable the local APIC in the APIC_BASE 1659 * MSR. This can only be done in software for Intel P6 or later 1660 * and AMD K7 (Model > 1) or later. 1661 */ 1662 if (boot_cpu_data.x86 >= 6) { 1663 rdmsr(MSR_IA32_APICBASE, l, h); 1664 if (!(l & MSR_IA32_APICBASE_ENABLE)) { 1665 pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 1666 l &= ~MSR_IA32_APICBASE_BASE; 1667 l |= MSR_IA32_APICBASE_ENABLE | addr; 1668 wrmsr(MSR_IA32_APICBASE, l, h); 1669 enabled_via_apicbase = 1; 1670 } 1671 } 1672 return apic_verify(); 1673 } 1674 1675 /* 1676 * Detect and initialize APIC 1677 */ 1678 static int __init detect_init_APIC(void) 1679 { 1680 /* Disabled by kernel option? */ 1681 if (disable_apic) 1682 return -1; 1683 1684 switch (boot_cpu_data.x86_vendor) { 1685 case X86_VENDOR_AMD: 1686 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 1687 (boot_cpu_data.x86 >= 15)) 1688 break; 1689 goto no_apic; 1690 case X86_VENDOR_INTEL: 1691 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 1692 (boot_cpu_data.x86 == 5 && cpu_has_apic)) 1693 break; 1694 goto no_apic; 1695 default: 1696 goto no_apic; 1697 } 1698 1699 if (!cpu_has_apic) { 1700 /* 1701 * Over-ride BIOS and try to enable the local APIC only if 1702 * "lapic" specified. 1703 */ 1704 if (!force_enable_local_apic) { 1705 pr_info("Local APIC disabled by BIOS -- " 1706 "you can enable it with \"lapic\"\n"); 1707 return -1; 1708 } 1709 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) 1710 return -1; 1711 } else { 1712 if (apic_verify()) 1713 return -1; 1714 } 1715 1716 apic_pm_activate(); 1717 1718 return 0; 1719 1720 no_apic: 1721 pr_info("No local APIC present or hardware disabled\n"); 1722 return -1; 1723 } 1724 #endif 1725 1726 /** 1727 * init_apic_mappings - initialize APIC mappings 1728 */ 1729 void __init init_apic_mappings(void) 1730 { 1731 unsigned int new_apicid; 1732 1733 if (x2apic_mode) { 1734 boot_cpu_physical_apicid = read_apic_id(); 1735 return; 1736 } 1737 1738 /* If no local APIC can be found return early */ 1739 if (!smp_found_config && detect_init_APIC()) { 1740 /* lets NOP'ify apic operations */ 1741 pr_info("APIC: disable apic facility\n"); 1742 apic_disable(); 1743 } else { 1744 apic_phys = mp_lapic_addr; 1745 1746 /* 1747 * acpi lapic path already maps that address in 1748 * acpi_register_lapic_address() 1749 */ 1750 if (!acpi_lapic && !smp_found_config) 1751 register_lapic_address(apic_phys); 1752 } 1753 1754 /* 1755 * Fetch the APIC ID of the BSP in case we have a 1756 * default configuration (or the MP table is broken). 1757 */ 1758 new_apicid = read_apic_id(); 1759 if (boot_cpu_physical_apicid != new_apicid) { 1760 boot_cpu_physical_apicid = new_apicid; 1761 /* 1762 * yeah -- we lie about apic_version 1763 * in case if apic was disabled via boot option 1764 * but it's not a problem for SMP compiled kernel 1765 * since smp_sanity_check is prepared for such a case 1766 * and disable smp mode 1767 */ 1768 apic_version[new_apicid] = 1769 GET_APIC_VERSION(apic_read(APIC_LVR)); 1770 } 1771 } 1772 1773 void __init register_lapic_address(unsigned long address) 1774 { 1775 mp_lapic_addr = address; 1776 1777 if (!x2apic_mode) { 1778 set_fixmap_nocache(FIX_APIC_BASE, address); 1779 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 1780 APIC_BASE, mp_lapic_addr); 1781 } 1782 if (boot_cpu_physical_apicid == -1U) { 1783 boot_cpu_physical_apicid = read_apic_id(); 1784 apic_version[boot_cpu_physical_apicid] = 1785 GET_APIC_VERSION(apic_read(APIC_LVR)); 1786 } 1787 } 1788 1789 /* 1790 * This initializes the IO-APIC and APIC hardware if this is 1791 * a UP kernel. 1792 */ 1793 int apic_version[MAX_LOCAL_APIC]; 1794 1795 int __init APIC_init_uniprocessor(void) 1796 { 1797 if (disable_apic) { 1798 pr_info("Apic disabled\n"); 1799 return -1; 1800 } 1801 #ifdef CONFIG_X86_64 1802 if (!cpu_has_apic) { 1803 disable_apic = 1; 1804 pr_info("Apic disabled by BIOS\n"); 1805 return -1; 1806 } 1807 #else 1808 if (!smp_found_config && !cpu_has_apic) 1809 return -1; 1810 1811 /* 1812 * Complain if the BIOS pretends there is one. 1813 */ 1814 if (!cpu_has_apic && 1815 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 1816 pr_err("BIOS bug, local APIC 0x%x not detected!...\n", 1817 boot_cpu_physical_apicid); 1818 return -1; 1819 } 1820 #endif 1821 1822 default_setup_apic_routing(); 1823 1824 verify_local_APIC(); 1825 connect_bsp_APIC(); 1826 1827 #ifdef CONFIG_X86_64 1828 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); 1829 #else 1830 /* 1831 * Hack: In case of kdump, after a crash, kernel might be booting 1832 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 1833 * might be zero if read from MP tables. Get it from LAPIC. 1834 */ 1835 # ifdef CONFIG_CRASH_DUMP 1836 boot_cpu_physical_apicid = read_apic_id(); 1837 # endif 1838 #endif 1839 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1840 setup_local_APIC(); 1841 1842 #ifdef CONFIG_X86_IO_APIC 1843 /* 1844 * Now enable IO-APICs, actually call clear_IO_APIC 1845 * We need clear_IO_APIC before enabling error vector 1846 */ 1847 if (!skip_ioapic_setup && nr_ioapics) 1848 enable_IO_APIC(); 1849 #endif 1850 1851 bsp_end_local_APIC_setup(); 1852 1853 #ifdef CONFIG_X86_IO_APIC 1854 if (smp_found_config && !skip_ioapic_setup && nr_ioapics) 1855 setup_IO_APIC(); 1856 else { 1857 nr_ioapics = 0; 1858 } 1859 #endif 1860 1861 x86_init.timers.setup_percpu_clockev(); 1862 return 0; 1863 } 1864 1865 /* 1866 * Local APIC interrupts 1867 */ 1868 1869 /* 1870 * This interrupt should _never_ happen with our APIC/SMP architecture 1871 */ 1872 void smp_spurious_interrupt(struct pt_regs *regs) 1873 { 1874 u32 v; 1875 1876 irq_enter(); 1877 exit_idle(); 1878 /* 1879 * Check if this really is a spurious interrupt and ACK it 1880 * if it is a vectored one. Just in case... 1881 * Spurious interrupts should not be ACKed. 1882 */ 1883 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); 1884 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) 1885 ack_APIC_irq(); 1886 1887 inc_irq_stat(irq_spurious_count); 1888 1889 /* see sw-dev-man vol 3, chapter 7.4.13.5 */ 1890 pr_info("spurious APIC interrupt on CPU#%d, " 1891 "should never happen.\n", smp_processor_id()); 1892 irq_exit(); 1893 } 1894 1895 /* 1896 * This interrupt should never happen with our APIC/SMP architecture 1897 */ 1898 void smp_error_interrupt(struct pt_regs *regs) 1899 { 1900 u32 v0, v1; 1901 u32 i = 0; 1902 static const char * const error_interrupt_reason[] = { 1903 "Send CS error", /* APIC Error Bit 0 */ 1904 "Receive CS error", /* APIC Error Bit 1 */ 1905 "Send accept error", /* APIC Error Bit 2 */ 1906 "Receive accept error", /* APIC Error Bit 3 */ 1907 "Redirectable IPI", /* APIC Error Bit 4 */ 1908 "Send illegal vector", /* APIC Error Bit 5 */ 1909 "Received illegal vector", /* APIC Error Bit 6 */ 1910 "Illegal register address", /* APIC Error Bit 7 */ 1911 }; 1912 1913 irq_enter(); 1914 exit_idle(); 1915 /* First tickle the hardware, only then report what went on. -- REW */ 1916 v0 = apic_read(APIC_ESR); 1917 apic_write(APIC_ESR, 0); 1918 v1 = apic_read(APIC_ESR); 1919 ack_APIC_irq(); 1920 atomic_inc(&irq_err_count); 1921 1922 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x(%02x)", 1923 smp_processor_id(), v0 , v1); 1924 1925 v1 = v1 & 0xff; 1926 while (v1) { 1927 if (v1 & 0x1) 1928 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); 1929 i++; 1930 v1 >>= 1; 1931 }; 1932 1933 apic_printk(APIC_DEBUG, KERN_CONT "\n"); 1934 1935 irq_exit(); 1936 } 1937 1938 /** 1939 * connect_bsp_APIC - attach the APIC to the interrupt system 1940 */ 1941 void __init connect_bsp_APIC(void) 1942 { 1943 #ifdef CONFIG_X86_32 1944 if (pic_mode) { 1945 /* 1946 * Do not trust the local APIC being empty at bootup. 1947 */ 1948 clear_local_APIC(); 1949 /* 1950 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 1951 * local APIC to INT and NMI lines. 1952 */ 1953 apic_printk(APIC_VERBOSE, "leaving PIC mode, " 1954 "enabling APIC mode.\n"); 1955 imcr_pic_to_apic(); 1956 } 1957 #endif 1958 if (apic->enable_apic_mode) 1959 apic->enable_apic_mode(); 1960 } 1961 1962 /** 1963 * disconnect_bsp_APIC - detach the APIC from the interrupt system 1964 * @virt_wire_setup: indicates, whether virtual wire mode is selected 1965 * 1966 * Virtual wire mode is necessary to deliver legacy interrupts even when the 1967 * APIC is disabled. 1968 */ 1969 void disconnect_bsp_APIC(int virt_wire_setup) 1970 { 1971 unsigned int value; 1972 1973 #ifdef CONFIG_X86_32 1974 if (pic_mode) { 1975 /* 1976 * Put the board back into PIC mode (has an effect only on 1977 * certain older boards). Note that APIC interrupts, including 1978 * IPIs, won't work beyond this point! The only exception are 1979 * INIT IPIs. 1980 */ 1981 apic_printk(APIC_VERBOSE, "disabling APIC mode, " 1982 "entering PIC mode.\n"); 1983 imcr_apic_to_pic(); 1984 return; 1985 } 1986 #endif 1987 1988 /* Go back to Virtual Wire compatibility mode */ 1989 1990 /* For the spurious interrupt use vector F, and enable it */ 1991 value = apic_read(APIC_SPIV); 1992 value &= ~APIC_VECTOR_MASK; 1993 value |= APIC_SPIV_APIC_ENABLED; 1994 value |= 0xf; 1995 apic_write(APIC_SPIV, value); 1996 1997 if (!virt_wire_setup) { 1998 /* 1999 * For LVT0 make it edge triggered, active high, 2000 * external and enabled 2001 */ 2002 value = apic_read(APIC_LVT0); 2003 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2004 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2005 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2006 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2007 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 2008 apic_write(APIC_LVT0, value); 2009 } else { 2010 /* Disable LVT0 */ 2011 apic_write(APIC_LVT0, APIC_LVT_MASKED); 2012 } 2013 2014 /* 2015 * For LVT1 make it edge triggered, active high, 2016 * nmi and enabled 2017 */ 2018 value = apic_read(APIC_LVT1); 2019 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2020 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2021 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2022 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2023 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 2024 apic_write(APIC_LVT1, value); 2025 } 2026 2027 void __cpuinit generic_processor_info(int apicid, int version) 2028 { 2029 int cpu, max = nr_cpu_ids; 2030 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, 2031 phys_cpu_present_map); 2032 2033 /* 2034 * If boot cpu has not been detected yet, then only allow upto 2035 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu 2036 */ 2037 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && 2038 apicid != boot_cpu_physical_apicid) { 2039 int thiscpu = max + disabled_cpus - 1; 2040 2041 pr_warning( 2042 "ACPI: NR_CPUS/possible_cpus limit of %i almost" 2043 " reached. Keeping one slot for boot cpu." 2044 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 2045 2046 disabled_cpus++; 2047 return; 2048 } 2049 2050 if (num_processors >= nr_cpu_ids) { 2051 int thiscpu = max + disabled_cpus; 2052 2053 pr_warning( 2054 "ACPI: NR_CPUS/possible_cpus limit of %i reached." 2055 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 2056 2057 disabled_cpus++; 2058 return; 2059 } 2060 2061 num_processors++; 2062 if (apicid == boot_cpu_physical_apicid) { 2063 /* 2064 * x86_bios_cpu_apicid is required to have processors listed 2065 * in same order as logical cpu numbers. Hence the first 2066 * entry is BSP, and so on. 2067 * boot_cpu_init() already hold bit 0 in cpu_present_mask 2068 * for BSP. 2069 */ 2070 cpu = 0; 2071 } else 2072 cpu = cpumask_next_zero(-1, cpu_present_mask); 2073 2074 /* 2075 * Validate version 2076 */ 2077 if (version == 0x0) { 2078 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", 2079 cpu, apicid); 2080 version = 0x10; 2081 } 2082 apic_version[apicid] = version; 2083 2084 if (version != apic_version[boot_cpu_physical_apicid]) { 2085 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", 2086 apic_version[boot_cpu_physical_apicid], cpu, version); 2087 } 2088 2089 physid_set(apicid, phys_cpu_present_map); 2090 if (apicid > max_physical_apicid) 2091 max_physical_apicid = apicid; 2092 2093 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 2094 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 2095 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 2096 #endif 2097 #ifdef CONFIG_X86_32 2098 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 2099 apic->x86_32_early_logical_apicid(cpu); 2100 #endif 2101 set_cpu_possible(cpu, true); 2102 set_cpu_present(cpu, true); 2103 } 2104 2105 int hard_smp_processor_id(void) 2106 { 2107 return read_apic_id(); 2108 } 2109 2110 void default_init_apic_ldr(void) 2111 { 2112 unsigned long val; 2113 2114 apic_write(APIC_DFR, APIC_DFR_VALUE); 2115 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; 2116 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); 2117 apic_write(APIC_LDR, val); 2118 } 2119 2120 /* 2121 * Power management 2122 */ 2123 #ifdef CONFIG_PM 2124 2125 static struct { 2126 /* 2127 * 'active' is true if the local APIC was enabled by us and 2128 * not the BIOS; this signifies that we are also responsible 2129 * for disabling it before entering apm/acpi suspend 2130 */ 2131 int active; 2132 /* r/w apic fields */ 2133 unsigned int apic_id; 2134 unsigned int apic_taskpri; 2135 unsigned int apic_ldr; 2136 unsigned int apic_dfr; 2137 unsigned int apic_spiv; 2138 unsigned int apic_lvtt; 2139 unsigned int apic_lvtpc; 2140 unsigned int apic_lvt0; 2141 unsigned int apic_lvt1; 2142 unsigned int apic_lvterr; 2143 unsigned int apic_tmict; 2144 unsigned int apic_tdcr; 2145 unsigned int apic_thmr; 2146 } apic_pm_state; 2147 2148 static int lapic_suspend(void) 2149 { 2150 unsigned long flags; 2151 int maxlvt; 2152 2153 if (!apic_pm_state.active) 2154 return 0; 2155 2156 maxlvt = lapic_get_maxlvt(); 2157 2158 apic_pm_state.apic_id = apic_read(APIC_ID); 2159 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 2160 apic_pm_state.apic_ldr = apic_read(APIC_LDR); 2161 apic_pm_state.apic_dfr = apic_read(APIC_DFR); 2162 apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2163 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2164 if (maxlvt >= 4) 2165 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2166 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2167 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2168 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2169 apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2170 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 2171 #ifdef CONFIG_X86_THERMAL_VECTOR 2172 if (maxlvt >= 5) 2173 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2174 #endif 2175 2176 local_irq_save(flags); 2177 disable_local_APIC(); 2178 2179 if (intr_remapping_enabled) 2180 disable_intr_remapping(); 2181 2182 local_irq_restore(flags); 2183 return 0; 2184 } 2185 2186 static void lapic_resume(void) 2187 { 2188 unsigned int l, h; 2189 unsigned long flags; 2190 int maxlvt; 2191 2192 if (!apic_pm_state.active) 2193 return; 2194 2195 local_irq_save(flags); 2196 if (intr_remapping_enabled) { 2197 /* 2198 * IO-APIC and PIC have their own resume routines. 2199 * We just mask them here to make sure the interrupt 2200 * subsystem is completely quiet while we enable x2apic 2201 * and interrupt-remapping. 2202 */ 2203 mask_ioapic_entries(); 2204 legacy_pic->mask_all(); 2205 } 2206 2207 if (x2apic_mode) 2208 enable_x2apic(); 2209 else { 2210 /* 2211 * Make sure the APICBASE points to the right address 2212 * 2213 * FIXME! This will be wrong if we ever support suspend on 2214 * SMP! We'll need to do this as part of the CPU restore! 2215 */ 2216 if (boot_cpu_data.x86 >= 6) { 2217 rdmsr(MSR_IA32_APICBASE, l, h); 2218 l &= ~MSR_IA32_APICBASE_BASE; 2219 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2220 wrmsr(MSR_IA32_APICBASE, l, h); 2221 } 2222 } 2223 2224 maxlvt = lapic_get_maxlvt(); 2225 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2226 apic_write(APIC_ID, apic_pm_state.apic_id); 2227 apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2228 apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2229 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2230 apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2231 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2232 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 2233 #if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL) 2234 if (maxlvt >= 5) 2235 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2236 #endif 2237 if (maxlvt >= 4) 2238 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2239 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2240 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2241 apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2242 apic_write(APIC_ESR, 0); 2243 apic_read(APIC_ESR); 2244 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2245 apic_write(APIC_ESR, 0); 2246 apic_read(APIC_ESR); 2247 2248 if (intr_remapping_enabled) 2249 reenable_intr_remapping(x2apic_mode); 2250 2251 local_irq_restore(flags); 2252 } 2253 2254 /* 2255 * This device has no shutdown method - fully functioning local APICs 2256 * are needed on every CPU up until machine_halt/restart/poweroff. 2257 */ 2258 2259 static struct syscore_ops lapic_syscore_ops = { 2260 .resume = lapic_resume, 2261 .suspend = lapic_suspend, 2262 }; 2263 2264 static void __cpuinit apic_pm_activate(void) 2265 { 2266 apic_pm_state.active = 1; 2267 } 2268 2269 static int __init init_lapic_sysfs(void) 2270 { 2271 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 2272 if (cpu_has_apic) 2273 register_syscore_ops(&lapic_syscore_ops); 2274 2275 return 0; 2276 } 2277 2278 /* local apic needs to resume before other devices access its registers. */ 2279 core_initcall(init_lapic_sysfs); 2280 2281 #else /* CONFIG_PM */ 2282 2283 static void apic_pm_activate(void) { } 2284 2285 #endif /* CONFIG_PM */ 2286 2287 #ifdef CONFIG_X86_64 2288 2289 static int __cpuinit apic_cluster_num(void) 2290 { 2291 int i, clusters, zeros; 2292 unsigned id; 2293 u16 *bios_cpu_apicid; 2294 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS); 2295 2296 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid); 2297 bitmap_zero(clustermap, NUM_APIC_CLUSTERS); 2298 2299 for (i = 0; i < nr_cpu_ids; i++) { 2300 /* are we being called early in kernel startup? */ 2301 if (bios_cpu_apicid) { 2302 id = bios_cpu_apicid[i]; 2303 } else if (i < nr_cpu_ids) { 2304 if (cpu_present(i)) 2305 id = per_cpu(x86_bios_cpu_apicid, i); 2306 else 2307 continue; 2308 } else 2309 break; 2310 2311 if (id != BAD_APICID) 2312 __set_bit(APIC_CLUSTERID(id), clustermap); 2313 } 2314 2315 /* Problem: Partially populated chassis may not have CPUs in some of 2316 * the APIC clusters they have been allocated. Only present CPUs have 2317 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap. 2318 * Since clusters are allocated sequentially, count zeros only if 2319 * they are bounded by ones. 2320 */ 2321 clusters = 0; 2322 zeros = 0; 2323 for (i = 0; i < NUM_APIC_CLUSTERS; i++) { 2324 if (test_bit(i, clustermap)) { 2325 clusters += 1 + zeros; 2326 zeros = 0; 2327 } else 2328 ++zeros; 2329 } 2330 2331 return clusters; 2332 } 2333 2334 static int __cpuinitdata multi_checked; 2335 static int __cpuinitdata multi; 2336 2337 static int __cpuinit set_multi(const struct dmi_system_id *d) 2338 { 2339 if (multi) 2340 return 0; 2341 pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2342 multi = 1; 2343 return 0; 2344 } 2345 2346 static const __cpuinitconst struct dmi_system_id multi_dmi_table[] = { 2347 { 2348 .callback = set_multi, 2349 .ident = "IBM System Summit2", 2350 .matches = { 2351 DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2352 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2353 }, 2354 }, 2355 {} 2356 }; 2357 2358 static void __cpuinit dmi_check_multi(void) 2359 { 2360 if (multi_checked) 2361 return; 2362 2363 dmi_check_system(multi_dmi_table); 2364 multi_checked = 1; 2365 } 2366 2367 /* 2368 * apic_is_clustered_box() -- Check if we can expect good TSC 2369 * 2370 * Thus far, the major user of this is IBM's Summit2 series: 2371 * Clustered boxes may have unsynced TSC problems if they are 2372 * multi-chassis. 2373 * Use DMI to check them 2374 */ 2375 __cpuinit int apic_is_clustered_box(void) 2376 { 2377 dmi_check_multi(); 2378 if (multi) 2379 return 1; 2380 2381 if (!is_vsmp_box()) 2382 return 0; 2383 2384 /* 2385 * ScaleMP vSMPowered boxes have one cluster per board and TSCs are 2386 * not guaranteed to be synced between boards 2387 */ 2388 if (apic_cluster_num() > 1) 2389 return 1; 2390 2391 return 0; 2392 } 2393 #endif 2394 2395 /* 2396 * APIC command line parameters 2397 */ 2398 static int __init setup_disableapic(char *arg) 2399 { 2400 disable_apic = 1; 2401 setup_clear_cpu_cap(X86_FEATURE_APIC); 2402 return 0; 2403 } 2404 early_param("disableapic", setup_disableapic); 2405 2406 /* same as disableapic, for compatibility */ 2407 static int __init setup_nolapic(char *arg) 2408 { 2409 return setup_disableapic(arg); 2410 } 2411 early_param("nolapic", setup_nolapic); 2412 2413 static int __init parse_lapic_timer_c2_ok(char *arg) 2414 { 2415 local_apic_timer_c2_ok = 1; 2416 return 0; 2417 } 2418 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2419 2420 static int __init parse_disable_apic_timer(char *arg) 2421 { 2422 disable_apic_timer = 1; 2423 return 0; 2424 } 2425 early_param("noapictimer", parse_disable_apic_timer); 2426 2427 static int __init parse_nolapic_timer(char *arg) 2428 { 2429 disable_apic_timer = 1; 2430 return 0; 2431 } 2432 early_param("nolapic_timer", parse_nolapic_timer); 2433 2434 static int __init apic_set_verbosity(char *arg) 2435 { 2436 if (!arg) { 2437 #ifdef CONFIG_X86_64 2438 skip_ioapic_setup = 0; 2439 return 0; 2440 #endif 2441 return -EINVAL; 2442 } 2443 2444 if (strcmp("debug", arg) == 0) 2445 apic_verbosity = APIC_DEBUG; 2446 else if (strcmp("verbose", arg) == 0) 2447 apic_verbosity = APIC_VERBOSE; 2448 else { 2449 pr_warning("APIC Verbosity level %s not recognised" 2450 " use apic=verbose or apic=debug\n", arg); 2451 return -EINVAL; 2452 } 2453 2454 return 0; 2455 } 2456 early_param("apic", apic_set_verbosity); 2457 2458 static int __init lapic_insert_resource(void) 2459 { 2460 if (!apic_phys) 2461 return -1; 2462 2463 /* Put local APIC into the resource map. */ 2464 lapic_resource.start = apic_phys; 2465 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2466 insert_resource(&iomem_resource, &lapic_resource); 2467 2468 return 0; 2469 } 2470 2471 /* 2472 * need call insert after e820_reserve_resources() 2473 * that is using request_resource 2474 */ 2475 late_initcall(lapic_insert_resource); 2476