1 /* 2 * Local APIC handling, local APIC timers 3 * 4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 5 * 6 * Fixes 7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 8 * thanks to Eric Gilmore 9 * and Rolf G. Tews 10 * for testing these extensively. 11 * Maciej W. Rozycki : Various updates and fixes. 12 * Mikael Pettersson : Power Management for UP-APIC. 13 * Pavel Machek and 14 * Mikael Pettersson : PM converted to driver model. 15 */ 16 17 #include <linux/perf_event.h> 18 #include <linux/kernel_stat.h> 19 #include <linux/mc146818rtc.h> 20 #include <linux/acpi_pmtmr.h> 21 #include <linux/clockchips.h> 22 #include <linux/interrupt.h> 23 #include <linux/memblock.h> 24 #include <linux/ftrace.h> 25 #include <linux/ioport.h> 26 #include <linux/export.h> 27 #include <linux/syscore_ops.h> 28 #include <linux/delay.h> 29 #include <linux/timex.h> 30 #include <linux/i8253.h> 31 #include <linux/dmar.h> 32 #include <linux/init.h> 33 #include <linux/cpu.h> 34 #include <linux/dmi.h> 35 #include <linux/smp.h> 36 #include <linux/mm.h> 37 38 #include <asm/trace/irq_vectors.h> 39 #include <asm/irq_remapping.h> 40 #include <asm/perf_event.h> 41 #include <asm/x86_init.h> 42 #include <asm/pgalloc.h> 43 #include <linux/atomic.h> 44 #include <asm/mpspec.h> 45 #include <asm/i8259.h> 46 #include <asm/proto.h> 47 #include <asm/apic.h> 48 #include <asm/io_apic.h> 49 #include <asm/desc.h> 50 #include <asm/hpet.h> 51 #include <asm/mtrr.h> 52 #include <asm/time.h> 53 #include <asm/smp.h> 54 #include <asm/mce.h> 55 #include <asm/tsc.h> 56 #include <asm/hypervisor.h> 57 #include <asm/cpu_device_id.h> 58 #include <asm/intel-family.h> 59 #include <asm/irq_regs.h> 60 61 unsigned int num_processors; 62 63 unsigned disabled_cpus; 64 65 /* Processor that is doing the boot up */ 66 unsigned int boot_cpu_physical_apicid = -1U; 67 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); 68 69 u8 boot_cpu_apic_version; 70 71 /* 72 * The highest APIC ID seen during enumeration. 73 */ 74 static unsigned int max_physical_apicid; 75 76 /* 77 * Bitmask of physically existing CPUs: 78 */ 79 physid_mask_t phys_cpu_present_map; 80 81 /* 82 * Processor to be disabled specified by kernel parameter 83 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to 84 * avoid undefined behaviour caused by sending INIT from AP to BSP. 85 */ 86 static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID; 87 88 /* 89 * This variable controls which CPUs receive external NMIs. By default, 90 * external NMIs are delivered only to the BSP. 91 */ 92 static int apic_extnmi = APIC_EXTNMI_BSP; 93 94 /* 95 * Map cpu index to physical APIC ID 96 */ 97 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); 98 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID); 99 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX); 100 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 101 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 102 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid); 103 104 #ifdef CONFIG_X86_32 105 106 /* 107 * On x86_32, the mapping between cpu and logical apicid may vary 108 * depending on apic in use. The following early percpu variable is 109 * used for the mapping. This is where the behaviors of x86_64 and 32 110 * actually diverge. Let's keep it ugly for now. 111 */ 112 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID); 113 114 /* Local APIC was disabled by the BIOS and enabled by the kernel */ 115 static int enabled_via_apicbase; 116 117 /* 118 * Handle interrupt mode configuration register (IMCR). 119 * This register controls whether the interrupt signals 120 * that reach the BSP come from the master PIC or from the 121 * local APIC. Before entering Symmetric I/O Mode, either 122 * the BIOS or the operating system must switch out of 123 * PIC Mode by changing the IMCR. 124 */ 125 static inline void imcr_pic_to_apic(void) 126 { 127 /* select IMCR register */ 128 outb(0x70, 0x22); 129 /* NMI and 8259 INTR go through APIC */ 130 outb(0x01, 0x23); 131 } 132 133 static inline void imcr_apic_to_pic(void) 134 { 135 /* select IMCR register */ 136 outb(0x70, 0x22); 137 /* NMI and 8259 INTR go directly to BSP */ 138 outb(0x00, 0x23); 139 } 140 #endif 141 142 /* 143 * Knob to control our willingness to enable the local APIC. 144 * 145 * +1=force-enable 146 */ 147 static int force_enable_local_apic __initdata; 148 149 /* 150 * APIC command line parameters 151 */ 152 static int __init parse_lapic(char *arg) 153 { 154 if (IS_ENABLED(CONFIG_X86_32) && !arg) 155 force_enable_local_apic = 1; 156 else if (arg && !strncmp(arg, "notscdeadline", 13)) 157 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 158 return 0; 159 } 160 early_param("lapic", parse_lapic); 161 162 #ifdef CONFIG_X86_64 163 static int apic_calibrate_pmtmr __initdata; 164 static __init int setup_apicpmtimer(char *s) 165 { 166 apic_calibrate_pmtmr = 1; 167 notsc_setup(NULL); 168 return 0; 169 } 170 __setup("apicpmtimer", setup_apicpmtimer); 171 #endif 172 173 unsigned long mp_lapic_addr; 174 int disable_apic; 175 /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 176 static int disable_apic_timer __initdata; 177 /* Local APIC timer works in C2 */ 178 int local_apic_timer_c2_ok; 179 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 180 181 /* 182 * Debug level, exported for io_apic.c 183 */ 184 unsigned int apic_verbosity; 185 186 int pic_mode; 187 188 /* Have we found an MP table */ 189 int smp_found_config; 190 191 static struct resource lapic_resource = { 192 .name = "Local APIC", 193 .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 194 }; 195 196 unsigned int lapic_timer_frequency = 0; 197 198 static void apic_pm_activate(void); 199 200 static unsigned long apic_phys; 201 202 /* 203 * Get the LAPIC version 204 */ 205 static inline int lapic_get_version(void) 206 { 207 return GET_APIC_VERSION(apic_read(APIC_LVR)); 208 } 209 210 /* 211 * Check, if the APIC is integrated or a separate chip 212 */ 213 static inline int lapic_is_integrated(void) 214 { 215 return APIC_INTEGRATED(lapic_get_version()); 216 } 217 218 /* 219 * Check, whether this is a modern or a first generation APIC 220 */ 221 static int modern_apic(void) 222 { 223 /* AMD systems use old APIC versions, so check the CPU */ 224 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 225 boot_cpu_data.x86 >= 0xf) 226 return 1; 227 228 /* Hygon systems use modern APIC */ 229 if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 230 return 1; 231 232 return lapic_get_version() >= 0x14; 233 } 234 235 /* 236 * right after this call apic become NOOP driven 237 * so apic->write/read doesn't do anything 238 */ 239 static void __init apic_disable(void) 240 { 241 pr_info("APIC: switched to apic NOOP\n"); 242 apic = &apic_noop; 243 } 244 245 void native_apic_wait_icr_idle(void) 246 { 247 while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 248 cpu_relax(); 249 } 250 251 u32 native_safe_apic_wait_icr_idle(void) 252 { 253 u32 send_status; 254 int timeout; 255 256 timeout = 0; 257 do { 258 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 259 if (!send_status) 260 break; 261 inc_irq_stat(icr_read_retry_count); 262 udelay(100); 263 } while (timeout++ < 1000); 264 265 return send_status; 266 } 267 268 void native_apic_icr_write(u32 low, u32 id) 269 { 270 unsigned long flags; 271 272 local_irq_save(flags); 273 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 274 apic_write(APIC_ICR, low); 275 local_irq_restore(flags); 276 } 277 278 u64 native_apic_icr_read(void) 279 { 280 u32 icr1, icr2; 281 282 icr2 = apic_read(APIC_ICR2); 283 icr1 = apic_read(APIC_ICR); 284 285 return icr1 | ((u64)icr2 << 32); 286 } 287 288 #ifdef CONFIG_X86_32 289 /** 290 * get_physical_broadcast - Get number of physical broadcast IDs 291 */ 292 int get_physical_broadcast(void) 293 { 294 return modern_apic() ? 0xff : 0xf; 295 } 296 #endif 297 298 /** 299 * lapic_get_maxlvt - get the maximum number of local vector table entries 300 */ 301 int lapic_get_maxlvt(void) 302 { 303 /* 304 * - we always have APIC integrated on 64bit mode 305 * - 82489DXs do not report # of LVT entries 306 */ 307 return lapic_is_integrated() ? GET_APIC_MAXLVT(apic_read(APIC_LVR)) : 2; 308 } 309 310 /* 311 * Local APIC timer 312 */ 313 314 /* Clock divisor */ 315 #define APIC_DIVISOR 16 316 #define TSC_DIVISOR 8 317 318 /* 319 * This function sets up the local APIC timer, with a timeout of 320 * 'clocks' APIC bus clock. During calibration we actually call 321 * this function twice on the boot CPU, once with a bogus timeout 322 * value, second time for real. The other (noncalibrating) CPUs 323 * call this function only once, with the real, calibrated value. 324 * 325 * We do reads before writes even if unnecessary, to get around the 326 * P5 APIC double write bug. 327 */ 328 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 329 { 330 unsigned int lvtt_value, tmp_value; 331 332 lvtt_value = LOCAL_TIMER_VECTOR; 333 if (!oneshot) 334 lvtt_value |= APIC_LVT_TIMER_PERIODIC; 335 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 336 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE; 337 338 if (!lapic_is_integrated()) 339 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 340 341 if (!irqen) 342 lvtt_value |= APIC_LVT_MASKED; 343 344 apic_write(APIC_LVTT, lvtt_value); 345 346 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { 347 /* 348 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, 349 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized. 350 * According to Intel, MFENCE can do the serialization here. 351 */ 352 asm volatile("mfence" : : : "memory"); 353 354 printk_once(KERN_DEBUG "TSC deadline timer enabled\n"); 355 return; 356 } 357 358 /* 359 * Divide PICLK by 16 360 */ 361 tmp_value = apic_read(APIC_TDCR); 362 apic_write(APIC_TDCR, 363 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 364 APIC_TDR_DIV_16); 365 366 if (!oneshot) 367 apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 368 } 369 370 /* 371 * Setup extended LVT, AMD specific 372 * 373 * Software should use the LVT offsets the BIOS provides. The offsets 374 * are determined by the subsystems using it like those for MCE 375 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts 376 * are supported. Beginning with family 10h at least 4 offsets are 377 * available. 378 * 379 * Since the offsets must be consistent for all cores, we keep track 380 * of the LVT offsets in software and reserve the offset for the same 381 * vector also to be used on other cores. An offset is freed by 382 * setting the entry to APIC_EILVT_MASKED. 383 * 384 * If the BIOS is right, there should be no conflicts. Otherwise a 385 * "[Firmware Bug]: ..." error message is generated. However, if 386 * software does not properly determines the offsets, it is not 387 * necessarily a BIOS bug. 388 */ 389 390 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; 391 392 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) 393 { 394 return (old & APIC_EILVT_MASKED) 395 || (new == APIC_EILVT_MASKED) 396 || ((new & ~APIC_EILVT_MASKED) == old); 397 } 398 399 static unsigned int reserve_eilvt_offset(int offset, unsigned int new) 400 { 401 unsigned int rsvd, vector; 402 403 if (offset >= APIC_EILVT_NR_MAX) 404 return ~0; 405 406 rsvd = atomic_read(&eilvt_offsets[offset]); 407 do { 408 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ 409 if (vector && !eilvt_entry_is_changeable(vector, new)) 410 /* may not change if vectors are different */ 411 return rsvd; 412 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); 413 } while (rsvd != new); 414 415 rsvd &= ~APIC_EILVT_MASKED; 416 if (rsvd && rsvd != vector) 417 pr_info("LVT offset %d assigned for vector 0x%02x\n", 418 offset, rsvd); 419 420 return new; 421 } 422 423 /* 424 * If mask=1, the LVT entry does not generate interrupts while mask=0 425 * enables the vector. See also the BKDGs. Must be called with 426 * preemption disabled. 427 */ 428 429 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) 430 { 431 unsigned long reg = APIC_EILVTn(offset); 432 unsigned int new, old, reserved; 433 434 new = (mask << 16) | (msg_type << 8) | vector; 435 old = apic_read(reg); 436 reserved = reserve_eilvt_offset(offset, new); 437 438 if (reserved != new) { 439 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 440 "vector 0x%x, but the register is already in use for " 441 "vector 0x%x on another cpu\n", 442 smp_processor_id(), reg, offset, new, reserved); 443 return -EINVAL; 444 } 445 446 if (!eilvt_entry_is_changeable(old, new)) { 447 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 448 "vector 0x%x, but the register is already in use for " 449 "vector 0x%x on this cpu\n", 450 smp_processor_id(), reg, offset, new, old); 451 return -EBUSY; 452 } 453 454 apic_write(reg, new); 455 456 return 0; 457 } 458 EXPORT_SYMBOL_GPL(setup_APIC_eilvt); 459 460 /* 461 * Program the next event, relative to now 462 */ 463 static int lapic_next_event(unsigned long delta, 464 struct clock_event_device *evt) 465 { 466 apic_write(APIC_TMICT, delta); 467 return 0; 468 } 469 470 static int lapic_next_deadline(unsigned long delta, 471 struct clock_event_device *evt) 472 { 473 u64 tsc; 474 475 tsc = rdtsc(); 476 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); 477 return 0; 478 } 479 480 static int lapic_timer_shutdown(struct clock_event_device *evt) 481 { 482 unsigned int v; 483 484 /* Lapic used as dummy for broadcast ? */ 485 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 486 return 0; 487 488 v = apic_read(APIC_LVTT); 489 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 490 apic_write(APIC_LVTT, v); 491 apic_write(APIC_TMICT, 0); 492 return 0; 493 } 494 495 static inline int 496 lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot) 497 { 498 /* Lapic used as dummy for broadcast ? */ 499 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 500 return 0; 501 502 __setup_APIC_LVTT(lapic_timer_frequency, oneshot, 1); 503 return 0; 504 } 505 506 static int lapic_timer_set_periodic(struct clock_event_device *evt) 507 { 508 return lapic_timer_set_periodic_oneshot(evt, false); 509 } 510 511 static int lapic_timer_set_oneshot(struct clock_event_device *evt) 512 { 513 return lapic_timer_set_periodic_oneshot(evt, true); 514 } 515 516 /* 517 * Local APIC timer broadcast function 518 */ 519 static void lapic_timer_broadcast(const struct cpumask *mask) 520 { 521 #ifdef CONFIG_SMP 522 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 523 #endif 524 } 525 526 527 /* 528 * The local apic timer can be used for any function which is CPU local. 529 */ 530 static struct clock_event_device lapic_clockevent = { 531 .name = "lapic", 532 .features = CLOCK_EVT_FEAT_PERIODIC | 533 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP 534 | CLOCK_EVT_FEAT_DUMMY, 535 .shift = 32, 536 .set_state_shutdown = lapic_timer_shutdown, 537 .set_state_periodic = lapic_timer_set_periodic, 538 .set_state_oneshot = lapic_timer_set_oneshot, 539 .set_state_oneshot_stopped = lapic_timer_shutdown, 540 .set_next_event = lapic_next_event, 541 .broadcast = lapic_timer_broadcast, 542 .rating = 100, 543 .irq = -1, 544 }; 545 static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 546 547 #define DEADLINE_MODEL_MATCH_FUNC(model, func) \ 548 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&func } 549 550 #define DEADLINE_MODEL_MATCH_REV(model, rev) \ 551 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)rev } 552 553 static u32 hsx_deadline_rev(void) 554 { 555 switch (boot_cpu_data.x86_stepping) { 556 case 0x02: return 0x3a; /* EP */ 557 case 0x04: return 0x0f; /* EX */ 558 } 559 560 return ~0U; 561 } 562 563 static u32 bdx_deadline_rev(void) 564 { 565 switch (boot_cpu_data.x86_stepping) { 566 case 0x02: return 0x00000011; 567 case 0x03: return 0x0700000e; 568 case 0x04: return 0x0f00000c; 569 case 0x05: return 0x0e000003; 570 } 571 572 return ~0U; 573 } 574 575 static u32 skx_deadline_rev(void) 576 { 577 switch (boot_cpu_data.x86_stepping) { 578 case 0x03: return 0x01000136; 579 case 0x04: return 0x02000014; 580 } 581 582 if (boot_cpu_data.x86_stepping > 4) 583 return 0; 584 585 return ~0U; 586 } 587 588 static const struct x86_cpu_id deadline_match[] = { 589 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_HASWELL_X, hsx_deadline_rev), 590 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_X, 0x0b000020), 591 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_BROADWELL_XEON_D, bdx_deadline_rev), 592 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_SKYLAKE_X, skx_deadline_rev), 593 594 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_CORE, 0x22), 595 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_ULT, 0x20), 596 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_GT3E, 0x17), 597 598 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_CORE, 0x25), 599 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_GT3E, 0x17), 600 601 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_MOBILE, 0xb2), 602 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_DESKTOP, 0xb2), 603 604 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_MOBILE, 0x52), 605 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_DESKTOP, 0x52), 606 607 {}, 608 }; 609 610 static void apic_check_deadline_errata(void) 611 { 612 const struct x86_cpu_id *m; 613 u32 rev; 614 615 if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER) || 616 boot_cpu_has(X86_FEATURE_HYPERVISOR)) 617 return; 618 619 m = x86_match_cpu(deadline_match); 620 if (!m) 621 return; 622 623 /* 624 * Function pointers will have the MSB set due to address layout, 625 * immediate revisions will not. 626 */ 627 if ((long)m->driver_data < 0) 628 rev = ((u32 (*)(void))(m->driver_data))(); 629 else 630 rev = (u32)m->driver_data; 631 632 if (boot_cpu_data.microcode >= rev) 633 return; 634 635 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 636 pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; " 637 "please update microcode to version: 0x%x (or later)\n", rev); 638 } 639 640 /* 641 * Setup the local APIC timer for this CPU. Copy the initialized values 642 * of the boot CPU and register the clock event in the framework. 643 */ 644 static void setup_APIC_timer(void) 645 { 646 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 647 648 if (this_cpu_has(X86_FEATURE_ARAT)) { 649 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 650 /* Make LAPIC timer preferrable over percpu HPET */ 651 lapic_clockevent.rating = 150; 652 } 653 654 memcpy(levt, &lapic_clockevent, sizeof(*levt)); 655 levt->cpumask = cpumask_of(smp_processor_id()); 656 657 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 658 levt->name = "lapic-deadline"; 659 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | 660 CLOCK_EVT_FEAT_DUMMY); 661 levt->set_next_event = lapic_next_deadline; 662 clockevents_config_and_register(levt, 663 tsc_khz * (1000 / TSC_DIVISOR), 664 0xF, ~0UL); 665 } else 666 clockevents_register_device(levt); 667 } 668 669 /* 670 * Install the updated TSC frequency from recalibration at the TSC 671 * deadline clockevent devices. 672 */ 673 static void __lapic_update_tsc_freq(void *info) 674 { 675 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 676 677 if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 678 return; 679 680 clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR)); 681 } 682 683 void lapic_update_tsc_freq(void) 684 { 685 /* 686 * The clockevent device's ->mult and ->shift can both be 687 * changed. In order to avoid races, schedule the frequency 688 * update code on each CPU. 689 */ 690 on_each_cpu(__lapic_update_tsc_freq, NULL, 0); 691 } 692 693 /* 694 * In this functions we calibrate APIC bus clocks to the external timer. 695 * 696 * We want to do the calibration only once since we want to have local timer 697 * irqs syncron. CPUs connected by the same APIC bus have the very same bus 698 * frequency. 699 * 700 * This was previously done by reading the PIT/HPET and waiting for a wrap 701 * around to find out, that a tick has elapsed. I have a box, where the PIT 702 * readout is broken, so it never gets out of the wait loop again. This was 703 * also reported by others. 704 * 705 * Monitoring the jiffies value is inaccurate and the clockevents 706 * infrastructure allows us to do a simple substitution of the interrupt 707 * handler. 708 * 709 * The calibration routine also uses the pm_timer when possible, as the PIT 710 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 711 * back to normal later in the boot process). 712 */ 713 714 #define LAPIC_CAL_LOOPS (HZ/10) 715 716 static __initdata int lapic_cal_loops = -1; 717 static __initdata long lapic_cal_t1, lapic_cal_t2; 718 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 719 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 720 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 721 722 /* 723 * Temporary interrupt handler. 724 */ 725 static void __init lapic_cal_handler(struct clock_event_device *dev) 726 { 727 unsigned long long tsc = 0; 728 long tapic = apic_read(APIC_TMCCT); 729 unsigned long pm = acpi_pm_read_early(); 730 731 if (boot_cpu_has(X86_FEATURE_TSC)) 732 tsc = rdtsc(); 733 734 switch (lapic_cal_loops++) { 735 case 0: 736 lapic_cal_t1 = tapic; 737 lapic_cal_tsc1 = tsc; 738 lapic_cal_pm1 = pm; 739 lapic_cal_j1 = jiffies; 740 break; 741 742 case LAPIC_CAL_LOOPS: 743 lapic_cal_t2 = tapic; 744 lapic_cal_tsc2 = tsc; 745 if (pm < lapic_cal_pm1) 746 pm += ACPI_PM_OVRRUN; 747 lapic_cal_pm2 = pm; 748 lapic_cal_j2 = jiffies; 749 break; 750 } 751 } 752 753 static int __init 754 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 755 { 756 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 757 const long pm_thresh = pm_100ms / 100; 758 unsigned long mult; 759 u64 res; 760 761 #ifndef CONFIG_X86_PM_TIMER 762 return -1; 763 #endif 764 765 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 766 767 /* Check, if the PM timer is available */ 768 if (!deltapm) 769 return -1; 770 771 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 772 773 if (deltapm > (pm_100ms - pm_thresh) && 774 deltapm < (pm_100ms + pm_thresh)) { 775 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 776 return 0; 777 } 778 779 res = (((u64)deltapm) * mult) >> 22; 780 do_div(res, 1000000); 781 pr_warning("APIC calibration not consistent " 782 "with PM-Timer: %ldms instead of 100ms\n",(long)res); 783 784 /* Correct the lapic counter value */ 785 res = (((u64)(*delta)) * pm_100ms); 786 do_div(res, deltapm); 787 pr_info("APIC delta adjusted to PM-Timer: " 788 "%lu (%ld)\n", (unsigned long)res, *delta); 789 *delta = (long)res; 790 791 /* Correct the tsc counter value */ 792 if (boot_cpu_has(X86_FEATURE_TSC)) { 793 res = (((u64)(*deltatsc)) * pm_100ms); 794 do_div(res, deltapm); 795 apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 796 "PM-Timer: %lu (%ld)\n", 797 (unsigned long)res, *deltatsc); 798 *deltatsc = (long)res; 799 } 800 801 return 0; 802 } 803 804 static int __init calibrate_APIC_clock(void) 805 { 806 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 807 void (*real_handler)(struct clock_event_device *dev); 808 unsigned long deltaj; 809 long delta, deltatsc; 810 int pm_referenced = 0; 811 812 /** 813 * check if lapic timer has already been calibrated by platform 814 * specific routine, such as tsc calibration code. if so, we just fill 815 * in the clockevent structure and return. 816 */ 817 818 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 819 return 0; 820 } else if (lapic_timer_frequency) { 821 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", 822 lapic_timer_frequency); 823 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR, 824 TICK_NSEC, lapic_clockevent.shift); 825 lapic_clockevent.max_delta_ns = 826 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); 827 lapic_clockevent.max_delta_ticks = 0x7FFFFF; 828 lapic_clockevent.min_delta_ns = 829 clockevent_delta2ns(0xF, &lapic_clockevent); 830 lapic_clockevent.min_delta_ticks = 0xF; 831 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 832 return 0; 833 } 834 835 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 836 "calibrating APIC timer ...\n"); 837 838 local_irq_disable(); 839 840 /* Replace the global interrupt handler */ 841 real_handler = global_clock_event->event_handler; 842 global_clock_event->event_handler = lapic_cal_handler; 843 844 /* 845 * Setup the APIC counter to maximum. There is no way the lapic 846 * can underflow in the 100ms detection time frame 847 */ 848 __setup_APIC_LVTT(0xffffffff, 0, 0); 849 850 /* Let the interrupts run */ 851 local_irq_enable(); 852 853 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 854 cpu_relax(); 855 856 local_irq_disable(); 857 858 /* Restore the real event handler */ 859 global_clock_event->event_handler = real_handler; 860 861 /* Build delta t1-t2 as apic timer counts down */ 862 delta = lapic_cal_t1 - lapic_cal_t2; 863 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 864 865 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 866 867 /* we trust the PM based calibration if possible */ 868 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 869 &delta, &deltatsc); 870 871 /* Calculate the scaled math multiplication factor */ 872 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 873 lapic_clockevent.shift); 874 lapic_clockevent.max_delta_ns = 875 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); 876 lapic_clockevent.max_delta_ticks = 0x7FFFFFFF; 877 lapic_clockevent.min_delta_ns = 878 clockevent_delta2ns(0xF, &lapic_clockevent); 879 lapic_clockevent.min_delta_ticks = 0xF; 880 881 lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 882 883 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 884 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); 885 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 886 lapic_timer_frequency); 887 888 if (boot_cpu_has(X86_FEATURE_TSC)) { 889 apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 890 "%ld.%04ld MHz.\n", 891 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 892 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 893 } 894 895 apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 896 "%u.%04u MHz.\n", 897 lapic_timer_frequency / (1000000 / HZ), 898 lapic_timer_frequency % (1000000 / HZ)); 899 900 /* 901 * Do a sanity check on the APIC calibration result 902 */ 903 if (lapic_timer_frequency < (1000000 / HZ)) { 904 local_irq_enable(); 905 pr_warning("APIC frequency too slow, disabling apic timer\n"); 906 return -1; 907 } 908 909 levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 910 911 /* 912 * PM timer calibration failed or not turned on 913 * so lets try APIC timer based calibration 914 */ 915 if (!pm_referenced) { 916 apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 917 918 /* 919 * Setup the apic timer manually 920 */ 921 levt->event_handler = lapic_cal_handler; 922 lapic_timer_set_periodic(levt); 923 lapic_cal_loops = -1; 924 925 /* Let the interrupts run */ 926 local_irq_enable(); 927 928 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 929 cpu_relax(); 930 931 /* Stop the lapic timer */ 932 local_irq_disable(); 933 lapic_timer_shutdown(levt); 934 935 /* Jiffies delta */ 936 deltaj = lapic_cal_j2 - lapic_cal_j1; 937 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 938 939 /* Check, if the jiffies result is consistent */ 940 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 941 apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 942 else 943 levt->features |= CLOCK_EVT_FEAT_DUMMY; 944 } 945 local_irq_enable(); 946 947 if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 948 pr_warning("APIC timer disabled due to verification failure\n"); 949 return -1; 950 } 951 952 return 0; 953 } 954 955 /* 956 * Setup the boot APIC 957 * 958 * Calibrate and verify the result. 959 */ 960 void __init setup_boot_APIC_clock(void) 961 { 962 /* 963 * The local apic timer can be disabled via the kernel 964 * commandline or from the CPU detection code. Register the lapic 965 * timer as a dummy clock event source on SMP systems, so the 966 * broadcast mechanism is used. On UP systems simply ignore it. 967 */ 968 if (disable_apic_timer) { 969 pr_info("Disabling APIC timer\n"); 970 /* No broadcast on UP ! */ 971 if (num_possible_cpus() > 1) { 972 lapic_clockevent.mult = 1; 973 setup_APIC_timer(); 974 } 975 return; 976 } 977 978 if (calibrate_APIC_clock()) { 979 /* No broadcast on UP ! */ 980 if (num_possible_cpus() > 1) 981 setup_APIC_timer(); 982 return; 983 } 984 985 /* 986 * If nmi_watchdog is set to IO_APIC, we need the 987 * PIT/HPET going. Otherwise register lapic as a dummy 988 * device. 989 */ 990 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 991 992 /* Setup the lapic or request the broadcast */ 993 setup_APIC_timer(); 994 amd_e400_c1e_apic_setup(); 995 } 996 997 void setup_secondary_APIC_clock(void) 998 { 999 setup_APIC_timer(); 1000 amd_e400_c1e_apic_setup(); 1001 } 1002 1003 /* 1004 * The guts of the apic timer interrupt 1005 */ 1006 static void local_apic_timer_interrupt(void) 1007 { 1008 struct clock_event_device *evt = this_cpu_ptr(&lapic_events); 1009 1010 /* 1011 * Normally we should not be here till LAPIC has been initialized but 1012 * in some cases like kdump, its possible that there is a pending LAPIC 1013 * timer interrupt from previous kernel's context and is delivered in 1014 * new kernel the moment interrupts are enabled. 1015 * 1016 * Interrupts are enabled early and LAPIC is setup much later, hence 1017 * its possible that when we get here evt->event_handler is NULL. 1018 * Check for event_handler being NULL and discard the interrupt as 1019 * spurious. 1020 */ 1021 if (!evt->event_handler) { 1022 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", 1023 smp_processor_id()); 1024 /* Switch it off */ 1025 lapic_timer_shutdown(evt); 1026 return; 1027 } 1028 1029 /* 1030 * the NMI deadlock-detector uses this. 1031 */ 1032 inc_irq_stat(apic_timer_irqs); 1033 1034 evt->event_handler(evt); 1035 } 1036 1037 /* 1038 * Local APIC timer interrupt. This is the most natural way for doing 1039 * local interrupts, but local timer interrupts can be emulated by 1040 * broadcast interrupts too. [in case the hw doesn't support APIC timers] 1041 * 1042 * [ if a single-CPU system runs an SMP kernel then we call the local 1043 * interrupt as well. Thus we cannot inline the local irq ... ] 1044 */ 1045 __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) 1046 { 1047 struct pt_regs *old_regs = set_irq_regs(regs); 1048 1049 /* 1050 * NOTE! We'd better ACK the irq immediately, 1051 * because timer handling can be slow. 1052 * 1053 * update_process_times() expects us to have done irq_enter(). 1054 * Besides, if we don't timer interrupts ignore the global 1055 * interrupt lock, which is the WrongThing (tm) to do. 1056 */ 1057 entering_ack_irq(); 1058 trace_local_timer_entry(LOCAL_TIMER_VECTOR); 1059 local_apic_timer_interrupt(); 1060 trace_local_timer_exit(LOCAL_TIMER_VECTOR); 1061 exiting_irq(); 1062 1063 set_irq_regs(old_regs); 1064 } 1065 1066 int setup_profiling_timer(unsigned int multiplier) 1067 { 1068 return -EINVAL; 1069 } 1070 1071 /* 1072 * Local APIC start and shutdown 1073 */ 1074 1075 /** 1076 * clear_local_APIC - shutdown the local APIC 1077 * 1078 * This is called, when a CPU is disabled and before rebooting, so the state of 1079 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 1080 * leftovers during boot. 1081 */ 1082 void clear_local_APIC(void) 1083 { 1084 int maxlvt; 1085 u32 v; 1086 1087 /* APIC hasn't been mapped yet */ 1088 if (!x2apic_mode && !apic_phys) 1089 return; 1090 1091 maxlvt = lapic_get_maxlvt(); 1092 /* 1093 * Masking an LVT entry can trigger a local APIC error 1094 * if the vector is zero. Mask LVTERR first to prevent this. 1095 */ 1096 if (maxlvt >= 3) { 1097 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 1098 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 1099 } 1100 /* 1101 * Careful: we have to set masks only first to deassert 1102 * any level-triggered sources. 1103 */ 1104 v = apic_read(APIC_LVTT); 1105 apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 1106 v = apic_read(APIC_LVT0); 1107 apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 1108 v = apic_read(APIC_LVT1); 1109 apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 1110 if (maxlvt >= 4) { 1111 v = apic_read(APIC_LVTPC); 1112 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 1113 } 1114 1115 /* lets not touch this if we didn't frob it */ 1116 #ifdef CONFIG_X86_THERMAL_VECTOR 1117 if (maxlvt >= 5) { 1118 v = apic_read(APIC_LVTTHMR); 1119 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 1120 } 1121 #endif 1122 #ifdef CONFIG_X86_MCE_INTEL 1123 if (maxlvt >= 6) { 1124 v = apic_read(APIC_LVTCMCI); 1125 if (!(v & APIC_LVT_MASKED)) 1126 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 1127 } 1128 #endif 1129 1130 /* 1131 * Clean APIC state for other OSs: 1132 */ 1133 apic_write(APIC_LVTT, APIC_LVT_MASKED); 1134 apic_write(APIC_LVT0, APIC_LVT_MASKED); 1135 apic_write(APIC_LVT1, APIC_LVT_MASKED); 1136 if (maxlvt >= 3) 1137 apic_write(APIC_LVTERR, APIC_LVT_MASKED); 1138 if (maxlvt >= 4) 1139 apic_write(APIC_LVTPC, APIC_LVT_MASKED); 1140 1141 /* Integrated APIC (!82489DX) ? */ 1142 if (lapic_is_integrated()) { 1143 if (maxlvt > 3) 1144 /* Clear ESR due to Pentium errata 3AP and 11AP */ 1145 apic_write(APIC_ESR, 0); 1146 apic_read(APIC_ESR); 1147 } 1148 } 1149 1150 /** 1151 * disable_local_APIC - clear and disable the local APIC 1152 */ 1153 void disable_local_APIC(void) 1154 { 1155 unsigned int value; 1156 1157 /* APIC hasn't been mapped yet */ 1158 if (!x2apic_mode && !apic_phys) 1159 return; 1160 1161 clear_local_APIC(); 1162 1163 /* 1164 * Disable APIC (implies clearing of registers 1165 * for 82489DX!). 1166 */ 1167 value = apic_read(APIC_SPIV); 1168 value &= ~APIC_SPIV_APIC_ENABLED; 1169 apic_write(APIC_SPIV, value); 1170 1171 #ifdef CONFIG_X86_32 1172 /* 1173 * When LAPIC was disabled by the BIOS and enabled by the kernel, 1174 * restore the disabled state. 1175 */ 1176 if (enabled_via_apicbase) { 1177 unsigned int l, h; 1178 1179 rdmsr(MSR_IA32_APICBASE, l, h); 1180 l &= ~MSR_IA32_APICBASE_ENABLE; 1181 wrmsr(MSR_IA32_APICBASE, l, h); 1182 } 1183 #endif 1184 } 1185 1186 /* 1187 * If Linux enabled the LAPIC against the BIOS default disable it down before 1188 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 1189 * not power-off. Additionally clear all LVT entries before disable_local_APIC 1190 * for the case where Linux didn't enable the LAPIC. 1191 */ 1192 void lapic_shutdown(void) 1193 { 1194 unsigned long flags; 1195 1196 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) 1197 return; 1198 1199 local_irq_save(flags); 1200 1201 #ifdef CONFIG_X86_32 1202 if (!enabled_via_apicbase) 1203 clear_local_APIC(); 1204 else 1205 #endif 1206 disable_local_APIC(); 1207 1208 1209 local_irq_restore(flags); 1210 } 1211 1212 /** 1213 * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1214 */ 1215 void __init sync_Arb_IDs(void) 1216 { 1217 /* 1218 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1219 * needed on AMD. 1220 */ 1221 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1222 return; 1223 1224 /* 1225 * Wait for idle. 1226 */ 1227 apic_wait_icr_idle(); 1228 1229 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1230 apic_write(APIC_ICR, APIC_DEST_ALLINC | 1231 APIC_INT_LEVELTRIG | APIC_DM_INIT); 1232 } 1233 1234 enum apic_intr_mode_id apic_intr_mode; 1235 1236 static int __init apic_intr_mode_select(void) 1237 { 1238 /* Check kernel option */ 1239 if (disable_apic) { 1240 pr_info("APIC disabled via kernel command line\n"); 1241 return APIC_PIC; 1242 } 1243 1244 /* Check BIOS */ 1245 #ifdef CONFIG_X86_64 1246 /* On 64-bit, the APIC must be integrated, Check local APIC only */ 1247 if (!boot_cpu_has(X86_FEATURE_APIC)) { 1248 disable_apic = 1; 1249 pr_info("APIC disabled by BIOS\n"); 1250 return APIC_PIC; 1251 } 1252 #else 1253 /* On 32-bit, the APIC may be integrated APIC or 82489DX */ 1254 1255 /* Neither 82489DX nor integrated APIC ? */ 1256 if (!boot_cpu_has(X86_FEATURE_APIC) && !smp_found_config) { 1257 disable_apic = 1; 1258 return APIC_PIC; 1259 } 1260 1261 /* If the BIOS pretends there is an integrated APIC ? */ 1262 if (!boot_cpu_has(X86_FEATURE_APIC) && 1263 APIC_INTEGRATED(boot_cpu_apic_version)) { 1264 disable_apic = 1; 1265 pr_err(FW_BUG "Local APIC %d not detected, force emulation\n", 1266 boot_cpu_physical_apicid); 1267 return APIC_PIC; 1268 } 1269 #endif 1270 1271 /* Check MP table or ACPI MADT configuration */ 1272 if (!smp_found_config) { 1273 disable_ioapic_support(); 1274 if (!acpi_lapic) { 1275 pr_info("APIC: ACPI MADT or MP tables are not detected\n"); 1276 return APIC_VIRTUAL_WIRE_NO_CONFIG; 1277 } 1278 return APIC_VIRTUAL_WIRE; 1279 } 1280 1281 #ifdef CONFIG_SMP 1282 /* If SMP should be disabled, then really disable it! */ 1283 if (!setup_max_cpus) { 1284 pr_info("APIC: SMP mode deactivated\n"); 1285 return APIC_SYMMETRIC_IO_NO_ROUTING; 1286 } 1287 1288 if (read_apic_id() != boot_cpu_physical_apicid) { 1289 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1290 read_apic_id(), boot_cpu_physical_apicid); 1291 /* Or can we switch back to PIC here? */ 1292 } 1293 #endif 1294 1295 return APIC_SYMMETRIC_IO; 1296 } 1297 1298 /* 1299 * An initial setup of the virtual wire mode. 1300 */ 1301 void __init init_bsp_APIC(void) 1302 { 1303 unsigned int value; 1304 1305 /* 1306 * Don't do the setup now if we have a SMP BIOS as the 1307 * through-I/O-APIC virtual wire mode might be active. 1308 */ 1309 if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC)) 1310 return; 1311 1312 /* 1313 * Do not trust the local APIC being empty at bootup. 1314 */ 1315 clear_local_APIC(); 1316 1317 /* 1318 * Enable APIC. 1319 */ 1320 value = apic_read(APIC_SPIV); 1321 value &= ~APIC_VECTOR_MASK; 1322 value |= APIC_SPIV_APIC_ENABLED; 1323 1324 #ifdef CONFIG_X86_32 1325 /* This bit is reserved on P4/Xeon and should be cleared */ 1326 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1327 (boot_cpu_data.x86 == 15)) 1328 value &= ~APIC_SPIV_FOCUS_DISABLED; 1329 else 1330 #endif 1331 value |= APIC_SPIV_FOCUS_DISABLED; 1332 value |= SPURIOUS_APIC_VECTOR; 1333 apic_write(APIC_SPIV, value); 1334 1335 /* 1336 * Set up the virtual wire mode. 1337 */ 1338 apic_write(APIC_LVT0, APIC_DM_EXTINT); 1339 value = APIC_DM_NMI; 1340 if (!lapic_is_integrated()) /* 82489DX */ 1341 value |= APIC_LVT_LEVEL_TRIGGER; 1342 if (apic_extnmi == APIC_EXTNMI_NONE) 1343 value |= APIC_LVT_MASKED; 1344 apic_write(APIC_LVT1, value); 1345 } 1346 1347 /* Init the interrupt delivery mode for the BSP */ 1348 void __init apic_intr_mode_init(void) 1349 { 1350 bool upmode = IS_ENABLED(CONFIG_UP_LATE_INIT); 1351 1352 apic_intr_mode = apic_intr_mode_select(); 1353 1354 switch (apic_intr_mode) { 1355 case APIC_PIC: 1356 pr_info("APIC: Keep in PIC mode(8259)\n"); 1357 return; 1358 case APIC_VIRTUAL_WIRE: 1359 pr_info("APIC: Switch to virtual wire mode setup\n"); 1360 default_setup_apic_routing(); 1361 break; 1362 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1363 pr_info("APIC: Switch to virtual wire mode setup with no configuration\n"); 1364 upmode = true; 1365 default_setup_apic_routing(); 1366 break; 1367 case APIC_SYMMETRIC_IO: 1368 pr_info("APIC: Switch to symmetric I/O mode setup\n"); 1369 default_setup_apic_routing(); 1370 break; 1371 case APIC_SYMMETRIC_IO_NO_ROUTING: 1372 pr_info("APIC: Switch to symmetric I/O mode setup in no SMP routine\n"); 1373 break; 1374 } 1375 1376 apic_bsp_setup(upmode); 1377 } 1378 1379 static void lapic_setup_esr(void) 1380 { 1381 unsigned int oldvalue, value, maxlvt; 1382 1383 if (!lapic_is_integrated()) { 1384 pr_info("No ESR for 82489DX.\n"); 1385 return; 1386 } 1387 1388 if (apic->disable_esr) { 1389 /* 1390 * Something untraceable is creating bad interrupts on 1391 * secondary quads ... for the moment, just leave the 1392 * ESR disabled - we can't do anything useful with the 1393 * errors anyway - mbligh 1394 */ 1395 pr_info("Leaving ESR disabled.\n"); 1396 return; 1397 } 1398 1399 maxlvt = lapic_get_maxlvt(); 1400 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1401 apic_write(APIC_ESR, 0); 1402 oldvalue = apic_read(APIC_ESR); 1403 1404 /* enables sending errors */ 1405 value = ERROR_APIC_VECTOR; 1406 apic_write(APIC_LVTERR, value); 1407 1408 /* 1409 * spec says clear errors after enabling vector. 1410 */ 1411 if (maxlvt > 3) 1412 apic_write(APIC_ESR, 0); 1413 value = apic_read(APIC_ESR); 1414 if (value != oldvalue) 1415 apic_printk(APIC_VERBOSE, "ESR value before enabling " 1416 "vector: 0x%08x after: 0x%08x\n", 1417 oldvalue, value); 1418 } 1419 1420 static void apic_pending_intr_clear(void) 1421 { 1422 long long max_loops = cpu_khz ? cpu_khz : 1000000; 1423 unsigned long long tsc = 0, ntsc; 1424 unsigned int queued; 1425 unsigned long value; 1426 int i, j, acked = 0; 1427 1428 if (boot_cpu_has(X86_FEATURE_TSC)) 1429 tsc = rdtsc(); 1430 /* 1431 * After a crash, we no longer service the interrupts and a pending 1432 * interrupt from previous kernel might still have ISR bit set. 1433 * 1434 * Most probably by now CPU has serviced that pending interrupt and 1435 * it might not have done the ack_APIC_irq() because it thought, 1436 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it 1437 * does not clear the ISR bit and cpu thinks it has already serivced 1438 * the interrupt. Hence a vector might get locked. It was noticed 1439 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. 1440 */ 1441 do { 1442 queued = 0; 1443 for (i = APIC_ISR_NR - 1; i >= 0; i--) 1444 queued |= apic_read(APIC_IRR + i*0x10); 1445 1446 for (i = APIC_ISR_NR - 1; i >= 0; i--) { 1447 value = apic_read(APIC_ISR + i*0x10); 1448 for_each_set_bit(j, &value, 32) { 1449 ack_APIC_irq(); 1450 acked++; 1451 } 1452 } 1453 if (acked > 256) { 1454 pr_err("LAPIC pending interrupts after %d EOI\n", acked); 1455 break; 1456 } 1457 if (queued) { 1458 if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) { 1459 ntsc = rdtsc(); 1460 max_loops = (cpu_khz << 10) - (ntsc - tsc); 1461 } else { 1462 max_loops--; 1463 } 1464 } 1465 } while (queued && max_loops > 0); 1466 WARN_ON(max_loops <= 0); 1467 } 1468 1469 /** 1470 * setup_local_APIC - setup the local APIC 1471 * 1472 * Used to setup local APIC while initializing BSP or bringing up APs. 1473 * Always called with preemption disabled. 1474 */ 1475 static void setup_local_APIC(void) 1476 { 1477 int cpu = smp_processor_id(); 1478 unsigned int value; 1479 #ifdef CONFIG_X86_32 1480 int logical_apicid, ldr_apicid; 1481 #endif 1482 1483 1484 if (disable_apic) { 1485 disable_ioapic_support(); 1486 return; 1487 } 1488 1489 #ifdef CONFIG_X86_32 1490 /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1491 if (lapic_is_integrated() && apic->disable_esr) { 1492 apic_write(APIC_ESR, 0); 1493 apic_write(APIC_ESR, 0); 1494 apic_write(APIC_ESR, 0); 1495 apic_write(APIC_ESR, 0); 1496 } 1497 #endif 1498 perf_events_lapic_init(); 1499 1500 /* 1501 * Double-check whether this APIC is really registered. 1502 * This is meaningless in clustered apic mode, so we skip it. 1503 */ 1504 BUG_ON(!apic->apic_id_registered()); 1505 1506 /* 1507 * Intel recommends to set DFR, LDR and TPR before enabling 1508 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1509 * document number 292116). So here it goes... 1510 */ 1511 apic->init_apic_ldr(); 1512 1513 #ifdef CONFIG_X86_32 1514 /* 1515 * APIC LDR is initialized. If logical_apicid mapping was 1516 * initialized during get_smp_config(), make sure it matches the 1517 * actual value. 1518 */ 1519 logical_apicid = early_per_cpu(x86_cpu_to_logical_apicid, cpu); 1520 ldr_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 1521 WARN_ON(logical_apicid != BAD_APICID && logical_apicid != ldr_apicid); 1522 /* always use the value from LDR */ 1523 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = ldr_apicid; 1524 #endif 1525 1526 /* 1527 * Set Task Priority to 'accept all'. We never change this 1528 * later on. 1529 */ 1530 value = apic_read(APIC_TASKPRI); 1531 value &= ~APIC_TPRI_MASK; 1532 apic_write(APIC_TASKPRI, value); 1533 1534 apic_pending_intr_clear(); 1535 1536 /* 1537 * Now that we are all set up, enable the APIC 1538 */ 1539 value = apic_read(APIC_SPIV); 1540 value &= ~APIC_VECTOR_MASK; 1541 /* 1542 * Enable APIC 1543 */ 1544 value |= APIC_SPIV_APIC_ENABLED; 1545 1546 #ifdef CONFIG_X86_32 1547 /* 1548 * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1549 * certain networking cards. If high frequency interrupts are 1550 * happening on a particular IOAPIC pin, plus the IOAPIC routing 1551 * entry is masked/unmasked at a high rate as well then sooner or 1552 * later IOAPIC line gets 'stuck', no more interrupts are received 1553 * from the device. If focus CPU is disabled then the hang goes 1554 * away, oh well :-( 1555 * 1556 * [ This bug can be reproduced easily with a level-triggered 1557 * PCI Ne2000 networking cards and PII/PIII processors, dual 1558 * BX chipset. ] 1559 */ 1560 /* 1561 * Actually disabling the focus CPU check just makes the hang less 1562 * frequent as it makes the interrupt distributon model be more 1563 * like LRU than MRU (the short-term load is more even across CPUs). 1564 */ 1565 1566 /* 1567 * - enable focus processor (bit==0) 1568 * - 64bit mode always use processor focus 1569 * so no need to set it 1570 */ 1571 value &= ~APIC_SPIV_FOCUS_DISABLED; 1572 #endif 1573 1574 /* 1575 * Set spurious IRQ vector 1576 */ 1577 value |= SPURIOUS_APIC_VECTOR; 1578 apic_write(APIC_SPIV, value); 1579 1580 /* 1581 * Set up LVT0, LVT1: 1582 * 1583 * set up through-local-APIC on the boot CPU's LINT0. This is not 1584 * strictly necessary in pure symmetric-IO mode, but sometimes 1585 * we delegate interrupts to the 8259A. 1586 */ 1587 /* 1588 * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1589 */ 1590 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 1591 if (!cpu && (pic_mode || !value || skip_ioapic_setup)) { 1592 value = APIC_DM_EXTINT; 1593 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); 1594 } else { 1595 value = APIC_DM_EXTINT | APIC_LVT_MASKED; 1596 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); 1597 } 1598 apic_write(APIC_LVT0, value); 1599 1600 /* 1601 * Only the BSP sees the LINT1 NMI signal by default. This can be 1602 * modified by apic_extnmi= boot option. 1603 */ 1604 if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) || 1605 apic_extnmi == APIC_EXTNMI_ALL) 1606 value = APIC_DM_NMI; 1607 else 1608 value = APIC_DM_NMI | APIC_LVT_MASKED; 1609 1610 /* Is 82489DX ? */ 1611 if (!lapic_is_integrated()) 1612 value |= APIC_LVT_LEVEL_TRIGGER; 1613 apic_write(APIC_LVT1, value); 1614 1615 #ifdef CONFIG_X86_MCE_INTEL 1616 /* Recheck CMCI information after local APIC is up on CPU #0 */ 1617 if (!cpu) 1618 cmci_recheck(); 1619 #endif 1620 } 1621 1622 static void end_local_APIC_setup(void) 1623 { 1624 lapic_setup_esr(); 1625 1626 #ifdef CONFIG_X86_32 1627 { 1628 unsigned int value; 1629 /* Disable the local apic timer */ 1630 value = apic_read(APIC_LVTT); 1631 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1632 apic_write(APIC_LVTT, value); 1633 } 1634 #endif 1635 1636 apic_pm_activate(); 1637 } 1638 1639 /* 1640 * APIC setup function for application processors. Called from smpboot.c 1641 */ 1642 void apic_ap_setup(void) 1643 { 1644 setup_local_APIC(); 1645 end_local_APIC_setup(); 1646 } 1647 1648 #ifdef CONFIG_X86_X2APIC 1649 int x2apic_mode; 1650 1651 enum { 1652 X2APIC_OFF, 1653 X2APIC_ON, 1654 X2APIC_DISABLED, 1655 }; 1656 static int x2apic_state; 1657 1658 static void __x2apic_disable(void) 1659 { 1660 u64 msr; 1661 1662 if (!boot_cpu_has(X86_FEATURE_APIC)) 1663 return; 1664 1665 rdmsrl(MSR_IA32_APICBASE, msr); 1666 if (!(msr & X2APIC_ENABLE)) 1667 return; 1668 /* Disable xapic and x2apic first and then reenable xapic mode */ 1669 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); 1670 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); 1671 printk_once(KERN_INFO "x2apic disabled\n"); 1672 } 1673 1674 static void __x2apic_enable(void) 1675 { 1676 u64 msr; 1677 1678 rdmsrl(MSR_IA32_APICBASE, msr); 1679 if (msr & X2APIC_ENABLE) 1680 return; 1681 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); 1682 printk_once(KERN_INFO "x2apic enabled\n"); 1683 } 1684 1685 static int __init setup_nox2apic(char *str) 1686 { 1687 if (x2apic_enabled()) { 1688 int apicid = native_apic_msr_read(APIC_ID); 1689 1690 if (apicid >= 255) { 1691 pr_warning("Apicid: %08x, cannot enforce nox2apic\n", 1692 apicid); 1693 return 0; 1694 } 1695 pr_warning("x2apic already enabled.\n"); 1696 __x2apic_disable(); 1697 } 1698 setup_clear_cpu_cap(X86_FEATURE_X2APIC); 1699 x2apic_state = X2APIC_DISABLED; 1700 x2apic_mode = 0; 1701 return 0; 1702 } 1703 early_param("nox2apic", setup_nox2apic); 1704 1705 /* Called from cpu_init() to enable x2apic on (secondary) cpus */ 1706 void x2apic_setup(void) 1707 { 1708 /* 1709 * If x2apic is not in ON state, disable it if already enabled 1710 * from BIOS. 1711 */ 1712 if (x2apic_state != X2APIC_ON) { 1713 __x2apic_disable(); 1714 return; 1715 } 1716 __x2apic_enable(); 1717 } 1718 1719 static __init void x2apic_disable(void) 1720 { 1721 u32 x2apic_id, state = x2apic_state; 1722 1723 x2apic_mode = 0; 1724 x2apic_state = X2APIC_DISABLED; 1725 1726 if (state != X2APIC_ON) 1727 return; 1728 1729 x2apic_id = read_apic_id(); 1730 if (x2apic_id >= 255) 1731 panic("Cannot disable x2apic, id: %08x\n", x2apic_id); 1732 1733 __x2apic_disable(); 1734 register_lapic_address(mp_lapic_addr); 1735 } 1736 1737 static __init void x2apic_enable(void) 1738 { 1739 if (x2apic_state != X2APIC_OFF) 1740 return; 1741 1742 x2apic_mode = 1; 1743 x2apic_state = X2APIC_ON; 1744 __x2apic_enable(); 1745 } 1746 1747 static __init void try_to_enable_x2apic(int remap_mode) 1748 { 1749 if (x2apic_state == X2APIC_DISABLED) 1750 return; 1751 1752 if (remap_mode != IRQ_REMAP_X2APIC_MODE) { 1753 /* IR is required if there is APIC ID > 255 even when running 1754 * under KVM 1755 */ 1756 if (max_physical_apicid > 255 || 1757 !x86_init.hyper.x2apic_available()) { 1758 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n"); 1759 x2apic_disable(); 1760 return; 1761 } 1762 1763 /* 1764 * without IR all CPUs can be addressed by IOAPIC/MSI 1765 * only in physical mode 1766 */ 1767 x2apic_phys = 1; 1768 } 1769 x2apic_enable(); 1770 } 1771 1772 void __init check_x2apic(void) 1773 { 1774 if (x2apic_enabled()) { 1775 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n"); 1776 x2apic_mode = 1; 1777 x2apic_state = X2APIC_ON; 1778 } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) { 1779 x2apic_state = X2APIC_DISABLED; 1780 } 1781 } 1782 #else /* CONFIG_X86_X2APIC */ 1783 static int __init validate_x2apic(void) 1784 { 1785 if (!apic_is_x2apic_enabled()) 1786 return 0; 1787 /* 1788 * Checkme: Can we simply turn off x2apic here instead of panic? 1789 */ 1790 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n"); 1791 } 1792 early_initcall(validate_x2apic); 1793 1794 static inline void try_to_enable_x2apic(int remap_mode) { } 1795 static inline void __x2apic_enable(void) { } 1796 #endif /* !CONFIG_X86_X2APIC */ 1797 1798 void __init enable_IR_x2apic(void) 1799 { 1800 unsigned long flags; 1801 int ret, ir_stat; 1802 1803 if (skip_ioapic_setup) { 1804 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n"); 1805 return; 1806 } 1807 1808 ir_stat = irq_remapping_prepare(); 1809 if (ir_stat < 0 && !x2apic_supported()) 1810 return; 1811 1812 ret = save_ioapic_entries(); 1813 if (ret) { 1814 pr_info("Saving IO-APIC state failed: %d\n", ret); 1815 return; 1816 } 1817 1818 local_irq_save(flags); 1819 legacy_pic->mask_all(); 1820 mask_ioapic_entries(); 1821 1822 /* If irq_remapping_prepare() succeeded, try to enable it */ 1823 if (ir_stat >= 0) 1824 ir_stat = irq_remapping_enable(); 1825 /* ir_stat contains the remap mode or an error code */ 1826 try_to_enable_x2apic(ir_stat); 1827 1828 if (ir_stat < 0) 1829 restore_ioapic_entries(); 1830 legacy_pic->restore_mask(); 1831 local_irq_restore(flags); 1832 } 1833 1834 #ifdef CONFIG_X86_64 1835 /* 1836 * Detect and enable local APICs on non-SMP boards. 1837 * Original code written by Keir Fraser. 1838 * On AMD64 we trust the BIOS - if it says no APIC it is likely 1839 * not correctly set up (usually the APIC timer won't work etc.) 1840 */ 1841 static int __init detect_init_APIC(void) 1842 { 1843 if (!boot_cpu_has(X86_FEATURE_APIC)) { 1844 pr_info("No local APIC present\n"); 1845 return -1; 1846 } 1847 1848 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1849 return 0; 1850 } 1851 #else 1852 1853 static int __init apic_verify(void) 1854 { 1855 u32 features, h, l; 1856 1857 /* 1858 * The APIC feature bit should now be enabled 1859 * in `cpuid' 1860 */ 1861 features = cpuid_edx(1); 1862 if (!(features & (1 << X86_FEATURE_APIC))) { 1863 pr_warning("Could not enable APIC!\n"); 1864 return -1; 1865 } 1866 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 1867 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1868 1869 /* The BIOS may have set up the APIC at some other address */ 1870 if (boot_cpu_data.x86 >= 6) { 1871 rdmsr(MSR_IA32_APICBASE, l, h); 1872 if (l & MSR_IA32_APICBASE_ENABLE) 1873 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 1874 } 1875 1876 pr_info("Found and enabled local APIC!\n"); 1877 return 0; 1878 } 1879 1880 int __init apic_force_enable(unsigned long addr) 1881 { 1882 u32 h, l; 1883 1884 if (disable_apic) 1885 return -1; 1886 1887 /* 1888 * Some BIOSes disable the local APIC in the APIC_BASE 1889 * MSR. This can only be done in software for Intel P6 or later 1890 * and AMD K7 (Model > 1) or later. 1891 */ 1892 if (boot_cpu_data.x86 >= 6) { 1893 rdmsr(MSR_IA32_APICBASE, l, h); 1894 if (!(l & MSR_IA32_APICBASE_ENABLE)) { 1895 pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 1896 l &= ~MSR_IA32_APICBASE_BASE; 1897 l |= MSR_IA32_APICBASE_ENABLE | addr; 1898 wrmsr(MSR_IA32_APICBASE, l, h); 1899 enabled_via_apicbase = 1; 1900 } 1901 } 1902 return apic_verify(); 1903 } 1904 1905 /* 1906 * Detect and initialize APIC 1907 */ 1908 static int __init detect_init_APIC(void) 1909 { 1910 /* Disabled by kernel option? */ 1911 if (disable_apic) 1912 return -1; 1913 1914 switch (boot_cpu_data.x86_vendor) { 1915 case X86_VENDOR_AMD: 1916 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 1917 (boot_cpu_data.x86 >= 15)) 1918 break; 1919 goto no_apic; 1920 case X86_VENDOR_HYGON: 1921 break; 1922 case X86_VENDOR_INTEL: 1923 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 1924 (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC))) 1925 break; 1926 goto no_apic; 1927 default: 1928 goto no_apic; 1929 } 1930 1931 if (!boot_cpu_has(X86_FEATURE_APIC)) { 1932 /* 1933 * Over-ride BIOS and try to enable the local APIC only if 1934 * "lapic" specified. 1935 */ 1936 if (!force_enable_local_apic) { 1937 pr_info("Local APIC disabled by BIOS -- " 1938 "you can enable it with \"lapic\"\n"); 1939 return -1; 1940 } 1941 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) 1942 return -1; 1943 } else { 1944 if (apic_verify()) 1945 return -1; 1946 } 1947 1948 apic_pm_activate(); 1949 1950 return 0; 1951 1952 no_apic: 1953 pr_info("No local APIC present or hardware disabled\n"); 1954 return -1; 1955 } 1956 #endif 1957 1958 /** 1959 * init_apic_mappings - initialize APIC mappings 1960 */ 1961 void __init init_apic_mappings(void) 1962 { 1963 unsigned int new_apicid; 1964 1965 apic_check_deadline_errata(); 1966 1967 if (x2apic_mode) { 1968 boot_cpu_physical_apicid = read_apic_id(); 1969 return; 1970 } 1971 1972 /* If no local APIC can be found return early */ 1973 if (!smp_found_config && detect_init_APIC()) { 1974 /* lets NOP'ify apic operations */ 1975 pr_info("APIC: disable apic facility\n"); 1976 apic_disable(); 1977 } else { 1978 apic_phys = mp_lapic_addr; 1979 1980 /* 1981 * If the system has ACPI MADT tables or MP info, the LAPIC 1982 * address is already registered. 1983 */ 1984 if (!acpi_lapic && !smp_found_config) 1985 register_lapic_address(apic_phys); 1986 } 1987 1988 /* 1989 * Fetch the APIC ID of the BSP in case we have a 1990 * default configuration (or the MP table is broken). 1991 */ 1992 new_apicid = read_apic_id(); 1993 if (boot_cpu_physical_apicid != new_apicid) { 1994 boot_cpu_physical_apicid = new_apicid; 1995 /* 1996 * yeah -- we lie about apic_version 1997 * in case if apic was disabled via boot option 1998 * but it's not a problem for SMP compiled kernel 1999 * since apic_intr_mode_select is prepared for such 2000 * a case and disable smp mode 2001 */ 2002 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 2003 } 2004 } 2005 2006 void __init register_lapic_address(unsigned long address) 2007 { 2008 mp_lapic_addr = address; 2009 2010 if (!x2apic_mode) { 2011 set_fixmap_nocache(FIX_APIC_BASE, address); 2012 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 2013 APIC_BASE, address); 2014 } 2015 if (boot_cpu_physical_apicid == -1U) { 2016 boot_cpu_physical_apicid = read_apic_id(); 2017 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 2018 } 2019 } 2020 2021 /* 2022 * Local APIC interrupts 2023 */ 2024 2025 /* 2026 * This interrupt should _never_ happen with our APIC/SMP architecture 2027 */ 2028 __visible void __irq_entry smp_spurious_interrupt(struct pt_regs *regs) 2029 { 2030 u8 vector = ~regs->orig_ax; 2031 u32 v; 2032 2033 entering_irq(); 2034 trace_spurious_apic_entry(vector); 2035 2036 /* 2037 * Check if this really is a spurious interrupt and ACK it 2038 * if it is a vectored one. Just in case... 2039 * Spurious interrupts should not be ACKed. 2040 */ 2041 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1)); 2042 if (v & (1 << (vector & 0x1f))) 2043 ack_APIC_irq(); 2044 2045 inc_irq_stat(irq_spurious_count); 2046 2047 /* see sw-dev-man vol 3, chapter 7.4.13.5 */ 2048 pr_info("spurious APIC interrupt through vector %02x on CPU#%d, " 2049 "should never happen.\n", vector, smp_processor_id()); 2050 2051 trace_spurious_apic_exit(vector); 2052 exiting_irq(); 2053 } 2054 2055 /* 2056 * This interrupt should never happen with our APIC/SMP architecture 2057 */ 2058 __visible void __irq_entry smp_error_interrupt(struct pt_regs *regs) 2059 { 2060 static const char * const error_interrupt_reason[] = { 2061 "Send CS error", /* APIC Error Bit 0 */ 2062 "Receive CS error", /* APIC Error Bit 1 */ 2063 "Send accept error", /* APIC Error Bit 2 */ 2064 "Receive accept error", /* APIC Error Bit 3 */ 2065 "Redirectable IPI", /* APIC Error Bit 4 */ 2066 "Send illegal vector", /* APIC Error Bit 5 */ 2067 "Received illegal vector", /* APIC Error Bit 6 */ 2068 "Illegal register address", /* APIC Error Bit 7 */ 2069 }; 2070 u32 v, i = 0; 2071 2072 entering_irq(); 2073 trace_error_apic_entry(ERROR_APIC_VECTOR); 2074 2075 /* First tickle the hardware, only then report what went on. -- REW */ 2076 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */ 2077 apic_write(APIC_ESR, 0); 2078 v = apic_read(APIC_ESR); 2079 ack_APIC_irq(); 2080 atomic_inc(&irq_err_count); 2081 2082 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x", 2083 smp_processor_id(), v); 2084 2085 v &= 0xff; 2086 while (v) { 2087 if (v & 0x1) 2088 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); 2089 i++; 2090 v >>= 1; 2091 } 2092 2093 apic_printk(APIC_DEBUG, KERN_CONT "\n"); 2094 2095 trace_error_apic_exit(ERROR_APIC_VECTOR); 2096 exiting_irq(); 2097 } 2098 2099 /** 2100 * connect_bsp_APIC - attach the APIC to the interrupt system 2101 */ 2102 static void __init connect_bsp_APIC(void) 2103 { 2104 #ifdef CONFIG_X86_32 2105 if (pic_mode) { 2106 /* 2107 * Do not trust the local APIC being empty at bootup. 2108 */ 2109 clear_local_APIC(); 2110 /* 2111 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 2112 * local APIC to INT and NMI lines. 2113 */ 2114 apic_printk(APIC_VERBOSE, "leaving PIC mode, " 2115 "enabling APIC mode.\n"); 2116 imcr_pic_to_apic(); 2117 } 2118 #endif 2119 } 2120 2121 /** 2122 * disconnect_bsp_APIC - detach the APIC from the interrupt system 2123 * @virt_wire_setup: indicates, whether virtual wire mode is selected 2124 * 2125 * Virtual wire mode is necessary to deliver legacy interrupts even when the 2126 * APIC is disabled. 2127 */ 2128 void disconnect_bsp_APIC(int virt_wire_setup) 2129 { 2130 unsigned int value; 2131 2132 #ifdef CONFIG_X86_32 2133 if (pic_mode) { 2134 /* 2135 * Put the board back into PIC mode (has an effect only on 2136 * certain older boards). Note that APIC interrupts, including 2137 * IPIs, won't work beyond this point! The only exception are 2138 * INIT IPIs. 2139 */ 2140 apic_printk(APIC_VERBOSE, "disabling APIC mode, " 2141 "entering PIC mode.\n"); 2142 imcr_apic_to_pic(); 2143 return; 2144 } 2145 #endif 2146 2147 /* Go back to Virtual Wire compatibility mode */ 2148 2149 /* For the spurious interrupt use vector F, and enable it */ 2150 value = apic_read(APIC_SPIV); 2151 value &= ~APIC_VECTOR_MASK; 2152 value |= APIC_SPIV_APIC_ENABLED; 2153 value |= 0xf; 2154 apic_write(APIC_SPIV, value); 2155 2156 if (!virt_wire_setup) { 2157 /* 2158 * For LVT0 make it edge triggered, active high, 2159 * external and enabled 2160 */ 2161 value = apic_read(APIC_LVT0); 2162 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2163 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2164 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2165 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2166 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 2167 apic_write(APIC_LVT0, value); 2168 } else { 2169 /* Disable LVT0 */ 2170 apic_write(APIC_LVT0, APIC_LVT_MASKED); 2171 } 2172 2173 /* 2174 * For LVT1 make it edge triggered, active high, 2175 * nmi and enabled 2176 */ 2177 value = apic_read(APIC_LVT1); 2178 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2179 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2180 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2181 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2182 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 2183 apic_write(APIC_LVT1, value); 2184 } 2185 2186 /* 2187 * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated 2188 * contiguously, it equals to current allocated max logical CPU ID plus 1. 2189 * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range, 2190 * so the maximum of nr_logical_cpuids is nr_cpu_ids. 2191 * 2192 * NOTE: Reserve 0 for BSP. 2193 */ 2194 static int nr_logical_cpuids = 1; 2195 2196 /* 2197 * Used to store mapping between logical CPU IDs and APIC IDs. 2198 */ 2199 static int cpuid_to_apicid[] = { 2200 [0 ... NR_CPUS - 1] = -1, 2201 }; 2202 2203 #ifdef CONFIG_SMP 2204 /** 2205 * apic_id_is_primary_thread - Check whether APIC ID belongs to a primary thread 2206 * @id: APIC ID to check 2207 */ 2208 bool apic_id_is_primary_thread(unsigned int apicid) 2209 { 2210 u32 mask; 2211 2212 if (smp_num_siblings == 1) 2213 return true; 2214 /* Isolate the SMT bit(s) in the APICID and check for 0 */ 2215 mask = (1U << (fls(smp_num_siblings) - 1)) - 1; 2216 return !(apicid & mask); 2217 } 2218 #endif 2219 2220 /* 2221 * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids 2222 * and cpuid_to_apicid[] synchronized. 2223 */ 2224 static int allocate_logical_cpuid(int apicid) 2225 { 2226 int i; 2227 2228 /* 2229 * cpuid <-> apicid mapping is persistent, so when a cpu is up, 2230 * check if the kernel has allocated a cpuid for it. 2231 */ 2232 for (i = 0; i < nr_logical_cpuids; i++) { 2233 if (cpuid_to_apicid[i] == apicid) 2234 return i; 2235 } 2236 2237 /* Allocate a new cpuid. */ 2238 if (nr_logical_cpuids >= nr_cpu_ids) { 2239 WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. " 2240 "Processor %d/0x%x and the rest are ignored.\n", 2241 nr_cpu_ids, nr_logical_cpuids, apicid); 2242 return -EINVAL; 2243 } 2244 2245 cpuid_to_apicid[nr_logical_cpuids] = apicid; 2246 return nr_logical_cpuids++; 2247 } 2248 2249 int generic_processor_info(int apicid, int version) 2250 { 2251 int cpu, max = nr_cpu_ids; 2252 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, 2253 phys_cpu_present_map); 2254 2255 /* 2256 * boot_cpu_physical_apicid is designed to have the apicid 2257 * returned by read_apic_id(), i.e, the apicid of the 2258 * currently booting-up processor. However, on some platforms, 2259 * it is temporarily modified by the apicid reported as BSP 2260 * through MP table. Concretely: 2261 * 2262 * - arch/x86/kernel/mpparse.c: MP_processor_info() 2263 * - arch/x86/mm/amdtopology.c: amd_numa_init() 2264 * 2265 * This function is executed with the modified 2266 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel 2267 * parameter doesn't work to disable APs on kdump 2nd kernel. 2268 * 2269 * Since fixing handling of boot_cpu_physical_apicid requires 2270 * another discussion and tests on each platform, we leave it 2271 * for now and here we use read_apic_id() directly in this 2272 * function, generic_processor_info(). 2273 */ 2274 if (disabled_cpu_apicid != BAD_APICID && 2275 disabled_cpu_apicid != read_apic_id() && 2276 disabled_cpu_apicid == apicid) { 2277 int thiscpu = num_processors + disabled_cpus; 2278 2279 pr_warning("APIC: Disabling requested cpu." 2280 " Processor %d/0x%x ignored.\n", 2281 thiscpu, apicid); 2282 2283 disabled_cpus++; 2284 return -ENODEV; 2285 } 2286 2287 /* 2288 * If boot cpu has not been detected yet, then only allow upto 2289 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu 2290 */ 2291 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && 2292 apicid != boot_cpu_physical_apicid) { 2293 int thiscpu = max + disabled_cpus - 1; 2294 2295 pr_warning( 2296 "APIC: NR_CPUS/possible_cpus limit of %i almost" 2297 " reached. Keeping one slot for boot cpu." 2298 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 2299 2300 disabled_cpus++; 2301 return -ENODEV; 2302 } 2303 2304 if (num_processors >= nr_cpu_ids) { 2305 int thiscpu = max + disabled_cpus; 2306 2307 pr_warning("APIC: NR_CPUS/possible_cpus limit of %i " 2308 "reached. Processor %d/0x%x ignored.\n", 2309 max, thiscpu, apicid); 2310 2311 disabled_cpus++; 2312 return -EINVAL; 2313 } 2314 2315 if (apicid == boot_cpu_physical_apicid) { 2316 /* 2317 * x86_bios_cpu_apicid is required to have processors listed 2318 * in same order as logical cpu numbers. Hence the first 2319 * entry is BSP, and so on. 2320 * boot_cpu_init() already hold bit 0 in cpu_present_mask 2321 * for BSP. 2322 */ 2323 cpu = 0; 2324 2325 /* Logical cpuid 0 is reserved for BSP. */ 2326 cpuid_to_apicid[0] = apicid; 2327 } else { 2328 cpu = allocate_logical_cpuid(apicid); 2329 if (cpu < 0) { 2330 disabled_cpus++; 2331 return -EINVAL; 2332 } 2333 } 2334 2335 /* 2336 * Validate version 2337 */ 2338 if (version == 0x0) { 2339 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", 2340 cpu, apicid); 2341 version = 0x10; 2342 } 2343 2344 if (version != boot_cpu_apic_version) { 2345 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", 2346 boot_cpu_apic_version, cpu, version); 2347 } 2348 2349 if (apicid > max_physical_apicid) 2350 max_physical_apicid = apicid; 2351 2352 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 2353 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 2354 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 2355 #endif 2356 #ifdef CONFIG_X86_32 2357 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 2358 apic->x86_32_early_logical_apicid(cpu); 2359 #endif 2360 set_cpu_possible(cpu, true); 2361 physid_set(apicid, phys_cpu_present_map); 2362 set_cpu_present(cpu, true); 2363 num_processors++; 2364 2365 return cpu; 2366 } 2367 2368 int hard_smp_processor_id(void) 2369 { 2370 return read_apic_id(); 2371 } 2372 2373 /* 2374 * Override the generic EOI implementation with an optimized version. 2375 * Only called during early boot when only one CPU is active and with 2376 * interrupts disabled, so we know this does not race with actual APIC driver 2377 * use. 2378 */ 2379 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) 2380 { 2381 struct apic **drv; 2382 2383 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { 2384 /* Should happen once for each apic */ 2385 WARN_ON((*drv)->eoi_write == eoi_write); 2386 (*drv)->native_eoi_write = (*drv)->eoi_write; 2387 (*drv)->eoi_write = eoi_write; 2388 } 2389 } 2390 2391 static void __init apic_bsp_up_setup(void) 2392 { 2393 #ifdef CONFIG_X86_64 2394 apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid)); 2395 #else 2396 /* 2397 * Hack: In case of kdump, after a crash, kernel might be booting 2398 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 2399 * might be zero if read from MP tables. Get it from LAPIC. 2400 */ 2401 # ifdef CONFIG_CRASH_DUMP 2402 boot_cpu_physical_apicid = read_apic_id(); 2403 # endif 2404 #endif 2405 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 2406 } 2407 2408 /** 2409 * apic_bsp_setup - Setup function for local apic and io-apic 2410 * @upmode: Force UP mode (for APIC_init_uniprocessor) 2411 * 2412 * Returns: 2413 * apic_id of BSP APIC 2414 */ 2415 void __init apic_bsp_setup(bool upmode) 2416 { 2417 connect_bsp_APIC(); 2418 if (upmode) 2419 apic_bsp_up_setup(); 2420 setup_local_APIC(); 2421 2422 enable_IO_APIC(); 2423 end_local_APIC_setup(); 2424 irq_remap_enable_fault_handling(); 2425 setup_IO_APIC(); 2426 } 2427 2428 #ifdef CONFIG_UP_LATE_INIT 2429 void __init up_late_init(void) 2430 { 2431 if (apic_intr_mode == APIC_PIC) 2432 return; 2433 2434 /* Setup local timer */ 2435 x86_init.timers.setup_percpu_clockev(); 2436 } 2437 #endif 2438 2439 /* 2440 * Power management 2441 */ 2442 #ifdef CONFIG_PM 2443 2444 static struct { 2445 /* 2446 * 'active' is true if the local APIC was enabled by us and 2447 * not the BIOS; this signifies that we are also responsible 2448 * for disabling it before entering apm/acpi suspend 2449 */ 2450 int active; 2451 /* r/w apic fields */ 2452 unsigned int apic_id; 2453 unsigned int apic_taskpri; 2454 unsigned int apic_ldr; 2455 unsigned int apic_dfr; 2456 unsigned int apic_spiv; 2457 unsigned int apic_lvtt; 2458 unsigned int apic_lvtpc; 2459 unsigned int apic_lvt0; 2460 unsigned int apic_lvt1; 2461 unsigned int apic_lvterr; 2462 unsigned int apic_tmict; 2463 unsigned int apic_tdcr; 2464 unsigned int apic_thmr; 2465 unsigned int apic_cmci; 2466 } apic_pm_state; 2467 2468 static int lapic_suspend(void) 2469 { 2470 unsigned long flags; 2471 int maxlvt; 2472 2473 if (!apic_pm_state.active) 2474 return 0; 2475 2476 maxlvt = lapic_get_maxlvt(); 2477 2478 apic_pm_state.apic_id = apic_read(APIC_ID); 2479 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 2480 apic_pm_state.apic_ldr = apic_read(APIC_LDR); 2481 apic_pm_state.apic_dfr = apic_read(APIC_DFR); 2482 apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2483 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2484 if (maxlvt >= 4) 2485 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2486 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2487 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2488 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2489 apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2490 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 2491 #ifdef CONFIG_X86_THERMAL_VECTOR 2492 if (maxlvt >= 5) 2493 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2494 #endif 2495 #ifdef CONFIG_X86_MCE_INTEL 2496 if (maxlvt >= 6) 2497 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI); 2498 #endif 2499 2500 local_irq_save(flags); 2501 disable_local_APIC(); 2502 2503 irq_remapping_disable(); 2504 2505 local_irq_restore(flags); 2506 return 0; 2507 } 2508 2509 static void lapic_resume(void) 2510 { 2511 unsigned int l, h; 2512 unsigned long flags; 2513 int maxlvt; 2514 2515 if (!apic_pm_state.active) 2516 return; 2517 2518 local_irq_save(flags); 2519 2520 /* 2521 * IO-APIC and PIC have their own resume routines. 2522 * We just mask them here to make sure the interrupt 2523 * subsystem is completely quiet while we enable x2apic 2524 * and interrupt-remapping. 2525 */ 2526 mask_ioapic_entries(); 2527 legacy_pic->mask_all(); 2528 2529 if (x2apic_mode) { 2530 __x2apic_enable(); 2531 } else { 2532 /* 2533 * Make sure the APICBASE points to the right address 2534 * 2535 * FIXME! This will be wrong if we ever support suspend on 2536 * SMP! We'll need to do this as part of the CPU restore! 2537 */ 2538 if (boot_cpu_data.x86 >= 6) { 2539 rdmsr(MSR_IA32_APICBASE, l, h); 2540 l &= ~MSR_IA32_APICBASE_BASE; 2541 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2542 wrmsr(MSR_IA32_APICBASE, l, h); 2543 } 2544 } 2545 2546 maxlvt = lapic_get_maxlvt(); 2547 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2548 apic_write(APIC_ID, apic_pm_state.apic_id); 2549 apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2550 apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2551 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2552 apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2553 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2554 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 2555 #ifdef CONFIG_X86_THERMAL_VECTOR 2556 if (maxlvt >= 5) 2557 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2558 #endif 2559 #ifdef CONFIG_X86_MCE_INTEL 2560 if (maxlvt >= 6) 2561 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci); 2562 #endif 2563 if (maxlvt >= 4) 2564 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2565 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2566 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2567 apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2568 apic_write(APIC_ESR, 0); 2569 apic_read(APIC_ESR); 2570 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2571 apic_write(APIC_ESR, 0); 2572 apic_read(APIC_ESR); 2573 2574 irq_remapping_reenable(x2apic_mode); 2575 2576 local_irq_restore(flags); 2577 } 2578 2579 /* 2580 * This device has no shutdown method - fully functioning local APICs 2581 * are needed on every CPU up until machine_halt/restart/poweroff. 2582 */ 2583 2584 static struct syscore_ops lapic_syscore_ops = { 2585 .resume = lapic_resume, 2586 .suspend = lapic_suspend, 2587 }; 2588 2589 static void apic_pm_activate(void) 2590 { 2591 apic_pm_state.active = 1; 2592 } 2593 2594 static int __init init_lapic_sysfs(void) 2595 { 2596 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 2597 if (boot_cpu_has(X86_FEATURE_APIC)) 2598 register_syscore_ops(&lapic_syscore_ops); 2599 2600 return 0; 2601 } 2602 2603 /* local apic needs to resume before other devices access its registers. */ 2604 core_initcall(init_lapic_sysfs); 2605 2606 #else /* CONFIG_PM */ 2607 2608 static void apic_pm_activate(void) { } 2609 2610 #endif /* CONFIG_PM */ 2611 2612 #ifdef CONFIG_X86_64 2613 2614 static int multi_checked; 2615 static int multi; 2616 2617 static int set_multi(const struct dmi_system_id *d) 2618 { 2619 if (multi) 2620 return 0; 2621 pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2622 multi = 1; 2623 return 0; 2624 } 2625 2626 static const struct dmi_system_id multi_dmi_table[] = { 2627 { 2628 .callback = set_multi, 2629 .ident = "IBM System Summit2", 2630 .matches = { 2631 DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2632 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2633 }, 2634 }, 2635 {} 2636 }; 2637 2638 static void dmi_check_multi(void) 2639 { 2640 if (multi_checked) 2641 return; 2642 2643 dmi_check_system(multi_dmi_table); 2644 multi_checked = 1; 2645 } 2646 2647 /* 2648 * apic_is_clustered_box() -- Check if we can expect good TSC 2649 * 2650 * Thus far, the major user of this is IBM's Summit2 series: 2651 * Clustered boxes may have unsynced TSC problems if they are 2652 * multi-chassis. 2653 * Use DMI to check them 2654 */ 2655 int apic_is_clustered_box(void) 2656 { 2657 dmi_check_multi(); 2658 return multi; 2659 } 2660 #endif 2661 2662 /* 2663 * APIC command line parameters 2664 */ 2665 static int __init setup_disableapic(char *arg) 2666 { 2667 disable_apic = 1; 2668 setup_clear_cpu_cap(X86_FEATURE_APIC); 2669 return 0; 2670 } 2671 early_param("disableapic", setup_disableapic); 2672 2673 /* same as disableapic, for compatibility */ 2674 static int __init setup_nolapic(char *arg) 2675 { 2676 return setup_disableapic(arg); 2677 } 2678 early_param("nolapic", setup_nolapic); 2679 2680 static int __init parse_lapic_timer_c2_ok(char *arg) 2681 { 2682 local_apic_timer_c2_ok = 1; 2683 return 0; 2684 } 2685 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2686 2687 static int __init parse_disable_apic_timer(char *arg) 2688 { 2689 disable_apic_timer = 1; 2690 return 0; 2691 } 2692 early_param("noapictimer", parse_disable_apic_timer); 2693 2694 static int __init parse_nolapic_timer(char *arg) 2695 { 2696 disable_apic_timer = 1; 2697 return 0; 2698 } 2699 early_param("nolapic_timer", parse_nolapic_timer); 2700 2701 static int __init apic_set_verbosity(char *arg) 2702 { 2703 if (!arg) { 2704 #ifdef CONFIG_X86_64 2705 skip_ioapic_setup = 0; 2706 return 0; 2707 #endif 2708 return -EINVAL; 2709 } 2710 2711 if (strcmp("debug", arg) == 0) 2712 apic_verbosity = APIC_DEBUG; 2713 else if (strcmp("verbose", arg) == 0) 2714 apic_verbosity = APIC_VERBOSE; 2715 #ifdef CONFIG_X86_64 2716 else { 2717 pr_warning("APIC Verbosity level %s not recognised" 2718 " use apic=verbose or apic=debug\n", arg); 2719 return -EINVAL; 2720 } 2721 #endif 2722 2723 return 0; 2724 } 2725 early_param("apic", apic_set_verbosity); 2726 2727 static int __init lapic_insert_resource(void) 2728 { 2729 if (!apic_phys) 2730 return -1; 2731 2732 /* Put local APIC into the resource map. */ 2733 lapic_resource.start = apic_phys; 2734 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2735 insert_resource(&iomem_resource, &lapic_resource); 2736 2737 return 0; 2738 } 2739 2740 /* 2741 * need call insert after e820__reserve_resources() 2742 * that is using request_resource 2743 */ 2744 late_initcall(lapic_insert_resource); 2745 2746 static int __init apic_set_disabled_cpu_apicid(char *arg) 2747 { 2748 if (!arg || !get_option(&arg, &disabled_cpu_apicid)) 2749 return -EINVAL; 2750 2751 return 0; 2752 } 2753 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); 2754 2755 static int __init apic_set_extnmi(char *arg) 2756 { 2757 if (!arg) 2758 return -EINVAL; 2759 2760 if (!strncmp("all", arg, 3)) 2761 apic_extnmi = APIC_EXTNMI_ALL; 2762 else if (!strncmp("none", arg, 4)) 2763 apic_extnmi = APIC_EXTNMI_NONE; 2764 else if (!strncmp("bsp", arg, 3)) 2765 apic_extnmi = APIC_EXTNMI_BSP; 2766 else { 2767 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg); 2768 return -EINVAL; 2769 } 2770 2771 return 0; 2772 } 2773 early_param("apic_extnmi", apic_set_extnmi); 2774