1 /* 2 * Local APIC handling, local APIC timers 3 * 4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 5 * 6 * Fixes 7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 8 * thanks to Eric Gilmore 9 * and Rolf G. Tews 10 * for testing these extensively. 11 * Maciej W. Rozycki : Various updates and fixes. 12 * Mikael Pettersson : Power Management for UP-APIC. 13 * Pavel Machek and 14 * Mikael Pettersson : PM converted to driver model. 15 */ 16 17 #include <linux/perf_event.h> 18 #include <linux/kernel_stat.h> 19 #include <linux/mc146818rtc.h> 20 #include <linux/acpi_pmtmr.h> 21 #include <linux/clockchips.h> 22 #include <linux/interrupt.h> 23 #include <linux/bootmem.h> 24 #include <linux/ftrace.h> 25 #include <linux/ioport.h> 26 #include <linux/export.h> 27 #include <linux/syscore_ops.h> 28 #include <linux/delay.h> 29 #include <linux/timex.h> 30 #include <linux/i8253.h> 31 #include <linux/dmar.h> 32 #include <linux/init.h> 33 #include <linux/cpu.h> 34 #include <linux/dmi.h> 35 #include <linux/smp.h> 36 #include <linux/mm.h> 37 38 #include <asm/trace/irq_vectors.h> 39 #include <asm/irq_remapping.h> 40 #include <asm/perf_event.h> 41 #include <asm/x86_init.h> 42 #include <asm/pgalloc.h> 43 #include <linux/atomic.h> 44 #include <asm/mpspec.h> 45 #include <asm/i8259.h> 46 #include <asm/proto.h> 47 #include <asm/apic.h> 48 #include <asm/io_apic.h> 49 #include <asm/desc.h> 50 #include <asm/hpet.h> 51 #include <asm/mtrr.h> 52 #include <asm/time.h> 53 #include <asm/smp.h> 54 #include <asm/mce.h> 55 #include <asm/tsc.h> 56 #include <asm/hypervisor.h> 57 58 unsigned int num_processors; 59 60 unsigned disabled_cpus; 61 62 /* Processor that is doing the boot up */ 63 unsigned int boot_cpu_physical_apicid = -1U; 64 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); 65 66 u8 boot_cpu_apic_version; 67 68 /* 69 * The highest APIC ID seen during enumeration. 70 */ 71 static unsigned int max_physical_apicid; 72 73 /* 74 * Bitmask of physically existing CPUs: 75 */ 76 physid_mask_t phys_cpu_present_map; 77 78 /* 79 * Processor to be disabled specified by kernel parameter 80 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to 81 * avoid undefined behaviour caused by sending INIT from AP to BSP. 82 */ 83 static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID; 84 85 /* 86 * This variable controls which CPUs receive external NMIs. By default, 87 * external NMIs are delivered only to the BSP. 88 */ 89 static int apic_extnmi = APIC_EXTNMI_BSP; 90 91 /* 92 * Map cpu index to physical APIC ID 93 */ 94 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); 95 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID); 96 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX); 97 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 98 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 99 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid); 100 101 #ifdef CONFIG_X86_32 102 103 /* 104 * On x86_32, the mapping between cpu and logical apicid may vary 105 * depending on apic in use. The following early percpu variable is 106 * used for the mapping. This is where the behaviors of x86_64 and 32 107 * actually diverge. Let's keep it ugly for now. 108 */ 109 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID); 110 111 /* Local APIC was disabled by the BIOS and enabled by the kernel */ 112 static int enabled_via_apicbase; 113 114 /* 115 * Handle interrupt mode configuration register (IMCR). 116 * This register controls whether the interrupt signals 117 * that reach the BSP come from the master PIC or from the 118 * local APIC. Before entering Symmetric I/O Mode, either 119 * the BIOS or the operating system must switch out of 120 * PIC Mode by changing the IMCR. 121 */ 122 static inline void imcr_pic_to_apic(void) 123 { 124 /* select IMCR register */ 125 outb(0x70, 0x22); 126 /* NMI and 8259 INTR go through APIC */ 127 outb(0x01, 0x23); 128 } 129 130 static inline void imcr_apic_to_pic(void) 131 { 132 /* select IMCR register */ 133 outb(0x70, 0x22); 134 /* NMI and 8259 INTR go directly to BSP */ 135 outb(0x00, 0x23); 136 } 137 #endif 138 139 /* 140 * Knob to control our willingness to enable the local APIC. 141 * 142 * +1=force-enable 143 */ 144 static int force_enable_local_apic __initdata; 145 146 /* 147 * APIC command line parameters 148 */ 149 static int __init parse_lapic(char *arg) 150 { 151 if (IS_ENABLED(CONFIG_X86_32) && !arg) 152 force_enable_local_apic = 1; 153 else if (arg && !strncmp(arg, "notscdeadline", 13)) 154 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 155 return 0; 156 } 157 early_param("lapic", parse_lapic); 158 159 #ifdef CONFIG_X86_64 160 static int apic_calibrate_pmtmr __initdata; 161 static __init int setup_apicpmtimer(char *s) 162 { 163 apic_calibrate_pmtmr = 1; 164 notsc_setup(NULL); 165 return 0; 166 } 167 __setup("apicpmtimer", setup_apicpmtimer); 168 #endif 169 170 unsigned long mp_lapic_addr; 171 int disable_apic; 172 /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 173 static int disable_apic_timer __initdata; 174 /* Local APIC timer works in C2 */ 175 int local_apic_timer_c2_ok; 176 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 177 178 int first_system_vector = FIRST_SYSTEM_VECTOR; 179 180 /* 181 * Debug level, exported for io_apic.c 182 */ 183 unsigned int apic_verbosity; 184 185 int pic_mode; 186 187 /* Have we found an MP table */ 188 int smp_found_config; 189 190 static struct resource lapic_resource = { 191 .name = "Local APIC", 192 .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 193 }; 194 195 unsigned int lapic_timer_frequency = 0; 196 197 static void apic_pm_activate(void); 198 199 static unsigned long apic_phys; 200 201 /* 202 * Get the LAPIC version 203 */ 204 static inline int lapic_get_version(void) 205 { 206 return GET_APIC_VERSION(apic_read(APIC_LVR)); 207 } 208 209 /* 210 * Check, if the APIC is integrated or a separate chip 211 */ 212 static inline int lapic_is_integrated(void) 213 { 214 #ifdef CONFIG_X86_64 215 return 1; 216 #else 217 return APIC_INTEGRATED(lapic_get_version()); 218 #endif 219 } 220 221 /* 222 * Check, whether this is a modern or a first generation APIC 223 */ 224 static int modern_apic(void) 225 { 226 /* AMD systems use old APIC versions, so check the CPU */ 227 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 228 boot_cpu_data.x86 >= 0xf) 229 return 1; 230 return lapic_get_version() >= 0x14; 231 } 232 233 /* 234 * right after this call apic become NOOP driven 235 * so apic->write/read doesn't do anything 236 */ 237 static void __init apic_disable(void) 238 { 239 pr_info("APIC: switched to apic NOOP\n"); 240 apic = &apic_noop; 241 } 242 243 void native_apic_wait_icr_idle(void) 244 { 245 while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 246 cpu_relax(); 247 } 248 249 u32 native_safe_apic_wait_icr_idle(void) 250 { 251 u32 send_status; 252 int timeout; 253 254 timeout = 0; 255 do { 256 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 257 if (!send_status) 258 break; 259 inc_irq_stat(icr_read_retry_count); 260 udelay(100); 261 } while (timeout++ < 1000); 262 263 return send_status; 264 } 265 266 void native_apic_icr_write(u32 low, u32 id) 267 { 268 unsigned long flags; 269 270 local_irq_save(flags); 271 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 272 apic_write(APIC_ICR, low); 273 local_irq_restore(flags); 274 } 275 276 u64 native_apic_icr_read(void) 277 { 278 u32 icr1, icr2; 279 280 icr2 = apic_read(APIC_ICR2); 281 icr1 = apic_read(APIC_ICR); 282 283 return icr1 | ((u64)icr2 << 32); 284 } 285 286 #ifdef CONFIG_X86_32 287 /** 288 * get_physical_broadcast - Get number of physical broadcast IDs 289 */ 290 int get_physical_broadcast(void) 291 { 292 return modern_apic() ? 0xff : 0xf; 293 } 294 #endif 295 296 /** 297 * lapic_get_maxlvt - get the maximum number of local vector table entries 298 */ 299 int lapic_get_maxlvt(void) 300 { 301 unsigned int v; 302 303 v = apic_read(APIC_LVR); 304 /* 305 * - we always have APIC integrated on 64bit mode 306 * - 82489DXs do not report # of LVT entries 307 */ 308 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2; 309 } 310 311 /* 312 * Local APIC timer 313 */ 314 315 /* Clock divisor */ 316 #define APIC_DIVISOR 16 317 #define TSC_DIVISOR 8 318 319 /* 320 * This function sets up the local APIC timer, with a timeout of 321 * 'clocks' APIC bus clock. During calibration we actually call 322 * this function twice on the boot CPU, once with a bogus timeout 323 * value, second time for real. The other (noncalibrating) CPUs 324 * call this function only once, with the real, calibrated value. 325 * 326 * We do reads before writes even if unnecessary, to get around the 327 * P5 APIC double write bug. 328 */ 329 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 330 { 331 unsigned int lvtt_value, tmp_value; 332 333 lvtt_value = LOCAL_TIMER_VECTOR; 334 if (!oneshot) 335 lvtt_value |= APIC_LVT_TIMER_PERIODIC; 336 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 337 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE; 338 339 if (!lapic_is_integrated()) 340 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 341 342 if (!irqen) 343 lvtt_value |= APIC_LVT_MASKED; 344 345 apic_write(APIC_LVTT, lvtt_value); 346 347 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { 348 /* 349 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, 350 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized. 351 * According to Intel, MFENCE can do the serialization here. 352 */ 353 asm volatile("mfence" : : : "memory"); 354 355 printk_once(KERN_DEBUG "TSC deadline timer enabled\n"); 356 return; 357 } 358 359 /* 360 * Divide PICLK by 16 361 */ 362 tmp_value = apic_read(APIC_TDCR); 363 apic_write(APIC_TDCR, 364 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 365 APIC_TDR_DIV_16); 366 367 if (!oneshot) 368 apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 369 } 370 371 /* 372 * Setup extended LVT, AMD specific 373 * 374 * Software should use the LVT offsets the BIOS provides. The offsets 375 * are determined by the subsystems using it like those for MCE 376 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts 377 * are supported. Beginning with family 10h at least 4 offsets are 378 * available. 379 * 380 * Since the offsets must be consistent for all cores, we keep track 381 * of the LVT offsets in software and reserve the offset for the same 382 * vector also to be used on other cores. An offset is freed by 383 * setting the entry to APIC_EILVT_MASKED. 384 * 385 * If the BIOS is right, there should be no conflicts. Otherwise a 386 * "[Firmware Bug]: ..." error message is generated. However, if 387 * software does not properly determines the offsets, it is not 388 * necessarily a BIOS bug. 389 */ 390 391 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; 392 393 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) 394 { 395 return (old & APIC_EILVT_MASKED) 396 || (new == APIC_EILVT_MASKED) 397 || ((new & ~APIC_EILVT_MASKED) == old); 398 } 399 400 static unsigned int reserve_eilvt_offset(int offset, unsigned int new) 401 { 402 unsigned int rsvd, vector; 403 404 if (offset >= APIC_EILVT_NR_MAX) 405 return ~0; 406 407 rsvd = atomic_read(&eilvt_offsets[offset]); 408 do { 409 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ 410 if (vector && !eilvt_entry_is_changeable(vector, new)) 411 /* may not change if vectors are different */ 412 return rsvd; 413 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); 414 } while (rsvd != new); 415 416 rsvd &= ~APIC_EILVT_MASKED; 417 if (rsvd && rsvd != vector) 418 pr_info("LVT offset %d assigned for vector 0x%02x\n", 419 offset, rsvd); 420 421 return new; 422 } 423 424 /* 425 * If mask=1, the LVT entry does not generate interrupts while mask=0 426 * enables the vector. See also the BKDGs. Must be called with 427 * preemption disabled. 428 */ 429 430 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) 431 { 432 unsigned long reg = APIC_EILVTn(offset); 433 unsigned int new, old, reserved; 434 435 new = (mask << 16) | (msg_type << 8) | vector; 436 old = apic_read(reg); 437 reserved = reserve_eilvt_offset(offset, new); 438 439 if (reserved != new) { 440 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 441 "vector 0x%x, but the register is already in use for " 442 "vector 0x%x on another cpu\n", 443 smp_processor_id(), reg, offset, new, reserved); 444 return -EINVAL; 445 } 446 447 if (!eilvt_entry_is_changeable(old, new)) { 448 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 449 "vector 0x%x, but the register is already in use for " 450 "vector 0x%x on this cpu\n", 451 smp_processor_id(), reg, offset, new, old); 452 return -EBUSY; 453 } 454 455 apic_write(reg, new); 456 457 return 0; 458 } 459 EXPORT_SYMBOL_GPL(setup_APIC_eilvt); 460 461 /* 462 * Program the next event, relative to now 463 */ 464 static int lapic_next_event(unsigned long delta, 465 struct clock_event_device *evt) 466 { 467 apic_write(APIC_TMICT, delta); 468 return 0; 469 } 470 471 static int lapic_next_deadline(unsigned long delta, 472 struct clock_event_device *evt) 473 { 474 u64 tsc; 475 476 tsc = rdtsc(); 477 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); 478 return 0; 479 } 480 481 static int lapic_timer_shutdown(struct clock_event_device *evt) 482 { 483 unsigned int v; 484 485 /* Lapic used as dummy for broadcast ? */ 486 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 487 return 0; 488 489 v = apic_read(APIC_LVTT); 490 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 491 apic_write(APIC_LVTT, v); 492 apic_write(APIC_TMICT, 0); 493 return 0; 494 } 495 496 static inline int 497 lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot) 498 { 499 /* Lapic used as dummy for broadcast ? */ 500 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 501 return 0; 502 503 __setup_APIC_LVTT(lapic_timer_frequency, oneshot, 1); 504 return 0; 505 } 506 507 static int lapic_timer_set_periodic(struct clock_event_device *evt) 508 { 509 return lapic_timer_set_periodic_oneshot(evt, false); 510 } 511 512 static int lapic_timer_set_oneshot(struct clock_event_device *evt) 513 { 514 return lapic_timer_set_periodic_oneshot(evt, true); 515 } 516 517 /* 518 * Local APIC timer broadcast function 519 */ 520 static void lapic_timer_broadcast(const struct cpumask *mask) 521 { 522 #ifdef CONFIG_SMP 523 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 524 #endif 525 } 526 527 528 /* 529 * The local apic timer can be used for any function which is CPU local. 530 */ 531 static struct clock_event_device lapic_clockevent = { 532 .name = "lapic", 533 .features = CLOCK_EVT_FEAT_PERIODIC | 534 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP 535 | CLOCK_EVT_FEAT_DUMMY, 536 .shift = 32, 537 .set_state_shutdown = lapic_timer_shutdown, 538 .set_state_periodic = lapic_timer_set_periodic, 539 .set_state_oneshot = lapic_timer_set_oneshot, 540 .set_state_oneshot_stopped = lapic_timer_shutdown, 541 .set_next_event = lapic_next_event, 542 .broadcast = lapic_timer_broadcast, 543 .rating = 100, 544 .irq = -1, 545 }; 546 static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 547 548 /* 549 * Setup the local APIC timer for this CPU. Copy the initialized values 550 * of the boot CPU and register the clock event in the framework. 551 */ 552 static void setup_APIC_timer(void) 553 { 554 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 555 556 if (this_cpu_has(X86_FEATURE_ARAT)) { 557 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 558 /* Make LAPIC timer preferrable over percpu HPET */ 559 lapic_clockevent.rating = 150; 560 } 561 562 memcpy(levt, &lapic_clockevent, sizeof(*levt)); 563 levt->cpumask = cpumask_of(smp_processor_id()); 564 565 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 566 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | 567 CLOCK_EVT_FEAT_DUMMY); 568 levt->set_next_event = lapic_next_deadline; 569 clockevents_config_and_register(levt, 570 tsc_khz * (1000 / TSC_DIVISOR), 571 0xF, ~0UL); 572 } else 573 clockevents_register_device(levt); 574 } 575 576 /* 577 * Install the updated TSC frequency from recalibration at the TSC 578 * deadline clockevent devices. 579 */ 580 static void __lapic_update_tsc_freq(void *info) 581 { 582 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 583 584 if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 585 return; 586 587 clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR)); 588 } 589 590 void lapic_update_tsc_freq(void) 591 { 592 /* 593 * The clockevent device's ->mult and ->shift can both be 594 * changed. In order to avoid races, schedule the frequency 595 * update code on each CPU. 596 */ 597 on_each_cpu(__lapic_update_tsc_freq, NULL, 0); 598 } 599 600 /* 601 * In this functions we calibrate APIC bus clocks to the external timer. 602 * 603 * We want to do the calibration only once since we want to have local timer 604 * irqs syncron. CPUs connected by the same APIC bus have the very same bus 605 * frequency. 606 * 607 * This was previously done by reading the PIT/HPET and waiting for a wrap 608 * around to find out, that a tick has elapsed. I have a box, where the PIT 609 * readout is broken, so it never gets out of the wait loop again. This was 610 * also reported by others. 611 * 612 * Monitoring the jiffies value is inaccurate and the clockevents 613 * infrastructure allows us to do a simple substitution of the interrupt 614 * handler. 615 * 616 * The calibration routine also uses the pm_timer when possible, as the PIT 617 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 618 * back to normal later in the boot process). 619 */ 620 621 #define LAPIC_CAL_LOOPS (HZ/10) 622 623 static __initdata int lapic_cal_loops = -1; 624 static __initdata long lapic_cal_t1, lapic_cal_t2; 625 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 626 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 627 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 628 629 /* 630 * Temporary interrupt handler. 631 */ 632 static void __init lapic_cal_handler(struct clock_event_device *dev) 633 { 634 unsigned long long tsc = 0; 635 long tapic = apic_read(APIC_TMCCT); 636 unsigned long pm = acpi_pm_read_early(); 637 638 if (boot_cpu_has(X86_FEATURE_TSC)) 639 tsc = rdtsc(); 640 641 switch (lapic_cal_loops++) { 642 case 0: 643 lapic_cal_t1 = tapic; 644 lapic_cal_tsc1 = tsc; 645 lapic_cal_pm1 = pm; 646 lapic_cal_j1 = jiffies; 647 break; 648 649 case LAPIC_CAL_LOOPS: 650 lapic_cal_t2 = tapic; 651 lapic_cal_tsc2 = tsc; 652 if (pm < lapic_cal_pm1) 653 pm += ACPI_PM_OVRRUN; 654 lapic_cal_pm2 = pm; 655 lapic_cal_j2 = jiffies; 656 break; 657 } 658 } 659 660 static int __init 661 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 662 { 663 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 664 const long pm_thresh = pm_100ms / 100; 665 unsigned long mult; 666 u64 res; 667 668 #ifndef CONFIG_X86_PM_TIMER 669 return -1; 670 #endif 671 672 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 673 674 /* Check, if the PM timer is available */ 675 if (!deltapm) 676 return -1; 677 678 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 679 680 if (deltapm > (pm_100ms - pm_thresh) && 681 deltapm < (pm_100ms + pm_thresh)) { 682 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 683 return 0; 684 } 685 686 res = (((u64)deltapm) * mult) >> 22; 687 do_div(res, 1000000); 688 pr_warning("APIC calibration not consistent " 689 "with PM-Timer: %ldms instead of 100ms\n",(long)res); 690 691 /* Correct the lapic counter value */ 692 res = (((u64)(*delta)) * pm_100ms); 693 do_div(res, deltapm); 694 pr_info("APIC delta adjusted to PM-Timer: " 695 "%lu (%ld)\n", (unsigned long)res, *delta); 696 *delta = (long)res; 697 698 /* Correct the tsc counter value */ 699 if (boot_cpu_has(X86_FEATURE_TSC)) { 700 res = (((u64)(*deltatsc)) * pm_100ms); 701 do_div(res, deltapm); 702 apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 703 "PM-Timer: %lu (%ld)\n", 704 (unsigned long)res, *deltatsc); 705 *deltatsc = (long)res; 706 } 707 708 return 0; 709 } 710 711 static int __init calibrate_APIC_clock(void) 712 { 713 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 714 void (*real_handler)(struct clock_event_device *dev); 715 unsigned long deltaj; 716 long delta, deltatsc; 717 int pm_referenced = 0; 718 719 /** 720 * check if lapic timer has already been calibrated by platform 721 * specific routine, such as tsc calibration code. if so, we just fill 722 * in the clockevent structure and return. 723 */ 724 725 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 726 return 0; 727 } else if (lapic_timer_frequency) { 728 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", 729 lapic_timer_frequency); 730 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR, 731 TICK_NSEC, lapic_clockevent.shift); 732 lapic_clockevent.max_delta_ns = 733 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); 734 lapic_clockevent.min_delta_ns = 735 clockevent_delta2ns(0xF, &lapic_clockevent); 736 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 737 return 0; 738 } 739 740 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 741 "calibrating APIC timer ...\n"); 742 743 local_irq_disable(); 744 745 /* Replace the global interrupt handler */ 746 real_handler = global_clock_event->event_handler; 747 global_clock_event->event_handler = lapic_cal_handler; 748 749 /* 750 * Setup the APIC counter to maximum. There is no way the lapic 751 * can underflow in the 100ms detection time frame 752 */ 753 __setup_APIC_LVTT(0xffffffff, 0, 0); 754 755 /* Let the interrupts run */ 756 local_irq_enable(); 757 758 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 759 cpu_relax(); 760 761 local_irq_disable(); 762 763 /* Restore the real event handler */ 764 global_clock_event->event_handler = real_handler; 765 766 /* Build delta t1-t2 as apic timer counts down */ 767 delta = lapic_cal_t1 - lapic_cal_t2; 768 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 769 770 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 771 772 /* we trust the PM based calibration if possible */ 773 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 774 &delta, &deltatsc); 775 776 /* Calculate the scaled math multiplication factor */ 777 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 778 lapic_clockevent.shift); 779 lapic_clockevent.max_delta_ns = 780 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); 781 lapic_clockevent.min_delta_ns = 782 clockevent_delta2ns(0xF, &lapic_clockevent); 783 784 lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 785 786 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 787 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); 788 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 789 lapic_timer_frequency); 790 791 if (boot_cpu_has(X86_FEATURE_TSC)) { 792 apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 793 "%ld.%04ld MHz.\n", 794 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 795 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 796 } 797 798 apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 799 "%u.%04u MHz.\n", 800 lapic_timer_frequency / (1000000 / HZ), 801 lapic_timer_frequency % (1000000 / HZ)); 802 803 /* 804 * Do a sanity check on the APIC calibration result 805 */ 806 if (lapic_timer_frequency < (1000000 / HZ)) { 807 local_irq_enable(); 808 pr_warning("APIC frequency too slow, disabling apic timer\n"); 809 return -1; 810 } 811 812 levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 813 814 /* 815 * PM timer calibration failed or not turned on 816 * so lets try APIC timer based calibration 817 */ 818 if (!pm_referenced) { 819 apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 820 821 /* 822 * Setup the apic timer manually 823 */ 824 levt->event_handler = lapic_cal_handler; 825 lapic_timer_set_periodic(levt); 826 lapic_cal_loops = -1; 827 828 /* Let the interrupts run */ 829 local_irq_enable(); 830 831 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 832 cpu_relax(); 833 834 /* Stop the lapic timer */ 835 local_irq_disable(); 836 lapic_timer_shutdown(levt); 837 838 /* Jiffies delta */ 839 deltaj = lapic_cal_j2 - lapic_cal_j1; 840 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 841 842 /* Check, if the jiffies result is consistent */ 843 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 844 apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 845 else 846 levt->features |= CLOCK_EVT_FEAT_DUMMY; 847 } 848 local_irq_enable(); 849 850 if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 851 pr_warning("APIC timer disabled due to verification failure\n"); 852 return -1; 853 } 854 855 return 0; 856 } 857 858 /* 859 * Setup the boot APIC 860 * 861 * Calibrate and verify the result. 862 */ 863 void __init setup_boot_APIC_clock(void) 864 { 865 /* 866 * The local apic timer can be disabled via the kernel 867 * commandline or from the CPU detection code. Register the lapic 868 * timer as a dummy clock event source on SMP systems, so the 869 * broadcast mechanism is used. On UP systems simply ignore it. 870 */ 871 if (disable_apic_timer) { 872 pr_info("Disabling APIC timer\n"); 873 /* No broadcast on UP ! */ 874 if (num_possible_cpus() > 1) { 875 lapic_clockevent.mult = 1; 876 setup_APIC_timer(); 877 } 878 return; 879 } 880 881 if (calibrate_APIC_clock()) { 882 /* No broadcast on UP ! */ 883 if (num_possible_cpus() > 1) 884 setup_APIC_timer(); 885 return; 886 } 887 888 /* 889 * If nmi_watchdog is set to IO_APIC, we need the 890 * PIT/HPET going. Otherwise register lapic as a dummy 891 * device. 892 */ 893 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 894 895 /* Setup the lapic or request the broadcast */ 896 setup_APIC_timer(); 897 amd_e400_c1e_apic_setup(); 898 } 899 900 void setup_secondary_APIC_clock(void) 901 { 902 setup_APIC_timer(); 903 amd_e400_c1e_apic_setup(); 904 } 905 906 /* 907 * The guts of the apic timer interrupt 908 */ 909 static void local_apic_timer_interrupt(void) 910 { 911 int cpu = smp_processor_id(); 912 struct clock_event_device *evt = &per_cpu(lapic_events, cpu); 913 914 /* 915 * Normally we should not be here till LAPIC has been initialized but 916 * in some cases like kdump, its possible that there is a pending LAPIC 917 * timer interrupt from previous kernel's context and is delivered in 918 * new kernel the moment interrupts are enabled. 919 * 920 * Interrupts are enabled early and LAPIC is setup much later, hence 921 * its possible that when we get here evt->event_handler is NULL. 922 * Check for event_handler being NULL and discard the interrupt as 923 * spurious. 924 */ 925 if (!evt->event_handler) { 926 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", cpu); 927 /* Switch it off */ 928 lapic_timer_shutdown(evt); 929 return; 930 } 931 932 /* 933 * the NMI deadlock-detector uses this. 934 */ 935 inc_irq_stat(apic_timer_irqs); 936 937 evt->event_handler(evt); 938 } 939 940 /* 941 * Local APIC timer interrupt. This is the most natural way for doing 942 * local interrupts, but local timer interrupts can be emulated by 943 * broadcast interrupts too. [in case the hw doesn't support APIC timers] 944 * 945 * [ if a single-CPU system runs an SMP kernel then we call the local 946 * interrupt as well. Thus we cannot inline the local irq ... ] 947 */ 948 __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) 949 { 950 struct pt_regs *old_regs = set_irq_regs(regs); 951 952 /* 953 * NOTE! We'd better ACK the irq immediately, 954 * because timer handling can be slow. 955 * 956 * update_process_times() expects us to have done irq_enter(). 957 * Besides, if we don't timer interrupts ignore the global 958 * interrupt lock, which is the WrongThing (tm) to do. 959 */ 960 entering_ack_irq(); 961 local_apic_timer_interrupt(); 962 exiting_irq(); 963 964 set_irq_regs(old_regs); 965 } 966 967 __visible void __irq_entry smp_trace_apic_timer_interrupt(struct pt_regs *regs) 968 { 969 struct pt_regs *old_regs = set_irq_regs(regs); 970 971 /* 972 * NOTE! We'd better ACK the irq immediately, 973 * because timer handling can be slow. 974 * 975 * update_process_times() expects us to have done irq_enter(). 976 * Besides, if we don't timer interrupts ignore the global 977 * interrupt lock, which is the WrongThing (tm) to do. 978 */ 979 entering_ack_irq(); 980 trace_local_timer_entry(LOCAL_TIMER_VECTOR); 981 local_apic_timer_interrupt(); 982 trace_local_timer_exit(LOCAL_TIMER_VECTOR); 983 exiting_irq(); 984 985 set_irq_regs(old_regs); 986 } 987 988 int setup_profiling_timer(unsigned int multiplier) 989 { 990 return -EINVAL; 991 } 992 993 /* 994 * Local APIC start and shutdown 995 */ 996 997 /** 998 * clear_local_APIC - shutdown the local APIC 999 * 1000 * This is called, when a CPU is disabled and before rebooting, so the state of 1001 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 1002 * leftovers during boot. 1003 */ 1004 void clear_local_APIC(void) 1005 { 1006 int maxlvt; 1007 u32 v; 1008 1009 /* APIC hasn't been mapped yet */ 1010 if (!x2apic_mode && !apic_phys) 1011 return; 1012 1013 maxlvt = lapic_get_maxlvt(); 1014 /* 1015 * Masking an LVT entry can trigger a local APIC error 1016 * if the vector is zero. Mask LVTERR first to prevent this. 1017 */ 1018 if (maxlvt >= 3) { 1019 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 1020 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 1021 } 1022 /* 1023 * Careful: we have to set masks only first to deassert 1024 * any level-triggered sources. 1025 */ 1026 v = apic_read(APIC_LVTT); 1027 apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 1028 v = apic_read(APIC_LVT0); 1029 apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 1030 v = apic_read(APIC_LVT1); 1031 apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 1032 if (maxlvt >= 4) { 1033 v = apic_read(APIC_LVTPC); 1034 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 1035 } 1036 1037 /* lets not touch this if we didn't frob it */ 1038 #ifdef CONFIG_X86_THERMAL_VECTOR 1039 if (maxlvt >= 5) { 1040 v = apic_read(APIC_LVTTHMR); 1041 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 1042 } 1043 #endif 1044 #ifdef CONFIG_X86_MCE_INTEL 1045 if (maxlvt >= 6) { 1046 v = apic_read(APIC_LVTCMCI); 1047 if (!(v & APIC_LVT_MASKED)) 1048 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 1049 } 1050 #endif 1051 1052 /* 1053 * Clean APIC state for other OSs: 1054 */ 1055 apic_write(APIC_LVTT, APIC_LVT_MASKED); 1056 apic_write(APIC_LVT0, APIC_LVT_MASKED); 1057 apic_write(APIC_LVT1, APIC_LVT_MASKED); 1058 if (maxlvt >= 3) 1059 apic_write(APIC_LVTERR, APIC_LVT_MASKED); 1060 if (maxlvt >= 4) 1061 apic_write(APIC_LVTPC, APIC_LVT_MASKED); 1062 1063 /* Integrated APIC (!82489DX) ? */ 1064 if (lapic_is_integrated()) { 1065 if (maxlvt > 3) 1066 /* Clear ESR due to Pentium errata 3AP and 11AP */ 1067 apic_write(APIC_ESR, 0); 1068 apic_read(APIC_ESR); 1069 } 1070 } 1071 1072 /** 1073 * disable_local_APIC - clear and disable the local APIC 1074 */ 1075 void disable_local_APIC(void) 1076 { 1077 unsigned int value; 1078 1079 /* APIC hasn't been mapped yet */ 1080 if (!x2apic_mode && !apic_phys) 1081 return; 1082 1083 clear_local_APIC(); 1084 1085 /* 1086 * Disable APIC (implies clearing of registers 1087 * for 82489DX!). 1088 */ 1089 value = apic_read(APIC_SPIV); 1090 value &= ~APIC_SPIV_APIC_ENABLED; 1091 apic_write(APIC_SPIV, value); 1092 1093 #ifdef CONFIG_X86_32 1094 /* 1095 * When LAPIC was disabled by the BIOS and enabled by the kernel, 1096 * restore the disabled state. 1097 */ 1098 if (enabled_via_apicbase) { 1099 unsigned int l, h; 1100 1101 rdmsr(MSR_IA32_APICBASE, l, h); 1102 l &= ~MSR_IA32_APICBASE_ENABLE; 1103 wrmsr(MSR_IA32_APICBASE, l, h); 1104 } 1105 #endif 1106 } 1107 1108 /* 1109 * If Linux enabled the LAPIC against the BIOS default disable it down before 1110 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 1111 * not power-off. Additionally clear all LVT entries before disable_local_APIC 1112 * for the case where Linux didn't enable the LAPIC. 1113 */ 1114 void lapic_shutdown(void) 1115 { 1116 unsigned long flags; 1117 1118 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) 1119 return; 1120 1121 local_irq_save(flags); 1122 1123 #ifdef CONFIG_X86_32 1124 if (!enabled_via_apicbase) 1125 clear_local_APIC(); 1126 else 1127 #endif 1128 disable_local_APIC(); 1129 1130 1131 local_irq_restore(flags); 1132 } 1133 1134 /** 1135 * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1136 */ 1137 void __init sync_Arb_IDs(void) 1138 { 1139 /* 1140 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1141 * needed on AMD. 1142 */ 1143 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1144 return; 1145 1146 /* 1147 * Wait for idle. 1148 */ 1149 apic_wait_icr_idle(); 1150 1151 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1152 apic_write(APIC_ICR, APIC_DEST_ALLINC | 1153 APIC_INT_LEVELTRIG | APIC_DM_INIT); 1154 } 1155 1156 /* 1157 * An initial setup of the virtual wire mode. 1158 */ 1159 void __init init_bsp_APIC(void) 1160 { 1161 unsigned int value; 1162 1163 /* 1164 * Don't do the setup now if we have a SMP BIOS as the 1165 * through-I/O-APIC virtual wire mode might be active. 1166 */ 1167 if (smp_found_config || !boot_cpu_has(X86_FEATURE_APIC)) 1168 return; 1169 1170 /* 1171 * Do not trust the local APIC being empty at bootup. 1172 */ 1173 clear_local_APIC(); 1174 1175 /* 1176 * Enable APIC. 1177 */ 1178 value = apic_read(APIC_SPIV); 1179 value &= ~APIC_VECTOR_MASK; 1180 value |= APIC_SPIV_APIC_ENABLED; 1181 1182 #ifdef CONFIG_X86_32 1183 /* This bit is reserved on P4/Xeon and should be cleared */ 1184 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && 1185 (boot_cpu_data.x86 == 15)) 1186 value &= ~APIC_SPIV_FOCUS_DISABLED; 1187 else 1188 #endif 1189 value |= APIC_SPIV_FOCUS_DISABLED; 1190 value |= SPURIOUS_APIC_VECTOR; 1191 apic_write(APIC_SPIV, value); 1192 1193 /* 1194 * Set up the virtual wire mode. 1195 */ 1196 apic_write(APIC_LVT0, APIC_DM_EXTINT); 1197 value = APIC_DM_NMI; 1198 if (!lapic_is_integrated()) /* 82489DX */ 1199 value |= APIC_LVT_LEVEL_TRIGGER; 1200 if (apic_extnmi == APIC_EXTNMI_NONE) 1201 value |= APIC_LVT_MASKED; 1202 apic_write(APIC_LVT1, value); 1203 } 1204 1205 static void lapic_setup_esr(void) 1206 { 1207 unsigned int oldvalue, value, maxlvt; 1208 1209 if (!lapic_is_integrated()) { 1210 pr_info("No ESR for 82489DX.\n"); 1211 return; 1212 } 1213 1214 if (apic->disable_esr) { 1215 /* 1216 * Something untraceable is creating bad interrupts on 1217 * secondary quads ... for the moment, just leave the 1218 * ESR disabled - we can't do anything useful with the 1219 * errors anyway - mbligh 1220 */ 1221 pr_info("Leaving ESR disabled.\n"); 1222 return; 1223 } 1224 1225 maxlvt = lapic_get_maxlvt(); 1226 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1227 apic_write(APIC_ESR, 0); 1228 oldvalue = apic_read(APIC_ESR); 1229 1230 /* enables sending errors */ 1231 value = ERROR_APIC_VECTOR; 1232 apic_write(APIC_LVTERR, value); 1233 1234 /* 1235 * spec says clear errors after enabling vector. 1236 */ 1237 if (maxlvt > 3) 1238 apic_write(APIC_ESR, 0); 1239 value = apic_read(APIC_ESR); 1240 if (value != oldvalue) 1241 apic_printk(APIC_VERBOSE, "ESR value before enabling " 1242 "vector: 0x%08x after: 0x%08x\n", 1243 oldvalue, value); 1244 } 1245 1246 /** 1247 * setup_local_APIC - setup the local APIC 1248 * 1249 * Used to setup local APIC while initializing BSP or bringing up APs. 1250 * Always called with preemption disabled. 1251 */ 1252 void setup_local_APIC(void) 1253 { 1254 int cpu = smp_processor_id(); 1255 unsigned int value, queued; 1256 int i, j, acked = 0; 1257 unsigned long long tsc = 0, ntsc; 1258 long long max_loops = cpu_khz ? cpu_khz : 1000000; 1259 1260 if (boot_cpu_has(X86_FEATURE_TSC)) 1261 tsc = rdtsc(); 1262 1263 if (disable_apic) { 1264 disable_ioapic_support(); 1265 return; 1266 } 1267 1268 #ifdef CONFIG_X86_32 1269 /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1270 if (lapic_is_integrated() && apic->disable_esr) { 1271 apic_write(APIC_ESR, 0); 1272 apic_write(APIC_ESR, 0); 1273 apic_write(APIC_ESR, 0); 1274 apic_write(APIC_ESR, 0); 1275 } 1276 #endif 1277 perf_events_lapic_init(); 1278 1279 /* 1280 * Double-check whether this APIC is really registered. 1281 * This is meaningless in clustered apic mode, so we skip it. 1282 */ 1283 BUG_ON(!apic->apic_id_registered()); 1284 1285 /* 1286 * Intel recommends to set DFR, LDR and TPR before enabling 1287 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1288 * document number 292116). So here it goes... 1289 */ 1290 apic->init_apic_ldr(); 1291 1292 #ifdef CONFIG_X86_32 1293 /* 1294 * APIC LDR is initialized. If logical_apicid mapping was 1295 * initialized during get_smp_config(), make sure it matches the 1296 * actual value. 1297 */ 1298 i = early_per_cpu(x86_cpu_to_logical_apicid, cpu); 1299 WARN_ON(i != BAD_APICID && i != logical_smp_processor_id()); 1300 /* always use the value from LDR */ 1301 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 1302 logical_smp_processor_id(); 1303 #endif 1304 1305 /* 1306 * Set Task Priority to 'accept all'. We never change this 1307 * later on. 1308 */ 1309 value = apic_read(APIC_TASKPRI); 1310 value &= ~APIC_TPRI_MASK; 1311 apic_write(APIC_TASKPRI, value); 1312 1313 /* 1314 * After a crash, we no longer service the interrupts and a pending 1315 * interrupt from previous kernel might still have ISR bit set. 1316 * 1317 * Most probably by now CPU has serviced that pending interrupt and 1318 * it might not have done the ack_APIC_irq() because it thought, 1319 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it 1320 * does not clear the ISR bit and cpu thinks it has already serivced 1321 * the interrupt. Hence a vector might get locked. It was noticed 1322 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. 1323 */ 1324 do { 1325 queued = 0; 1326 for (i = APIC_ISR_NR - 1; i >= 0; i--) 1327 queued |= apic_read(APIC_IRR + i*0x10); 1328 1329 for (i = APIC_ISR_NR - 1; i >= 0; i--) { 1330 value = apic_read(APIC_ISR + i*0x10); 1331 for (j = 31; j >= 0; j--) { 1332 if (value & (1<<j)) { 1333 ack_APIC_irq(); 1334 acked++; 1335 } 1336 } 1337 } 1338 if (acked > 256) { 1339 printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n", 1340 acked); 1341 break; 1342 } 1343 if (queued) { 1344 if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) { 1345 ntsc = rdtsc(); 1346 max_loops = (cpu_khz << 10) - (ntsc - tsc); 1347 } else 1348 max_loops--; 1349 } 1350 } while (queued && max_loops > 0); 1351 WARN_ON(max_loops <= 0); 1352 1353 /* 1354 * Now that we are all set up, enable the APIC 1355 */ 1356 value = apic_read(APIC_SPIV); 1357 value &= ~APIC_VECTOR_MASK; 1358 /* 1359 * Enable APIC 1360 */ 1361 value |= APIC_SPIV_APIC_ENABLED; 1362 1363 #ifdef CONFIG_X86_32 1364 /* 1365 * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1366 * certain networking cards. If high frequency interrupts are 1367 * happening on a particular IOAPIC pin, plus the IOAPIC routing 1368 * entry is masked/unmasked at a high rate as well then sooner or 1369 * later IOAPIC line gets 'stuck', no more interrupts are received 1370 * from the device. If focus CPU is disabled then the hang goes 1371 * away, oh well :-( 1372 * 1373 * [ This bug can be reproduced easily with a level-triggered 1374 * PCI Ne2000 networking cards and PII/PIII processors, dual 1375 * BX chipset. ] 1376 */ 1377 /* 1378 * Actually disabling the focus CPU check just makes the hang less 1379 * frequent as it makes the interrupt distributon model be more 1380 * like LRU than MRU (the short-term load is more even across CPUs). 1381 */ 1382 1383 /* 1384 * - enable focus processor (bit==0) 1385 * - 64bit mode always use processor focus 1386 * so no need to set it 1387 */ 1388 value &= ~APIC_SPIV_FOCUS_DISABLED; 1389 #endif 1390 1391 /* 1392 * Set spurious IRQ vector 1393 */ 1394 value |= SPURIOUS_APIC_VECTOR; 1395 apic_write(APIC_SPIV, value); 1396 1397 /* 1398 * Set up LVT0, LVT1: 1399 * 1400 * set up through-local-APIC on the BP's LINT0. This is not 1401 * strictly necessary in pure symmetric-IO mode, but sometimes 1402 * we delegate interrupts to the 8259A. 1403 */ 1404 /* 1405 * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1406 */ 1407 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 1408 if (!cpu && (pic_mode || !value)) { 1409 value = APIC_DM_EXTINT; 1410 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); 1411 } else { 1412 value = APIC_DM_EXTINT | APIC_LVT_MASKED; 1413 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); 1414 } 1415 apic_write(APIC_LVT0, value); 1416 1417 /* 1418 * Only the BSP sees the LINT1 NMI signal by default. This can be 1419 * modified by apic_extnmi= boot option. 1420 */ 1421 if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) || 1422 apic_extnmi == APIC_EXTNMI_ALL) 1423 value = APIC_DM_NMI; 1424 else 1425 value = APIC_DM_NMI | APIC_LVT_MASKED; 1426 if (!lapic_is_integrated()) /* 82489DX */ 1427 value |= APIC_LVT_LEVEL_TRIGGER; 1428 apic_write(APIC_LVT1, value); 1429 1430 #ifdef CONFIG_X86_MCE_INTEL 1431 /* Recheck CMCI information after local APIC is up on CPU #0 */ 1432 if (!cpu) 1433 cmci_recheck(); 1434 #endif 1435 } 1436 1437 static void end_local_APIC_setup(void) 1438 { 1439 lapic_setup_esr(); 1440 1441 #ifdef CONFIG_X86_32 1442 { 1443 unsigned int value; 1444 /* Disable the local apic timer */ 1445 value = apic_read(APIC_LVTT); 1446 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1447 apic_write(APIC_LVTT, value); 1448 } 1449 #endif 1450 1451 apic_pm_activate(); 1452 } 1453 1454 /* 1455 * APIC setup function for application processors. Called from smpboot.c 1456 */ 1457 void apic_ap_setup(void) 1458 { 1459 setup_local_APIC(); 1460 end_local_APIC_setup(); 1461 } 1462 1463 #ifdef CONFIG_X86_X2APIC 1464 int x2apic_mode; 1465 1466 enum { 1467 X2APIC_OFF, 1468 X2APIC_ON, 1469 X2APIC_DISABLED, 1470 }; 1471 static int x2apic_state; 1472 1473 static void __x2apic_disable(void) 1474 { 1475 u64 msr; 1476 1477 if (!boot_cpu_has(X86_FEATURE_APIC)) 1478 return; 1479 1480 rdmsrl(MSR_IA32_APICBASE, msr); 1481 if (!(msr & X2APIC_ENABLE)) 1482 return; 1483 /* Disable xapic and x2apic first and then reenable xapic mode */ 1484 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); 1485 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); 1486 printk_once(KERN_INFO "x2apic disabled\n"); 1487 } 1488 1489 static void __x2apic_enable(void) 1490 { 1491 u64 msr; 1492 1493 rdmsrl(MSR_IA32_APICBASE, msr); 1494 if (msr & X2APIC_ENABLE) 1495 return; 1496 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); 1497 printk_once(KERN_INFO "x2apic enabled\n"); 1498 } 1499 1500 static int __init setup_nox2apic(char *str) 1501 { 1502 if (x2apic_enabled()) { 1503 int apicid = native_apic_msr_read(APIC_ID); 1504 1505 if (apicid >= 255) { 1506 pr_warning("Apicid: %08x, cannot enforce nox2apic\n", 1507 apicid); 1508 return 0; 1509 } 1510 pr_warning("x2apic already enabled.\n"); 1511 __x2apic_disable(); 1512 } 1513 setup_clear_cpu_cap(X86_FEATURE_X2APIC); 1514 x2apic_state = X2APIC_DISABLED; 1515 x2apic_mode = 0; 1516 return 0; 1517 } 1518 early_param("nox2apic", setup_nox2apic); 1519 1520 /* Called from cpu_init() to enable x2apic on (secondary) cpus */ 1521 void x2apic_setup(void) 1522 { 1523 /* 1524 * If x2apic is not in ON state, disable it if already enabled 1525 * from BIOS. 1526 */ 1527 if (x2apic_state != X2APIC_ON) { 1528 __x2apic_disable(); 1529 return; 1530 } 1531 __x2apic_enable(); 1532 } 1533 1534 static __init void x2apic_disable(void) 1535 { 1536 u32 x2apic_id, state = x2apic_state; 1537 1538 x2apic_mode = 0; 1539 x2apic_state = X2APIC_DISABLED; 1540 1541 if (state != X2APIC_ON) 1542 return; 1543 1544 x2apic_id = read_apic_id(); 1545 if (x2apic_id >= 255) 1546 panic("Cannot disable x2apic, id: %08x\n", x2apic_id); 1547 1548 __x2apic_disable(); 1549 register_lapic_address(mp_lapic_addr); 1550 } 1551 1552 static __init void x2apic_enable(void) 1553 { 1554 if (x2apic_state != X2APIC_OFF) 1555 return; 1556 1557 x2apic_mode = 1; 1558 x2apic_state = X2APIC_ON; 1559 __x2apic_enable(); 1560 } 1561 1562 static __init void try_to_enable_x2apic(int remap_mode) 1563 { 1564 if (x2apic_state == X2APIC_DISABLED) 1565 return; 1566 1567 if (remap_mode != IRQ_REMAP_X2APIC_MODE) { 1568 /* IR is required if there is APIC ID > 255 even when running 1569 * under KVM 1570 */ 1571 if (max_physical_apicid > 255 || 1572 !hypervisor_x2apic_available()) { 1573 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n"); 1574 x2apic_disable(); 1575 return; 1576 } 1577 1578 /* 1579 * without IR all CPUs can be addressed by IOAPIC/MSI 1580 * only in physical mode 1581 */ 1582 x2apic_phys = 1; 1583 } 1584 x2apic_enable(); 1585 } 1586 1587 void __init check_x2apic(void) 1588 { 1589 if (x2apic_enabled()) { 1590 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n"); 1591 x2apic_mode = 1; 1592 x2apic_state = X2APIC_ON; 1593 } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) { 1594 x2apic_state = X2APIC_DISABLED; 1595 } 1596 } 1597 #else /* CONFIG_X86_X2APIC */ 1598 static int __init validate_x2apic(void) 1599 { 1600 if (!apic_is_x2apic_enabled()) 1601 return 0; 1602 /* 1603 * Checkme: Can we simply turn off x2apic here instead of panic? 1604 */ 1605 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n"); 1606 } 1607 early_initcall(validate_x2apic); 1608 1609 static inline void try_to_enable_x2apic(int remap_mode) { } 1610 static inline void __x2apic_enable(void) { } 1611 #endif /* !CONFIG_X86_X2APIC */ 1612 1613 static int __init try_to_enable_IR(void) 1614 { 1615 #ifdef CONFIG_X86_IO_APIC 1616 if (!x2apic_enabled() && skip_ioapic_setup) { 1617 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n"); 1618 return -1; 1619 } 1620 #endif 1621 return irq_remapping_enable(); 1622 } 1623 1624 void __init enable_IR_x2apic(void) 1625 { 1626 unsigned long flags; 1627 int ret, ir_stat; 1628 1629 if (skip_ioapic_setup) 1630 return; 1631 1632 ir_stat = irq_remapping_prepare(); 1633 if (ir_stat < 0 && !x2apic_supported()) 1634 return; 1635 1636 ret = save_ioapic_entries(); 1637 if (ret) { 1638 pr_info("Saving IO-APIC state failed: %d\n", ret); 1639 return; 1640 } 1641 1642 local_irq_save(flags); 1643 legacy_pic->mask_all(); 1644 mask_ioapic_entries(); 1645 1646 /* If irq_remapping_prepare() succeeded, try to enable it */ 1647 if (ir_stat >= 0) 1648 ir_stat = try_to_enable_IR(); 1649 /* ir_stat contains the remap mode or an error code */ 1650 try_to_enable_x2apic(ir_stat); 1651 1652 if (ir_stat < 0) 1653 restore_ioapic_entries(); 1654 legacy_pic->restore_mask(); 1655 local_irq_restore(flags); 1656 } 1657 1658 #ifdef CONFIG_X86_64 1659 /* 1660 * Detect and enable local APICs on non-SMP boards. 1661 * Original code written by Keir Fraser. 1662 * On AMD64 we trust the BIOS - if it says no APIC it is likely 1663 * not correctly set up (usually the APIC timer won't work etc.) 1664 */ 1665 static int __init detect_init_APIC(void) 1666 { 1667 if (!boot_cpu_has(X86_FEATURE_APIC)) { 1668 pr_info("No local APIC present\n"); 1669 return -1; 1670 } 1671 1672 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1673 return 0; 1674 } 1675 #else 1676 1677 static int __init apic_verify(void) 1678 { 1679 u32 features, h, l; 1680 1681 /* 1682 * The APIC feature bit should now be enabled 1683 * in `cpuid' 1684 */ 1685 features = cpuid_edx(1); 1686 if (!(features & (1 << X86_FEATURE_APIC))) { 1687 pr_warning("Could not enable APIC!\n"); 1688 return -1; 1689 } 1690 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 1691 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1692 1693 /* The BIOS may have set up the APIC at some other address */ 1694 if (boot_cpu_data.x86 >= 6) { 1695 rdmsr(MSR_IA32_APICBASE, l, h); 1696 if (l & MSR_IA32_APICBASE_ENABLE) 1697 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 1698 } 1699 1700 pr_info("Found and enabled local APIC!\n"); 1701 return 0; 1702 } 1703 1704 int __init apic_force_enable(unsigned long addr) 1705 { 1706 u32 h, l; 1707 1708 if (disable_apic) 1709 return -1; 1710 1711 /* 1712 * Some BIOSes disable the local APIC in the APIC_BASE 1713 * MSR. This can only be done in software for Intel P6 or later 1714 * and AMD K7 (Model > 1) or later. 1715 */ 1716 if (boot_cpu_data.x86 >= 6) { 1717 rdmsr(MSR_IA32_APICBASE, l, h); 1718 if (!(l & MSR_IA32_APICBASE_ENABLE)) { 1719 pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 1720 l &= ~MSR_IA32_APICBASE_BASE; 1721 l |= MSR_IA32_APICBASE_ENABLE | addr; 1722 wrmsr(MSR_IA32_APICBASE, l, h); 1723 enabled_via_apicbase = 1; 1724 } 1725 } 1726 return apic_verify(); 1727 } 1728 1729 /* 1730 * Detect and initialize APIC 1731 */ 1732 static int __init detect_init_APIC(void) 1733 { 1734 /* Disabled by kernel option? */ 1735 if (disable_apic) 1736 return -1; 1737 1738 switch (boot_cpu_data.x86_vendor) { 1739 case X86_VENDOR_AMD: 1740 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 1741 (boot_cpu_data.x86 >= 15)) 1742 break; 1743 goto no_apic; 1744 case X86_VENDOR_INTEL: 1745 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 1746 (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC))) 1747 break; 1748 goto no_apic; 1749 default: 1750 goto no_apic; 1751 } 1752 1753 if (!boot_cpu_has(X86_FEATURE_APIC)) { 1754 /* 1755 * Over-ride BIOS and try to enable the local APIC only if 1756 * "lapic" specified. 1757 */ 1758 if (!force_enable_local_apic) { 1759 pr_info("Local APIC disabled by BIOS -- " 1760 "you can enable it with \"lapic\"\n"); 1761 return -1; 1762 } 1763 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) 1764 return -1; 1765 } else { 1766 if (apic_verify()) 1767 return -1; 1768 } 1769 1770 apic_pm_activate(); 1771 1772 return 0; 1773 1774 no_apic: 1775 pr_info("No local APIC present or hardware disabled\n"); 1776 return -1; 1777 } 1778 #endif 1779 1780 /** 1781 * init_apic_mappings - initialize APIC mappings 1782 */ 1783 void __init init_apic_mappings(void) 1784 { 1785 unsigned int new_apicid; 1786 1787 if (x2apic_mode) { 1788 boot_cpu_physical_apicid = read_apic_id(); 1789 return; 1790 } 1791 1792 /* If no local APIC can be found return early */ 1793 if (!smp_found_config && detect_init_APIC()) { 1794 /* lets NOP'ify apic operations */ 1795 pr_info("APIC: disable apic facility\n"); 1796 apic_disable(); 1797 } else { 1798 apic_phys = mp_lapic_addr; 1799 1800 /* 1801 * acpi lapic path already maps that address in 1802 * acpi_register_lapic_address() 1803 */ 1804 if (!acpi_lapic && !smp_found_config) 1805 register_lapic_address(apic_phys); 1806 } 1807 1808 /* 1809 * Fetch the APIC ID of the BSP in case we have a 1810 * default configuration (or the MP table is broken). 1811 */ 1812 new_apicid = read_apic_id(); 1813 if (boot_cpu_physical_apicid != new_apicid) { 1814 boot_cpu_physical_apicid = new_apicid; 1815 /* 1816 * yeah -- we lie about apic_version 1817 * in case if apic was disabled via boot option 1818 * but it's not a problem for SMP compiled kernel 1819 * since smp_sanity_check is prepared for such a case 1820 * and disable smp mode 1821 */ 1822 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 1823 } 1824 } 1825 1826 void __init register_lapic_address(unsigned long address) 1827 { 1828 mp_lapic_addr = address; 1829 1830 if (!x2apic_mode) { 1831 set_fixmap_nocache(FIX_APIC_BASE, address); 1832 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 1833 APIC_BASE, address); 1834 } 1835 if (boot_cpu_physical_apicid == -1U) { 1836 boot_cpu_physical_apicid = read_apic_id(); 1837 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 1838 } 1839 } 1840 1841 /* 1842 * Local APIC interrupts 1843 */ 1844 1845 /* 1846 * This interrupt should _never_ happen with our APIC/SMP architecture 1847 */ 1848 static void __smp_spurious_interrupt(u8 vector) 1849 { 1850 u32 v; 1851 1852 /* 1853 * Check if this really is a spurious interrupt and ACK it 1854 * if it is a vectored one. Just in case... 1855 * Spurious interrupts should not be ACKed. 1856 */ 1857 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1)); 1858 if (v & (1 << (vector & 0x1f))) 1859 ack_APIC_irq(); 1860 1861 inc_irq_stat(irq_spurious_count); 1862 1863 /* see sw-dev-man vol 3, chapter 7.4.13.5 */ 1864 pr_info("spurious APIC interrupt through vector %02x on CPU#%d, " 1865 "should never happen.\n", vector, smp_processor_id()); 1866 } 1867 1868 __visible void smp_spurious_interrupt(struct pt_regs *regs) 1869 { 1870 entering_irq(); 1871 __smp_spurious_interrupt(~regs->orig_ax); 1872 exiting_irq(); 1873 } 1874 1875 __visible void smp_trace_spurious_interrupt(struct pt_regs *regs) 1876 { 1877 u8 vector = ~regs->orig_ax; 1878 1879 entering_irq(); 1880 trace_spurious_apic_entry(vector); 1881 __smp_spurious_interrupt(vector); 1882 trace_spurious_apic_exit(vector); 1883 exiting_irq(); 1884 } 1885 1886 /* 1887 * This interrupt should never happen with our APIC/SMP architecture 1888 */ 1889 static void __smp_error_interrupt(struct pt_regs *regs) 1890 { 1891 u32 v; 1892 u32 i = 0; 1893 static const char * const error_interrupt_reason[] = { 1894 "Send CS error", /* APIC Error Bit 0 */ 1895 "Receive CS error", /* APIC Error Bit 1 */ 1896 "Send accept error", /* APIC Error Bit 2 */ 1897 "Receive accept error", /* APIC Error Bit 3 */ 1898 "Redirectable IPI", /* APIC Error Bit 4 */ 1899 "Send illegal vector", /* APIC Error Bit 5 */ 1900 "Received illegal vector", /* APIC Error Bit 6 */ 1901 "Illegal register address", /* APIC Error Bit 7 */ 1902 }; 1903 1904 /* First tickle the hardware, only then report what went on. -- REW */ 1905 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */ 1906 apic_write(APIC_ESR, 0); 1907 v = apic_read(APIC_ESR); 1908 ack_APIC_irq(); 1909 atomic_inc(&irq_err_count); 1910 1911 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x", 1912 smp_processor_id(), v); 1913 1914 v &= 0xff; 1915 while (v) { 1916 if (v & 0x1) 1917 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); 1918 i++; 1919 v >>= 1; 1920 } 1921 1922 apic_printk(APIC_DEBUG, KERN_CONT "\n"); 1923 1924 } 1925 1926 __visible void smp_error_interrupt(struct pt_regs *regs) 1927 { 1928 entering_irq(); 1929 __smp_error_interrupt(regs); 1930 exiting_irq(); 1931 } 1932 1933 __visible void smp_trace_error_interrupt(struct pt_regs *regs) 1934 { 1935 entering_irq(); 1936 trace_error_apic_entry(ERROR_APIC_VECTOR); 1937 __smp_error_interrupt(regs); 1938 trace_error_apic_exit(ERROR_APIC_VECTOR); 1939 exiting_irq(); 1940 } 1941 1942 /** 1943 * connect_bsp_APIC - attach the APIC to the interrupt system 1944 */ 1945 static void __init connect_bsp_APIC(void) 1946 { 1947 #ifdef CONFIG_X86_32 1948 if (pic_mode) { 1949 /* 1950 * Do not trust the local APIC being empty at bootup. 1951 */ 1952 clear_local_APIC(); 1953 /* 1954 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 1955 * local APIC to INT and NMI lines. 1956 */ 1957 apic_printk(APIC_VERBOSE, "leaving PIC mode, " 1958 "enabling APIC mode.\n"); 1959 imcr_pic_to_apic(); 1960 } 1961 #endif 1962 } 1963 1964 /** 1965 * disconnect_bsp_APIC - detach the APIC from the interrupt system 1966 * @virt_wire_setup: indicates, whether virtual wire mode is selected 1967 * 1968 * Virtual wire mode is necessary to deliver legacy interrupts even when the 1969 * APIC is disabled. 1970 */ 1971 void disconnect_bsp_APIC(int virt_wire_setup) 1972 { 1973 unsigned int value; 1974 1975 #ifdef CONFIG_X86_32 1976 if (pic_mode) { 1977 /* 1978 * Put the board back into PIC mode (has an effect only on 1979 * certain older boards). Note that APIC interrupts, including 1980 * IPIs, won't work beyond this point! The only exception are 1981 * INIT IPIs. 1982 */ 1983 apic_printk(APIC_VERBOSE, "disabling APIC mode, " 1984 "entering PIC mode.\n"); 1985 imcr_apic_to_pic(); 1986 return; 1987 } 1988 #endif 1989 1990 /* Go back to Virtual Wire compatibility mode */ 1991 1992 /* For the spurious interrupt use vector F, and enable it */ 1993 value = apic_read(APIC_SPIV); 1994 value &= ~APIC_VECTOR_MASK; 1995 value |= APIC_SPIV_APIC_ENABLED; 1996 value |= 0xf; 1997 apic_write(APIC_SPIV, value); 1998 1999 if (!virt_wire_setup) { 2000 /* 2001 * For LVT0 make it edge triggered, active high, 2002 * external and enabled 2003 */ 2004 value = apic_read(APIC_LVT0); 2005 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2006 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2007 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2008 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2009 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 2010 apic_write(APIC_LVT0, value); 2011 } else { 2012 /* Disable LVT0 */ 2013 apic_write(APIC_LVT0, APIC_LVT_MASKED); 2014 } 2015 2016 /* 2017 * For LVT1 make it edge triggered, active high, 2018 * nmi and enabled 2019 */ 2020 value = apic_read(APIC_LVT1); 2021 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2022 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2023 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2024 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2025 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 2026 apic_write(APIC_LVT1, value); 2027 } 2028 2029 /* 2030 * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated 2031 * contiguously, it equals to current allocated max logical CPU ID plus 1. 2032 * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range, 2033 * so the maximum of nr_logical_cpuids is nr_cpu_ids. 2034 * 2035 * NOTE: Reserve 0 for BSP. 2036 */ 2037 static int nr_logical_cpuids = 1; 2038 2039 /* 2040 * Used to store mapping between logical CPU IDs and APIC IDs. 2041 */ 2042 static int cpuid_to_apicid[] = { 2043 [0 ... NR_CPUS - 1] = -1, 2044 }; 2045 2046 /* 2047 * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids 2048 * and cpuid_to_apicid[] synchronized. 2049 */ 2050 static int allocate_logical_cpuid(int apicid) 2051 { 2052 int i; 2053 2054 /* 2055 * cpuid <-> apicid mapping is persistent, so when a cpu is up, 2056 * check if the kernel has allocated a cpuid for it. 2057 */ 2058 for (i = 0; i < nr_logical_cpuids; i++) { 2059 if (cpuid_to_apicid[i] == apicid) 2060 return i; 2061 } 2062 2063 /* Allocate a new cpuid. */ 2064 if (nr_logical_cpuids >= nr_cpu_ids) { 2065 WARN_ONCE(1, "Only %d processors supported." 2066 "Processor %d/0x%x and the rest are ignored.\n", 2067 nr_cpu_ids - 1, nr_logical_cpuids, apicid); 2068 return -1; 2069 } 2070 2071 cpuid_to_apicid[nr_logical_cpuids] = apicid; 2072 return nr_logical_cpuids++; 2073 } 2074 2075 int __generic_processor_info(int apicid, int version, bool enabled) 2076 { 2077 int cpu, max = nr_cpu_ids; 2078 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, 2079 phys_cpu_present_map); 2080 2081 /* 2082 * boot_cpu_physical_apicid is designed to have the apicid 2083 * returned by read_apic_id(), i.e, the apicid of the 2084 * currently booting-up processor. However, on some platforms, 2085 * it is temporarily modified by the apicid reported as BSP 2086 * through MP table. Concretely: 2087 * 2088 * - arch/x86/kernel/mpparse.c: MP_processor_info() 2089 * - arch/x86/mm/amdtopology.c: amd_numa_init() 2090 * 2091 * This function is executed with the modified 2092 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel 2093 * parameter doesn't work to disable APs on kdump 2nd kernel. 2094 * 2095 * Since fixing handling of boot_cpu_physical_apicid requires 2096 * another discussion and tests on each platform, we leave it 2097 * for now and here we use read_apic_id() directly in this 2098 * function, __generic_processor_info(). 2099 */ 2100 if (disabled_cpu_apicid != BAD_APICID && 2101 disabled_cpu_apicid != read_apic_id() && 2102 disabled_cpu_apicid == apicid) { 2103 int thiscpu = num_processors + disabled_cpus; 2104 2105 pr_warning("APIC: Disabling requested cpu." 2106 " Processor %d/0x%x ignored.\n", 2107 thiscpu, apicid); 2108 2109 disabled_cpus++; 2110 return -ENODEV; 2111 } 2112 2113 /* 2114 * If boot cpu has not been detected yet, then only allow upto 2115 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu 2116 */ 2117 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && 2118 apicid != boot_cpu_physical_apicid) { 2119 int thiscpu = max + disabled_cpus - 1; 2120 2121 pr_warning( 2122 "APIC: NR_CPUS/possible_cpus limit of %i almost" 2123 " reached. Keeping one slot for boot cpu." 2124 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 2125 2126 disabled_cpus++; 2127 return -ENODEV; 2128 } 2129 2130 if (num_processors >= nr_cpu_ids) { 2131 int thiscpu = max + disabled_cpus; 2132 2133 if (enabled) { 2134 pr_warning("APIC: NR_CPUS/possible_cpus limit of %i " 2135 "reached. Processor %d/0x%x ignored.\n", 2136 max, thiscpu, apicid); 2137 } 2138 2139 disabled_cpus++; 2140 return -EINVAL; 2141 } 2142 2143 if (apicid == boot_cpu_physical_apicid) { 2144 /* 2145 * x86_bios_cpu_apicid is required to have processors listed 2146 * in same order as logical cpu numbers. Hence the first 2147 * entry is BSP, and so on. 2148 * boot_cpu_init() already hold bit 0 in cpu_present_mask 2149 * for BSP. 2150 */ 2151 cpu = 0; 2152 2153 /* Logical cpuid 0 is reserved for BSP. */ 2154 cpuid_to_apicid[0] = apicid; 2155 } else { 2156 cpu = allocate_logical_cpuid(apicid); 2157 if (cpu < 0) { 2158 disabled_cpus++; 2159 return -EINVAL; 2160 } 2161 } 2162 2163 /* 2164 * Validate version 2165 */ 2166 if (version == 0x0) { 2167 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", 2168 cpu, apicid); 2169 version = 0x10; 2170 } 2171 2172 if (version != boot_cpu_apic_version) { 2173 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", 2174 boot_cpu_apic_version, cpu, version); 2175 } 2176 2177 if (apicid > max_physical_apicid) 2178 max_physical_apicid = apicid; 2179 2180 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 2181 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 2182 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 2183 #endif 2184 #ifdef CONFIG_X86_32 2185 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 2186 apic->x86_32_early_logical_apicid(cpu); 2187 #endif 2188 set_cpu_possible(cpu, true); 2189 2190 if (enabled) { 2191 num_processors++; 2192 physid_set(apicid, phys_cpu_present_map); 2193 set_cpu_present(cpu, true); 2194 } else { 2195 disabled_cpus++; 2196 } 2197 2198 return cpu; 2199 } 2200 2201 int generic_processor_info(int apicid, int version) 2202 { 2203 return __generic_processor_info(apicid, version, true); 2204 } 2205 2206 int hard_smp_processor_id(void) 2207 { 2208 return read_apic_id(); 2209 } 2210 2211 void default_init_apic_ldr(void) 2212 { 2213 unsigned long val; 2214 2215 apic_write(APIC_DFR, APIC_DFR_VALUE); 2216 val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; 2217 val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); 2218 apic_write(APIC_LDR, val); 2219 } 2220 2221 int default_cpu_mask_to_apicid_and(const struct cpumask *cpumask, 2222 const struct cpumask *andmask, 2223 unsigned int *apicid) 2224 { 2225 unsigned int cpu; 2226 2227 for_each_cpu_and(cpu, cpumask, andmask) { 2228 if (cpumask_test_cpu(cpu, cpu_online_mask)) 2229 break; 2230 } 2231 2232 if (likely(cpu < nr_cpu_ids)) { 2233 *apicid = per_cpu(x86_cpu_to_apicid, cpu); 2234 return 0; 2235 } 2236 2237 return -EINVAL; 2238 } 2239 2240 /* 2241 * Override the generic EOI implementation with an optimized version. 2242 * Only called during early boot when only one CPU is active and with 2243 * interrupts disabled, so we know this does not race with actual APIC driver 2244 * use. 2245 */ 2246 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) 2247 { 2248 struct apic **drv; 2249 2250 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { 2251 /* Should happen once for each apic */ 2252 WARN_ON((*drv)->eoi_write == eoi_write); 2253 (*drv)->native_eoi_write = (*drv)->eoi_write; 2254 (*drv)->eoi_write = eoi_write; 2255 } 2256 } 2257 2258 static void __init apic_bsp_up_setup(void) 2259 { 2260 #ifdef CONFIG_X86_64 2261 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid)); 2262 #else 2263 /* 2264 * Hack: In case of kdump, after a crash, kernel might be booting 2265 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 2266 * might be zero if read from MP tables. Get it from LAPIC. 2267 */ 2268 # ifdef CONFIG_CRASH_DUMP 2269 boot_cpu_physical_apicid = read_apic_id(); 2270 # endif 2271 #endif 2272 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 2273 } 2274 2275 /** 2276 * apic_bsp_setup - Setup function for local apic and io-apic 2277 * @upmode: Force UP mode (for APIC_init_uniprocessor) 2278 * 2279 * Returns: 2280 * apic_id of BSP APIC 2281 */ 2282 int __init apic_bsp_setup(bool upmode) 2283 { 2284 int id; 2285 2286 connect_bsp_APIC(); 2287 if (upmode) 2288 apic_bsp_up_setup(); 2289 setup_local_APIC(); 2290 2291 if (x2apic_mode) 2292 id = apic_read(APIC_LDR); 2293 else 2294 id = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 2295 2296 enable_IO_APIC(); 2297 end_local_APIC_setup(); 2298 irq_remap_enable_fault_handling(); 2299 setup_IO_APIC(); 2300 /* Setup local timer */ 2301 x86_init.timers.setup_percpu_clockev(); 2302 return id; 2303 } 2304 2305 /* 2306 * This initializes the IO-APIC and APIC hardware if this is 2307 * a UP kernel. 2308 */ 2309 int __init APIC_init_uniprocessor(void) 2310 { 2311 if (disable_apic) { 2312 pr_info("Apic disabled\n"); 2313 return -1; 2314 } 2315 #ifdef CONFIG_X86_64 2316 if (!boot_cpu_has(X86_FEATURE_APIC)) { 2317 disable_apic = 1; 2318 pr_info("Apic disabled by BIOS\n"); 2319 return -1; 2320 } 2321 #else 2322 if (!smp_found_config && !boot_cpu_has(X86_FEATURE_APIC)) 2323 return -1; 2324 2325 /* 2326 * Complain if the BIOS pretends there is one. 2327 */ 2328 if (!boot_cpu_has(X86_FEATURE_APIC) && 2329 APIC_INTEGRATED(boot_cpu_apic_version)) { 2330 pr_err("BIOS bug, local APIC 0x%x not detected!...\n", 2331 boot_cpu_physical_apicid); 2332 return -1; 2333 } 2334 #endif 2335 2336 if (!smp_found_config) 2337 disable_ioapic_support(); 2338 2339 default_setup_apic_routing(); 2340 apic_bsp_setup(true); 2341 return 0; 2342 } 2343 2344 #ifdef CONFIG_UP_LATE_INIT 2345 void __init up_late_init(void) 2346 { 2347 APIC_init_uniprocessor(); 2348 } 2349 #endif 2350 2351 /* 2352 * Power management 2353 */ 2354 #ifdef CONFIG_PM 2355 2356 static struct { 2357 /* 2358 * 'active' is true if the local APIC was enabled by us and 2359 * not the BIOS; this signifies that we are also responsible 2360 * for disabling it before entering apm/acpi suspend 2361 */ 2362 int active; 2363 /* r/w apic fields */ 2364 unsigned int apic_id; 2365 unsigned int apic_taskpri; 2366 unsigned int apic_ldr; 2367 unsigned int apic_dfr; 2368 unsigned int apic_spiv; 2369 unsigned int apic_lvtt; 2370 unsigned int apic_lvtpc; 2371 unsigned int apic_lvt0; 2372 unsigned int apic_lvt1; 2373 unsigned int apic_lvterr; 2374 unsigned int apic_tmict; 2375 unsigned int apic_tdcr; 2376 unsigned int apic_thmr; 2377 unsigned int apic_cmci; 2378 } apic_pm_state; 2379 2380 static int lapic_suspend(void) 2381 { 2382 unsigned long flags; 2383 int maxlvt; 2384 2385 if (!apic_pm_state.active) 2386 return 0; 2387 2388 maxlvt = lapic_get_maxlvt(); 2389 2390 apic_pm_state.apic_id = apic_read(APIC_ID); 2391 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 2392 apic_pm_state.apic_ldr = apic_read(APIC_LDR); 2393 apic_pm_state.apic_dfr = apic_read(APIC_DFR); 2394 apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2395 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2396 if (maxlvt >= 4) 2397 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2398 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2399 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2400 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2401 apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2402 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 2403 #ifdef CONFIG_X86_THERMAL_VECTOR 2404 if (maxlvt >= 5) 2405 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2406 #endif 2407 #ifdef CONFIG_X86_MCE_INTEL 2408 if (maxlvt >= 6) 2409 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI); 2410 #endif 2411 2412 local_irq_save(flags); 2413 disable_local_APIC(); 2414 2415 irq_remapping_disable(); 2416 2417 local_irq_restore(flags); 2418 return 0; 2419 } 2420 2421 static void lapic_resume(void) 2422 { 2423 unsigned int l, h; 2424 unsigned long flags; 2425 int maxlvt; 2426 2427 if (!apic_pm_state.active) 2428 return; 2429 2430 local_irq_save(flags); 2431 2432 /* 2433 * IO-APIC and PIC have their own resume routines. 2434 * We just mask them here to make sure the interrupt 2435 * subsystem is completely quiet while we enable x2apic 2436 * and interrupt-remapping. 2437 */ 2438 mask_ioapic_entries(); 2439 legacy_pic->mask_all(); 2440 2441 if (x2apic_mode) { 2442 __x2apic_enable(); 2443 } else { 2444 /* 2445 * Make sure the APICBASE points to the right address 2446 * 2447 * FIXME! This will be wrong if we ever support suspend on 2448 * SMP! We'll need to do this as part of the CPU restore! 2449 */ 2450 if (boot_cpu_data.x86 >= 6) { 2451 rdmsr(MSR_IA32_APICBASE, l, h); 2452 l &= ~MSR_IA32_APICBASE_BASE; 2453 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2454 wrmsr(MSR_IA32_APICBASE, l, h); 2455 } 2456 } 2457 2458 maxlvt = lapic_get_maxlvt(); 2459 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2460 apic_write(APIC_ID, apic_pm_state.apic_id); 2461 apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2462 apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2463 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2464 apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2465 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2466 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 2467 #ifdef CONFIG_X86_THERMAL_VECTOR 2468 if (maxlvt >= 5) 2469 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2470 #endif 2471 #ifdef CONFIG_X86_MCE_INTEL 2472 if (maxlvt >= 6) 2473 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci); 2474 #endif 2475 if (maxlvt >= 4) 2476 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2477 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2478 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2479 apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2480 apic_write(APIC_ESR, 0); 2481 apic_read(APIC_ESR); 2482 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2483 apic_write(APIC_ESR, 0); 2484 apic_read(APIC_ESR); 2485 2486 irq_remapping_reenable(x2apic_mode); 2487 2488 local_irq_restore(flags); 2489 } 2490 2491 /* 2492 * This device has no shutdown method - fully functioning local APICs 2493 * are needed on every CPU up until machine_halt/restart/poweroff. 2494 */ 2495 2496 static struct syscore_ops lapic_syscore_ops = { 2497 .resume = lapic_resume, 2498 .suspend = lapic_suspend, 2499 }; 2500 2501 static void apic_pm_activate(void) 2502 { 2503 apic_pm_state.active = 1; 2504 } 2505 2506 static int __init init_lapic_sysfs(void) 2507 { 2508 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 2509 if (boot_cpu_has(X86_FEATURE_APIC)) 2510 register_syscore_ops(&lapic_syscore_ops); 2511 2512 return 0; 2513 } 2514 2515 /* local apic needs to resume before other devices access its registers. */ 2516 core_initcall(init_lapic_sysfs); 2517 2518 #else /* CONFIG_PM */ 2519 2520 static void apic_pm_activate(void) { } 2521 2522 #endif /* CONFIG_PM */ 2523 2524 #ifdef CONFIG_X86_64 2525 2526 static int multi_checked; 2527 static int multi; 2528 2529 static int set_multi(const struct dmi_system_id *d) 2530 { 2531 if (multi) 2532 return 0; 2533 pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2534 multi = 1; 2535 return 0; 2536 } 2537 2538 static const struct dmi_system_id multi_dmi_table[] = { 2539 { 2540 .callback = set_multi, 2541 .ident = "IBM System Summit2", 2542 .matches = { 2543 DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2544 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2545 }, 2546 }, 2547 {} 2548 }; 2549 2550 static void dmi_check_multi(void) 2551 { 2552 if (multi_checked) 2553 return; 2554 2555 dmi_check_system(multi_dmi_table); 2556 multi_checked = 1; 2557 } 2558 2559 /* 2560 * apic_is_clustered_box() -- Check if we can expect good TSC 2561 * 2562 * Thus far, the major user of this is IBM's Summit2 series: 2563 * Clustered boxes may have unsynced TSC problems if they are 2564 * multi-chassis. 2565 * Use DMI to check them 2566 */ 2567 int apic_is_clustered_box(void) 2568 { 2569 dmi_check_multi(); 2570 return multi; 2571 } 2572 #endif 2573 2574 /* 2575 * APIC command line parameters 2576 */ 2577 static int __init setup_disableapic(char *arg) 2578 { 2579 disable_apic = 1; 2580 setup_clear_cpu_cap(X86_FEATURE_APIC); 2581 return 0; 2582 } 2583 early_param("disableapic", setup_disableapic); 2584 2585 /* same as disableapic, for compatibility */ 2586 static int __init setup_nolapic(char *arg) 2587 { 2588 return setup_disableapic(arg); 2589 } 2590 early_param("nolapic", setup_nolapic); 2591 2592 static int __init parse_lapic_timer_c2_ok(char *arg) 2593 { 2594 local_apic_timer_c2_ok = 1; 2595 return 0; 2596 } 2597 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2598 2599 static int __init parse_disable_apic_timer(char *arg) 2600 { 2601 disable_apic_timer = 1; 2602 return 0; 2603 } 2604 early_param("noapictimer", parse_disable_apic_timer); 2605 2606 static int __init parse_nolapic_timer(char *arg) 2607 { 2608 disable_apic_timer = 1; 2609 return 0; 2610 } 2611 early_param("nolapic_timer", parse_nolapic_timer); 2612 2613 static int __init apic_set_verbosity(char *arg) 2614 { 2615 if (!arg) { 2616 #ifdef CONFIG_X86_64 2617 skip_ioapic_setup = 0; 2618 return 0; 2619 #endif 2620 return -EINVAL; 2621 } 2622 2623 if (strcmp("debug", arg) == 0) 2624 apic_verbosity = APIC_DEBUG; 2625 else if (strcmp("verbose", arg) == 0) 2626 apic_verbosity = APIC_VERBOSE; 2627 else { 2628 pr_warning("APIC Verbosity level %s not recognised" 2629 " use apic=verbose or apic=debug\n", arg); 2630 return -EINVAL; 2631 } 2632 2633 return 0; 2634 } 2635 early_param("apic", apic_set_verbosity); 2636 2637 static int __init lapic_insert_resource(void) 2638 { 2639 if (!apic_phys) 2640 return -1; 2641 2642 /* Put local APIC into the resource map. */ 2643 lapic_resource.start = apic_phys; 2644 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2645 insert_resource(&iomem_resource, &lapic_resource); 2646 2647 return 0; 2648 } 2649 2650 /* 2651 * need call insert after e820_reserve_resources() 2652 * that is using request_resource 2653 */ 2654 late_initcall(lapic_insert_resource); 2655 2656 static int __init apic_set_disabled_cpu_apicid(char *arg) 2657 { 2658 if (!arg || !get_option(&arg, &disabled_cpu_apicid)) 2659 return -EINVAL; 2660 2661 return 0; 2662 } 2663 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); 2664 2665 static int __init apic_set_extnmi(char *arg) 2666 { 2667 if (!arg) 2668 return -EINVAL; 2669 2670 if (!strncmp("all", arg, 3)) 2671 apic_extnmi = APIC_EXTNMI_ALL; 2672 else if (!strncmp("none", arg, 4)) 2673 apic_extnmi = APIC_EXTNMI_NONE; 2674 else if (!strncmp("bsp", arg, 3)) 2675 apic_extnmi = APIC_EXTNMI_BSP; 2676 else { 2677 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg); 2678 return -EINVAL; 2679 } 2680 2681 return 0; 2682 } 2683 early_param("apic_extnmi", apic_set_extnmi); 2684