1 /* 2 * Local APIC handling, local APIC timers 3 * 4 * (c) 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 5 * 6 * Fixes 7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 8 * thanks to Eric Gilmore 9 * and Rolf G. Tews 10 * for testing these extensively. 11 * Maciej W. Rozycki : Various updates and fixes. 12 * Mikael Pettersson : Power Management for UP-APIC. 13 * Pavel Machek and 14 * Mikael Pettersson : PM converted to driver model. 15 */ 16 17 #include <linux/perf_event.h> 18 #include <linux/kernel_stat.h> 19 #include <linux/mc146818rtc.h> 20 #include <linux/acpi_pmtmr.h> 21 #include <linux/clockchips.h> 22 #include <linux/interrupt.h> 23 #include <linux/bootmem.h> 24 #include <linux/ftrace.h> 25 #include <linux/ioport.h> 26 #include <linux/export.h> 27 #include <linux/syscore_ops.h> 28 #include <linux/delay.h> 29 #include <linux/timex.h> 30 #include <linux/i8253.h> 31 #include <linux/dmar.h> 32 #include <linux/init.h> 33 #include <linux/cpu.h> 34 #include <linux/dmi.h> 35 #include <linux/smp.h> 36 #include <linux/mm.h> 37 38 #include <asm/trace/irq_vectors.h> 39 #include <asm/irq_remapping.h> 40 #include <asm/perf_event.h> 41 #include <asm/x86_init.h> 42 #include <asm/pgalloc.h> 43 #include <linux/atomic.h> 44 #include <asm/mpspec.h> 45 #include <asm/i8259.h> 46 #include <asm/proto.h> 47 #include <asm/apic.h> 48 #include <asm/io_apic.h> 49 #include <asm/desc.h> 50 #include <asm/hpet.h> 51 #include <asm/mtrr.h> 52 #include <asm/time.h> 53 #include <asm/smp.h> 54 #include <asm/mce.h> 55 #include <asm/tsc.h> 56 #include <asm/hypervisor.h> 57 #include <asm/cpu_device_id.h> 58 #include <asm/intel-family.h> 59 60 unsigned int num_processors; 61 62 unsigned disabled_cpus; 63 64 /* Processor that is doing the boot up */ 65 unsigned int boot_cpu_physical_apicid = -1U; 66 EXPORT_SYMBOL_GPL(boot_cpu_physical_apicid); 67 68 u8 boot_cpu_apic_version; 69 70 /* 71 * The highest APIC ID seen during enumeration. 72 */ 73 static unsigned int max_physical_apicid; 74 75 /* 76 * Bitmask of physically existing CPUs: 77 */ 78 physid_mask_t phys_cpu_present_map; 79 80 /* 81 * Processor to be disabled specified by kernel parameter 82 * disable_cpu_apicid=<int>, mostly used for the kdump 2nd kernel to 83 * avoid undefined behaviour caused by sending INIT from AP to BSP. 84 */ 85 static unsigned int disabled_cpu_apicid __read_mostly = BAD_APICID; 86 87 /* 88 * This variable controls which CPUs receive external NMIs. By default, 89 * external NMIs are delivered only to the BSP. 90 */ 91 static int apic_extnmi = APIC_EXTNMI_BSP; 92 93 /* 94 * Map cpu index to physical APIC ID 95 */ 96 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_cpu_to_apicid, BAD_APICID); 97 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid, BAD_APICID); 98 DEFINE_EARLY_PER_CPU_READ_MOSTLY(u32, x86_cpu_to_acpiid, U32_MAX); 99 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_apicid); 100 EXPORT_EARLY_PER_CPU_SYMBOL(x86_bios_cpu_apicid); 101 EXPORT_EARLY_PER_CPU_SYMBOL(x86_cpu_to_acpiid); 102 103 #ifdef CONFIG_X86_32 104 105 /* 106 * On x86_32, the mapping between cpu and logical apicid may vary 107 * depending on apic in use. The following early percpu variable is 108 * used for the mapping. This is where the behaviors of x86_64 and 32 109 * actually diverge. Let's keep it ugly for now. 110 */ 111 DEFINE_EARLY_PER_CPU_READ_MOSTLY(int, x86_cpu_to_logical_apicid, BAD_APICID); 112 113 /* Local APIC was disabled by the BIOS and enabled by the kernel */ 114 static int enabled_via_apicbase; 115 116 /* 117 * Handle interrupt mode configuration register (IMCR). 118 * This register controls whether the interrupt signals 119 * that reach the BSP come from the master PIC or from the 120 * local APIC. Before entering Symmetric I/O Mode, either 121 * the BIOS or the operating system must switch out of 122 * PIC Mode by changing the IMCR. 123 */ 124 static inline void imcr_pic_to_apic(void) 125 { 126 /* select IMCR register */ 127 outb(0x70, 0x22); 128 /* NMI and 8259 INTR go through APIC */ 129 outb(0x01, 0x23); 130 } 131 132 static inline void imcr_apic_to_pic(void) 133 { 134 /* select IMCR register */ 135 outb(0x70, 0x22); 136 /* NMI and 8259 INTR go directly to BSP */ 137 outb(0x00, 0x23); 138 } 139 #endif 140 141 /* 142 * Knob to control our willingness to enable the local APIC. 143 * 144 * +1=force-enable 145 */ 146 static int force_enable_local_apic __initdata; 147 148 /* 149 * APIC command line parameters 150 */ 151 static int __init parse_lapic(char *arg) 152 { 153 if (IS_ENABLED(CONFIG_X86_32) && !arg) 154 force_enable_local_apic = 1; 155 else if (arg && !strncmp(arg, "notscdeadline", 13)) 156 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 157 return 0; 158 } 159 early_param("lapic", parse_lapic); 160 161 #ifdef CONFIG_X86_64 162 static int apic_calibrate_pmtmr __initdata; 163 static __init int setup_apicpmtimer(char *s) 164 { 165 apic_calibrate_pmtmr = 1; 166 notsc_setup(NULL); 167 return 0; 168 } 169 __setup("apicpmtimer", setup_apicpmtimer); 170 #endif 171 172 unsigned long mp_lapic_addr; 173 int disable_apic; 174 /* Disable local APIC timer from the kernel commandline or via dmi quirk */ 175 static int disable_apic_timer __initdata; 176 /* Local APIC timer works in C2 */ 177 int local_apic_timer_c2_ok; 178 EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok); 179 180 /* 181 * Debug level, exported for io_apic.c 182 */ 183 unsigned int apic_verbosity; 184 185 int pic_mode; 186 187 /* Have we found an MP table */ 188 int smp_found_config; 189 190 static struct resource lapic_resource = { 191 .name = "Local APIC", 192 .flags = IORESOURCE_MEM | IORESOURCE_BUSY, 193 }; 194 195 unsigned int lapic_timer_frequency = 0; 196 197 static void apic_pm_activate(void); 198 199 static unsigned long apic_phys; 200 201 /* 202 * Get the LAPIC version 203 */ 204 static inline int lapic_get_version(void) 205 { 206 return GET_APIC_VERSION(apic_read(APIC_LVR)); 207 } 208 209 /* 210 * Check, if the APIC is integrated or a separate chip 211 */ 212 static inline int lapic_is_integrated(void) 213 { 214 return APIC_INTEGRATED(lapic_get_version()); 215 } 216 217 /* 218 * Check, whether this is a modern or a first generation APIC 219 */ 220 static int modern_apic(void) 221 { 222 /* AMD systems use old APIC versions, so check the CPU */ 223 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD && 224 boot_cpu_data.x86 >= 0xf) 225 return 1; 226 return lapic_get_version() >= 0x14; 227 } 228 229 /* 230 * right after this call apic become NOOP driven 231 * so apic->write/read doesn't do anything 232 */ 233 static void __init apic_disable(void) 234 { 235 pr_info("APIC: switched to apic NOOP\n"); 236 apic = &apic_noop; 237 } 238 239 void native_apic_wait_icr_idle(void) 240 { 241 while (apic_read(APIC_ICR) & APIC_ICR_BUSY) 242 cpu_relax(); 243 } 244 245 u32 native_safe_apic_wait_icr_idle(void) 246 { 247 u32 send_status; 248 int timeout; 249 250 timeout = 0; 251 do { 252 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY; 253 if (!send_status) 254 break; 255 inc_irq_stat(icr_read_retry_count); 256 udelay(100); 257 } while (timeout++ < 1000); 258 259 return send_status; 260 } 261 262 void native_apic_icr_write(u32 low, u32 id) 263 { 264 unsigned long flags; 265 266 local_irq_save(flags); 267 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id)); 268 apic_write(APIC_ICR, low); 269 local_irq_restore(flags); 270 } 271 272 u64 native_apic_icr_read(void) 273 { 274 u32 icr1, icr2; 275 276 icr2 = apic_read(APIC_ICR2); 277 icr1 = apic_read(APIC_ICR); 278 279 return icr1 | ((u64)icr2 << 32); 280 } 281 282 #ifdef CONFIG_X86_32 283 /** 284 * get_physical_broadcast - Get number of physical broadcast IDs 285 */ 286 int get_physical_broadcast(void) 287 { 288 return modern_apic() ? 0xff : 0xf; 289 } 290 #endif 291 292 /** 293 * lapic_get_maxlvt - get the maximum number of local vector table entries 294 */ 295 int lapic_get_maxlvt(void) 296 { 297 /* 298 * - we always have APIC integrated on 64bit mode 299 * - 82489DXs do not report # of LVT entries 300 */ 301 return lapic_is_integrated() ? GET_APIC_MAXLVT(apic_read(APIC_LVR)) : 2; 302 } 303 304 /* 305 * Local APIC timer 306 */ 307 308 /* Clock divisor */ 309 #define APIC_DIVISOR 16 310 #define TSC_DIVISOR 8 311 312 /* 313 * This function sets up the local APIC timer, with a timeout of 314 * 'clocks' APIC bus clock. During calibration we actually call 315 * this function twice on the boot CPU, once with a bogus timeout 316 * value, second time for real. The other (noncalibrating) CPUs 317 * call this function only once, with the real, calibrated value. 318 * 319 * We do reads before writes even if unnecessary, to get around the 320 * P5 APIC double write bug. 321 */ 322 static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen) 323 { 324 unsigned int lvtt_value, tmp_value; 325 326 lvtt_value = LOCAL_TIMER_VECTOR; 327 if (!oneshot) 328 lvtt_value |= APIC_LVT_TIMER_PERIODIC; 329 else if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 330 lvtt_value |= APIC_LVT_TIMER_TSCDEADLINE; 331 332 if (!lapic_is_integrated()) 333 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV); 334 335 if (!irqen) 336 lvtt_value |= APIC_LVT_MASKED; 337 338 apic_write(APIC_LVTT, lvtt_value); 339 340 if (lvtt_value & APIC_LVT_TIMER_TSCDEADLINE) { 341 /* 342 * See Intel SDM: TSC-Deadline Mode chapter. In xAPIC mode, 343 * writing to the APIC LVTT and TSC_DEADLINE MSR isn't serialized. 344 * According to Intel, MFENCE can do the serialization here. 345 */ 346 asm volatile("mfence" : : : "memory"); 347 348 printk_once(KERN_DEBUG "TSC deadline timer enabled\n"); 349 return; 350 } 351 352 /* 353 * Divide PICLK by 16 354 */ 355 tmp_value = apic_read(APIC_TDCR); 356 apic_write(APIC_TDCR, 357 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) | 358 APIC_TDR_DIV_16); 359 360 if (!oneshot) 361 apic_write(APIC_TMICT, clocks / APIC_DIVISOR); 362 } 363 364 /* 365 * Setup extended LVT, AMD specific 366 * 367 * Software should use the LVT offsets the BIOS provides. The offsets 368 * are determined by the subsystems using it like those for MCE 369 * threshold or IBS. On K8 only offset 0 (APIC500) and MCE interrupts 370 * are supported. Beginning with family 10h at least 4 offsets are 371 * available. 372 * 373 * Since the offsets must be consistent for all cores, we keep track 374 * of the LVT offsets in software and reserve the offset for the same 375 * vector also to be used on other cores. An offset is freed by 376 * setting the entry to APIC_EILVT_MASKED. 377 * 378 * If the BIOS is right, there should be no conflicts. Otherwise a 379 * "[Firmware Bug]: ..." error message is generated. However, if 380 * software does not properly determines the offsets, it is not 381 * necessarily a BIOS bug. 382 */ 383 384 static atomic_t eilvt_offsets[APIC_EILVT_NR_MAX]; 385 386 static inline int eilvt_entry_is_changeable(unsigned int old, unsigned int new) 387 { 388 return (old & APIC_EILVT_MASKED) 389 || (new == APIC_EILVT_MASKED) 390 || ((new & ~APIC_EILVT_MASKED) == old); 391 } 392 393 static unsigned int reserve_eilvt_offset(int offset, unsigned int new) 394 { 395 unsigned int rsvd, vector; 396 397 if (offset >= APIC_EILVT_NR_MAX) 398 return ~0; 399 400 rsvd = atomic_read(&eilvt_offsets[offset]); 401 do { 402 vector = rsvd & ~APIC_EILVT_MASKED; /* 0: unassigned */ 403 if (vector && !eilvt_entry_is_changeable(vector, new)) 404 /* may not change if vectors are different */ 405 return rsvd; 406 rsvd = atomic_cmpxchg(&eilvt_offsets[offset], rsvd, new); 407 } while (rsvd != new); 408 409 rsvd &= ~APIC_EILVT_MASKED; 410 if (rsvd && rsvd != vector) 411 pr_info("LVT offset %d assigned for vector 0x%02x\n", 412 offset, rsvd); 413 414 return new; 415 } 416 417 /* 418 * If mask=1, the LVT entry does not generate interrupts while mask=0 419 * enables the vector. See also the BKDGs. Must be called with 420 * preemption disabled. 421 */ 422 423 int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) 424 { 425 unsigned long reg = APIC_EILVTn(offset); 426 unsigned int new, old, reserved; 427 428 new = (mask << 16) | (msg_type << 8) | vector; 429 old = apic_read(reg); 430 reserved = reserve_eilvt_offset(offset, new); 431 432 if (reserved != new) { 433 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 434 "vector 0x%x, but the register is already in use for " 435 "vector 0x%x on another cpu\n", 436 smp_processor_id(), reg, offset, new, reserved); 437 return -EINVAL; 438 } 439 440 if (!eilvt_entry_is_changeable(old, new)) { 441 pr_err(FW_BUG "cpu %d, try to use APIC%lX (LVT offset %d) for " 442 "vector 0x%x, but the register is already in use for " 443 "vector 0x%x on this cpu\n", 444 smp_processor_id(), reg, offset, new, old); 445 return -EBUSY; 446 } 447 448 apic_write(reg, new); 449 450 return 0; 451 } 452 EXPORT_SYMBOL_GPL(setup_APIC_eilvt); 453 454 /* 455 * Program the next event, relative to now 456 */ 457 static int lapic_next_event(unsigned long delta, 458 struct clock_event_device *evt) 459 { 460 apic_write(APIC_TMICT, delta); 461 return 0; 462 } 463 464 static int lapic_next_deadline(unsigned long delta, 465 struct clock_event_device *evt) 466 { 467 u64 tsc; 468 469 tsc = rdtsc(); 470 wrmsrl(MSR_IA32_TSC_DEADLINE, tsc + (((u64) delta) * TSC_DIVISOR)); 471 return 0; 472 } 473 474 static int lapic_timer_shutdown(struct clock_event_device *evt) 475 { 476 unsigned int v; 477 478 /* Lapic used as dummy for broadcast ? */ 479 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 480 return 0; 481 482 v = apic_read(APIC_LVTT); 483 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 484 apic_write(APIC_LVTT, v); 485 apic_write(APIC_TMICT, 0); 486 return 0; 487 } 488 489 static inline int 490 lapic_timer_set_periodic_oneshot(struct clock_event_device *evt, bool oneshot) 491 { 492 /* Lapic used as dummy for broadcast ? */ 493 if (evt->features & CLOCK_EVT_FEAT_DUMMY) 494 return 0; 495 496 __setup_APIC_LVTT(lapic_timer_frequency, oneshot, 1); 497 return 0; 498 } 499 500 static int lapic_timer_set_periodic(struct clock_event_device *evt) 501 { 502 return lapic_timer_set_periodic_oneshot(evt, false); 503 } 504 505 static int lapic_timer_set_oneshot(struct clock_event_device *evt) 506 { 507 return lapic_timer_set_periodic_oneshot(evt, true); 508 } 509 510 /* 511 * Local APIC timer broadcast function 512 */ 513 static void lapic_timer_broadcast(const struct cpumask *mask) 514 { 515 #ifdef CONFIG_SMP 516 apic->send_IPI_mask(mask, LOCAL_TIMER_VECTOR); 517 #endif 518 } 519 520 521 /* 522 * The local apic timer can be used for any function which is CPU local. 523 */ 524 static struct clock_event_device lapic_clockevent = { 525 .name = "lapic", 526 .features = CLOCK_EVT_FEAT_PERIODIC | 527 CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP 528 | CLOCK_EVT_FEAT_DUMMY, 529 .shift = 32, 530 .set_state_shutdown = lapic_timer_shutdown, 531 .set_state_periodic = lapic_timer_set_periodic, 532 .set_state_oneshot = lapic_timer_set_oneshot, 533 .set_state_oneshot_stopped = lapic_timer_shutdown, 534 .set_next_event = lapic_next_event, 535 .broadcast = lapic_timer_broadcast, 536 .rating = 100, 537 .irq = -1, 538 }; 539 static DEFINE_PER_CPU(struct clock_event_device, lapic_events); 540 541 #define DEADLINE_MODEL_MATCH_FUNC(model, func) \ 542 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&func } 543 544 #define DEADLINE_MODEL_MATCH_REV(model, rev) \ 545 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)rev } 546 547 static u32 hsx_deadline_rev(void) 548 { 549 switch (boot_cpu_data.x86_mask) { 550 case 0x02: return 0x3a; /* EP */ 551 case 0x04: return 0x0f; /* EX */ 552 } 553 554 return ~0U; 555 } 556 557 static u32 bdx_deadline_rev(void) 558 { 559 switch (boot_cpu_data.x86_mask) { 560 case 0x02: return 0x00000011; 561 case 0x03: return 0x0700000e; 562 case 0x04: return 0x0f00000c; 563 case 0x05: return 0x0e000003; 564 } 565 566 return ~0U; 567 } 568 569 static u32 skx_deadline_rev(void) 570 { 571 switch (boot_cpu_data.x86_mask) { 572 case 0x03: return 0x01000136; 573 case 0x04: return 0x02000014; 574 } 575 576 return ~0U; 577 } 578 579 static const struct x86_cpu_id deadline_match[] = { 580 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_HASWELL_X, hsx_deadline_rev), 581 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_X, 0x0b000020), 582 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_BROADWELL_XEON_D, bdx_deadline_rev), 583 DEADLINE_MODEL_MATCH_FUNC( INTEL_FAM6_SKYLAKE_X, skx_deadline_rev), 584 585 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_CORE, 0x22), 586 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_ULT, 0x20), 587 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_HASWELL_GT3E, 0x17), 588 589 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_CORE, 0x25), 590 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_BROADWELL_GT3E, 0x17), 591 592 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_MOBILE, 0xb2), 593 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_SKYLAKE_DESKTOP, 0xb2), 594 595 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_MOBILE, 0x52), 596 DEADLINE_MODEL_MATCH_REV ( INTEL_FAM6_KABYLAKE_DESKTOP, 0x52), 597 598 {}, 599 }; 600 601 static void apic_check_deadline_errata(void) 602 { 603 const struct x86_cpu_id *m; 604 u32 rev; 605 606 if (!boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER) || 607 boot_cpu_has(X86_FEATURE_HYPERVISOR)) 608 return; 609 610 m = x86_match_cpu(deadline_match); 611 if (!m) 612 return; 613 614 /* 615 * Function pointers will have the MSB set due to address layout, 616 * immediate revisions will not. 617 */ 618 if ((long)m->driver_data < 0) 619 rev = ((u32 (*)(void))(m->driver_data))(); 620 else 621 rev = (u32)m->driver_data; 622 623 if (boot_cpu_data.microcode >= rev) 624 return; 625 626 setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER); 627 pr_err(FW_BUG "TSC_DEADLINE disabled due to Errata; " 628 "please update microcode to version: 0x%x (or later)\n", rev); 629 } 630 631 /* 632 * Setup the local APIC timer for this CPU. Copy the initialized values 633 * of the boot CPU and register the clock event in the framework. 634 */ 635 static void setup_APIC_timer(void) 636 { 637 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 638 639 if (this_cpu_has(X86_FEATURE_ARAT)) { 640 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_C3STOP; 641 /* Make LAPIC timer preferrable over percpu HPET */ 642 lapic_clockevent.rating = 150; 643 } 644 645 memcpy(levt, &lapic_clockevent, sizeof(*levt)); 646 levt->cpumask = cpumask_of(smp_processor_id()); 647 648 if (this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 649 levt->name = "lapic-deadline"; 650 levt->features &= ~(CLOCK_EVT_FEAT_PERIODIC | 651 CLOCK_EVT_FEAT_DUMMY); 652 levt->set_next_event = lapic_next_deadline; 653 clockevents_config_and_register(levt, 654 tsc_khz * (1000 / TSC_DIVISOR), 655 0xF, ~0UL); 656 } else 657 clockevents_register_device(levt); 658 } 659 660 /* 661 * Install the updated TSC frequency from recalibration at the TSC 662 * deadline clockevent devices. 663 */ 664 static void __lapic_update_tsc_freq(void *info) 665 { 666 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 667 668 if (!this_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) 669 return; 670 671 clockevents_update_freq(levt, tsc_khz * (1000 / TSC_DIVISOR)); 672 } 673 674 void lapic_update_tsc_freq(void) 675 { 676 /* 677 * The clockevent device's ->mult and ->shift can both be 678 * changed. In order to avoid races, schedule the frequency 679 * update code on each CPU. 680 */ 681 on_each_cpu(__lapic_update_tsc_freq, NULL, 0); 682 } 683 684 /* 685 * In this functions we calibrate APIC bus clocks to the external timer. 686 * 687 * We want to do the calibration only once since we want to have local timer 688 * irqs syncron. CPUs connected by the same APIC bus have the very same bus 689 * frequency. 690 * 691 * This was previously done by reading the PIT/HPET and waiting for a wrap 692 * around to find out, that a tick has elapsed. I have a box, where the PIT 693 * readout is broken, so it never gets out of the wait loop again. This was 694 * also reported by others. 695 * 696 * Monitoring the jiffies value is inaccurate and the clockevents 697 * infrastructure allows us to do a simple substitution of the interrupt 698 * handler. 699 * 700 * The calibration routine also uses the pm_timer when possible, as the PIT 701 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes 702 * back to normal later in the boot process). 703 */ 704 705 #define LAPIC_CAL_LOOPS (HZ/10) 706 707 static __initdata int lapic_cal_loops = -1; 708 static __initdata long lapic_cal_t1, lapic_cal_t2; 709 static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2; 710 static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2; 711 static __initdata unsigned long lapic_cal_j1, lapic_cal_j2; 712 713 /* 714 * Temporary interrupt handler. 715 */ 716 static void __init lapic_cal_handler(struct clock_event_device *dev) 717 { 718 unsigned long long tsc = 0; 719 long tapic = apic_read(APIC_TMCCT); 720 unsigned long pm = acpi_pm_read_early(); 721 722 if (boot_cpu_has(X86_FEATURE_TSC)) 723 tsc = rdtsc(); 724 725 switch (lapic_cal_loops++) { 726 case 0: 727 lapic_cal_t1 = tapic; 728 lapic_cal_tsc1 = tsc; 729 lapic_cal_pm1 = pm; 730 lapic_cal_j1 = jiffies; 731 break; 732 733 case LAPIC_CAL_LOOPS: 734 lapic_cal_t2 = tapic; 735 lapic_cal_tsc2 = tsc; 736 if (pm < lapic_cal_pm1) 737 pm += ACPI_PM_OVRRUN; 738 lapic_cal_pm2 = pm; 739 lapic_cal_j2 = jiffies; 740 break; 741 } 742 } 743 744 static int __init 745 calibrate_by_pmtimer(long deltapm, long *delta, long *deltatsc) 746 { 747 const long pm_100ms = PMTMR_TICKS_PER_SEC / 10; 748 const long pm_thresh = pm_100ms / 100; 749 unsigned long mult; 750 u64 res; 751 752 #ifndef CONFIG_X86_PM_TIMER 753 return -1; 754 #endif 755 756 apic_printk(APIC_VERBOSE, "... PM-Timer delta = %ld\n", deltapm); 757 758 /* Check, if the PM timer is available */ 759 if (!deltapm) 760 return -1; 761 762 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22); 763 764 if (deltapm > (pm_100ms - pm_thresh) && 765 deltapm < (pm_100ms + pm_thresh)) { 766 apic_printk(APIC_VERBOSE, "... PM-Timer result ok\n"); 767 return 0; 768 } 769 770 res = (((u64)deltapm) * mult) >> 22; 771 do_div(res, 1000000); 772 pr_warning("APIC calibration not consistent " 773 "with PM-Timer: %ldms instead of 100ms\n",(long)res); 774 775 /* Correct the lapic counter value */ 776 res = (((u64)(*delta)) * pm_100ms); 777 do_div(res, deltapm); 778 pr_info("APIC delta adjusted to PM-Timer: " 779 "%lu (%ld)\n", (unsigned long)res, *delta); 780 *delta = (long)res; 781 782 /* Correct the tsc counter value */ 783 if (boot_cpu_has(X86_FEATURE_TSC)) { 784 res = (((u64)(*deltatsc)) * pm_100ms); 785 do_div(res, deltapm); 786 apic_printk(APIC_VERBOSE, "TSC delta adjusted to " 787 "PM-Timer: %lu (%ld)\n", 788 (unsigned long)res, *deltatsc); 789 *deltatsc = (long)res; 790 } 791 792 return 0; 793 } 794 795 static int __init calibrate_APIC_clock(void) 796 { 797 struct clock_event_device *levt = this_cpu_ptr(&lapic_events); 798 void (*real_handler)(struct clock_event_device *dev); 799 unsigned long deltaj; 800 long delta, deltatsc; 801 int pm_referenced = 0; 802 803 /** 804 * check if lapic timer has already been calibrated by platform 805 * specific routine, such as tsc calibration code. if so, we just fill 806 * in the clockevent structure and return. 807 */ 808 809 if (boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER)) { 810 return 0; 811 } else if (lapic_timer_frequency) { 812 apic_printk(APIC_VERBOSE, "lapic timer already calibrated %d\n", 813 lapic_timer_frequency); 814 lapic_clockevent.mult = div_sc(lapic_timer_frequency/APIC_DIVISOR, 815 TICK_NSEC, lapic_clockevent.shift); 816 lapic_clockevent.max_delta_ns = 817 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent); 818 lapic_clockevent.max_delta_ticks = 0x7FFFFF; 819 lapic_clockevent.min_delta_ns = 820 clockevent_delta2ns(0xF, &lapic_clockevent); 821 lapic_clockevent.min_delta_ticks = 0xF; 822 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 823 return 0; 824 } 825 826 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n" 827 "calibrating APIC timer ...\n"); 828 829 local_irq_disable(); 830 831 /* Replace the global interrupt handler */ 832 real_handler = global_clock_event->event_handler; 833 global_clock_event->event_handler = lapic_cal_handler; 834 835 /* 836 * Setup the APIC counter to maximum. There is no way the lapic 837 * can underflow in the 100ms detection time frame 838 */ 839 __setup_APIC_LVTT(0xffffffff, 0, 0); 840 841 /* Let the interrupts run */ 842 local_irq_enable(); 843 844 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 845 cpu_relax(); 846 847 local_irq_disable(); 848 849 /* Restore the real event handler */ 850 global_clock_event->event_handler = real_handler; 851 852 /* Build delta t1-t2 as apic timer counts down */ 853 delta = lapic_cal_t1 - lapic_cal_t2; 854 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta); 855 856 deltatsc = (long)(lapic_cal_tsc2 - lapic_cal_tsc1); 857 858 /* we trust the PM based calibration if possible */ 859 pm_referenced = !calibrate_by_pmtimer(lapic_cal_pm2 - lapic_cal_pm1, 860 &delta, &deltatsc); 861 862 /* Calculate the scaled math multiplication factor */ 863 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS, 864 lapic_clockevent.shift); 865 lapic_clockevent.max_delta_ns = 866 clockevent_delta2ns(0x7FFFFFFF, &lapic_clockevent); 867 lapic_clockevent.max_delta_ticks = 0x7FFFFFFF; 868 lapic_clockevent.min_delta_ns = 869 clockevent_delta2ns(0xF, &lapic_clockevent); 870 lapic_clockevent.min_delta_ticks = 0xF; 871 872 lapic_timer_frequency = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS; 873 874 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta); 875 apic_printk(APIC_VERBOSE, "..... mult: %u\n", lapic_clockevent.mult); 876 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n", 877 lapic_timer_frequency); 878 879 if (boot_cpu_has(X86_FEATURE_TSC)) { 880 apic_printk(APIC_VERBOSE, "..... CPU clock speed is " 881 "%ld.%04ld MHz.\n", 882 (deltatsc / LAPIC_CAL_LOOPS) / (1000000 / HZ), 883 (deltatsc / LAPIC_CAL_LOOPS) % (1000000 / HZ)); 884 } 885 886 apic_printk(APIC_VERBOSE, "..... host bus clock speed is " 887 "%u.%04u MHz.\n", 888 lapic_timer_frequency / (1000000 / HZ), 889 lapic_timer_frequency % (1000000 / HZ)); 890 891 /* 892 * Do a sanity check on the APIC calibration result 893 */ 894 if (lapic_timer_frequency < (1000000 / HZ)) { 895 local_irq_enable(); 896 pr_warning("APIC frequency too slow, disabling apic timer\n"); 897 return -1; 898 } 899 900 levt->features &= ~CLOCK_EVT_FEAT_DUMMY; 901 902 /* 903 * PM timer calibration failed or not turned on 904 * so lets try APIC timer based calibration 905 */ 906 if (!pm_referenced) { 907 apic_printk(APIC_VERBOSE, "... verify APIC timer\n"); 908 909 /* 910 * Setup the apic timer manually 911 */ 912 levt->event_handler = lapic_cal_handler; 913 lapic_timer_set_periodic(levt); 914 lapic_cal_loops = -1; 915 916 /* Let the interrupts run */ 917 local_irq_enable(); 918 919 while (lapic_cal_loops <= LAPIC_CAL_LOOPS) 920 cpu_relax(); 921 922 /* Stop the lapic timer */ 923 local_irq_disable(); 924 lapic_timer_shutdown(levt); 925 926 /* Jiffies delta */ 927 deltaj = lapic_cal_j2 - lapic_cal_j1; 928 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj); 929 930 /* Check, if the jiffies result is consistent */ 931 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2) 932 apic_printk(APIC_VERBOSE, "... jiffies result ok\n"); 933 else 934 levt->features |= CLOCK_EVT_FEAT_DUMMY; 935 } 936 local_irq_enable(); 937 938 if (levt->features & CLOCK_EVT_FEAT_DUMMY) { 939 pr_warning("APIC timer disabled due to verification failure\n"); 940 return -1; 941 } 942 943 return 0; 944 } 945 946 /* 947 * Setup the boot APIC 948 * 949 * Calibrate and verify the result. 950 */ 951 void __init setup_boot_APIC_clock(void) 952 { 953 /* 954 * The local apic timer can be disabled via the kernel 955 * commandline or from the CPU detection code. Register the lapic 956 * timer as a dummy clock event source on SMP systems, so the 957 * broadcast mechanism is used. On UP systems simply ignore it. 958 */ 959 if (disable_apic_timer) { 960 pr_info("Disabling APIC timer\n"); 961 /* No broadcast on UP ! */ 962 if (num_possible_cpus() > 1) { 963 lapic_clockevent.mult = 1; 964 setup_APIC_timer(); 965 } 966 return; 967 } 968 969 if (calibrate_APIC_clock()) { 970 /* No broadcast on UP ! */ 971 if (num_possible_cpus() > 1) 972 setup_APIC_timer(); 973 return; 974 } 975 976 /* 977 * If nmi_watchdog is set to IO_APIC, we need the 978 * PIT/HPET going. Otherwise register lapic as a dummy 979 * device. 980 */ 981 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY; 982 983 /* Setup the lapic or request the broadcast */ 984 setup_APIC_timer(); 985 amd_e400_c1e_apic_setup(); 986 } 987 988 void setup_secondary_APIC_clock(void) 989 { 990 setup_APIC_timer(); 991 amd_e400_c1e_apic_setup(); 992 } 993 994 /* 995 * The guts of the apic timer interrupt 996 */ 997 static void local_apic_timer_interrupt(void) 998 { 999 struct clock_event_device *evt = this_cpu_ptr(&lapic_events); 1000 1001 /* 1002 * Normally we should not be here till LAPIC has been initialized but 1003 * in some cases like kdump, its possible that there is a pending LAPIC 1004 * timer interrupt from previous kernel's context and is delivered in 1005 * new kernel the moment interrupts are enabled. 1006 * 1007 * Interrupts are enabled early and LAPIC is setup much later, hence 1008 * its possible that when we get here evt->event_handler is NULL. 1009 * Check for event_handler being NULL and discard the interrupt as 1010 * spurious. 1011 */ 1012 if (!evt->event_handler) { 1013 pr_warning("Spurious LAPIC timer interrupt on cpu %d\n", 1014 smp_processor_id()); 1015 /* Switch it off */ 1016 lapic_timer_shutdown(evt); 1017 return; 1018 } 1019 1020 /* 1021 * the NMI deadlock-detector uses this. 1022 */ 1023 inc_irq_stat(apic_timer_irqs); 1024 1025 evt->event_handler(evt); 1026 } 1027 1028 /* 1029 * Local APIC timer interrupt. This is the most natural way for doing 1030 * local interrupts, but local timer interrupts can be emulated by 1031 * broadcast interrupts too. [in case the hw doesn't support APIC timers] 1032 * 1033 * [ if a single-CPU system runs an SMP kernel then we call the local 1034 * interrupt as well. Thus we cannot inline the local irq ... ] 1035 */ 1036 __visible void __irq_entry smp_apic_timer_interrupt(struct pt_regs *regs) 1037 { 1038 struct pt_regs *old_regs = set_irq_regs(regs); 1039 1040 /* 1041 * NOTE! We'd better ACK the irq immediately, 1042 * because timer handling can be slow. 1043 * 1044 * update_process_times() expects us to have done irq_enter(). 1045 * Besides, if we don't timer interrupts ignore the global 1046 * interrupt lock, which is the WrongThing (tm) to do. 1047 */ 1048 entering_ack_irq(); 1049 trace_local_timer_entry(LOCAL_TIMER_VECTOR); 1050 local_apic_timer_interrupt(); 1051 trace_local_timer_exit(LOCAL_TIMER_VECTOR); 1052 exiting_irq(); 1053 1054 set_irq_regs(old_regs); 1055 } 1056 1057 int setup_profiling_timer(unsigned int multiplier) 1058 { 1059 return -EINVAL; 1060 } 1061 1062 /* 1063 * Local APIC start and shutdown 1064 */ 1065 1066 /** 1067 * clear_local_APIC - shutdown the local APIC 1068 * 1069 * This is called, when a CPU is disabled and before rebooting, so the state of 1070 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS 1071 * leftovers during boot. 1072 */ 1073 void clear_local_APIC(void) 1074 { 1075 int maxlvt; 1076 u32 v; 1077 1078 /* APIC hasn't been mapped yet */ 1079 if (!x2apic_mode && !apic_phys) 1080 return; 1081 1082 maxlvt = lapic_get_maxlvt(); 1083 /* 1084 * Masking an LVT entry can trigger a local APIC error 1085 * if the vector is zero. Mask LVTERR first to prevent this. 1086 */ 1087 if (maxlvt >= 3) { 1088 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */ 1089 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED); 1090 } 1091 /* 1092 * Careful: we have to set masks only first to deassert 1093 * any level-triggered sources. 1094 */ 1095 v = apic_read(APIC_LVTT); 1096 apic_write(APIC_LVTT, v | APIC_LVT_MASKED); 1097 v = apic_read(APIC_LVT0); 1098 apic_write(APIC_LVT0, v | APIC_LVT_MASKED); 1099 v = apic_read(APIC_LVT1); 1100 apic_write(APIC_LVT1, v | APIC_LVT_MASKED); 1101 if (maxlvt >= 4) { 1102 v = apic_read(APIC_LVTPC); 1103 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED); 1104 } 1105 1106 /* lets not touch this if we didn't frob it */ 1107 #ifdef CONFIG_X86_THERMAL_VECTOR 1108 if (maxlvt >= 5) { 1109 v = apic_read(APIC_LVTTHMR); 1110 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED); 1111 } 1112 #endif 1113 #ifdef CONFIG_X86_MCE_INTEL 1114 if (maxlvt >= 6) { 1115 v = apic_read(APIC_LVTCMCI); 1116 if (!(v & APIC_LVT_MASKED)) 1117 apic_write(APIC_LVTCMCI, v | APIC_LVT_MASKED); 1118 } 1119 #endif 1120 1121 /* 1122 * Clean APIC state for other OSs: 1123 */ 1124 apic_write(APIC_LVTT, APIC_LVT_MASKED); 1125 apic_write(APIC_LVT0, APIC_LVT_MASKED); 1126 apic_write(APIC_LVT1, APIC_LVT_MASKED); 1127 if (maxlvt >= 3) 1128 apic_write(APIC_LVTERR, APIC_LVT_MASKED); 1129 if (maxlvt >= 4) 1130 apic_write(APIC_LVTPC, APIC_LVT_MASKED); 1131 1132 /* Integrated APIC (!82489DX) ? */ 1133 if (lapic_is_integrated()) { 1134 if (maxlvt > 3) 1135 /* Clear ESR due to Pentium errata 3AP and 11AP */ 1136 apic_write(APIC_ESR, 0); 1137 apic_read(APIC_ESR); 1138 } 1139 } 1140 1141 /** 1142 * disable_local_APIC - clear and disable the local APIC 1143 */ 1144 void disable_local_APIC(void) 1145 { 1146 unsigned int value; 1147 1148 /* APIC hasn't been mapped yet */ 1149 if (!x2apic_mode && !apic_phys) 1150 return; 1151 1152 clear_local_APIC(); 1153 1154 /* 1155 * Disable APIC (implies clearing of registers 1156 * for 82489DX!). 1157 */ 1158 value = apic_read(APIC_SPIV); 1159 value &= ~APIC_SPIV_APIC_ENABLED; 1160 apic_write(APIC_SPIV, value); 1161 1162 #ifdef CONFIG_X86_32 1163 /* 1164 * When LAPIC was disabled by the BIOS and enabled by the kernel, 1165 * restore the disabled state. 1166 */ 1167 if (enabled_via_apicbase) { 1168 unsigned int l, h; 1169 1170 rdmsr(MSR_IA32_APICBASE, l, h); 1171 l &= ~MSR_IA32_APICBASE_ENABLE; 1172 wrmsr(MSR_IA32_APICBASE, l, h); 1173 } 1174 #endif 1175 } 1176 1177 /* 1178 * If Linux enabled the LAPIC against the BIOS default disable it down before 1179 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and 1180 * not power-off. Additionally clear all LVT entries before disable_local_APIC 1181 * for the case where Linux didn't enable the LAPIC. 1182 */ 1183 void lapic_shutdown(void) 1184 { 1185 unsigned long flags; 1186 1187 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config()) 1188 return; 1189 1190 local_irq_save(flags); 1191 1192 #ifdef CONFIG_X86_32 1193 if (!enabled_via_apicbase) 1194 clear_local_APIC(); 1195 else 1196 #endif 1197 disable_local_APIC(); 1198 1199 1200 local_irq_restore(flags); 1201 } 1202 1203 /** 1204 * sync_Arb_IDs - synchronize APIC bus arbitration IDs 1205 */ 1206 void __init sync_Arb_IDs(void) 1207 { 1208 /* 1209 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not 1210 * needed on AMD. 1211 */ 1212 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1213 return; 1214 1215 /* 1216 * Wait for idle. 1217 */ 1218 apic_wait_icr_idle(); 1219 1220 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n"); 1221 apic_write(APIC_ICR, APIC_DEST_ALLINC | 1222 APIC_INT_LEVELTRIG | APIC_DM_INIT); 1223 } 1224 1225 enum apic_intr_mode_id apic_intr_mode; 1226 1227 static int __init apic_intr_mode_select(void) 1228 { 1229 /* Check kernel option */ 1230 if (disable_apic) { 1231 pr_info("APIC disabled via kernel command line\n"); 1232 return APIC_PIC; 1233 } 1234 1235 /* Check BIOS */ 1236 #ifdef CONFIG_X86_64 1237 /* On 64-bit, the APIC must be integrated, Check local APIC only */ 1238 if (!boot_cpu_has(X86_FEATURE_APIC)) { 1239 disable_apic = 1; 1240 pr_info("APIC disabled by BIOS\n"); 1241 return APIC_PIC; 1242 } 1243 #else 1244 /* On 32-bit, the APIC may be integrated APIC or 82489DX */ 1245 1246 /* Neither 82489DX nor integrated APIC ? */ 1247 if (!boot_cpu_has(X86_FEATURE_APIC) && !smp_found_config) { 1248 disable_apic = 1; 1249 return APIC_PIC; 1250 } 1251 1252 /* If the BIOS pretends there is an integrated APIC ? */ 1253 if (!boot_cpu_has(X86_FEATURE_APIC) && 1254 APIC_INTEGRATED(boot_cpu_apic_version)) { 1255 disable_apic = 1; 1256 pr_err(FW_BUG "Local APIC %d not detected, force emulation\n", 1257 boot_cpu_physical_apicid); 1258 return APIC_PIC; 1259 } 1260 #endif 1261 1262 /* Check MP table or ACPI MADT configuration */ 1263 if (!smp_found_config) { 1264 disable_ioapic_support(); 1265 if (!acpi_lapic) { 1266 pr_info("APIC: ACPI MADT or MP tables are not detected\n"); 1267 return APIC_VIRTUAL_WIRE_NO_CONFIG; 1268 } 1269 return APIC_VIRTUAL_WIRE; 1270 } 1271 1272 #ifdef CONFIG_SMP 1273 /* If SMP should be disabled, then really disable it! */ 1274 if (!setup_max_cpus) { 1275 pr_info("APIC: SMP mode deactivated\n"); 1276 return APIC_SYMMETRIC_IO_NO_ROUTING; 1277 } 1278 1279 if (read_apic_id() != boot_cpu_physical_apicid) { 1280 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1281 read_apic_id(), boot_cpu_physical_apicid); 1282 /* Or can we switch back to PIC here? */ 1283 } 1284 #endif 1285 1286 return APIC_SYMMETRIC_IO; 1287 } 1288 1289 /* Init the interrupt delivery mode for the BSP */ 1290 void __init apic_intr_mode_init(void) 1291 { 1292 bool upmode = IS_ENABLED(CONFIG_UP_LATE_INIT); 1293 1294 apic_intr_mode = apic_intr_mode_select(); 1295 1296 switch (apic_intr_mode) { 1297 case APIC_PIC: 1298 pr_info("APIC: Keep in PIC mode(8259)\n"); 1299 return; 1300 case APIC_VIRTUAL_WIRE: 1301 pr_info("APIC: Switch to virtual wire mode setup\n"); 1302 default_setup_apic_routing(); 1303 break; 1304 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1305 pr_info("APIC: Switch to virtual wire mode setup with no configuration\n"); 1306 upmode = true; 1307 default_setup_apic_routing(); 1308 break; 1309 case APIC_SYMMETRIC_IO: 1310 pr_info("APIC: Switch to symmetric I/O mode setup\n"); 1311 default_setup_apic_routing(); 1312 break; 1313 case APIC_SYMMETRIC_IO_NO_ROUTING: 1314 pr_info("APIC: Switch to symmetric I/O mode setup in no SMP routine\n"); 1315 break; 1316 } 1317 1318 apic_bsp_setup(upmode); 1319 } 1320 1321 static void lapic_setup_esr(void) 1322 { 1323 unsigned int oldvalue, value, maxlvt; 1324 1325 if (!lapic_is_integrated()) { 1326 pr_info("No ESR for 82489DX.\n"); 1327 return; 1328 } 1329 1330 if (apic->disable_esr) { 1331 /* 1332 * Something untraceable is creating bad interrupts on 1333 * secondary quads ... for the moment, just leave the 1334 * ESR disabled - we can't do anything useful with the 1335 * errors anyway - mbligh 1336 */ 1337 pr_info("Leaving ESR disabled.\n"); 1338 return; 1339 } 1340 1341 maxlvt = lapic_get_maxlvt(); 1342 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 1343 apic_write(APIC_ESR, 0); 1344 oldvalue = apic_read(APIC_ESR); 1345 1346 /* enables sending errors */ 1347 value = ERROR_APIC_VECTOR; 1348 apic_write(APIC_LVTERR, value); 1349 1350 /* 1351 * spec says clear errors after enabling vector. 1352 */ 1353 if (maxlvt > 3) 1354 apic_write(APIC_ESR, 0); 1355 value = apic_read(APIC_ESR); 1356 if (value != oldvalue) 1357 apic_printk(APIC_VERBOSE, "ESR value before enabling " 1358 "vector: 0x%08x after: 0x%08x\n", 1359 oldvalue, value); 1360 } 1361 1362 /** 1363 * setup_local_APIC - setup the local APIC 1364 * 1365 * Used to setup local APIC while initializing BSP or bringing up APs. 1366 * Always called with preemption disabled. 1367 */ 1368 void setup_local_APIC(void) 1369 { 1370 int cpu = smp_processor_id(); 1371 unsigned int value, queued; 1372 int i, j, acked = 0; 1373 unsigned long long tsc = 0, ntsc; 1374 long long max_loops = cpu_khz ? cpu_khz : 1000000; 1375 1376 if (boot_cpu_has(X86_FEATURE_TSC)) 1377 tsc = rdtsc(); 1378 1379 if (disable_apic) { 1380 disable_ioapic_support(); 1381 return; 1382 } 1383 1384 #ifdef CONFIG_X86_32 1385 /* Pound the ESR really hard over the head with a big hammer - mbligh */ 1386 if (lapic_is_integrated() && apic->disable_esr) { 1387 apic_write(APIC_ESR, 0); 1388 apic_write(APIC_ESR, 0); 1389 apic_write(APIC_ESR, 0); 1390 apic_write(APIC_ESR, 0); 1391 } 1392 #endif 1393 perf_events_lapic_init(); 1394 1395 /* 1396 * Double-check whether this APIC is really registered. 1397 * This is meaningless in clustered apic mode, so we skip it. 1398 */ 1399 BUG_ON(!apic->apic_id_registered()); 1400 1401 /* 1402 * Intel recommends to set DFR, LDR and TPR before enabling 1403 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 1404 * document number 292116). So here it goes... 1405 */ 1406 apic->init_apic_ldr(); 1407 1408 #ifdef CONFIG_X86_32 1409 /* 1410 * APIC LDR is initialized. If logical_apicid mapping was 1411 * initialized during get_smp_config(), make sure it matches the 1412 * actual value. 1413 */ 1414 i = early_per_cpu(x86_cpu_to_logical_apicid, cpu); 1415 WARN_ON(i != BAD_APICID && i != logical_smp_processor_id()); 1416 /* always use the value from LDR */ 1417 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 1418 logical_smp_processor_id(); 1419 #endif 1420 1421 /* 1422 * Set Task Priority to 'accept all'. We never change this 1423 * later on. 1424 */ 1425 value = apic_read(APIC_TASKPRI); 1426 value &= ~APIC_TPRI_MASK; 1427 apic_write(APIC_TASKPRI, value); 1428 1429 /* 1430 * After a crash, we no longer service the interrupts and a pending 1431 * interrupt from previous kernel might still have ISR bit set. 1432 * 1433 * Most probably by now CPU has serviced that pending interrupt and 1434 * it might not have done the ack_APIC_irq() because it thought, 1435 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it 1436 * does not clear the ISR bit and cpu thinks it has already serivced 1437 * the interrupt. Hence a vector might get locked. It was noticed 1438 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR. 1439 */ 1440 do { 1441 queued = 0; 1442 for (i = APIC_ISR_NR - 1; i >= 0; i--) 1443 queued |= apic_read(APIC_IRR + i*0x10); 1444 1445 for (i = APIC_ISR_NR - 1; i >= 0; i--) { 1446 value = apic_read(APIC_ISR + i*0x10); 1447 for (j = 31; j >= 0; j--) { 1448 if (value & (1<<j)) { 1449 ack_APIC_irq(); 1450 acked++; 1451 } 1452 } 1453 } 1454 if (acked > 256) { 1455 printk(KERN_ERR "LAPIC pending interrupts after %d EOI\n", 1456 acked); 1457 break; 1458 } 1459 if (queued) { 1460 if (boot_cpu_has(X86_FEATURE_TSC) && cpu_khz) { 1461 ntsc = rdtsc(); 1462 max_loops = (cpu_khz << 10) - (ntsc - tsc); 1463 } else 1464 max_loops--; 1465 } 1466 } while (queued && max_loops > 0); 1467 WARN_ON(max_loops <= 0); 1468 1469 /* 1470 * Now that we are all set up, enable the APIC 1471 */ 1472 value = apic_read(APIC_SPIV); 1473 value &= ~APIC_VECTOR_MASK; 1474 /* 1475 * Enable APIC 1476 */ 1477 value |= APIC_SPIV_APIC_ENABLED; 1478 1479 #ifdef CONFIG_X86_32 1480 /* 1481 * Some unknown Intel IO/APIC (or APIC) errata is biting us with 1482 * certain networking cards. If high frequency interrupts are 1483 * happening on a particular IOAPIC pin, plus the IOAPIC routing 1484 * entry is masked/unmasked at a high rate as well then sooner or 1485 * later IOAPIC line gets 'stuck', no more interrupts are received 1486 * from the device. If focus CPU is disabled then the hang goes 1487 * away, oh well :-( 1488 * 1489 * [ This bug can be reproduced easily with a level-triggered 1490 * PCI Ne2000 networking cards and PII/PIII processors, dual 1491 * BX chipset. ] 1492 */ 1493 /* 1494 * Actually disabling the focus CPU check just makes the hang less 1495 * frequent as it makes the interrupt distributon model be more 1496 * like LRU than MRU (the short-term load is more even across CPUs). 1497 */ 1498 1499 /* 1500 * - enable focus processor (bit==0) 1501 * - 64bit mode always use processor focus 1502 * so no need to set it 1503 */ 1504 value &= ~APIC_SPIV_FOCUS_DISABLED; 1505 #endif 1506 1507 /* 1508 * Set spurious IRQ vector 1509 */ 1510 value |= SPURIOUS_APIC_VECTOR; 1511 apic_write(APIC_SPIV, value); 1512 1513 /* 1514 * Set up LVT0, LVT1: 1515 * 1516 * set up through-local-APIC on the boot CPU's LINT0. This is not 1517 * strictly necessary in pure symmetric-IO mode, but sometimes 1518 * we delegate interrupts to the 8259A. 1519 */ 1520 /* 1521 * TODO: set up through-local-APIC from through-I/O-APIC? --macro 1522 */ 1523 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 1524 if (!cpu && (pic_mode || !value)) { 1525 value = APIC_DM_EXTINT; 1526 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", cpu); 1527 } else { 1528 value = APIC_DM_EXTINT | APIC_LVT_MASKED; 1529 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", cpu); 1530 } 1531 apic_write(APIC_LVT0, value); 1532 1533 /* 1534 * Only the BSP sees the LINT1 NMI signal by default. This can be 1535 * modified by apic_extnmi= boot option. 1536 */ 1537 if ((!cpu && apic_extnmi != APIC_EXTNMI_NONE) || 1538 apic_extnmi == APIC_EXTNMI_ALL) 1539 value = APIC_DM_NMI; 1540 else 1541 value = APIC_DM_NMI | APIC_LVT_MASKED; 1542 1543 /* Is 82489DX ? */ 1544 if (!lapic_is_integrated()) 1545 value |= APIC_LVT_LEVEL_TRIGGER; 1546 apic_write(APIC_LVT1, value); 1547 1548 #ifdef CONFIG_X86_MCE_INTEL 1549 /* Recheck CMCI information after local APIC is up on CPU #0 */ 1550 if (!cpu) 1551 cmci_recheck(); 1552 #endif 1553 } 1554 1555 static void end_local_APIC_setup(void) 1556 { 1557 lapic_setup_esr(); 1558 1559 #ifdef CONFIG_X86_32 1560 { 1561 unsigned int value; 1562 /* Disable the local apic timer */ 1563 value = apic_read(APIC_LVTT); 1564 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR); 1565 apic_write(APIC_LVTT, value); 1566 } 1567 #endif 1568 1569 apic_pm_activate(); 1570 } 1571 1572 /* 1573 * APIC setup function for application processors. Called from smpboot.c 1574 */ 1575 void apic_ap_setup(void) 1576 { 1577 setup_local_APIC(); 1578 end_local_APIC_setup(); 1579 } 1580 1581 #ifdef CONFIG_X86_X2APIC 1582 int x2apic_mode; 1583 1584 enum { 1585 X2APIC_OFF, 1586 X2APIC_ON, 1587 X2APIC_DISABLED, 1588 }; 1589 static int x2apic_state; 1590 1591 static void __x2apic_disable(void) 1592 { 1593 u64 msr; 1594 1595 if (!boot_cpu_has(X86_FEATURE_APIC)) 1596 return; 1597 1598 rdmsrl(MSR_IA32_APICBASE, msr); 1599 if (!(msr & X2APIC_ENABLE)) 1600 return; 1601 /* Disable xapic and x2apic first and then reenable xapic mode */ 1602 wrmsrl(MSR_IA32_APICBASE, msr & ~(X2APIC_ENABLE | XAPIC_ENABLE)); 1603 wrmsrl(MSR_IA32_APICBASE, msr & ~X2APIC_ENABLE); 1604 printk_once(KERN_INFO "x2apic disabled\n"); 1605 } 1606 1607 static void __x2apic_enable(void) 1608 { 1609 u64 msr; 1610 1611 rdmsrl(MSR_IA32_APICBASE, msr); 1612 if (msr & X2APIC_ENABLE) 1613 return; 1614 wrmsrl(MSR_IA32_APICBASE, msr | X2APIC_ENABLE); 1615 printk_once(KERN_INFO "x2apic enabled\n"); 1616 } 1617 1618 static int __init setup_nox2apic(char *str) 1619 { 1620 if (x2apic_enabled()) { 1621 int apicid = native_apic_msr_read(APIC_ID); 1622 1623 if (apicid >= 255) { 1624 pr_warning("Apicid: %08x, cannot enforce nox2apic\n", 1625 apicid); 1626 return 0; 1627 } 1628 pr_warning("x2apic already enabled.\n"); 1629 __x2apic_disable(); 1630 } 1631 setup_clear_cpu_cap(X86_FEATURE_X2APIC); 1632 x2apic_state = X2APIC_DISABLED; 1633 x2apic_mode = 0; 1634 return 0; 1635 } 1636 early_param("nox2apic", setup_nox2apic); 1637 1638 /* Called from cpu_init() to enable x2apic on (secondary) cpus */ 1639 void x2apic_setup(void) 1640 { 1641 /* 1642 * If x2apic is not in ON state, disable it if already enabled 1643 * from BIOS. 1644 */ 1645 if (x2apic_state != X2APIC_ON) { 1646 __x2apic_disable(); 1647 return; 1648 } 1649 __x2apic_enable(); 1650 } 1651 1652 static __init void x2apic_disable(void) 1653 { 1654 u32 x2apic_id, state = x2apic_state; 1655 1656 x2apic_mode = 0; 1657 x2apic_state = X2APIC_DISABLED; 1658 1659 if (state != X2APIC_ON) 1660 return; 1661 1662 x2apic_id = read_apic_id(); 1663 if (x2apic_id >= 255) 1664 panic("Cannot disable x2apic, id: %08x\n", x2apic_id); 1665 1666 __x2apic_disable(); 1667 register_lapic_address(mp_lapic_addr); 1668 } 1669 1670 static __init void x2apic_enable(void) 1671 { 1672 if (x2apic_state != X2APIC_OFF) 1673 return; 1674 1675 x2apic_mode = 1; 1676 x2apic_state = X2APIC_ON; 1677 __x2apic_enable(); 1678 } 1679 1680 static __init void try_to_enable_x2apic(int remap_mode) 1681 { 1682 if (x2apic_state == X2APIC_DISABLED) 1683 return; 1684 1685 if (remap_mode != IRQ_REMAP_X2APIC_MODE) { 1686 /* IR is required if there is APIC ID > 255 even when running 1687 * under KVM 1688 */ 1689 if (max_physical_apicid > 255 || 1690 !x86_init.hyper.x2apic_available()) { 1691 pr_info("x2apic: IRQ remapping doesn't support X2APIC mode\n"); 1692 x2apic_disable(); 1693 return; 1694 } 1695 1696 /* 1697 * without IR all CPUs can be addressed by IOAPIC/MSI 1698 * only in physical mode 1699 */ 1700 x2apic_phys = 1; 1701 } 1702 x2apic_enable(); 1703 } 1704 1705 void __init check_x2apic(void) 1706 { 1707 if (x2apic_enabled()) { 1708 pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n"); 1709 x2apic_mode = 1; 1710 x2apic_state = X2APIC_ON; 1711 } else if (!boot_cpu_has(X86_FEATURE_X2APIC)) { 1712 x2apic_state = X2APIC_DISABLED; 1713 } 1714 } 1715 #else /* CONFIG_X86_X2APIC */ 1716 static int __init validate_x2apic(void) 1717 { 1718 if (!apic_is_x2apic_enabled()) 1719 return 0; 1720 /* 1721 * Checkme: Can we simply turn off x2apic here instead of panic? 1722 */ 1723 panic("BIOS has enabled x2apic but kernel doesn't support x2apic, please disable x2apic in BIOS.\n"); 1724 } 1725 early_initcall(validate_x2apic); 1726 1727 static inline void try_to_enable_x2apic(int remap_mode) { } 1728 static inline void __x2apic_enable(void) { } 1729 #endif /* !CONFIG_X86_X2APIC */ 1730 1731 void __init enable_IR_x2apic(void) 1732 { 1733 unsigned long flags; 1734 int ret, ir_stat; 1735 1736 if (skip_ioapic_setup) { 1737 pr_info("Not enabling interrupt remapping due to skipped IO-APIC setup\n"); 1738 return; 1739 } 1740 1741 ir_stat = irq_remapping_prepare(); 1742 if (ir_stat < 0 && !x2apic_supported()) 1743 return; 1744 1745 ret = save_ioapic_entries(); 1746 if (ret) { 1747 pr_info("Saving IO-APIC state failed: %d\n", ret); 1748 return; 1749 } 1750 1751 local_irq_save(flags); 1752 legacy_pic->mask_all(); 1753 mask_ioapic_entries(); 1754 1755 /* If irq_remapping_prepare() succeeded, try to enable it */ 1756 if (ir_stat >= 0) 1757 ir_stat = irq_remapping_enable(); 1758 /* ir_stat contains the remap mode or an error code */ 1759 try_to_enable_x2apic(ir_stat); 1760 1761 if (ir_stat < 0) 1762 restore_ioapic_entries(); 1763 legacy_pic->restore_mask(); 1764 local_irq_restore(flags); 1765 } 1766 1767 #ifdef CONFIG_X86_64 1768 /* 1769 * Detect and enable local APICs on non-SMP boards. 1770 * Original code written by Keir Fraser. 1771 * On AMD64 we trust the BIOS - if it says no APIC it is likely 1772 * not correctly set up (usually the APIC timer won't work etc.) 1773 */ 1774 static int __init detect_init_APIC(void) 1775 { 1776 if (!boot_cpu_has(X86_FEATURE_APIC)) { 1777 pr_info("No local APIC present\n"); 1778 return -1; 1779 } 1780 1781 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1782 return 0; 1783 } 1784 #else 1785 1786 static int __init apic_verify(void) 1787 { 1788 u32 features, h, l; 1789 1790 /* 1791 * The APIC feature bit should now be enabled 1792 * in `cpuid' 1793 */ 1794 features = cpuid_edx(1); 1795 if (!(features & (1 << X86_FEATURE_APIC))) { 1796 pr_warning("Could not enable APIC!\n"); 1797 return -1; 1798 } 1799 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC); 1800 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 1801 1802 /* The BIOS may have set up the APIC at some other address */ 1803 if (boot_cpu_data.x86 >= 6) { 1804 rdmsr(MSR_IA32_APICBASE, l, h); 1805 if (l & MSR_IA32_APICBASE_ENABLE) 1806 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE; 1807 } 1808 1809 pr_info("Found and enabled local APIC!\n"); 1810 return 0; 1811 } 1812 1813 int __init apic_force_enable(unsigned long addr) 1814 { 1815 u32 h, l; 1816 1817 if (disable_apic) 1818 return -1; 1819 1820 /* 1821 * Some BIOSes disable the local APIC in the APIC_BASE 1822 * MSR. This can only be done in software for Intel P6 or later 1823 * and AMD K7 (Model > 1) or later. 1824 */ 1825 if (boot_cpu_data.x86 >= 6) { 1826 rdmsr(MSR_IA32_APICBASE, l, h); 1827 if (!(l & MSR_IA32_APICBASE_ENABLE)) { 1828 pr_info("Local APIC disabled by BIOS -- reenabling.\n"); 1829 l &= ~MSR_IA32_APICBASE_BASE; 1830 l |= MSR_IA32_APICBASE_ENABLE | addr; 1831 wrmsr(MSR_IA32_APICBASE, l, h); 1832 enabled_via_apicbase = 1; 1833 } 1834 } 1835 return apic_verify(); 1836 } 1837 1838 /* 1839 * Detect and initialize APIC 1840 */ 1841 static int __init detect_init_APIC(void) 1842 { 1843 /* Disabled by kernel option? */ 1844 if (disable_apic) 1845 return -1; 1846 1847 switch (boot_cpu_data.x86_vendor) { 1848 case X86_VENDOR_AMD: 1849 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) || 1850 (boot_cpu_data.x86 >= 15)) 1851 break; 1852 goto no_apic; 1853 case X86_VENDOR_INTEL: 1854 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 || 1855 (boot_cpu_data.x86 == 5 && boot_cpu_has(X86_FEATURE_APIC))) 1856 break; 1857 goto no_apic; 1858 default: 1859 goto no_apic; 1860 } 1861 1862 if (!boot_cpu_has(X86_FEATURE_APIC)) { 1863 /* 1864 * Over-ride BIOS and try to enable the local APIC only if 1865 * "lapic" specified. 1866 */ 1867 if (!force_enable_local_apic) { 1868 pr_info("Local APIC disabled by BIOS -- " 1869 "you can enable it with \"lapic\"\n"); 1870 return -1; 1871 } 1872 if (apic_force_enable(APIC_DEFAULT_PHYS_BASE)) 1873 return -1; 1874 } else { 1875 if (apic_verify()) 1876 return -1; 1877 } 1878 1879 apic_pm_activate(); 1880 1881 return 0; 1882 1883 no_apic: 1884 pr_info("No local APIC present or hardware disabled\n"); 1885 return -1; 1886 } 1887 #endif 1888 1889 /** 1890 * init_apic_mappings - initialize APIC mappings 1891 */ 1892 void __init init_apic_mappings(void) 1893 { 1894 unsigned int new_apicid; 1895 1896 apic_check_deadline_errata(); 1897 1898 if (x2apic_mode) { 1899 boot_cpu_physical_apicid = read_apic_id(); 1900 return; 1901 } 1902 1903 /* If no local APIC can be found return early */ 1904 if (!smp_found_config && detect_init_APIC()) { 1905 /* lets NOP'ify apic operations */ 1906 pr_info("APIC: disable apic facility\n"); 1907 apic_disable(); 1908 } else { 1909 apic_phys = mp_lapic_addr; 1910 1911 /* 1912 * If the system has ACPI MADT tables or MP info, the LAPIC 1913 * address is already registered. 1914 */ 1915 if (!acpi_lapic && !smp_found_config) 1916 register_lapic_address(apic_phys); 1917 } 1918 1919 /* 1920 * Fetch the APIC ID of the BSP in case we have a 1921 * default configuration (or the MP table is broken). 1922 */ 1923 new_apicid = read_apic_id(); 1924 if (boot_cpu_physical_apicid != new_apicid) { 1925 boot_cpu_physical_apicid = new_apicid; 1926 /* 1927 * yeah -- we lie about apic_version 1928 * in case if apic was disabled via boot option 1929 * but it's not a problem for SMP compiled kernel 1930 * since apic_intr_mode_select is prepared for such 1931 * a case and disable smp mode 1932 */ 1933 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 1934 } 1935 } 1936 1937 void __init register_lapic_address(unsigned long address) 1938 { 1939 mp_lapic_addr = address; 1940 1941 if (!x2apic_mode) { 1942 set_fixmap_nocache(FIX_APIC_BASE, address); 1943 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n", 1944 APIC_BASE, address); 1945 } 1946 if (boot_cpu_physical_apicid == -1U) { 1947 boot_cpu_physical_apicid = read_apic_id(); 1948 boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR)); 1949 } 1950 } 1951 1952 /* 1953 * Local APIC interrupts 1954 */ 1955 1956 /* 1957 * This interrupt should _never_ happen with our APIC/SMP architecture 1958 */ 1959 __visible void __irq_entry smp_spurious_interrupt(struct pt_regs *regs) 1960 { 1961 u8 vector = ~regs->orig_ax; 1962 u32 v; 1963 1964 entering_irq(); 1965 trace_spurious_apic_entry(vector); 1966 1967 /* 1968 * Check if this really is a spurious interrupt and ACK it 1969 * if it is a vectored one. Just in case... 1970 * Spurious interrupts should not be ACKed. 1971 */ 1972 v = apic_read(APIC_ISR + ((vector & ~0x1f) >> 1)); 1973 if (v & (1 << (vector & 0x1f))) 1974 ack_APIC_irq(); 1975 1976 inc_irq_stat(irq_spurious_count); 1977 1978 /* see sw-dev-man vol 3, chapter 7.4.13.5 */ 1979 pr_info("spurious APIC interrupt through vector %02x on CPU#%d, " 1980 "should never happen.\n", vector, smp_processor_id()); 1981 1982 trace_spurious_apic_exit(vector); 1983 exiting_irq(); 1984 } 1985 1986 /* 1987 * This interrupt should never happen with our APIC/SMP architecture 1988 */ 1989 __visible void __irq_entry smp_error_interrupt(struct pt_regs *regs) 1990 { 1991 static const char * const error_interrupt_reason[] = { 1992 "Send CS error", /* APIC Error Bit 0 */ 1993 "Receive CS error", /* APIC Error Bit 1 */ 1994 "Send accept error", /* APIC Error Bit 2 */ 1995 "Receive accept error", /* APIC Error Bit 3 */ 1996 "Redirectable IPI", /* APIC Error Bit 4 */ 1997 "Send illegal vector", /* APIC Error Bit 5 */ 1998 "Received illegal vector", /* APIC Error Bit 6 */ 1999 "Illegal register address", /* APIC Error Bit 7 */ 2000 }; 2001 u32 v, i = 0; 2002 2003 entering_irq(); 2004 trace_error_apic_entry(ERROR_APIC_VECTOR); 2005 2006 /* First tickle the hardware, only then report what went on. -- REW */ 2007 if (lapic_get_maxlvt() > 3) /* Due to the Pentium erratum 3AP. */ 2008 apic_write(APIC_ESR, 0); 2009 v = apic_read(APIC_ESR); 2010 ack_APIC_irq(); 2011 atomic_inc(&irq_err_count); 2012 2013 apic_printk(APIC_DEBUG, KERN_DEBUG "APIC error on CPU%d: %02x", 2014 smp_processor_id(), v); 2015 2016 v &= 0xff; 2017 while (v) { 2018 if (v & 0x1) 2019 apic_printk(APIC_DEBUG, KERN_CONT " : %s", error_interrupt_reason[i]); 2020 i++; 2021 v >>= 1; 2022 } 2023 2024 apic_printk(APIC_DEBUG, KERN_CONT "\n"); 2025 2026 trace_error_apic_exit(ERROR_APIC_VECTOR); 2027 exiting_irq(); 2028 } 2029 2030 /** 2031 * connect_bsp_APIC - attach the APIC to the interrupt system 2032 */ 2033 static void __init connect_bsp_APIC(void) 2034 { 2035 #ifdef CONFIG_X86_32 2036 if (pic_mode) { 2037 /* 2038 * Do not trust the local APIC being empty at bootup. 2039 */ 2040 clear_local_APIC(); 2041 /* 2042 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's 2043 * local APIC to INT and NMI lines. 2044 */ 2045 apic_printk(APIC_VERBOSE, "leaving PIC mode, " 2046 "enabling APIC mode.\n"); 2047 imcr_pic_to_apic(); 2048 } 2049 #endif 2050 } 2051 2052 /** 2053 * disconnect_bsp_APIC - detach the APIC from the interrupt system 2054 * @virt_wire_setup: indicates, whether virtual wire mode is selected 2055 * 2056 * Virtual wire mode is necessary to deliver legacy interrupts even when the 2057 * APIC is disabled. 2058 */ 2059 void disconnect_bsp_APIC(int virt_wire_setup) 2060 { 2061 unsigned int value; 2062 2063 #ifdef CONFIG_X86_32 2064 if (pic_mode) { 2065 /* 2066 * Put the board back into PIC mode (has an effect only on 2067 * certain older boards). Note that APIC interrupts, including 2068 * IPIs, won't work beyond this point! The only exception are 2069 * INIT IPIs. 2070 */ 2071 apic_printk(APIC_VERBOSE, "disabling APIC mode, " 2072 "entering PIC mode.\n"); 2073 imcr_apic_to_pic(); 2074 return; 2075 } 2076 #endif 2077 2078 /* Go back to Virtual Wire compatibility mode */ 2079 2080 /* For the spurious interrupt use vector F, and enable it */ 2081 value = apic_read(APIC_SPIV); 2082 value &= ~APIC_VECTOR_MASK; 2083 value |= APIC_SPIV_APIC_ENABLED; 2084 value |= 0xf; 2085 apic_write(APIC_SPIV, value); 2086 2087 if (!virt_wire_setup) { 2088 /* 2089 * For LVT0 make it edge triggered, active high, 2090 * external and enabled 2091 */ 2092 value = apic_read(APIC_LVT0); 2093 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2094 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2095 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2096 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2097 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT); 2098 apic_write(APIC_LVT0, value); 2099 } else { 2100 /* Disable LVT0 */ 2101 apic_write(APIC_LVT0, APIC_LVT_MASKED); 2102 } 2103 2104 /* 2105 * For LVT1 make it edge triggered, active high, 2106 * nmi and enabled 2107 */ 2108 value = apic_read(APIC_LVT1); 2109 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING | 2110 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR | 2111 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED); 2112 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING; 2113 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI); 2114 apic_write(APIC_LVT1, value); 2115 } 2116 2117 /* 2118 * The number of allocated logical CPU IDs. Since logical CPU IDs are allocated 2119 * contiguously, it equals to current allocated max logical CPU ID plus 1. 2120 * All allocated CPU IDs should be in the [0, nr_logical_cpuids) range, 2121 * so the maximum of nr_logical_cpuids is nr_cpu_ids. 2122 * 2123 * NOTE: Reserve 0 for BSP. 2124 */ 2125 static int nr_logical_cpuids = 1; 2126 2127 /* 2128 * Used to store mapping between logical CPU IDs and APIC IDs. 2129 */ 2130 static int cpuid_to_apicid[] = { 2131 [0 ... NR_CPUS - 1] = -1, 2132 }; 2133 2134 /* 2135 * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids 2136 * and cpuid_to_apicid[] synchronized. 2137 */ 2138 static int allocate_logical_cpuid(int apicid) 2139 { 2140 int i; 2141 2142 /* 2143 * cpuid <-> apicid mapping is persistent, so when a cpu is up, 2144 * check if the kernel has allocated a cpuid for it. 2145 */ 2146 for (i = 0; i < nr_logical_cpuids; i++) { 2147 if (cpuid_to_apicid[i] == apicid) 2148 return i; 2149 } 2150 2151 /* Allocate a new cpuid. */ 2152 if (nr_logical_cpuids >= nr_cpu_ids) { 2153 WARN_ONCE(1, "APIC: NR_CPUS/possible_cpus limit of %u reached. " 2154 "Processor %d/0x%x and the rest are ignored.\n", 2155 nr_cpu_ids, nr_logical_cpuids, apicid); 2156 return -EINVAL; 2157 } 2158 2159 cpuid_to_apicid[nr_logical_cpuids] = apicid; 2160 return nr_logical_cpuids++; 2161 } 2162 2163 int generic_processor_info(int apicid, int version) 2164 { 2165 int cpu, max = nr_cpu_ids; 2166 bool boot_cpu_detected = physid_isset(boot_cpu_physical_apicid, 2167 phys_cpu_present_map); 2168 2169 /* 2170 * boot_cpu_physical_apicid is designed to have the apicid 2171 * returned by read_apic_id(), i.e, the apicid of the 2172 * currently booting-up processor. However, on some platforms, 2173 * it is temporarily modified by the apicid reported as BSP 2174 * through MP table. Concretely: 2175 * 2176 * - arch/x86/kernel/mpparse.c: MP_processor_info() 2177 * - arch/x86/mm/amdtopology.c: amd_numa_init() 2178 * 2179 * This function is executed with the modified 2180 * boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel 2181 * parameter doesn't work to disable APs on kdump 2nd kernel. 2182 * 2183 * Since fixing handling of boot_cpu_physical_apicid requires 2184 * another discussion and tests on each platform, we leave it 2185 * for now and here we use read_apic_id() directly in this 2186 * function, generic_processor_info(). 2187 */ 2188 if (disabled_cpu_apicid != BAD_APICID && 2189 disabled_cpu_apicid != read_apic_id() && 2190 disabled_cpu_apicid == apicid) { 2191 int thiscpu = num_processors + disabled_cpus; 2192 2193 pr_warning("APIC: Disabling requested cpu." 2194 " Processor %d/0x%x ignored.\n", 2195 thiscpu, apicid); 2196 2197 disabled_cpus++; 2198 return -ENODEV; 2199 } 2200 2201 /* 2202 * If boot cpu has not been detected yet, then only allow upto 2203 * nr_cpu_ids - 1 processors and keep one slot free for boot cpu 2204 */ 2205 if (!boot_cpu_detected && num_processors >= nr_cpu_ids - 1 && 2206 apicid != boot_cpu_physical_apicid) { 2207 int thiscpu = max + disabled_cpus - 1; 2208 2209 pr_warning( 2210 "APIC: NR_CPUS/possible_cpus limit of %i almost" 2211 " reached. Keeping one slot for boot cpu." 2212 " Processor %d/0x%x ignored.\n", max, thiscpu, apicid); 2213 2214 disabled_cpus++; 2215 return -ENODEV; 2216 } 2217 2218 if (num_processors >= nr_cpu_ids) { 2219 int thiscpu = max + disabled_cpus; 2220 2221 pr_warning("APIC: NR_CPUS/possible_cpus limit of %i " 2222 "reached. Processor %d/0x%x ignored.\n", 2223 max, thiscpu, apicid); 2224 2225 disabled_cpus++; 2226 return -EINVAL; 2227 } 2228 2229 if (apicid == boot_cpu_physical_apicid) { 2230 /* 2231 * x86_bios_cpu_apicid is required to have processors listed 2232 * in same order as logical cpu numbers. Hence the first 2233 * entry is BSP, and so on. 2234 * boot_cpu_init() already hold bit 0 in cpu_present_mask 2235 * for BSP. 2236 */ 2237 cpu = 0; 2238 2239 /* Logical cpuid 0 is reserved for BSP. */ 2240 cpuid_to_apicid[0] = apicid; 2241 } else { 2242 cpu = allocate_logical_cpuid(apicid); 2243 if (cpu < 0) { 2244 disabled_cpus++; 2245 return -EINVAL; 2246 } 2247 } 2248 2249 /* 2250 * Validate version 2251 */ 2252 if (version == 0x0) { 2253 pr_warning("BIOS bug: APIC version is 0 for CPU %d/0x%x, fixing up to 0x10\n", 2254 cpu, apicid); 2255 version = 0x10; 2256 } 2257 2258 if (version != boot_cpu_apic_version) { 2259 pr_warning("BIOS bug: APIC version mismatch, boot CPU: %x, CPU %d: version %x\n", 2260 boot_cpu_apic_version, cpu, version); 2261 } 2262 2263 if (apicid > max_physical_apicid) 2264 max_physical_apicid = apicid; 2265 2266 #if defined(CONFIG_SMP) || defined(CONFIG_X86_64) 2267 early_per_cpu(x86_cpu_to_apicid, cpu) = apicid; 2268 early_per_cpu(x86_bios_cpu_apicid, cpu) = apicid; 2269 #endif 2270 #ifdef CONFIG_X86_32 2271 early_per_cpu(x86_cpu_to_logical_apicid, cpu) = 2272 apic->x86_32_early_logical_apicid(cpu); 2273 #endif 2274 set_cpu_possible(cpu, true); 2275 physid_set(apicid, phys_cpu_present_map); 2276 set_cpu_present(cpu, true); 2277 num_processors++; 2278 2279 return cpu; 2280 } 2281 2282 int hard_smp_processor_id(void) 2283 { 2284 return read_apic_id(); 2285 } 2286 2287 /* 2288 * Override the generic EOI implementation with an optimized version. 2289 * Only called during early boot when only one CPU is active and with 2290 * interrupts disabled, so we know this does not race with actual APIC driver 2291 * use. 2292 */ 2293 void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) 2294 { 2295 struct apic **drv; 2296 2297 for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) { 2298 /* Should happen once for each apic */ 2299 WARN_ON((*drv)->eoi_write == eoi_write); 2300 (*drv)->native_eoi_write = (*drv)->eoi_write; 2301 (*drv)->eoi_write = eoi_write; 2302 } 2303 } 2304 2305 static void __init apic_bsp_up_setup(void) 2306 { 2307 #ifdef CONFIG_X86_64 2308 apic_write(APIC_ID, apic->set_apic_id(boot_cpu_physical_apicid)); 2309 #else 2310 /* 2311 * Hack: In case of kdump, after a crash, kernel might be booting 2312 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid 2313 * might be zero if read from MP tables. Get it from LAPIC. 2314 */ 2315 # ifdef CONFIG_CRASH_DUMP 2316 boot_cpu_physical_apicid = read_apic_id(); 2317 # endif 2318 #endif 2319 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 2320 } 2321 2322 /** 2323 * apic_bsp_setup - Setup function for local apic and io-apic 2324 * @upmode: Force UP mode (for APIC_init_uniprocessor) 2325 * 2326 * Returns: 2327 * apic_id of BSP APIC 2328 */ 2329 void __init apic_bsp_setup(bool upmode) 2330 { 2331 connect_bsp_APIC(); 2332 if (upmode) 2333 apic_bsp_up_setup(); 2334 setup_local_APIC(); 2335 2336 enable_IO_APIC(); 2337 end_local_APIC_setup(); 2338 irq_remap_enable_fault_handling(); 2339 setup_IO_APIC(); 2340 } 2341 2342 #ifdef CONFIG_UP_LATE_INIT 2343 void __init up_late_init(void) 2344 { 2345 if (apic_intr_mode == APIC_PIC) 2346 return; 2347 2348 /* Setup local timer */ 2349 x86_init.timers.setup_percpu_clockev(); 2350 } 2351 #endif 2352 2353 /* 2354 * Power management 2355 */ 2356 #ifdef CONFIG_PM 2357 2358 static struct { 2359 /* 2360 * 'active' is true if the local APIC was enabled by us and 2361 * not the BIOS; this signifies that we are also responsible 2362 * for disabling it before entering apm/acpi suspend 2363 */ 2364 int active; 2365 /* r/w apic fields */ 2366 unsigned int apic_id; 2367 unsigned int apic_taskpri; 2368 unsigned int apic_ldr; 2369 unsigned int apic_dfr; 2370 unsigned int apic_spiv; 2371 unsigned int apic_lvtt; 2372 unsigned int apic_lvtpc; 2373 unsigned int apic_lvt0; 2374 unsigned int apic_lvt1; 2375 unsigned int apic_lvterr; 2376 unsigned int apic_tmict; 2377 unsigned int apic_tdcr; 2378 unsigned int apic_thmr; 2379 unsigned int apic_cmci; 2380 } apic_pm_state; 2381 2382 static int lapic_suspend(void) 2383 { 2384 unsigned long flags; 2385 int maxlvt; 2386 2387 if (!apic_pm_state.active) 2388 return 0; 2389 2390 maxlvt = lapic_get_maxlvt(); 2391 2392 apic_pm_state.apic_id = apic_read(APIC_ID); 2393 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI); 2394 apic_pm_state.apic_ldr = apic_read(APIC_LDR); 2395 apic_pm_state.apic_dfr = apic_read(APIC_DFR); 2396 apic_pm_state.apic_spiv = apic_read(APIC_SPIV); 2397 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT); 2398 if (maxlvt >= 4) 2399 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC); 2400 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0); 2401 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1); 2402 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR); 2403 apic_pm_state.apic_tmict = apic_read(APIC_TMICT); 2404 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR); 2405 #ifdef CONFIG_X86_THERMAL_VECTOR 2406 if (maxlvt >= 5) 2407 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR); 2408 #endif 2409 #ifdef CONFIG_X86_MCE_INTEL 2410 if (maxlvt >= 6) 2411 apic_pm_state.apic_cmci = apic_read(APIC_LVTCMCI); 2412 #endif 2413 2414 local_irq_save(flags); 2415 disable_local_APIC(); 2416 2417 irq_remapping_disable(); 2418 2419 local_irq_restore(flags); 2420 return 0; 2421 } 2422 2423 static void lapic_resume(void) 2424 { 2425 unsigned int l, h; 2426 unsigned long flags; 2427 int maxlvt; 2428 2429 if (!apic_pm_state.active) 2430 return; 2431 2432 local_irq_save(flags); 2433 2434 /* 2435 * IO-APIC and PIC have their own resume routines. 2436 * We just mask them here to make sure the interrupt 2437 * subsystem is completely quiet while we enable x2apic 2438 * and interrupt-remapping. 2439 */ 2440 mask_ioapic_entries(); 2441 legacy_pic->mask_all(); 2442 2443 if (x2apic_mode) { 2444 __x2apic_enable(); 2445 } else { 2446 /* 2447 * Make sure the APICBASE points to the right address 2448 * 2449 * FIXME! This will be wrong if we ever support suspend on 2450 * SMP! We'll need to do this as part of the CPU restore! 2451 */ 2452 if (boot_cpu_data.x86 >= 6) { 2453 rdmsr(MSR_IA32_APICBASE, l, h); 2454 l &= ~MSR_IA32_APICBASE_BASE; 2455 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr; 2456 wrmsr(MSR_IA32_APICBASE, l, h); 2457 } 2458 } 2459 2460 maxlvt = lapic_get_maxlvt(); 2461 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED); 2462 apic_write(APIC_ID, apic_pm_state.apic_id); 2463 apic_write(APIC_DFR, apic_pm_state.apic_dfr); 2464 apic_write(APIC_LDR, apic_pm_state.apic_ldr); 2465 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri); 2466 apic_write(APIC_SPIV, apic_pm_state.apic_spiv); 2467 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0); 2468 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1); 2469 #ifdef CONFIG_X86_THERMAL_VECTOR 2470 if (maxlvt >= 5) 2471 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr); 2472 #endif 2473 #ifdef CONFIG_X86_MCE_INTEL 2474 if (maxlvt >= 6) 2475 apic_write(APIC_LVTCMCI, apic_pm_state.apic_cmci); 2476 #endif 2477 if (maxlvt >= 4) 2478 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc); 2479 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt); 2480 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr); 2481 apic_write(APIC_TMICT, apic_pm_state.apic_tmict); 2482 apic_write(APIC_ESR, 0); 2483 apic_read(APIC_ESR); 2484 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr); 2485 apic_write(APIC_ESR, 0); 2486 apic_read(APIC_ESR); 2487 2488 irq_remapping_reenable(x2apic_mode); 2489 2490 local_irq_restore(flags); 2491 } 2492 2493 /* 2494 * This device has no shutdown method - fully functioning local APICs 2495 * are needed on every CPU up until machine_halt/restart/poweroff. 2496 */ 2497 2498 static struct syscore_ops lapic_syscore_ops = { 2499 .resume = lapic_resume, 2500 .suspend = lapic_suspend, 2501 }; 2502 2503 static void apic_pm_activate(void) 2504 { 2505 apic_pm_state.active = 1; 2506 } 2507 2508 static int __init init_lapic_sysfs(void) 2509 { 2510 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */ 2511 if (boot_cpu_has(X86_FEATURE_APIC)) 2512 register_syscore_ops(&lapic_syscore_ops); 2513 2514 return 0; 2515 } 2516 2517 /* local apic needs to resume before other devices access its registers. */ 2518 core_initcall(init_lapic_sysfs); 2519 2520 #else /* CONFIG_PM */ 2521 2522 static void apic_pm_activate(void) { } 2523 2524 #endif /* CONFIG_PM */ 2525 2526 #ifdef CONFIG_X86_64 2527 2528 static int multi_checked; 2529 static int multi; 2530 2531 static int set_multi(const struct dmi_system_id *d) 2532 { 2533 if (multi) 2534 return 0; 2535 pr_info("APIC: %s detected, Multi Chassis\n", d->ident); 2536 multi = 1; 2537 return 0; 2538 } 2539 2540 static const struct dmi_system_id multi_dmi_table[] = { 2541 { 2542 .callback = set_multi, 2543 .ident = "IBM System Summit2", 2544 .matches = { 2545 DMI_MATCH(DMI_SYS_VENDOR, "IBM"), 2546 DMI_MATCH(DMI_PRODUCT_NAME, "Summit2"), 2547 }, 2548 }, 2549 {} 2550 }; 2551 2552 static void dmi_check_multi(void) 2553 { 2554 if (multi_checked) 2555 return; 2556 2557 dmi_check_system(multi_dmi_table); 2558 multi_checked = 1; 2559 } 2560 2561 /* 2562 * apic_is_clustered_box() -- Check if we can expect good TSC 2563 * 2564 * Thus far, the major user of this is IBM's Summit2 series: 2565 * Clustered boxes may have unsynced TSC problems if they are 2566 * multi-chassis. 2567 * Use DMI to check them 2568 */ 2569 int apic_is_clustered_box(void) 2570 { 2571 dmi_check_multi(); 2572 return multi; 2573 } 2574 #endif 2575 2576 /* 2577 * APIC command line parameters 2578 */ 2579 static int __init setup_disableapic(char *arg) 2580 { 2581 disable_apic = 1; 2582 setup_clear_cpu_cap(X86_FEATURE_APIC); 2583 return 0; 2584 } 2585 early_param("disableapic", setup_disableapic); 2586 2587 /* same as disableapic, for compatibility */ 2588 static int __init setup_nolapic(char *arg) 2589 { 2590 return setup_disableapic(arg); 2591 } 2592 early_param("nolapic", setup_nolapic); 2593 2594 static int __init parse_lapic_timer_c2_ok(char *arg) 2595 { 2596 local_apic_timer_c2_ok = 1; 2597 return 0; 2598 } 2599 early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok); 2600 2601 static int __init parse_disable_apic_timer(char *arg) 2602 { 2603 disable_apic_timer = 1; 2604 return 0; 2605 } 2606 early_param("noapictimer", parse_disable_apic_timer); 2607 2608 static int __init parse_nolapic_timer(char *arg) 2609 { 2610 disable_apic_timer = 1; 2611 return 0; 2612 } 2613 early_param("nolapic_timer", parse_nolapic_timer); 2614 2615 static int __init apic_set_verbosity(char *arg) 2616 { 2617 if (!arg) { 2618 #ifdef CONFIG_X86_64 2619 skip_ioapic_setup = 0; 2620 return 0; 2621 #endif 2622 return -EINVAL; 2623 } 2624 2625 if (strcmp("debug", arg) == 0) 2626 apic_verbosity = APIC_DEBUG; 2627 else if (strcmp("verbose", arg) == 0) 2628 apic_verbosity = APIC_VERBOSE; 2629 #ifdef CONFIG_X86_64 2630 else { 2631 pr_warning("APIC Verbosity level %s not recognised" 2632 " use apic=verbose or apic=debug\n", arg); 2633 return -EINVAL; 2634 } 2635 #endif 2636 2637 return 0; 2638 } 2639 early_param("apic", apic_set_verbosity); 2640 2641 static int __init lapic_insert_resource(void) 2642 { 2643 if (!apic_phys) 2644 return -1; 2645 2646 /* Put local APIC into the resource map. */ 2647 lapic_resource.start = apic_phys; 2648 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1; 2649 insert_resource(&iomem_resource, &lapic_resource); 2650 2651 return 0; 2652 } 2653 2654 /* 2655 * need call insert after e820__reserve_resources() 2656 * that is using request_resource 2657 */ 2658 late_initcall(lapic_insert_resource); 2659 2660 static int __init apic_set_disabled_cpu_apicid(char *arg) 2661 { 2662 if (!arg || !get_option(&arg, &disabled_cpu_apicid)) 2663 return -EINVAL; 2664 2665 return 0; 2666 } 2667 early_param("disable_cpu_apicid", apic_set_disabled_cpu_apicid); 2668 2669 static int __init apic_set_extnmi(char *arg) 2670 { 2671 if (!arg) 2672 return -EINVAL; 2673 2674 if (!strncmp("all", arg, 3)) 2675 apic_extnmi = APIC_EXTNMI_ALL; 2676 else if (!strncmp("none", arg, 4)) 2677 apic_extnmi = APIC_EXTNMI_NONE; 2678 else if (!strncmp("bsp", arg, 3)) 2679 apic_extnmi = APIC_EXTNMI_BSP; 2680 else { 2681 pr_warn("Unknown external NMI delivery mode `%s' ignored\n", arg); 2682 return -EINVAL; 2683 } 2684 2685 return 0; 2686 } 2687 early_param("apic_extnmi", apic_set_extnmi); 2688